commit 5ca41210fe73ddc08ca4bdec52ffc5765052d8b4
author Marek Vasut <marex@denx.de> Thu Sep 21 20:44:17 2023 +0200
committer Stefano Babic <sbabic@denx.de> Mon Oct 16 16:25:10 2023 +0200
tree 02374f08d19626c71184a90729a5a44a3d646b3b
parent a0494277f0bcbcccd50fbe44fb1c3f6a1f71bded

arm64: dts: imx8mp: Switch to DT overlays for i.MX8MP DHCOM SoM

Add DT overlays to support additional DH i.MX8MP DHCOM SoM 660-100
population options with 1x or 2x RMII PHY mounted on PDK2 or PDK3
carrier boards.

Use SPL DTO support to apply matching SoM specific DTO to cater
for the SoM differences. Remove ad-hoc patching of control DT from
fdtdec_board_setup().

Signed-off-by: Marek Vasut <marex@denx.de>

arch/arm/dts/imx8mp-dhcom-som-overlay-eth1xfast.dts

diff --git a/arch/arm/dts/imx8mp-dhcom-som-overlay-eth1xfast.dts b/arch/arm/dts/imx8mp-dhcom-som-overlay-eth1xfast.dts
new file mode 100644
index 0000000..bb5a2b6
--- /dev/null
+++ b/arch/arm/dts/imx8mp-dhcom-som-overlay-eth1xfast.dts
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023 Marek Vasut <marex@denx.de>
+ */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/imx8mp-clock.h>
+
+&eqos {	/* First ethernet */
+	pinctrl-0 = <&pinctrl_eqos_rmii>;
+	phy-handle = <&ethphy0f>;
+	phy-mode = "rmii";
+
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
+				 <&clk IMX8MP_SYS_PLL2_100M>,
+				 <&clk IMX8MP_SYS_PLL2_50M>;
+	assigned-clock-rates = <0>, <100000000>, <50000000>;
+};
+
+&ethphy0g {	/* Micrel KSZ9131RNXI */
+	status = "disabled";
+};
+
+&ethphy0f {	/* SMSC LAN8740Ai */
+	status = "okay";
+};
+
+&fec {	/* Second ethernet -- HS connector not populated on 1x RMII PHY SoM */
+	status = "disabled";
+};
+
+/* No WiFi/BT chipset on this SoM variant. */
+
+&uart2 {
+	bluetooth {
+		status = "disabled";
+	};
+};
+
+&usdhc1 {
+	status = "disabled";
+};