// SPDX-License-Identifier: GPL-2.0+
/*
 * dts file for Xilinx ZynqMP Mini Configuration
 *
 * (C) Copyright 2018, Xilinx, Inc.
 *
 * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
 */

/dts-v1/;

/ {
	model = "ZynqMP MINI EMMC0";
	compatible = "xlnx,zynqmp";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &dcc;
		mmc0 = &sdhci0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x20000000>;
	};

	dcc: dcc {
		compatible = "arm,dcc";
		status = "disabled";
		bootph-all;
	};

	clk_xin: clk-xin {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <200000000>;
	};

	amba: axi {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		sdhci0: mmc@ff160000 {
			bootph-all;
			compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
			status = "disabled";
			non-removable;
			bus-width = <8>;
			reg = <0x0 0xff160000 0x0 0x1000>;
			clock-names = "clk_xin", "clk_ahb";
			clocks = <&clk_xin &clk_xin>;
		};
	};
};

&dcc {
	status = "okay";
};

&sdhci0 {
	status = "okay";
};