tree 7e5d6145ff6b76113d02152461a7d829f63ef95f
parent 0f2c979199b9c24ff326865ec1f53a6c08586e68
author Neha Malcom Francis <n-francis@ti.com> 1680692075 +0530
committer Tom Rini <trini@konsulko.com> 1683219834 -0400

k3: pmic: Clear ESM masks

ESM MCU masks must be set to 0h so that PMIC can handle errors
that require attention for example SYS_SAFETY_ERRn. The required bits
must be cleared: ESM_MCU_RST_MASK, ESM_MCU_FAIL_MASK, ESM_MCU_PIN_MASK.

If PMIC expected to handle errors, make sure EVM is configured to
connect SOC_SAFETY_ERRz (Main) to the PMIC.

Note that even though the User Guide for TPS65941 for J721E mentions
that these bits are reset to 0h; it is not reflected once board boots to
kernel, possibly due to NVM configurations. Eithercase, it is best to
account for this from R5 SPL side as well.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>