powerpc: remove support for kmtergr1 and MPC8309
The kmtegr1 board is out of maintenance and can be removed. As it is the
only board in the tree using MPC8309 the support for this CPU is dropped
completely.
Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
diff --git a/include/configs/km/km-mpc8309.h b/include/configs/km/km-mpc8309.h
deleted file mode 100644
index 0468ed5..0000000
--- a/include/configs/km/km-mpc8309.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * High Level Configuration Options
- */
-
-#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
-
-/* QE microcode/firmware address */
-/* between the u-boot partition and env */
-
-/*
- * System IO Config
- */
-/* 0x14000180 SICR_1 */
-#ifndef CONFIG_SYS_SICRL
-#define CONFIG_SYS_SICRL (0 \
- | SICR_1_UART1_UART1RTS \
- | SICR_1_I2C_CKSTOP \
- | SICR_1_IRQ_A_IRQ \
- | SICR_1_IRQ_B_IRQ \
- | SICR_1_GPIO_A_GPIO \
- | SICR_1_GPIO_B_GPIO \
- | SICR_1_GPIO_C_GPIO \
- | SICR_1_GPIO_D_GPIO \
- | SICR_1_GPIO_E_GPIO \
- | SICR_1_GPIO_F_GPIO \
- | SICR_1_USB_A_UART2S \
- | SICR_1_USB_B_UART2RTS \
- | SICR_1_FEC1_FEC1 \
- | SICR_1_FEC2_FEC2 \
- )
-#endif
-
-/* 0x00080400 SICR_2 */
-#define CONFIG_SYS_SICRH (0 \
- | SICR_2_FEC3_FEC3 \
- | SICR_2_HDLC1_A_HDLC1 \
- | SICR_2_ELBC_A_LA \
- | SICR_2_ELBC_B_LCLK \
- | SICR_2_HDLC2_A_HDLC2 \
- | SICR_2_USB_D_GPIO \
- | SICR_2_PCI_PCI \
- | SICR_2_HDLC1_B_HDLC1 \
- | SICR_2_HDLC1_C_HDLC1 \
- | SICR_2_HDLC2_B_GPIO \
- | SICR_2_HDLC2_C_HDLC2 \
- | SICR_2_QUIESCE_B \
- )
-
-/* GPR_1 */
-#define CONFIG_SYS_GPR1 0x50008060
-
-#define CONFIG_SYS_DDRCDR (\
- DDRCDR_EN | \
- DDRCDR_PZ_MAXZ | \
- DDRCDR_NZ_MAXZ | \
- DDRCDR_M_ODR)
-
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
- SDRAM_CFG_32_BE | \
- SDRAM_CFG_SREN | \
- SDRAM_CFG_HSE)
-
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
- (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
-
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
- CSCONFIG_ODT_RD_NEVER | \
- CSCONFIG_ODT_WR_ONLY_CURRENT | \
- CSCONFIG_ROW_BIT_13 | \
- CSCONFIG_COL_BIT_10)
-
-#define CONFIG_SYS_DDR_MODE 0x47860242
-#define CONFIG_SYS_DDR_MODE2 0x8080c000
-
-#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
- (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
- (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
- (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
- (0 << TIMING_CFG0_WWT_SHIFT) | \
- (0 << TIMING_CFG0_RRT_SHIFT) | \
- (0 << TIMING_CFG0_WRT_SHIFT) | \
- (0 << TIMING_CFG0_RWT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
- (2 << TIMING_CFG1_WRTORD_SHIFT) | \
- (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
- (3 << TIMING_CFG1_WRREC_SHIFT) | \
- (7 << TIMING_CFG1_REFREC_SHIFT) | \
- (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
- (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
- (3 << TIMING_CFG1_PRETOACT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
- (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
- (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
- (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
- (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
- (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
- (5 << TIMING_CFG2_CPO_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-
-#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
-#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
-
-/* EEprom support */
-
-/* ethernet port connected to piggy (UEC2) */
-#define CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */
-#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
-#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12
-#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR 0
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h
deleted file mode 100644
index bdd35cc..0000000
--- a/include/configs/kmtegr1.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * Copyright (C) 2007 Logic Product Development, Inc.
- * Peter Barada <peterb@logicpd.com>
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- * Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * (C) Copyright 2010
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-
-#define CONFIG_HOSTNAME "kmtegr1"
-#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
-#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
-
-#define CONFIG_NAND_ECC_BCH
-#define CONFIG_NAND_KMETER1
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
-
-#define CONFIG_SYS_SICRL (0 \
- | SICR_1_UART1_UART1RTS \
- | SICR_1_I2C_CKSTOP \
- | SICR_1_IRQ_A_IRQ \
- | SICR_1_IRQ_B_IRQ \
- | SICR_1_GPIO_A_GPIO \
- | SICR_1_GPIO_B_GPIO \
- | SICR_1_GPIO_C_GPIO \
- | SICR_1_GPIO_D_GPIO \
- | SICR_1_GPIO_E_LCS \
- | SICR_1_GPIO_F_GPIO \
- | SICR_1_USB_A_UART2S \
- | SICR_1_USB_B_UART2RTS \
- | SICR_1_FEC1_FEC1 \
- | SICR_1_FEC2_FEC2 \
- )
-
-/* include common defines/options for all Keymile boards */
-#include "km/keymile-common.h"
-#include "km/km-powerpc.h"
-#include "km/km-mpc83xx.h"
-#include "km/km-mpc8309.h"
-
-/* must be after the include because KMBEC_FPGA is otherwise undefined */
-#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
-
-#endif /* __CONFIG_H */
diff --git a/include/linux/immap_qe.h b/include/linux/immap_qe.h
index 022771f..45307f5 100644
--- a/include/linux/immap_qe.h
+++ b/include/linux/immap_qe.h
@@ -16,7 +16,7 @@
#define QE_MURAM_SIZE 0xc000UL
#define MAX_QE_RISC 2
#define QE_NUM_OF_SNUM 28
-#elif defined(CONFIG_ARCH_MPC832X) || defined(CONFIG_ARCH_MPC8309)
+#elif defined(CONFIG_ARCH_MPC832X)
#define QE_MURAM_SIZE 0x4000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 2181a90..5926c80 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -340,85 +340,6 @@
#define SICRH_TSOBI2_V3P3 (0 << 0)
#define SICRH_TSOBI2_V2P5 (1 << 0)
-#elif defined(CONFIG_ARCH_MPC8309)
-/* SICR_1 */
-#define SICR_1_UART1_UART1S (0 << (30-2))
-#define SICR_1_UART1_UART1RTS (1 << (30-2))
-#define SICR_1_I2C_I2C (0 << (30-4))
-#define SICR_1_I2C_CKSTOP (1 << (30-4))
-#define SICR_1_IRQ_A_IRQ (0 << (30-6))
-#define SICR_1_IRQ_A_MCP (1 << (30-6))
-#define SICR_1_IRQ_B_IRQ (0 << (30-8))
-#define SICR_1_IRQ_B_CKSTOP (1 << (30-8))
-#define SICR_1_GPIO_A_GPIO (0 << (30-10))
-#define SICR_1_GPIO_A_SD (2 << (30-10))
-#define SICR_1_GPIO_A_DDR (3 << (30-10))
-#define SICR_1_GPIO_B_GPIO (0 << (30-12))
-#define SICR_1_GPIO_B_SD (2 << (30-12))
-#define SICR_1_GPIO_B_QE (3 << (30-12))
-#define SICR_1_GPIO_C_GPIO (0 << (30-14))
-#define SICR_1_GPIO_C_CAN (1 << (30-14))
-#define SICR_1_GPIO_C_DDR (2 << (30-14))
-#define SICR_1_GPIO_C_LCS (3 << (30-14))
-#define SICR_1_GPIO_D_GPIO (0 << (30-16))
-#define SICR_1_GPIO_D_CAN (1 << (30-16))
-#define SICR_1_GPIO_D_DDR (2 << (30-16))
-#define SICR_1_GPIO_D_LCS (3 << (30-16))
-#define SICR_1_GPIO_E_GPIO (0 << (30-18))
-#define SICR_1_GPIO_E_CAN (1 << (30-18))
-#define SICR_1_GPIO_E_DDR (2 << (30-18))
-#define SICR_1_GPIO_E_LCS (3 << (30-18))
-#define SICR_1_GPIO_F_GPIO (0 << (30-20))
-#define SICR_1_GPIO_F_CAN (1 << (30-20))
-#define SICR_1_GPIO_F_CK (2 << (30-20))
-#define SICR_1_USB_A_USBDR (0 << (30-22))
-#define SICR_1_USB_A_UART2S (1 << (30-22))
-#define SICR_1_USB_B_USBDR (0 << (30-24))
-#define SICR_1_USB_B_UART2S (1 << (30-24))
-#define SICR_1_USB_B_UART2RTS (2 << (30-24))
-#define SICR_1_USB_C_USBDR (0 << (30-26))
-#define SICR_1_USB_C_QE_EXT (3 << (30-26))
-#define SICR_1_FEC1_FEC1 (0 << (30-28))
-#define SICR_1_FEC1_GTM (1 << (30-28))
-#define SICR_1_FEC1_GPIO (2 << (30-28))
-#define SICR_1_FEC2_FEC2 (0 << (30-30))
-#define SICR_1_FEC2_GTM (1 << (30-30))
-#define SICR_1_FEC2_GPIO (2 << (30-30))
-/* SICR_2 */
-#define SICR_2_FEC3_FEC3 (0 << (30-0))
-#define SICR_2_FEC3_TMR (1 << (30-0))
-#define SICR_2_FEC3_GPIO (2 << (30-0))
-#define SICR_2_HDLC1_A_HDLC1 (0 << (30-2))
-#define SICR_2_HDLC1_A_GPIO (1 << (30-2))
-#define SICR_2_HDLC1_A_TDM1 (2 << (30-2))
-#define SICR_2_ELBC_A_LA (0 << (30-4))
-#define SICR_2_ELBC_B_LCLK (0 << (30-6))
-#define SICR_2_HDLC2_A_HDLC2 (0 << (30-8))
-#define SICR_2_HDLC2_A_GPIO (0 << (30-8))
-#define SICR_2_HDLC2_A_TDM2 (0 << (30-8))
-/* bits 10-11 unused */
-#define SICR_2_USB_D_USBDR (0 << (30-12))
-#define SICR_2_USB_D_GPIO (2 << (30-12))
-#define SICR_2_USB_D_QE_BRG (3 << (30-12))
-#define SICR_2_PCI_PCI (0 << (30-14))
-#define SICR_2_PCI_CPCI_HS (2 << (30-14))
-#define SICR_2_HDLC1_B_HDLC1 (0 << (30-16))
-#define SICR_2_HDLC1_B_GPIO (1 << (30-16))
-#define SICR_2_HDLC1_B_QE_BRG (2 << (30-16))
-#define SICR_2_HDLC1_B_TDM1 (3 << (30-16))
-#define SICR_2_HDLC1_C_HDLC1 (0 << (30-18))
-#define SICR_2_HDLC1_C_GPIO (1 << (30-18))
-#define SICR_2_HDLC1_C_TDM1 (2 << (30-18))
-#define SICR_2_HDLC2_B_HDLC2 (0 << (30-20))
-#define SICR_2_HDLC2_B_GPIO (1 << (30-20))
-#define SICR_2_HDLC2_B_QE_BRG (2 << (30-20))
-#define SICR_2_HDLC2_B_TDM2 (3 << (30-20))
-#define SICR_2_HDLC2_C_HDLC2 (0 << (30-22))
-#define SICR_2_HDLC2_C_GPIO (1 << (30-22))
-#define SICR_2_HDLC2_C_TDM2 (2 << (30-22))
-#define SICR_2_HDLC2_C_QE_BRG (3 << (30-22))
-#define SICR_2_QUIESCE_B (0 << (30-24))
-
#endif
/*
@@ -610,63 +531,6 @@
#define HRCWL_SVCOD_DIV_8 0x10000000
#define HRCWL_SVCOD_DIV_2 0x20000000
#define HRCWL_SVCOD_DIV_1 0x30000000
-#elif defined(CONFIG_ARCH_MPC8309)
-
-#define HRCWL_CEVCOD 0x000000C0
-#define HRCWL_CEVCOD_SHIFT 6
-/*
- * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012
- * these are different than with 8360, 832x
- */
-#define HRCWL_CE_PLL_VCO_DIV_2 0x00000000
-#define HRCWL_CE_PLL_VCO_DIV_4 0x00000040
-#define HRCWL_CE_PLL_VCO_DIV_8 0x00000080
-
-#define HRCWL_CEPDF 0x00000020
-#define HRCWL_CEPDF_SHIFT 5
-#define HRCWL_CE_PLL_DIV_1X1 0x00000000
-#define HRCWL_CE_PLL_DIV_2X1 0x00000020
-
-#define HRCWL_CEPMF 0x0000001F
-#define HRCWL_CEPMF_SHIFT 0
-#define HRCWL_CE_TO_PLL_1X16_ 0x00000000
-#define HRCWL_CE_TO_PLL_1X2 0x00000002
-#define HRCWL_CE_TO_PLL_1X3 0x00000003
-#define HRCWL_CE_TO_PLL_1X4 0x00000004
-#define HRCWL_CE_TO_PLL_1X5 0x00000005
-#define HRCWL_CE_TO_PLL_1X6 0x00000006
-#define HRCWL_CE_TO_PLL_1X7 0x00000007
-#define HRCWL_CE_TO_PLL_1X8 0x00000008
-#define HRCWL_CE_TO_PLL_1X9 0x00000009
-#define HRCWL_CE_TO_PLL_1X10 0x0000000A
-#define HRCWL_CE_TO_PLL_1X11 0x0000000B
-#define HRCWL_CE_TO_PLL_1X12 0x0000000C
-#define HRCWL_CE_TO_PLL_1X13 0x0000000D
-#define HRCWL_CE_TO_PLL_1X14 0x0000000E
-#define HRCWL_CE_TO_PLL_1X15 0x0000000F
-#define HRCWL_CE_TO_PLL_1X16 0x00000010
-#define HRCWL_CE_TO_PLL_1X17 0x00000011
-#define HRCWL_CE_TO_PLL_1X18 0x00000012
-#define HRCWL_CE_TO_PLL_1X19 0x00000013
-#define HRCWL_CE_TO_PLL_1X20 0x00000014
-#define HRCWL_CE_TO_PLL_1X21 0x00000015
-#define HRCWL_CE_TO_PLL_1X22 0x00000016
-#define HRCWL_CE_TO_PLL_1X23 0x00000017
-#define HRCWL_CE_TO_PLL_1X24 0x00000018
-#define HRCWL_CE_TO_PLL_1X25 0x00000019
-#define HRCWL_CE_TO_PLL_1X26 0x0000001A
-#define HRCWL_CE_TO_PLL_1X27 0x0000001B
-#define HRCWL_CE_TO_PLL_1X28 0x0000001C
-#define HRCWL_CE_TO_PLL_1X29 0x0000001D
-#define HRCWL_CE_TO_PLL_1X30 0x0000001E
-#define HRCWL_CE_TO_PLL_1X31 0x0000001F
-
-#define HRCWL_SVCOD 0x30000000
-#define HRCWL_SVCOD_SHIFT 28
-#define HRCWL_SVCOD_DIV_2 0x00000000
-#define HRCWL_SVCOD_DIV_4 0x10000000
-#define HRCWL_SVCOD_DIV_8 0x20000000
-#define HRCWL_SVCOD_DIV_1 0x30000000
#endif
/*
@@ -1027,21 +891,6 @@
#define SCCR_SATACM_1 0x00000055
#define SCCR_SATACM_2 0x000000aa
#define SCCR_SATACM_3 0x000000ff
-#elif defined(CONFIG_ARCH_MPC8309)
-/* SCCR bits - MPC8309 specific */
-#define SCCR_SDHCCM 0x0c000000
-#define SCCR_SDHCCM_SHIFT 26
-#define SCCR_SDHCCM_0 0x00000000
-#define SCCR_SDHCCM_1 0x04000000
-#define SCCR_SDHCCM_2 0x08000000
-#define SCCR_SDHCCM_3 0x0c000000
-
-#define SCCR_USBDRCM 0x00c00000
-#define SCCR_USBDRCM_SHIFT 22
-#define SCCR_USBDRCM_0 0x00000000
-#define SCCR_USBDRCM_1 0x00400000
-#define SCCR_USBDRCM_2 0x00800000
-#define SCCR_USBDRCM_3 0x00c00000
#endif
#define SCCR_PCIEXP1CM 0x00300000