powerpc: remove support for kmtergr1 and MPC8309
The kmtegr1 board is out of maintenance and can be removed. As it is the
only board in the tree using MPC8309 the support for this CPU is dropped
completely.
Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 9d24f02..ec3405e 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -132,15 +132,6 @@
select MPC83XX_PCIE1_SUPPORT
select MPC83XX_SECOND_I2C
-config ARCH_MPC8309
- bool
- select ARCH_MPC830X
- select MPC83XX_QUICC_ENGINE
- select MPC83XX_PCI_SUPPORT
- select MPC83XX_SECOND_I2C
- select SYS_FSL_ERRATUM_ESDHC111
- select FSL_ELBC
-
config ARCH_MPC831X
bool
select MPC83XX_PCI_SUPPORT
diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
index 71fa738..b67ccd6 100644
--- a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
@@ -160,10 +160,6 @@
config QUICC_VCO_DIVIDER_4
bool "4"
-config QUICC_VCO_DIVIDER_8
- depends on ARCH_MPC8309
- bool "8"
-
endchoice
choice
@@ -399,14 +395,6 @@
depends on ARCH_MPC837X
bool "PCI2"
-config BOOT_ROM_INTERFACE_ESDHC
- depends on ARCH_MPC8309
- bool "eSDHC"
-
-config BOOT_ROM_INTERFACE_SPI
- depends on ARCH_MPC8309
- bool "SPI"
-
config BOOT_ROM_INTERFACE_GPCM_8BIT
bool "Local bus GPCM - 8-bit ROM"
@@ -623,8 +611,6 @@
hex
default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM
default 0x4 if BOOT_ROM_INTERFACE_PCI1
- default 0x8 if BOOT_ROM_INTERFACE_ESDHC
- default 0xc if BOOT_ROM_INTERFACE_SPI
default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
default 0x14 if BOOT_ROM_INTERFACE_GPCM_8BIT
default 0x18 if BOOT_ROM_INTERFACE_GPCM_16BIT
@@ -676,12 +662,8 @@
config QUICC_VCO_DIVIDER
int
default 0 if !MPC83XX_QUICC_ENGINE
- default 0 if QUICC_VCO_DIVIDER_2 && ARCH_MPC8309
- default 1 if QUICC_VCO_DIVIDER_4 && ARCH_MPC8309
- default 2 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8309
default 2 if QUICC_VCO_DIVIDER_2 && (ARCH_MPC832X || ARCH_MPC8360)
default 0 if QUICC_VCO_DIVIDER_4 && (ARCH_MPC832X || ARCH_MPC8360)
- default 1 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8360
config QUICC_DIV_FACTOR
int
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
index e6b6130..86c5f42 100644
--- a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
+++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
@@ -1,6 +1,6 @@
menu "LCRR - Clock Ratio Register register"
-if !ARCH_MPC8309 && !ARCH_MPC831X && !ARCH_MPC832X
+if !ARCH_MPC831X && !ARCH_MPC832X
choice
prompt "DLL bypass"
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index f835263..b7a87fe 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -93,8 +93,6 @@
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
-#elif defined(CONFIG_ARCH_MPC8309)
- u32 usbdr_clk;
#endif
#ifdef CONFIG_ARCH_MPC834X
u32 usbmph_clk;
@@ -107,9 +105,7 @@
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
#endif
-#if !defined(CONFIG_ARCH_MPC8309)
u32 enc_clk;
-#endif
u32 lbiu_clk;
u32 lclk_clk;
u32 mem_clk;
@@ -252,7 +248,6 @@
return -6;
}
#endif
-#if !defined(CONFIG_ARCH_MPC8309)
switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
case 0:
enc_clk = 0;
@@ -270,7 +265,6 @@
/* unknown SCCR_ENCCM value */
return -7;
}
-#endif
#if defined(CONFIG_FSL_ESDHC)
switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
@@ -304,8 +298,6 @@
i2c1_clk = sdhc_clk;
#elif defined(CONFIG_ARCH_MPC837X)
i2c1_clk = enc_clk;
-#elif defined(CONFIG_ARCH_MPC8309)
- i2c1_clk = csb_clk;
#endif
#if !defined(CONFIG_ARCH_MPC832X)
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
@@ -434,8 +426,6 @@
gd->arch.tsec1_clk = tsec1_clk;
gd->arch.tsec2_clk = tsec2_clk;
gd->arch.usbdr_clk = usbdr_clk;
-#elif defined(CONFIG_ARCH_MPC8309)
- gd->arch.usbdr_clk = usbdr_clk;
#endif
#if defined(CONFIG_ARCH_MPC834X)
gd->arch.usbmph_clk = usbmph_clk;
@@ -448,9 +438,7 @@
#if !defined(CONFIG_ARCH_MPC832X)
gd->arch.i2c2_clk = i2c2_clk;
#endif
-#if !defined(CONFIG_ARCH_MPC8309)
gd->arch.enc_clk = enc_clk;
-#endif
gd->arch.lbiu_clk = lbiu_clk;
gd->arch.lclk_clk = lclk_clk;
gd->mem_clk = mem_clk;
@@ -524,10 +512,8 @@
printf(" DDR Secondary: %-4s MHz\n",
strmhz(buf, gd->arch.mem_sec_clk));
#endif
-#if !defined(CONFIG_ARCH_MPC8309)
printf(" SEC: %-4s MHz\n",
strmhz(buf, gd->arch.enc_clk));
-#endif
printf(" I2C1: %-4s MHz\n",
strmhz(buf, gd->arch.i2c1_clk));
#if !defined(CONFIG_ARCH_MPC832X)
@@ -546,9 +532,6 @@
strmhz(buf, gd->arch.tsec2_clk));
printf(" USB DR: %-4s MHz\n",
strmhz(buf, gd->arch.usbdr_clk));
-#elif defined(CONFIG_ARCH_MPC8309)
- printf(" USB DR: %-4s MHz\n",
- strmhz(buf, gd->arch.usbdr_clk));
#endif
#if defined(CONFIG_ARCH_MPC834X)
printf(" USB MPH: %-4s MHz\n",
diff --git a/arch/powerpc/dts/km8309-uboot.dtsi b/arch/powerpc/dts/km8309-uboot.dtsi
deleted file mode 100644
index a93bdb2..0000000
--- a/arch/powerpc/dts/km8309-uboot.dtsi
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Hitachi Power Grids 8309 U-Boot specific Device Tree Source parts
- *
- * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
- *
- */
-
-/ {
- cpus {
- u-boot,dm-pre-reloc;
- PowerPC,8309@0 {
- u-boot,dm-pre-reloc;
- };
- };
-
- chosen {
- stdout-path = &serial0;
- };
-};
-
-&qe {
- compatible = "fsl,qe", "simple-bus";
-};
-
-&soc {
- u-boot,dm-pre-reloc;
-};
-
-&serial0 {
- clock-frequency = <132000000>;
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/powerpc/dts/kmtegr1.dts b/arch/powerpc/dts/kmtegr1.dts
deleted file mode 100644
index d40d971..0000000
--- a/arch/powerpc/dts/kmtegr1.dts
+++ /dev/null
@@ -1,392 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Hitachi Power Grids TEGR1 Device Tree Source
- *
- * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
- *
- */
-
-/dts-v1/;
-
-/ {
- model = "KMTEGR1";
- compatible = "hitachi,kmpbec8309";
- #address-cells = <1>;
- #size-cells = <1>;
-
- aliases {
- ethernet0 = &enet_zynq;
- ethernet1 = &enet_piggy2;
- serial0 = &serial0;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- PowerPC,8309@0 {
- device_type = "cpu";
- reg = <0x0>;
- d-cache-line-size = <32>; // 32 bytes
- i-cache-line-size = <32>; // 32 bytes
- d-cache-size = <16384>; // L1, 16K
- i-cache-size = <16384>; // L1, 16K
- timebase-frequency = <66000000>;
- bus-frequency = <264000000>;
- clock-frequency = <264000000>;
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x10000000>;
- };
-
- soc: soc8309@e0000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "soc";
- compatible = "simple-bus";
- ranges = <0x0 0xe0000000 0x00100000>;
- reg = <0xe0000000 0x00000200>;
- bus-frequency = <264000000>;
-
- i2c@3000 {
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <0>;
- compatible = "fsl,mpc8313-i2c","fsl-i2c";
- reg = <0x3000 0x100>;
- interrupts = <14 0x8>;
- interrupt-parent = <&ipic>;
- clock-frequency = <400000>;
-
- mux@70 {
- compatible = "nxp,pca9547";
- reg = <0x70>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- /*
- * Inventory EEPROM of the
- * unit itself
- */
- ivm@50 {
- label = "MAIN_CTRL";
- compatible = "dummy";
- reg = <0x50>;
- };
- };
-
- i2c@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* Temperature sensors */
- temp@48 {
- label = "front";
- compatible = "national,lm75";
- reg = <0x48>;
- };
-
- temp@49 {
- label = "board";
- compatible = "national,lm75";
- reg = <0x49>;
- };
-
- temp@4a {
- label = "power";
- compatible = "national,lm75";
- reg = <0x4a>;
- };
-
- temp@4b {
- label = "bottom";
- compatible = "national,lm75";
- reg = <0x4b>;
- };
- };
-
- i2c@6 {
- reg = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- };
-
- i2c@5 {
- reg = <5>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- };
-
- i2c@7 {
- reg = <7>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- };
-
- i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- };
- };
- };
-
- serial0: serial@4500 {
- cell-index = <0>;
- device_type = "serial";
- compatible = "fsl,ns16550", "ns16550";
- reg = <0x4500 0x100>;
- clock-frequency = <264000000>;
- interrupts = <9 0x8>;
- interrupt-parent = <&ipic>;
- };
-
- dma@82a8 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,mpc8309-dma", "fsl,elo-dma";
- reg = <0x82a8 4>;
- ranges = <0 0x8100 0x1a8>;
- interrupt-parent = <&ipic>;
- interrupts = <71 8>;
- cell-index = <0>;
- dma-channel@0 {
- compatible = "fsl,mpc8309-dma-channel",
- "fsl,elo-dma-channel";
- reg = <0 0x80>;
- interrupt-parent = <&ipic>;
- interrupts = <71 8>;
- };
- dma-channel@80 {
- compatible = "fsl,mpc8309-dma-channel",
- "fsl,elo-dma-channel";
- reg = <0x80 0x80>;
- interrupt-parent = <&ipic>;
- interrupts = <71 8>;
- };
- dma-channel@100 {
- compatible = "fsl,mpc8309-dma-channel",
- "fsl,elo-dma-channel";
- reg = <0x100 0x80>;
- interrupt-parent = <&ipic>;
- interrupts = <71 8>;
- };
- dma-channel@180 {
- compatible = "fsl,mpc8309-dma-channel",
- "fsl,elo-dma-channel";
- reg = <0x180 0x28>;
- interrupt-parent = <&ipic>;
- interrupts = <71 8>;
- };
- };
-
- ipic: pic@700 {
- #address-cells = <0>;
- #interrupt-cells = <2>;
- compatible = "fsl,pq2pro-pic", "fsl,ipic";
- interrupt-controller;
- reg = <0x700 0x100>;
- device_type = "ipic";
- };
-
- gpio1: gpio-controller@c00 {
- #gpio-cells = <2>;
- compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio";
- reg = <0xc00 0x100>;
- interrupts = <75 0x8>;
- interrupt-parent = <&ipic>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio-controller@d00 {
- #gpio-cells = <2>;
- compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio";
- reg = <0xd00 0x100>;
- interrupts = <75 0x8>;
- interrupt-parent = <&ipic>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- spi@7000 {
- cell-index = <0>;
- compatible = "fsl,spi";
- reg = <0x7000 0x1000>;
- interrupts = <16 0x8>;
- interrupt-parent = <&ipic>;
- mode = "cpu";
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* GPIO_15 chipselect for ZYNQ flash */
- gpios = <&gpio1 15 0>;
-
- zynq_flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spansion,m25p80";
- reg = <0>;
- spi-max-frequency = <4000000>;
- m25p,fast-read;
- partition@0 {
- label = "bootloader";
- reg = <0x0 0x01000000>;
- };
- };
- };
- };
-
- qe: qe@e0100000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "qe";
- compatible = "fsl,qe";
- ranges = <0x0 0xe0100000 0x00100000>;
- reg = <0xe0100000 0x480>;
- brg-frequency = <0>;
- bus-frequency = <396000000>;
- fsl,qe-num-snums = <32>;
-
- muram@10000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,qe-muram", "fsl,cpm-muram";
- ranges = <0x0 0x00010000 0x00004000>;
-
- data-only@0 {
- compatible = "fsl,qe-muram-data",
- "fsl,cpm-muram-data";
- reg = <0x0 0x4000>;
- };
- };
-
- /* ZYNQ (UCC1, MDIO 0x10, MII) */
- enet_zynq: ethernet@2000 {
- device_type = "network";
- compatible = "ucc_geth";
- cell-index = <1>;
- reg = <0x2000 0x200>;
- interrupts = <32>;
- interrupt-parent = <&qeic>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- /*id=0, full-dup, 100M, no-pause, no-asym_p*/
- fixed-link = <0 1 100 0 0>;
- rx-clock-name = "clk9";
- tx-clock-name = "clk10";
- phy-connection-type = "mii";
- };
-
- /* Piggy2 (UCC3, MDIO 0x00, RMII) */
- enet_piggy2: ucc@2200 {
- device_type = "network";
- compatible = "ucc_geth";
- cell-index = <3>;
- reg = <0x2200 0x200>;
- interrupts = <34>;
- interrupt-parent = <&qeic>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- rx-clock-name = "none";
- tx-clock-name = "clk12";
- phy-handle = <&phy_piggy2>;
- phy-connection-type = "rmii";
- };
-
- mdio@2320 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x2320 0x38>;
- compatible = "fsl,ucc-mdio";
-
- /* Piggy2 (UCC3, MDIO 0x00, RMII) */
- phy_piggy2: ethernet-phy@0 {
- reg = <0x0>;
- device_type = "ethernet-phy";
- };
-
- /* Explicitly set the tbi-phy to a non-zero address
- * so that it does not conflict with phy_piggy2 that
- * is unfortunately at address 0
- */
- tbi1: tbi-phy@1 {
- reg = <0x1>;
- device_type = "tbi-phy";
- };
- };
-
- qeic: interrupt-controller@80 {
- interrupt-controller;
- compatible = "fsl,qe-ic";
- #address-cells = <0>;
- #interrupt-cells = <1>;
- reg = <0x80 0x80>;
- big-endian;
- interrupts = <32 8 33 8>;
- interrupt-parent = <&ipic>;
- };
- bootcount@0x13ff8 {
- device_type = "bootcount";
- compatible = "u-boot,bootcount";
- reg = <0x13ff8 0x08>;
- };
-
- };
- localbus@e0005000 {
- #address-cells = <2>;
- #size-cells = <1>;
- compatible = "fsl,mpc8309-localbus", "fsl,pq2pro-localbus",
- "simple-bus";
- reg = <0xe0005000 0xd8>;
- ranges = <0 0 0xf0000000 0x04000000
- 1 0 0xe8000000 0x01000000
- 2 0 0xe0000000 0x10000000
- 3 0 0xb0000000 0x10000000>;
-
- flash@0,0 {
- compatible = "cfi-flash";
- reg = <0 0x00000000 0x04000000>;
- bank-width = <2>;
- nornand = "nor";
- #address-cells = <1>;
- #size-cells = <1>;
- use-advanced-sector-protection;
- partition@0 { /* 768KB */
- label = "u-boot";
- reg = <0 0xc0000>;
- };
- partition@c0000 { /* 256KB */
- label = "qe-fw";
- reg = <0xc0000 0x40000>;
- };
- partition@100000 { /* 128KB */
- label = "env";
- reg = <0x100000 0x20000>;
- };
- partition@120000 { /* 128KB */
- label = "envred";
- reg = <0x120000 0x20000>;
- };
- partition@140000 { /* 64256KB */
- label = "ubi0";
- reg = <0x140000 0x3EC0000>;
- };
- };
- };
-};
-
-#include "km8309-uboot.dtsi"
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
index b740675..19c2506 100644
--- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
@@ -8,8 +8,7 @@
*/
#if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308)
#define MPC83XX_GPIO_CTRLRS 1
-#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) || \
- defined(CONFIG_ARCH_MPC8309)
+#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
#define MPC83XX_GPIO_CTRLRS 2
#else
#define MPC83XX_GPIO_CTRLRS 0
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 770adcd..6709e69 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -32,8 +32,6 @@
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
-# elif defined(CONFIG_ARCH_MPC8309)
- u32 usbdr_clk;
# endif
# if defined(CONFIG_ARCH_MPC834X)
u32 usbmph_clk;
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 6d1ddbc..c731347 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -64,14 +64,7 @@
#else
u32 pecr2; /* PCI Express control register 2 */
#endif
-#if defined(CONFIG_ARCH_MPC8309)
- u32 can_dbg_ctrl;
- u32 res9a;
- u32 gpr1;
- u8 res9b[0xAC];
-#else
u8 res9[0xB8];
-#endif
} sysconf83xx_t;
/*
@@ -604,11 +597,7 @@
* On Chip ROM
*/
typedef struct rom83xx {
-#if defined(CONFIG_ARCH_MPC8309)
- u8 mem[0x8000];
-#else
u8 mem[0x10000];
-#endif
} rom83xx_t;
/*
@@ -856,55 +845,6 @@
security83xx_t security;
u8 res8[0xC0000];
u8 qe[0x100000]; /* QE block */
-} immap_t;
-#elif defined(CONFIG_ARCH_MPC8309)
-typedef struct immap {
- sysconf83xx_t sysconf; /* System configuration */
- wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
- rtclk83xx_t rtc; /* Real Time Clock Module Registers */
- rtclk83xx_t pit; /* Periodic Interval Timer */
- gtm83xx_t gtm[2]; /* Global Timers Module */
- ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
- arbiter83xx_t arbiter; /* System Arbiter Registers */
- reset83xx_t reset; /* Reset Module */
- clk83xx_t clk; /* System Clock Module */
- pmc83xx_t pmc; /* Power Management Control Module */
- gpio83xx_t gpio[2]; /* General purpose I/O module */
- u8 res0[0x500]; /* res0 1.25 KBytes added for 8309 */
- qepi83xx_t qepi; /* QE Ports Interrupts Registers */
- qepio83xx_t qepio; /* QE Parallel I/O ports */
- u8 res1[0x800];
- ddr83xx_t ddr; /* DDR Memory Controller Memory */
- fsl_i2c_t i2c[2]; /* I2C Controllers */
- u8 res2[0x1300];
- duart83xx_t duart[2]; /* DUART */
- u8 res3[0x200];
- duart83xx_t duart1[2]; /* DUART */
- u8 res4[0x500];
- fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
- u8 res5[0x1000];
- spi8xxx_t spi; /* Serial Peripheral Interface */
- dma83xx_t dma; /* DMA */
- pciconf83xx_t pci_conf[1]; /* PCI Configuration Registers */
- u8 res7[0x80];
- ios83xx_t ios; /* Sequencer (IOS) */
- pcictrl83xx_t pci_ctrl[1]; /* PCI Control & Status Registers */
- u8 res8[0x13A00];
- u8 can1[0x1000]; /* Flexcan 1 */
- u8 can2[0x1000]; /* Flexcan 2 */
- u8 res9[0x5000];
- usb83xx_t usb;
- u8 res10[0x5000];
- u8 can3[0x1000]; /* Flexcan 3 */
- u8 can4[0x1000]; /* Flexcan 4 */
- u8 res11[0x1000];
- u8 dma1[0x2000]; /* DMA */
- sdhc83xx_t sdhc; /* SDHC Controller */
- u8 res12[0xC1000];
- rom83xx_t rom; /* On Chip ROM */
- u8 res13[0x8000];
- u8 qe[0x100000]; /* QE block */
- u8 res14[0xE00000];/* Added for 8309 */
} immap_t;
#endif
diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h
index f2210a1..83cfe23 100644
--- a/arch/powerpc/include/asm/mpc8xxx_spi.h
+++ b/arch/powerpc/include/asm/mpc8xxx_spi.h
@@ -11,7 +11,6 @@
#include <asm/types.h>
#if defined(CONFIG_ARCH_MPC8308) || \
- defined(CONFIG_ARCH_MPC8309) || \
defined(CONFIG_ARCH_MPC8313) || \
defined(CONFIG_ARCH_MPC834X) || \
defined(CONFIG_ARCH_MPC837X)