Merge tag 'u-boot-imx-20230201' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
For 2023.04
-----------
- several conversion to DM_SERIAL and DM_I2C
- fixes for Toradex boards
- PSCI
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14965
diff --git a/MAINTAINERS b/MAINTAINERS
index 2dd2b46..3e8e193 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -150,6 +150,7 @@
T: git https://source.denx.de/u-boot/custodians/u-boot-amlogic.git
F: arch/arm/mach-meson/
F: arch/arm/include/asm/arch-meson/
+F: cmd/meson/
F: drivers/clk/meson/
F: drivers/serial/serial_meson.c
F: drivers/reset/reset-meson.c
diff --git a/Makefile b/Makefile
index 9c38cc2..7eaf454 100644
--- a/Makefile
+++ b/Makefile
@@ -1,9 +1,9 @@
# SPDX-License-Identifier: GPL-2.0+
VERSION = 2023
-PATCHLEVEL = 01
+PATCHLEVEL = 04
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 48de9ab..d9b719f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -202,7 +202,9 @@
meson-g12b-gtking.dtb \
meson-g12b-gtking-pro.dtb \
meson-g12b-gsking-x.dtb \
+ meson-g12b-odroid-go-ultra.dtb \
meson-g12b-odroid-n2.dtb \
+ meson-g12b-odroid-n2l.dtb \
meson-g12b-odroid-n2-plus.dtb \
meson-sm1-bananapi-m5.dtb \
meson-sm1-khadas-vim3l.dtb \
diff --git a/arch/arm/dts/meson-g12-common.dtsi b/arch/arm/dts/meson-g12-common.dtsi
index 00c6f53..9dbd508 100644
--- a/arch/arm/dts/meson-g12-common.dtsi
+++ b/arch/arm/dts/meson-g12-common.dtsi
@@ -58,7 +58,7 @@
secure-monitor = <&sm>;
};
- gpu_opp_table: gpu-opp-table {
+ gpu_opp_table: opp-table-gpu {
compatible = "operating-points-v2";
opp-124999998 {
@@ -107,6 +107,12 @@
no-map;
};
+ /* 32 MiB reserved for ARM Trusted Firmware (BL32) */
+ secmon_reserved_bl32: secmon@5300000 {
+ reg = <0x0 0x05300000 0x0 0x2000000>;
+ no-map;
+ };
+
linux,cma {
compatible = "shared-dma-pool";
reusable;
@@ -159,61 +165,6 @@
status = "disabled";
};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay = <1000>;
- polling-delay-passive = <100>;
- thermal-sensors = <&cpu_temp>;
-
- trips {
- cpu_passive: cpu-passive {
- temperature = <85000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "passive";
- };
-
- cpu_hot: cpu-hot {
- temperature = <95000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "hot";
- };
-
- cpu_critical: cpu-critical {
- temperature = <110000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "critical";
- };
- };
- };
-
- ddr_thermal: ddr-thermal {
- polling-delay = <1000>;
- polling-delay-passive = <100>;
- thermal-sensors = <&ddr_temp>;
-
- trips {
- ddr_passive: ddr-passive {
- temperature = <85000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "passive";
- };
-
- ddr_critical: ddr-critical {
- temperature = <110000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "critical";
- };
- };
-
- cooling-maps {
- map {
- trip = <&ddr_passive>;
- cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
- };
-
ethmac: ethernet@ff3f0000 {
compatible = "amlogic,meson-g12a-dwmac",
"snps,dwmac-3.70a",
@@ -894,6 +845,22 @@
};
};
+ pwm_f_z_pins: pwm-f-z {
+ mux {
+ groups = "pwm_f_z";
+ function = "pwm_f";
+ bias-disable;
+ };
+ };
+
+ pwm_f_a_pins: pwm-f-a {
+ mux {
+ groups = "pwm_f_a";
+ function = "pwm_f";
+ bias-disable;
+ };
+ };
+
pwm_f_x_pins: pwm-f-x {
mux {
groups = "pwm_f_x";
@@ -1738,6 +1705,12 @@
};
};
+ pmu: pmu@ff638000 {
+ reg = <0x0 0xff638000 0x0 0x100>,
+ <0x0 0xff638c00 0x0 0x100>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>;
+ };
+
aobus: bus@ff800000 {
compatible = "simple-bus";
reg = <0x0 0xff800000 0x0 0x100000>;
@@ -1936,6 +1909,33 @@
};
};
+ uart_ao_b_2_3_pins: uart-ao-b-2-3 {
+ mux {
+ groups = "uart_ao_b_tx_2",
+ "uart_ao_b_rx_3";
+ function = "uart_ao_b";
+ bias-disable;
+ };
+ };
+
+ uart_ao_b_8_9_pins: uart-ao-b-8-9 {
+ mux {
+ groups = "uart_ao_b_tx_8",
+ "uart_ao_b_rx_9";
+ function = "uart_ao_b";
+ bias-disable;
+ };
+ };
+
+ uart_ao_b_cts_rts_pins: uart-ao-b-cts-rts {
+ mux {
+ groups = "uart_ao_b_cts",
+ "uart_ao_b_rts";
+ function = "uart_ao_b";
+ bias-disable;
+ };
+ };
+
pwm_a_e_pins: pwm-a-e {
mux {
groups = "pwm_a_e";
@@ -2415,6 +2415,61 @@
};
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ thermal-sensors = <&cpu_temp>;
+
+ trips {
+ cpu_passive: cpu-passive {
+ temperature = <85000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+
+ cpu_hot: cpu-hot {
+ temperature = <95000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "hot";
+ };
+
+ cpu_critical: cpu-critical {
+ temperature = <110000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ ddr_thermal: ddr-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ thermal-sensors = <&ddr_temp>;
+
+ trips {
+ ddr_passive: ddr-passive {
+ temperature = <85000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+
+ ddr_critical: ddr-critical {
+ temperature = <110000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map {
+ trip = <&ddr_passive>;
+ cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
diff --git a/arch/arm/dts/meson-g12a.dtsi b/arch/arm/dts/meson-g12a.dtsi
index fb0ab27..7677764 100644
--- a/arch/arm/dts/meson-g12a.dtsi
+++ b/arch/arm/dts/meson-g12a.dtsi
@@ -50,6 +50,7 @@
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
@@ -133,3 +134,7 @@
};
};
};
+
+&pmu {
+ compatible = "amlogic,g12a-ddr-pmu";
+};
diff --git a/arch/arm/dts/meson-g12b-odroid-go-ultra-u-boot.dtsi b/arch/arm/dts/meson-g12b-odroid-go-ultra-u-boot.dtsi
new file mode 100644
index 0000000..00852f5
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-odroid-go-ultra-u-boot.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
+ */
+
+#include "meson-g12-common-u-boot.dtsi"
+
+/* RK817/818 BOOST regulator aren't supported yet, so remove phandles from PHY nodes */
+
+&usb2_phy1 {
+ /delete-property/ phy-supply;
+};
+
+&usb3_pcie_phy {
+ /delete-property/ phy-supply;
+};
diff --git a/arch/arm/dts/meson-g12b-odroid-go-ultra.dts b/arch/arm/dts/meson-g12b-odroid-go-ultra.dts
new file mode 100644
index 0000000..1e40709
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-odroid-go-ultra.dts
@@ -0,0 +1,722 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Neil Armstrong <neil.armstrong@linaro.org>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-s922x.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-toacodec.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "hardkernel,odroid-go-ultra", "amlogic,s922x", "amlogic,g12b";
+ model = "Hardkernel ODROID-GO-Ultra";
+
+ aliases {
+ serial0 = &uart_AO;
+ rtc0 = &vrtc;
+ };
+
+ adc-joystick-left {
+ compatible = "adc-joystick";
+ io-channels = <&saradc 2>, <&saradc 3>;
+ poll-interval = <10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ axis@0 {
+ reg = <0>;
+ linux,code = <ABS_Y>;
+ abs-range = <3150 950>;
+ abs-fuzz = <32>;
+ abs-flat = <64>;
+ };
+ axis@1 {
+ reg = <1>;
+ linux,code = <ABS_X>;
+ abs-range = <700 2900>;
+ abs-fuzz = <32>;
+ abs-flat = <64>;
+ };
+ };
+
+ adc-joystick-right {
+ compatible = "adc-joystick";
+ io-channels = <&saradc 0>, <&saradc 1>;
+ poll-interval = <10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ axis@0 {
+ reg = <0>;
+ linux,code = <ABS_RY>;
+ abs-range = <3150 950>;
+ abs-fuzz = <32>;
+ abs-flat = <64>;
+ };
+ axis@1 {
+ reg = <1>;
+ linux,code = <ABS_RX>;
+ abs-range = <800 3000>;
+ abs-fuzz = <32>;
+ abs-flat = <64>;
+ };
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ codec_clk: codec-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <12288000>;
+ clock-output-names = "codec_clk";
+ #clock-cells = <0>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <10>;
+ pinctrl-0 = <&keypad_gpio_pins>;
+ pinctrl-names = "default";
+
+ volume-up-button {
+ label = "VOLUME-UP";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&gpio GPIOX_8 GPIO_ACTIVE_LOW>;
+ };
+ volume-down-button {
+ label = "VOLUME-DOWN";
+ linux,code = <KEY_VOLUMEDOWN>;
+ gpios = <&gpio GPIOX_9 GPIO_ACTIVE_LOW>;
+ };
+ dpad-up-button {
+ label = "DPAD-UP";
+ linux,code = <BTN_DPAD_UP>;
+ gpios = <&gpio GPIOX_0 GPIO_ACTIVE_LOW>;
+ };
+ dpad-down-button {
+ label = "DPAD-DOWN";
+ linux,code = <BTN_DPAD_DOWN>;
+ gpios = <&gpio GPIOX_1 GPIO_ACTIVE_LOW>;
+ };
+ dpad-left-button {
+ label = "DPAD-LEFT";
+ linux,code = <BTN_DPAD_LEFT>;
+ gpios = <&gpio GPIOX_2 GPIO_ACTIVE_LOW>;
+ };
+ dpad-right-button {
+ label = "DPAD-RIGHT";
+ linux,code = <BTN_DPAD_RIGHT>;
+ gpios = <&gpio GPIOX_3 GPIO_ACTIVE_LOW>;
+ };
+ a-button {
+ label = "A";
+ linux,code = <BTN_EAST>;
+ gpios = <&gpio GPIOX_4 GPIO_ACTIVE_LOW>;
+ };
+ b-button {
+ label = "B";
+ linux,code = <BTN_SOUTH>;
+ gpios = <&gpio GPIOX_5 GPIO_ACTIVE_LOW>;
+ };
+ y-button {
+ label = "Y";
+ linux,code = <BTN_WEST>;
+ gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ };
+ x-button {
+ label = "X";
+ linux,code = <BTN_NORTH>;
+ gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
+ };
+ f1-button {
+ label = "F1";
+ linux,code = <BTN_TRIGGER_HAPPY1>;
+ gpios = <&gpio GPIOX_17 GPIO_ACTIVE_LOW>;
+ };
+ f2-button {
+ label = "F2";
+ linux,code = <BTN_TRIGGER_HAPPY2>;
+ gpios = <&gpio GPIOX_10 GPIO_ACTIVE_LOW>;
+ };
+ f3-button {
+ label = "F3";
+ linux,code = <BTN_TRIGGER_HAPPY3>;
+ gpios = <&gpio GPIOX_11 GPIO_ACTIVE_LOW>;
+ };
+ f4-button {
+ label = "F4";
+ linux,code = <BTN_TRIGGER_HAPPY4>;
+ gpios = <&gpio GPIOX_12 GPIO_ACTIVE_LOW>;
+ };
+ f5-button {
+ label = "F5";
+ linux,code = <BTN_TRIGGER_HAPPY5>;
+ gpios = <&gpio GPIOX_13 GPIO_ACTIVE_LOW>;
+ };
+ f6-button {
+ label = "F6";
+ linux,code = <BTN_TRIGGER_HAPPY6>;
+ gpios = <&gpio GPIOX_16 GPIO_ACTIVE_LOW>;
+ };
+ top-left-button {
+ label = "TOP Left";
+ linux,code = <BTN_TL>;
+ gpios = <&gpio GPIOX_14 GPIO_ACTIVE_LOW>;
+ };
+ top-left2-button {
+ label = "TOP Left 2";
+ linux,code = <BTN_TL2>;
+ gpios = <&gpio GPIOX_19 GPIO_ACTIVE_LOW>;
+ };
+ top-right-button {
+ label = "TOP Right";
+ linux,code = <BTN_TR>;
+ gpios = <&gpio GPIOX_15 GPIO_ACTIVE_LOW>;
+ };
+ top-right2-button {
+ label = "TOP Right 2";
+ linux,code = <BTN_TR2>;
+ gpios = <&gpio GPIOX_18 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ vdd_sys: regulator-vdd-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_SYS";
+ regulator-min-microvolt = <3800000>;
+ regulator-max-microvolt = <3800000>;
+ regulator-always-on;
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "Odroid GO Ultra";
+ audio-widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones",
+ "Speaker", "Internal Speakers";
+ audio-aux-devs = <&tdmout_b>, <&tdmin_b>, <&speaker_amp>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT",
+ "TDMIN_B IN 1", "TDM_B Capture",
+ "TDMIN_B IN 4", "TDM_B Loopback",
+ "TODDR_A IN 1", "TDMIN_B OUT",
+ "MICL", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "Speaker Amplifier INL", "HPOL",
+ "Speaker Amplifier INR", "HPOR",
+ "Internal Speakers", "Speaker Amplifier OUTL",
+ "Internal Speakers", "Speaker Amplifier OUTR";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&toddr_a>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&rk817>;
+ };
+ };
+ };
+
+ speaker_amp: speaker-amplifier {
+ compatible = "simple-audio-amplifier";
+ sound-name-prefix = "Speaker Amplifier";
+ VCC-supply = <&hp_5v>;
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu100 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu101 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu102 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu103 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+/* RK817 only supports 12.5mV steps, round up the values */
+&cpu_opp_table_0 {
+ opp-1000000000 {
+ opp-microvolt = <737500>;
+ };
+ opp-1200000000 {
+ opp-microvolt = <737500>;
+ };
+ opp-1398000000 {
+ opp-microvolt = <762500>;
+ };
+ opp-1512000000 {
+ opp-microvolt = <800000>;
+ };
+ opp-1608000000 {
+ opp-microvolt = <837500>;
+ };
+ opp-1704000000 {
+ opp-microvolt = <862500>;
+ };
+ opp-1896000000 {
+ opp-microvolt = <987500>;
+ };
+ opp-1992000000 {
+ opp-microvolt = <1012500>;
+ };
+};
+
+/* RK818 only supports 12.5mV steps, round up the values */
+&cpub_opp_table_1 {
+ opp-1000000000 {
+ opp-microvolt = <775000>;
+ };
+ opp-1200000000 {
+ opp-microvolt = <775000>;
+ };
+ opp-1398000000 {
+ opp-microvolt = <800000>;
+ };
+ opp-1512000000 {
+ opp-microvolt = <825000>;
+ };
+ opp-1608000000 {
+ opp-microvolt = <862500>;
+ };
+ opp-1704000000 {
+ opp-microvolt = <900000>;
+ };
+ opp-1800000000 {
+ opp-microvolt = <987500>;
+ };
+ opp-1908000000 {
+ opp-microvolt = <1025000>;
+ };
+};
+
+&i2c_AO {
+ status = "okay";
+ pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>;
+ pinctrl-names = "default";
+
+ rk818: pmic@1c {
+ compatible = "rockchip,rk818";
+ reg = <0x1c>;
+ interrupt-parent = <&gpio_intc>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_7 */
+
+ vcc1-supply = <&vdd_sys>;
+ vcc2-supply = <&vdd_sys>;
+ vcc3-supply = <&vdd_sys>;
+ vcc4-supply = <&vdd_sys>;
+ vcc6-supply = <&vdd_sys>;
+ vcc7-supply = <&vcc_2v3>;
+ vcc8-supply = <&vcc_2v3>;
+ vcc9-supply = <&vddao_3v3>;
+ boost-supply = <&vdd_sys>;
+ switch-supply = <&vdd_sys>;
+
+ regulators {
+ vddcpu_a: DCDC_REG1 {
+ regulator-name = "vddcpu_a";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <775000>;
+ regulator-max-microvolt = <1025000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <775000>;
+ };
+ };
+
+ vdd_ee: DCDC_REG2 {
+ regulator-name = "vdd_ee";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <875000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <875000>;
+ };
+ };
+
+ vddq_1v1: DCDC_REG3 {
+ regulator-name = "vddq_1v1";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vddao_3v3: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vddao_3v3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ hp_5v: DCDC_BOOST {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "hp_5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vddio_ao1v8: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vddio_ao1v8";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vddq_1v8: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vddq_1v8";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vddio_c: LDO_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vddio_c";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_sd: SWITCH_REG {
+ regulator-name = "vcc_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ OTG_SWITCH {
+ regulator-name = "otg_switch";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c3 {
+ status = "okay";
+ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+ pinctrl-names = "default";
+
+ rk817: pmic@20 {
+ compatible = "rockchip,rk817";
+ reg = <0x20>;
+ interrupt-parent = <&gpio_intc>;
+
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_5 */
+
+ vcc1-supply = <&vdd_sys>;
+ vcc2-supply = <&vdd_sys>;
+ vcc3-supply = <&vdd_sys>;
+ vcc4-supply = <&vdd_sys>;
+ vcc5-supply = <&vdd_sys>;
+ vcc6-supply = <&vdd_sys>;
+ vcc7-supply = <&vdd_sys>;
+ vcc8-supply = <&vdd_sys>;
+ vcc9-supply = <&rk817_boost>;
+
+ #sound-dai-cells = <0>;
+ clocks = <&codec_clk>;
+ clock-names = "mclk";
+
+ #clock-cells = <1>;
+
+ regulators {
+ vddcpu_b: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <737500>;
+ regulator-max-microvolt = <1012500>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vddcpu_b";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc_2v3: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2300000>;
+ regulator-max-microvolt = <2400000>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc_2v3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vdd_codec";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_lcd: LDO_REG8 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_lcd";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk817_boost: BOOST {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5400000>;
+ regulator-name = "rk817_boost";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ usb_host: OTG_SWITCH {
+ regulator-name = "usb_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+ð_phy {
+ status = "disabled";
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&periphs_pinctrl {
+ keypad_gpio_pins: keypad-gpio {
+ mux {
+ groups = "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3",
+ "GPIOX_4", "GPIOX_5", "GPIOX_6", "GPIOX_7",
+ "GPIOX_8", "GPIOX_9", "GPIOX_10", "GPIOX_11",
+ "GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15",
+ "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19";
+ function = "gpio_periphs";
+ bias-pull-up;
+ output-disable;
+ };
+ };
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao1v8>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vddio_c>;
+
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vddio_ao1v8>;
+};
+
+
+&tdmif_b {
+ pinctrl-0 = <&tdm_b_dout0_pins>, <&tdm_b_fs_pins>, <&tdm_b_sclk_pins>, <&tdm_b_din1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD1>,
+ <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD1>;
+ assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_B_SCLK>,
+ <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
+ assigned-clock-rates = <0>, <0>;
+};
+
+&tdmin_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&toddr_a {
+ status = "okay";
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "peripheral";
+};
+
+&usb2_phy0 {
+ status = "okay";
+};
+
+&usb2_phy1 {
+ status = "okay";
+ phy-supply = <&usb_host>;
+};
diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dtsi b/arch/arm/dts/meson-g12b-odroid-n2.dtsi
index 344573e..24d0442 100644
--- a/arch/arm/dts/meson-g12b-odroid-n2.dtsi
+++ b/arch/arm/dts/meson-g12b-odroid-n2.dtsi
@@ -4,20 +4,14 @@
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
-#include <dt-bindings/sound/meson-g12a-toacodec.h>
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+#include "meson-g12b-odroid.dtsi"
/ {
aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
rtc0 = &rtc;
- rtc1 = &vrtc;
};
- dioo2133: audio-amplifier-0 {
+ dio2133: audio-amplifier-0 {
compatible = "simple-audio-amplifier";
enable-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
VCC-supply = <&vcc_5v>;
@@ -25,139 +19,6 @@
status = "okay";
};
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-blue {
- label = "n2:blue";
- gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- tflash_vdd: regulator-tflash_vdd {
- compatible = "regulator-fixed";
-
- regulator-name = "TFLASH_VDD";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
- };
-
- tf_io: gpio-regulator-tf_io {
- compatible = "regulator-gpio";
-
- regulator-name = "TF_IO";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
- gpios-states = <0>;
-
- states = <3300000 0>,
- <1800000 1>;
- };
-
- flash_1v8: regulator-flash_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "FLASH_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- main_12v: regulator-main_12v {
- compatible = "regulator-fixed";
- regulator-name = "12V";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-always-on;
- };
-
- vcc_5v: regulator-vcc_5v {
- compatible = "regulator-fixed";
- regulator-name = "5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- vin-supply = <&main_12v>;
- };
-
- vcc_1v8: regulator-vcc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- /* FIXME: actually controlled by VDDCPU_B_EN */
- };
-
- vddcpu_a: regulator-vddcpu-a {
- /*
- * MP8756GD Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU_A";
- regulator-min-microvolt = <721000>;
- regulator-max-microvolt = <1022000>;
-
- vin-supply = <&main_12v>;
-
- pwms = <&pwm_ab 0 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- vddcpu_b: regulator-vddcpu-b {
- /*
- * Silergy SY8120B1ABC Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU_B";
- regulator-min-microvolt = <721000>;
- regulator-max-microvolt = <1022000>;
-
- vin-supply = <&main_12v>;
-
- pwms = <&pwm_AO_cd 1 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
hub_5v: regulator-hub_5v {
compatible = "regulator-fixed";
regulator-name = "HUB_5V";
@@ -170,54 +31,13 @@
enable-active-high;
};
- usb_pwr_en: regulator-usb_pwr_en {
- compatible = "regulator-fixed";
- regulator-name = "USB_PWR_EN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- /* Connected to the microUSB port power enable */
- gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vddao_1v8: regulator-vddao_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- vddao_3v3: regulator-vddao_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&main_12v>;
- regulator-always-on;
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
sound {
compatible = "amlogic,axg-sound-card";
model = "ODROID-N2";
audio-widgets = "Line", "Lineout";
audio-aux-devs = <&tdmout_b>, <&tdmout_c>, <&tdmin_a>,
<&tdmin_b>, <&tdmin_c>, <&tdmin_lb>,
- <&dioo2133>;
+ <&dio2133>;
audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
"TDMOUT_B IN 1", "FRDDR_B OUT 1",
"TDMOUT_B IN 2", "FRDDR_C OUT 1",
@@ -344,68 +164,13 @@
status = "okay";
};
-&arb {
- status = "okay";
-};
-
-&cec_AO {
- pinctrl-0 = <&cec_ao_a_h_pins>;
- pinctrl-names = "default";
- status = "disabled";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cecb_AO {
- pinctrl-0 = <&cec_ao_b_h_pins>;
+ðmac {
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&clkc_audio {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu1 {
- cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu100 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu101 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu102 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu103 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
+ phy-mode = "rgmii";
+ phy-handle = <&external_phy>;
+ amlogic,tx-delay-ns = <2>;
};
&ext_mdio {
@@ -424,27 +189,6 @@
};
};
-ðmac {
- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
- pinctrl-names = "default";
- status = "okay";
- phy-mode = "rgmii";
- phy-handle = <&external_phy>;
- amlogic,tx-delay-ns = <2>;
-};
-
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
&gpio {
gpio-line-names =
/* GPIOZ */
@@ -505,26 +249,6 @@
};
};
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&vcc_5v>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
- linux,rc-map-name = "rc-odroid";
-};
-
&i2c3 {
status = "okay";
pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
@@ -537,62 +261,11 @@
};
};
-&pwm_ab {
- pinctrl-0 = <&pwm_a_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin0";
+&ir {
status = "okay";
-};
-
-&pwm_AO_cd {
- pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin1";
- status = "okay";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddao_1v8>;
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&tflash_vdd>;
- vqmmc-supply = <&tf_io>;
-
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&flash_1v8>;
+ linux,rc-map-name = "rc-odroid";
};
/*
@@ -607,7 +280,7 @@
pinctrl-0 = <&nor_pins>;
pinctrl-names = "default";
- mx25u64: spi-flash@0 {
+ mx25u64: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mxicy,mx25u6435f", "jedec,spi-nor";
@@ -616,73 +289,14 @@
};
};
-&tdmif_b {
- status = "okay";
-};
-
-&tdmif_c {
- status = "okay";
-};
-
-&tdmin_a {
- status = "okay";
-};
-
-&tdmin_b {
- status = "okay";
-};
-
-&tdmin_c {
- status = "okay";
-};
-
-&tdmin_lb {
- status = "okay";
-};
-
-&tdmout_b {
- status = "okay";
-};
-
-&tdmout_c {
- status = "okay";
-};
-
&toacodec {
status = "okay";
-};
-
-&tohdmitx {
- status = "okay";
-};
-
-&toddr_a {
- status = "okay";
-};
-
-&toddr_b {
- status = "okay";
-};
-
-&toddr_c {
- status = "okay";
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
};
&usb {
- status = "okay";
vbus-supply = <&usb_pwr_en>;
};
-&usb2_phy0 {
- phy-supply = <&vcc_5v>;
-};
-
&usb2_phy1 {
/* Enable the hub which is connected to this port */
phy-supply = <&hub_5v>;
diff --git a/arch/arm/dts/meson-g12b-odroid-n2l-u-boot.dtsi b/arch/arm/dts/meson-g12b-odroid-n2l-u-boot.dtsi
new file mode 100644
index 0000000..236f246
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-odroid-n2l-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-g12-common-u-boot.dtsi"
diff --git a/arch/arm/dts/meson-g12b-odroid-n2l.dts b/arch/arm/dts/meson-g12b-odroid-n2l.dts
new file mode 100644
index 0000000..70919f4
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-odroid-n2l.dts
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Dongjin Kim <tobetter@gmail.com>
+ */
+
+/dts-v1/;
+
+/* The Amlogic S922X Rev. C supports the same OPPs as the A311D variant */
+#include "meson-g12b-a311d.dtsi"
+#include "meson-g12b-odroid.dtsi"
+
+/ {
+ compatible = "hardkernel,odroid-n2l", "amlogic,s922x", "amlogic,g12b";
+ model = "Hardkernel ODROID-N2L";
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "ODROID-N2L";
+ audio-aux-devs = <&tdmout_b>, <&tdmin_a>, <&tdmin_b>,
+ <&tdmin_c>, <&tdmin_lb>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT",
+ "TDMIN_A IN 4", "TDM_B Loopback",
+ "TDMIN_B IN 4", "TDM_B Loopback",
+ "TDMIN_C IN 4", "TDM_B Loopback",
+ "TDMIN_LB IN 1", "TDM_B Loopback",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT",
+ "TODDR_A IN 1", "TDMIN_B OUT",
+ "TODDR_B IN 1", "TDMIN_B OUT",
+ "TODDR_C IN 1", "TDMIN_B OUT",
+ "TODDR_A IN 2", "TDMIN_C OUT",
+ "TODDR_B IN 2", "TDMIN_C OUT",
+ "TODDR_C IN 2", "TDMIN_C OUT",
+ "TODDR_A IN 6", "TDMIN_LB OUT",
+ "TODDR_B IN 6", "TDMIN_LB OUT",
+ "TODDR_C IN 6", "TDMIN_LB OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ dai-link-3 {
+ sound-dai = <&toddr_a>;
+ };
+
+ dai-link-4 {
+ sound-dai = <&toddr_b>;
+ };
+
+ dai-link-5 {
+ sound-dai = <&toddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-6 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-7 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+ð_phy {
+ status = "disabled";
+};
+
+&vddcpu_a {
+ regulator-min-microvolt = <680000>;
+ regulator-max-microvolt = <1040000>;
+
+ pwms = <&pwm_ab 0 1500 0>;
+};
+
+&vddcpu_b {
+ regulator-min-microvolt = <680000>;
+ regulator-max-microvolt = <1040000>;
+
+ pwms = <&pwm_AO_cd 1 1500 0>;
+};
+
+&usb2_phy0 {
+ phy-supply = <&usb_pwr_en>;
+};
+
+&usb2_phy1 {
+ phy-supply = <&usb_pwr_en>;
+};
diff --git a/arch/arm/dts/meson-g12b-odroid.dtsi b/arch/arm/dts/meson-g12b-odroid.dtsi
new file mode 100644
index 0000000..9e12a34
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-odroid.dtsi
@@ -0,0 +1,445 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-toacodec.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ rtc1 = &vrtc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ fan: gpio-fan {
+ compatible = "gpio-fan";
+ gpios = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_HIGH>;
+ /* Using Dummy Speed */
+ gpio-fan,speed-map = <0 0>, <1 1>;
+ #cooling-cells = <2>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-blue {
+ label = "n2:blue";
+ gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ tflash_vdd: regulator-tflash_vdd {
+ compatible = "regulator-fixed";
+
+ regulator-name = "TFLASH_VDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ tf_io: gpio-regulator-tf_io {
+ compatible = "regulator-gpio";
+
+ regulator-name = "TF_IO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+
+ states = <3300000 0>,
+ <1800000 1>;
+ };
+
+ flash_1v8: regulator-flash_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "FLASH_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ main_12v: regulator-main_12v {
+ compatible = "regulator-fixed";
+ regulator-name = "12V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ };
+
+ usb_pwr_en: regulator-usb_pwr_en {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_PWR_EN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+
+ /* Connected to the microUSB port power enable */
+ gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcc_5v: regulator-vcc_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ vin-supply = <&main_12v>;
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ };
+
+ vcc_1v8: regulator-vcc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ /* FIXME: actually controlled by VDDCPU_B_EN */
+ };
+
+ vddcpu_a: regulator-vddcpu-a {
+ /*
+ * MP8756GD Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU_A";
+ regulator-min-microvolt = <721000>;
+ regulator-max-microvolt = <1022000>;
+
+ pwm-supply = <&main_12v>;
+
+ pwms = <&pwm_ab 0 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vddcpu_b: regulator-vddcpu-b {
+ /*
+ * Silergy SY8120B1ABC Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU_B";
+ regulator-min-microvolt = <721000>;
+ regulator-max-microvolt = <1022000>;
+
+ pwm-supply = <&main_12v>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vddao_1v8: regulator-vddao_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&main_12v>;
+ regulator-always-on;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&cec_AO {
+ pinctrl-0 = <&cec_ao_a_h_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+ pinctrl-0 = <&cec_ao_b_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu100 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu101 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu102 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu103 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu_thermal {
+ trips {
+ cpu_active: cpu-active {
+ temperature = <60000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map {
+ trip = <&cpu_active>;
+ cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&ddr_thermal {
+ trips {
+ ddr_active: ddr-active {
+ temperature = <60000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map {
+ trip = <&ddr_active>;
+ cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&vcc_5v>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&pwm_ab {
+ pinctrl-0 = <&pwm_a_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin0";
+ status = "okay";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&tflash_vdd>;
+ vqmmc-supply = <&tf_io>;
+
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&flash_1v8>;
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmif_c {
+ status = "okay";
+};
+
+&tdmin_a {
+ status = "okay";
+};
+
+&tdmin_b {
+ status = "okay";
+};
+
+&tdmin_c {
+ status = "okay";
+};
+
+&tdmin_lb {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tdmout_c {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+&toddr_a {
+ status = "okay";
+};
+
+&toddr_b {
+ status = "okay";
+};
+
+&toddr_c {
+ status = "okay";
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb2_phy0 {
+ phy-supply = <&vcc_5v>;
+};
diff --git a/arch/arm/dts/meson-g12b.dtsi b/arch/arm/dts/meson-g12b.dtsi
index ee8fcae..75ff00f 100644
--- a/arch/arm/dts/meson-g12b.dtsi
+++ b/arch/arm/dts/meson-g12b.dtsi
@@ -105,6 +105,7 @@
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
};
@@ -139,3 +140,7 @@
&mali {
dma-coherent;
};
+
+&pmu {
+ compatible = "amlogic,g12b-ddr-pmu";
+};
diff --git a/arch/arm/dts/meson-sm1.dtsi b/arch/arm/dts/meson-sm1.dtsi
index 3d8b1f4..56ca0ba 100644
--- a/arch/arm/dts/meson-sm1.dtsi
+++ b/arch/arm/dts/meson-sm1.dtsi
@@ -88,6 +88,7 @@
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
@@ -95,26 +96,6 @@
compatible = "operating-points-v2";
opp-shared;
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- opp-microvolt = <730000>;
- };
-
- opp-250000000 {
- opp-hz = /bits/ 64 <250000000>;
- opp-microvolt = <730000>;
- };
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <730000>;
- };
-
- opp-667000000 {
- opp-hz = /bits/ 64 <666666666>;
- opp-microvolt = <750000>;
- };
-
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <770000>;
@@ -356,6 +337,33 @@
status = "disabled";
};
+ spdifin: audio-controller@400 {
+ compatible = "amlogic,g12a-spdifin",
+ "amlogic,axg-spdifin";
+ reg = <0x0 0x400 0x0 0x30>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SPDIFIN";
+ interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
+ <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
+ clock-names = "pclk", "refclk";
+ resets = <&clkc_audio AUD_RESET_SPDIFIN>;
+ status = "disabled";
+ };
+
+ spdifout_a: audio-controller@480 {
+ compatible = "amlogic,g12a-spdifout",
+ "amlogic,axg-spdifout";
+ reg = <0x0 0x480 0x0 0x50>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SPDIFOUT_A";
+ clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
+ <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
+ clock-names = "pclk", "mclk";
+ resets = <&clkc_audio AUD_RESET_SPDIFOUT>;
+ status = "disabled";
+ };
+
tdmout_a: audio-controller@500 {
compatible = "amlogic,sm1-tdmout";
reg = <0x0 0x500 0x0 0x40>;
@@ -513,6 +521,10 @@
power-domains = <&pwrc PWRC_SM1_PCIE_ID>;
};
+&pmu {
+ compatible = "amlogic,sm1-ddr-pmu";
+};
+
&pwrc {
compatible = "amlogic,meson-sm1-pwrc";
};
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi
index f147dc2..6c662a7 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -11,7 +11,7 @@
};
};
-#ifdef CONFIG_TPL
+#ifdef CONFIG_SPL
&binman {
simple-bin {
filename = "u-boot-rockchip.bin";
diff --git a/arch/arm/include/asm/arch-meson/sm.h b/arch/arm/include/asm/arch-meson/sm.h
index f3ae46a..53b7517 100644
--- a/arch/arm/include/asm/arch-meson/sm.h
+++ b/arch/arm/include/asm/arch-meson/sm.h
@@ -6,10 +6,35 @@
#ifndef __MESON_SM_H__
#define __MESON_SM_H__
+/**
+ * meson_sm_read_efuse - read efuse memory into buffer
+ *
+ * @offset: offset from the start efuse memory
+ * @buffer: pointer to buffer
+ * @size: number of bytes to read
+ * @return: number of bytes read
+ */
ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size);
+/**
+ * meson_sm_write_efuse - write into efuse memory from buffer
+ *
+ * @offset: offset from the start efuse memory
+ * @buffer: pointer to buffer
+ * @size: number of bytes to write
+ * @return: number of bytes written
+ */
+ssize_t meson_sm_write_efuse(uintptr_t offset, void *buffer, size_t size);
+
#define SM_SERIAL_SIZE 12
+/**
+ * meson_sm_get_serial - read chip unique id into buffer
+ *
+ * @buffer: pointer to buffer
+ * @size: buffer size.
+ * @return: zero on success or -errno on failure
+ */
int meson_sm_get_serial(void *buffer, size_t size);
enum {
@@ -28,6 +53,9 @@
REBOOT_REASON_WATCHDOG_REBOOT = 13,
};
+/**
+ * meson_sm_get_reboot_reason - get reboot reason
+ */
int meson_sm_get_reboot_reason(void);
#endif /* __MESON_SM_H__ */
diff --git a/arch/arm/mach-meson/board-axg.c b/arch/arm/mach-meson/board-axg.c
index 236ec81..fdf1875 100644
--- a/arch/arm/mach-meson/board-axg.c
+++ b/arch/arm/mach-meson/board-axg.c
@@ -15,12 +15,6 @@
#include <asm/io.h>
#include <asm/armv8/mmu.h>
#include <linux/sizes.h>
-#include <usb.h>
-#include <linux/usb/otg.h>
-#include <asm/arch/usb-gx.h>
-#include <usb/dwc2_udc.h>
-#include <clk.h>
-#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -90,126 +84,3 @@
};
struct mm_region *mem_map = axg_mem_map;
-
-#if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \
- CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
-static struct dwc2_plat_otg_data meson_gx_dwc2_data;
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- struct fdtdec_phandle_args args;
- const void *blob = gd->fdt_blob;
- int node, dwc2_node;
- struct udevice *dev, *clk_dev;
- struct clk clk;
- int ret;
-
- /* find the usb glue node */
- node = fdt_node_offset_by_compatible(blob, -1,
- "amlogic,meson-axg-usb-ctrl");
- if (node < 0) {
- debug("Not found usb-control node\n");
- return -ENODEV;
- }
-
- if (!fdtdec_get_is_enabled(blob, node)) {
- debug("usb is disabled in the device tree\n");
- return -ENODEV;
- }
-
- ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
- if (ret) {
- debug("Not found usb-control device\n");
- return ret;
- }
-
- /* find the dwc2 node */
- dwc2_node = fdt_node_offset_by_compatible(blob, node,
- "amlogic,meson-g12a-usb");
- if (dwc2_node < 0) {
- debug("Not found dwc2 node\n");
- return -ENODEV;
- }
-
- if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
- debug("dwc2 is disabled in the device tree\n");
- return -ENODEV;
- }
-
- meson_gx_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
- if (meson_gx_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
- debug("usbotg: can't get base address\n");
- return -ENODATA;
- }
-
- /* Enable clock */
- ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
- "#clock-cells", 0, 0, &args);
- if (ret) {
- debug("usbotg has no clocks defined in the device tree\n");
- return ret;
- }
-
- ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
- if (ret)
- return ret;
-
- if (args.args_count != 1) {
- debug("Can't find clock ID in the device tree\n");
- return -ENODATA;
- }
-
- clk.dev = clk_dev;
- clk.id = args.args[0];
-
- ret = clk_enable(&clk);
- if (ret) {
- debug("Failed to enable usbotg clock\n");
- return ret;
- }
-
- meson_gx_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
- "g-rx-fifo-size", 0);
- meson_gx_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
- "g-np-tx-fifo-size", 0);
- meson_gx_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
- "g-tx-fifo-size", 0);
-
- /* Switch to peripheral mode */
- ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_PERIPHERAL);
- if (ret)
- return ret;
-
- return dwc2_udc_probe(&meson_gx_dwc2_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- const void *blob = gd->fdt_blob;
- struct udevice *dev;
- int node;
- int ret;
-
- /* find the usb glue node */
- node = fdt_node_offset_by_compatible(blob, -1,
- "amlogic,meson-axg-usb-ctrl");
- if (node < 0) {
- debug("Not found usb-control node\n");
- return -ENODEV;
- }
-
- if (!fdtdec_get_is_enabled(blob, node))
- return -ENODEV;
-
- ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
- if (ret)
- return ret;
-
- /* Switch to OTG mode */
- ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_HOST);
- if (ret)
- return ret;
-
- return 0;
-}
-#endif
diff --git a/arch/arm/mach-meson/board-g12a.c b/arch/arm/mach-meson/board-g12a.c
index 2e59eee..d5a830f 100644
--- a/arch/arm/mach-meson/board-g12a.c
+++ b/arch/arm/mach-meson/board-g12a.c
@@ -17,12 +17,6 @@
#include <asm/io.h>
#include <asm/armv8/mmu.h>
#include <linux/sizes.h>
-#include <usb.h>
-#include <linux/usb/otg.h>
-#include <asm/arch/usb.h>
-#include <usb/dwc2_udc.h>
-#include <phy.h>
-#include <clk.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -96,124 +90,3 @@
};
struct mm_region *mem_map = g12a_mem_map;
-
-#if CONFIG_IS_ENABLED(USB_DWC3_MESON_G12A) && \
- CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
-static struct dwc2_plat_otg_data meson_g12a_dwc2_data;
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- struct fdtdec_phandle_args args;
- const void *blob = gd->fdt_blob;
- int node, dwc2_node;
- struct udevice *dev, *clk_dev;
- struct clk clk;
- int ret;
-
- /* find the usb glue node */
- node = fdt_node_offset_by_compatible(blob, -1,
- "amlogic,meson-g12a-usb-ctrl");
- if (node < 0) {
- debug("Not found usb-control node\n");
- return -ENODEV;
- }
-
- if (!fdtdec_get_is_enabled(blob, node)) {
- debug("usb is disabled in the device tree\n");
- return -ENODEV;
- }
-
- ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
- if (ret) {
- debug("Not found usb-control device\n");
- return ret;
- }
-
- /* find the dwc2 node */
- dwc2_node = fdt_node_offset_by_compatible(blob, node,
- "amlogic,meson-g12a-usb");
- if (dwc2_node < 0) {
- debug("Not found dwc2 node\n");
- return -ENODEV;
- }
-
- if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
- debug("dwc2 is disabled in the device tree\n");
- return -ENODEV;
- }
-
- meson_g12a_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
- if (meson_g12a_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
- debug("usbotg: can't get base address\n");
- return -ENODATA;
- }
-
- /* Enable clock */
- ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
- "#clock-cells", 0, 0, &args);
- if (ret) {
- debug("usbotg has no clocks defined in the device tree\n");
- return ret;
- }
-
- ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
- if (ret)
- return ret;
-
- if (args.args_count != 1) {
- debug("Can't find clock ID in the device tree\n");
- return -ENODATA;
- }
-
- clk.dev = clk_dev;
- clk.id = args.args[0];
-
- ret = clk_enable(&clk);
- if (ret) {
- debug("Failed to enable usbotg clock\n");
- return ret;
- }
-
- meson_g12a_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
- "g-rx-fifo-size", 0);
- meson_g12a_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
- "g-np-tx-fifo-size", 0);
- meson_g12a_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
- "g-tx-fifo-size", 0);
-
- /* Switch to peripheral mode */
- ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_PERIPHERAL);
- if (ret)
- return ret;
-
- return dwc2_udc_probe(&meson_g12a_dwc2_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- const void *blob = gd->fdt_blob;
- struct udevice *dev;
- int node;
- int ret;
-
- /* find the usb glue node */
- node = fdt_node_offset_by_compatible(blob, -1,
- "amlogic,meson-g12a-usb-ctrl");
- if (node < 0)
- return -ENODEV;
-
- if (!fdtdec_get_is_enabled(blob, node))
- return -ENODEV;
-
- ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
- if (ret)
- return ret;
-
- /* Switch to OTG mode */
- ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_HOST);
- if (ret)
- return ret;
-
- return 0;
-}
-#endif
diff --git a/arch/arm/mach-meson/board-gx.c b/arch/arm/mach-meson/board-gx.c
index 01fafd8..f28f84d 100644
--- a/arch/arm/mach-meson/board-gx.c
+++ b/arch/arm/mach-meson/board-gx.c
@@ -16,12 +16,6 @@
#include <asm/io.h>
#include <asm/armv8/mmu.h>
#include <linux/sizes.h>
-#include <usb.h>
-#include <linux/usb/otg.h>
-#include <asm/arch/usb-gx.h>
-#include <usb/dwc2_udc.h>
-#include <clk.h>
-#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -108,134 +102,3 @@
};
struct mm_region *mem_map = gx_mem_map;
-
-#if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \
- CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
-static struct dwc2_plat_otg_data meson_gx_dwc2_data;
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- struct fdtdec_phandle_args args;
- const void *blob = gd->fdt_blob;
- int node, dwc2_node;
- struct udevice *dev, *clk_dev;
- struct clk clk;
- int ret;
-
- /* find the usb glue node */
- node = fdt_node_offset_by_compatible(blob, -1,
- "amlogic,meson-gxl-usb-ctrl");
- if (node < 0) {
- node = fdt_node_offset_by_compatible(blob, -1,
- "amlogic,meson-gxm-usb-ctrl");
- if (node < 0) {
- debug("Not found usb-control node\n");
- return -ENODEV;
- }
- }
-
- if (!fdtdec_get_is_enabled(blob, node)) {
- debug("usb is disabled in the device tree\n");
- return -ENODEV;
- }
-
- ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
- if (ret) {
- debug("Not found usb-control device\n");
- return ret;
- }
-
- /* find the dwc2 node */
- dwc2_node = fdt_node_offset_by_compatible(blob, node,
- "amlogic,meson-g12a-usb");
- if (dwc2_node < 0) {
- debug("Not found dwc2 node\n");
- return -ENODEV;
- }
-
- if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
- debug("dwc2 is disabled in the device tree\n");
- return -ENODEV;
- }
-
- meson_gx_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
- if (meson_gx_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
- debug("usbotg: can't get base address\n");
- return -ENODATA;
- }
-
- /* Enable clock */
- ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
- "#clock-cells", 0, 0, &args);
- if (ret) {
- debug("usbotg has no clocks defined in the device tree\n");
- return ret;
- }
-
- ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
- if (ret)
- return ret;
-
- if (args.args_count != 1) {
- debug("Can't find clock ID in the device tree\n");
- return -ENODATA;
- }
-
- clk.dev = clk_dev;
- clk.id = args.args[0];
-
- ret = clk_enable(&clk);
- if (ret) {
- debug("Failed to enable usbotg clock\n");
- return ret;
- }
-
- meson_gx_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
- "g-rx-fifo-size", 0);
- meson_gx_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
- "g-np-tx-fifo-size", 0);
- meson_gx_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
- "g-tx-fifo-size", 0);
-
- /* Switch to peripheral mode */
- ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_PERIPHERAL);
- if (ret)
- return ret;
-
- return dwc2_udc_probe(&meson_gx_dwc2_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- const void *blob = gd->fdt_blob;
- struct udevice *dev;
- int node;
- int ret;
-
- /* find the usb glue node */
- node = fdt_node_offset_by_compatible(blob, -1,
- "amlogic,meson-gxl-usb-ctrl");
- if (node < 0) {
- node = fdt_node_offset_by_compatible(blob, -1,
- "amlogic,meson-gxm-usb-ctrl");
- if (node < 0) {
- debug("Not found usb-control node\n");
- return -ENODEV;
- }
- }
-
- if (!fdtdec_get_is_enabled(blob, node))
- return -ENODEV;
-
- ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
- if (ret)
- return ret;
-
- /* Switch to OTG mode */
- ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_HOST);
- if (ret)
- return ret;
-
- return 0;
-}
-#endif
diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c
index d6eb910..f2ca7e7 100644
--- a/arch/arm/mach-meson/sm.c
+++ b/arch/arm/mach-meson/sm.c
@@ -6,8 +6,6 @@
*/
#include <common.h>
-#include <command.h>
-#include <env.h>
#include <log.h>
#include <asm/arch/sm.h>
#include <asm/cache.h>
@@ -139,145 +137,3 @@
/* The SMC call is not used, we directly use AO_SEC_SD_CFG15 */
return FIELD_GET(REBOOT_REASON_MASK, reason);
}
-
-static int do_sm_serial(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- ulong address;
- int ret;
-
- if (argc < 2)
- return CMD_RET_USAGE;
-
- address = simple_strtoul(argv[1], NULL, 0);
-
- ret = meson_sm_get_serial((void *)address, SM_CHIP_ID_SIZE);
- if (ret)
- return CMD_RET_FAILURE;
-
- return CMD_RET_SUCCESS;
-}
-
-#define MAX_REBOOT_REASONS 14
-
-static const char *reboot_reasons[MAX_REBOOT_REASONS] = {
- [REBOOT_REASON_COLD] = "cold_boot",
- [REBOOT_REASON_NORMAL] = "normal",
- [REBOOT_REASON_RECOVERY] = "recovery",
- [REBOOT_REASON_UPDATE] = "update",
- [REBOOT_REASON_FASTBOOT] = "fastboot",
- [REBOOT_REASON_SUSPEND_OFF] = "suspend_off",
- [REBOOT_REASON_HIBERNATE] = "hibernate",
- [REBOOT_REASON_BOOTLOADER] = "bootloader",
- [REBOOT_REASON_SHUTDOWN_REBOOT] = "shutdown_reboot",
- [REBOOT_REASON_RPMBP] = "rpmbp",
- [REBOOT_REASON_CRASH_DUMP] = "crash_dump",
- [REBOOT_REASON_KERNEL_PANIC] = "kernel_panic",
- [REBOOT_REASON_WATCHDOG_REBOOT] = "watchdog_reboot",
-};
-
-static int do_sm_reboot_reason(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- const char *reason_str;
- char *destarg = NULL;
- int reason;
-
- if (argc > 1)
- destarg = argv[1];
-
- reason = meson_sm_get_reboot_reason();
- if (reason < 0)
- return CMD_RET_FAILURE;
-
- if (reason >= MAX_REBOOT_REASONS ||
- !reboot_reasons[reason])
- reason_str = "unknown";
- else
- reason_str = reboot_reasons[reason];
-
- if (destarg)
- env_set(destarg, reason_str);
- else
- printf("reboot reason: %s (%x)\n", reason_str, reason);
-
- return CMD_RET_SUCCESS;
-}
-
-static int do_efuse_read(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- ulong address, offset, size;
- int ret;
-
- if (argc < 4)
- return CMD_RET_USAGE;
-
- offset = simple_strtoul(argv[1], NULL, 0);
- size = simple_strtoul(argv[2], NULL, 0);
-
- address = simple_strtoul(argv[3], NULL, 0);
-
- ret = meson_sm_read_efuse(offset, (void *)address, size);
- if (ret != size)
- return CMD_RET_FAILURE;
-
- return CMD_RET_SUCCESS;
-}
-
-static int do_efuse_write(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- ulong address, offset, size;
- int ret;
-
- if (argc < 4)
- return CMD_RET_USAGE;
-
- offset = simple_strtoul(argv[1], NULL, 0);
- size = simple_strtoul(argv[2], NULL, 0);
-
- address = simple_strtoul(argv[3], NULL, 0);
-
- ret = meson_sm_write_efuse(offset, (void *)address, size);
- if (ret != size)
- return CMD_RET_FAILURE;
-
- return CMD_RET_SUCCESS;
-}
-
-static struct cmd_tbl cmd_sm_sub[] = {
- U_BOOT_CMD_MKENT(serial, 2, 1, do_sm_serial, "", ""),
- U_BOOT_CMD_MKENT(reboot_reason, 1, 1, do_sm_reboot_reason, "", ""),
- U_BOOT_CMD_MKENT(efuseread, 4, 1, do_efuse_read, "", ""),
- U_BOOT_CMD_MKENT(efusewrite, 4, 0, do_efuse_write, "", ""),
-};
-
-static int do_sm(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- struct cmd_tbl *c;
-
- if (argc < 2)
- return CMD_RET_USAGE;
-
- /* Strip off leading 'sm' command argument */
- argc--;
- argv++;
-
- c = find_cmd_tbl(argv[0], &cmd_sm_sub[0], ARRAY_SIZE(cmd_sm_sub));
-
- if (c)
- return c->cmd(cmdtp, flag, argc, argv);
- else
- return CMD_RET_USAGE;
-}
-
-U_BOOT_CMD(
- sm, 5, 0, do_sm,
- "Secure Monitor Control",
- "serial <address> - read chip unique id to memory address\n"
- "sm reboot_reason [name] - get reboot reason and store to to environment\n"
- "sm efuseread <offset> <size> <address> - read efuse to memory address\n"
- "sm efusewrite <offset> <size> <address> - write into efuse from memory address"
-);
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 4fe2c75..dc0446e 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -2733,4 +2733,11 @@
and is indicated using the index from enum bus_mode in
include/mmc.h. A speed mode can be set only if it has already
been enabled in the device tree.
+
+config CMD_MESON
+ bool "Amlogic Meson commands"
+ depends on ARCH_MESON
+ default y
+ help
+ Enable useful commands for the Meson Soc family developed by Amlogic Inc.
endmenu
diff --git a/cmd/Makefile b/cmd/Makefile
index 0b6a96c..7b6ff73 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -226,6 +226,9 @@
obj-$(CONFIG_SANDBOX) += sandbox/
obj-$(CONFIG_X86) += x86/
+# Meson
+obj-$(CONFIG_CMD_MESON) += meson/
+
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
endif # !CONFIG_SPL_BUILD
diff --git a/cmd/meson/Makefile b/cmd/meson/Makefile
new file mode 100644
index 0000000..ee26c17
--- /dev/null
+++ b/cmd/meson/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2022, SberDevices. All rights reserved.
+
+obj-y += sm.o
diff --git a/cmd/meson/sm.c b/cmd/meson/sm.c
new file mode 100644
index 0000000..de9a242
--- /dev/null
+++ b/cmd/meson/sm.c
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2016 Beniamino Galvani
+ *
+ * Author: Beniamino Galvani <b.galvani@gmail.com>
+ * Author: Vyacheslav Bocharov <adeep@lexina.in>
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Author: Alexey Romanov <avromanov@sberdevices.ru>
+ */
+
+#include <command.h>
+#include <common.h>
+#include <env.h>
+#include <asm/arch/sm.h>
+#include <stdlib.h>
+#include <display_options.h>
+
+static int do_sm_serial(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong address;
+ int ret;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ address = simple_strtoul(argv[1], NULL, 0);
+
+ ret = meson_sm_get_serial((void *)address, SM_SERIAL_SIZE);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+#define MAX_REBOOT_REASONS 14
+
+static const char *reboot_reasons[MAX_REBOOT_REASONS] = {
+ [REBOOT_REASON_COLD] = "cold_boot",
+ [REBOOT_REASON_NORMAL] = "normal",
+ [REBOOT_REASON_RECOVERY] = "recovery",
+ [REBOOT_REASON_UPDATE] = "update",
+ [REBOOT_REASON_FASTBOOT] = "fastboot",
+ [REBOOT_REASON_SUSPEND_OFF] = "suspend_off",
+ [REBOOT_REASON_HIBERNATE] = "hibernate",
+ [REBOOT_REASON_BOOTLOADER] = "bootloader",
+ [REBOOT_REASON_SHUTDOWN_REBOOT] = "shutdown_reboot",
+ [REBOOT_REASON_RPMBP] = "rpmbp",
+ [REBOOT_REASON_CRASH_DUMP] = "crash_dump",
+ [REBOOT_REASON_KERNEL_PANIC] = "kernel_panic",
+ [REBOOT_REASON_WATCHDOG_REBOOT] = "watchdog_reboot",
+};
+
+static int do_sm_reboot_reason(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ const char *reason_str;
+ char *destarg = NULL;
+ int reason;
+
+ if (argc > 1)
+ destarg = argv[1];
+
+ reason = meson_sm_get_reboot_reason();
+ if (reason < 0)
+ return CMD_RET_FAILURE;
+
+ if (reason >= MAX_REBOOT_REASONS ||
+ !reboot_reasons[reason])
+ reason_str = "unknown";
+ else
+ reason_str = reboot_reasons[reason];
+
+ if (destarg)
+ env_set(destarg, reason_str);
+ else
+ printf("reboot reason: %s (%x)\n", reason_str, reason);
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_efuse_read(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong address, offset, size;
+ int ret;
+
+ if (argc < 4)
+ return CMD_RET_USAGE;
+
+ offset = simple_strtoul(argv[1], NULL, 0);
+ size = simple_strtoul(argv[2], NULL, 0);
+
+ address = simple_strtoul(argv[3], NULL, 0);
+
+ ret = meson_sm_read_efuse(offset, (void *)address, size);
+ if (ret != size)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_efuse_write(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong address, offset, size;
+ int ret;
+
+ if (argc < 4)
+ return CMD_RET_USAGE;
+
+ offset = simple_strtoul(argv[1], NULL, 0);
+ size = simple_strtoul(argv[2], NULL, 0);
+
+ address = simple_strtoul(argv[3], NULL, 0);
+
+ ret = meson_sm_write_efuse(offset, (void *)address, size);
+ if (ret != size)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_efuse_dump(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong offset, size;
+ u8 *buffer;
+ int ret;
+
+ if (argc != 3)
+ return CMD_RET_USAGE;
+
+ offset = simple_strtoul(argv[1], NULL, 0);
+ size = simple_strtoul(argv[2], NULL, 0);
+ buffer = malloc(size);
+ if (!buffer) {
+ pr_err("Failed to allocate %lu bytes\n", size);
+ return CMD_RET_FAILURE;
+ }
+
+ ret = meson_sm_read_efuse(offset, (void *)buffer, size);
+ if (ret != size) {
+ ret = CMD_RET_FAILURE;
+ goto free_buffer;
+ }
+
+ print_buffer(0, buffer, 1, size, 0);
+
+free_buffer:
+ free(buffer);
+ return ret;
+}
+
+static struct cmd_tbl cmd_sm_sub[] = {
+ U_BOOT_CMD_MKENT(serial, 2, 1, do_sm_serial, "", ""),
+ U_BOOT_CMD_MKENT(reboot_reason, 1, 1, do_sm_reboot_reason, "", ""),
+ U_BOOT_CMD_MKENT(efuseread, 4, 1, do_efuse_read, "", ""),
+ U_BOOT_CMD_MKENT(efusewrite, 4, 0, do_efuse_write, "", ""),
+ U_BOOT_CMD_MKENT(efusedump, 3, 1, do_efuse_dump, "", ""),
+};
+
+static int do_sm(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct cmd_tbl *c;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ /* Strip off leading 'sm' command argument */
+ argc--;
+ argv++;
+
+ c = find_cmd_tbl(argv[0], &cmd_sm_sub[0], ARRAY_SIZE(cmd_sm_sub));
+
+ if (c)
+ return c->cmd(cmdtp, flag, argc, argv);
+ else
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+ sm, 5, 0, do_sm,
+ "Secure Monitor Control",
+ "serial <address> - read chip unique id to memory address\n"
+ "sm reboot_reason [name] - get reboot reason and store to environment\n"
+ "sm efuseread <offset> <size> <address> - read efuse to memory address\n"
+ "sm efusewrite <offset> <size> <address> - write into efuse from memory address\n"
+ "sm efusedump <offset> <size> - dump efuse data range to console"
+);
diff --git a/cmd/mmc.c b/cmd/mmc.c
index c79d940..94deb9a 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -1020,16 +1020,12 @@
}
#ifdef CONFIG_CMD_BKOPS_ENABLE
-static int do_mmc_bkops_enable(struct cmd_tbl *cmdtp, int flag,
- int argc, char *const argv[])
+static int mmc_bkops_common(char *device, bool autobkops, bool enable)
{
- int dev;
struct mmc *mmc;
-
- if (argc != 2)
- return CMD_RET_USAGE;
+ int dev;
- dev = dectoul(argv[1], NULL);
+ dev = dectoul(device, NULL);
mmc = init_mmc_device(dev, false);
if (!mmc)
@@ -1040,7 +1036,41 @@
return CMD_RET_FAILURE;
}
+ return mmc_set_bkops_enable(mmc, autobkops, enable);
+}
+
+static int do_mmc_bkops(struct cmd_tbl *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ bool autobkops, enable;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+
- return mmc_set_bkops_enable(mmc);
+ if (!strcmp(argv[2], "manual"))
+ autobkops = false;
+ else if (!strcmp(argv[2], "auto"))
+ autobkops = true;
+ else
+ return CMD_RET_FAILURE;
+
+ if (!strcmp(argv[3], "disable"))
+ enable = false;
+ else if (!strcmp(argv[3], "enable"))
+ enable = true;
+ else
+ return CMD_RET_FAILURE;
+
+ return mmc_bkops_common(argv[1], autobkops, enable);
+}
+
+static int do_mmc_bkops_enable(struct cmd_tbl *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ return mmc_bkops_common(argv[1], false, true);
}
#endif
@@ -1102,6 +1132,7 @@
U_BOOT_CMD_MKENT(setdsr, 2, 0, do_mmc_setdsr, "", ""),
#ifdef CONFIG_CMD_BKOPS_ENABLE
U_BOOT_CMD_MKENT(bkops-enable, 2, 0, do_mmc_bkops_enable, "", ""),
+ U_BOOT_CMD_MKENT(bkops, 4, 0, do_mmc_bkops, "", ""),
#endif
};
@@ -1188,6 +1219,8 @@
#ifdef CONFIG_CMD_BKOPS_ENABLE
"mmc bkops-enable <dev> - enable background operations handshake on device\n"
" WARNING: This is a write-once setting.\n"
+ "mmc bkops <dev> [auto|manual] [enable|disable]\n"
+ " - configure background operations handshake on device\n"
#endif
);
diff --git a/configs/bananapi-m5_defconfig b/configs/bananapi-m5_defconfig
index 0eb4fa7..cb6eca7 100644
--- a/configs/bananapi-m5_defconfig
+++ b/configs/bananapi-m5_defconfig
@@ -49,6 +49,7 @@
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/beelink-gsking-x_defconfig b/configs/beelink-gsking-x_defconfig
index ae018bb..3e06002 100644
--- a/configs/beelink-gsking-x_defconfig
+++ b/configs/beelink-gsking-x_defconfig
@@ -50,6 +50,7 @@
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/beelink-gtking_defconfig b/configs/beelink-gtking_defconfig
index d5b071d..091858b 100644
--- a/configs/beelink-gtking_defconfig
+++ b/configs/beelink-gtking_defconfig
@@ -50,6 +50,7 @@
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/beelink-gtkingpro_defconfig b/configs/beelink-gtkingpro_defconfig
index b179f7b..965639e 100644
--- a/configs/beelink-gtkingpro_defconfig
+++ b/configs/beelink-gtkingpro_defconfig
@@ -50,6 +50,7 @@
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/jethub_j100_defconfig b/configs/jethub_j100_defconfig
index c265158..dac775b 100644
--- a/configs/jethub_j100_defconfig
+++ b/configs/jethub_j100_defconfig
@@ -55,6 +55,7 @@
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC2=y
diff --git a/configs/jethub_j80_defconfig b/configs/jethub_j80_defconfig
index f3c47a0..1d11a96 100644
--- a/configs/jethub_j80_defconfig
+++ b/configs/jethub_j80_defconfig
@@ -59,6 +59,7 @@
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC2=y
diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig
index a8d11a8..3af6b44 100644
--- a/configs/khadas-vim2_defconfig
+++ b/configs/khadas-vim2_defconfig
@@ -59,6 +59,7 @@
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SMBIOS=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/khadas-vim3_android_ab_defconfig b/configs/khadas-vim3_android_ab_defconfig
index 01a9157..f212b86 100644
--- a/configs/khadas-vim3_android_ab_defconfig
+++ b/configs/khadas-vim3_android_ab_defconfig
@@ -84,6 +84,7 @@
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SMBIOS=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/khadas-vim3_android_defconfig b/configs/khadas-vim3_android_defconfig
index 7a2815d..3ac915e 100644
--- a/configs/khadas-vim3_android_defconfig
+++ b/configs/khadas-vim3_android_defconfig
@@ -82,6 +82,7 @@
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SMBIOS=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vim3_defconfig
index 792ee71..26a1485 100644
--- a/configs/khadas-vim3_defconfig
+++ b/configs/khadas-vim3_defconfig
@@ -70,6 +70,7 @@
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SMBIOS=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/khadas-vim3l_android_ab_defconfig b/configs/khadas-vim3l_android_ab_defconfig
index e182a3e..c3eb25a 100644
--- a/configs/khadas-vim3l_android_ab_defconfig
+++ b/configs/khadas-vim3l_android_ab_defconfig
@@ -84,6 +84,7 @@
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SMBIOS=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/khadas-vim3l_android_defconfig b/configs/khadas-vim3l_android_defconfig
index bf3e2df..5e29827 100644
--- a/configs/khadas-vim3l_android_defconfig
+++ b/configs/khadas-vim3l_android_defconfig
@@ -82,6 +82,7 @@
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SMBIOS=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/khadas-vim3l_defconfig b/configs/khadas-vim3l_defconfig
index a99d4ca..a3fd6a1 100644
--- a/configs/khadas-vim3l_defconfig
+++ b/configs/khadas-vim3l_defconfig
@@ -70,6 +70,7 @@
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SMBIOS=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig
index d1ed45f..6bb2200 100644
--- a/configs/khadas-vim_defconfig
+++ b/configs/khadas-vim_defconfig
@@ -50,6 +50,7 @@
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SMBIOS=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig
index a333106..2f44771 100644
--- a/configs/libretech-ac_defconfig
+++ b/configs/libretech-ac_defconfig
@@ -65,6 +65,7 @@
CONFIG_DM_SPI=y
CONFIG_MESON_SPIFC=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig
index 60b40e6..05311d8 100644
--- a/configs/libretech-cc_defconfig
+++ b/configs/libretech-cc_defconfig
@@ -49,6 +49,7 @@
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/libretech-s905d-pc_defconfig b/configs/libretech-s905d-pc_defconfig
index d3e600e..4e3aee7 100644
--- a/configs/libretech-s905d-pc_defconfig
+++ b/configs/libretech-s905d-pc_defconfig
@@ -61,6 +61,7 @@
CONFIG_DM_SPI=y
CONFIG_MESON_SPIFC=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/libretech-s912-pc_defconfig b/configs/libretech-s912-pc_defconfig
index 8b4f052..c9ceb35 100644
--- a/configs/libretech-s912-pc_defconfig
+++ b/configs/libretech-s912-pc_defconfig
@@ -60,6 +60,7 @@
CONFIG_DM_SPI=y
CONFIG_MESON_SPIFC=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/odroid-c4_defconfig b/configs/odroid-c4_defconfig
index af37b4d..2c449a1 100644
--- a/configs/odroid-c4_defconfig
+++ b/configs/odroid-c4_defconfig
@@ -50,6 +50,7 @@
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/odroid-go-ultra_defconfig b/configs/odroid-go-ultra_defconfig
new file mode 100644
index 0000000..a4d349f
--- /dev/null
+++ b/configs/odroid-go-ultra_defconfig
@@ -0,0 +1,70 @@
+CONFIG_ARM=y
+CONFIG_SYS_BOARD="w400"
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-odroid-go-ultra"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" odroid-go-ultra"
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DEBUG_UART=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_REMAKE_ELF=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/odroid-hc4_defconfig b/configs/odroid-hc4_defconfig
index 1af9c11..2893802 100644
--- a/configs/odroid-hc4_defconfig
+++ b/configs/odroid-hc4_defconfig
@@ -68,6 +68,7 @@
CONFIG_DM_SPI=y
CONFIG_MESON_SPIFC=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/odroid-n2_defconfig b/configs/odroid-n2_defconfig
index fcd9962..190645d 100644
--- a/configs/odroid-n2_defconfig
+++ b/configs/odroid-n2_defconfig
@@ -50,6 +50,7 @@
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/odroid-n2l_defconfig b/configs/odroid-n2l_defconfig
new file mode 100644
index 0000000..7f9e64d
--- /dev/null
+++ b/configs/odroid-n2l_defconfig
@@ -0,0 +1,70 @@
+CONFIG_ARM=y
+CONFIG_SYS_BOARD="w400"
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-odroid-n2l"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" odroid-n2l"
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DEBUG_UART=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_REMAKE_ELF=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/radxa-zero_defconfig b/configs/radxa-zero_defconfig
index 19bd9f3..0c6d375 100644
--- a/configs/radxa-zero_defconfig
+++ b/configs/radxa-zero_defconfig
@@ -45,6 +45,7 @@
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/s400_defconfig b/configs/s400_defconfig
index 827bd54..91930d7 100644
--- a/configs/s400_defconfig
+++ b/configs/s400_defconfig
@@ -42,6 +42,7 @@
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/sei510_defconfig b/configs/sei510_defconfig
index 30b49cc..96e114a 100644
--- a/configs/sei510_defconfig
+++ b/configs/sei510_defconfig
@@ -70,6 +70,7 @@
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/sei610_defconfig b/configs/sei610_defconfig
index a922765..bba46a8 100644
--- a/configs/sei610_defconfig
+++ b/configs/sei610_defconfig
@@ -70,6 +70,7 @@
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/u200_defconfig b/configs/u200_defconfig
index f346b38..1d19c06 100644
--- a/configs/u200_defconfig
+++ b/configs/u200_defconfig
@@ -44,6 +44,7 @@
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/wetek-core2_defconfig b/configs/wetek-core2_defconfig
index 13940dd..b730700 100644
--- a/configs/wetek-core2_defconfig
+++ b/configs/wetek-core2_defconfig
@@ -51,6 +51,7 @@
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/doc/board/amlogic/index.rst b/doc/board/amlogic/index.rst
index 4d407f9..f945f67 100644
--- a/doc/board/amlogic/index.rst
+++ b/doc/board/amlogic/index.rst
@@ -19,7 +19,9 @@
| | Nanopi-K2 | Khadas-VIM | Libretech-PC | JetHub J100 | SEI510 | Khadas-VIM3 | Khadas-VIM3L |
| | P200 | LibreTech-CC v1 | WeTek Core2 | | Radxa Zero | GT-King/Pro | Odroid-C4 |
| | P201 | LibreTech-AC v2 | | | | GSKing-X | Odroid-HC4 |
-| | | JetHub J80 | | | | | BananaPi-M5 |
+| | | JetHub J80 | | | | Odroid-Go- | BananaPi-M5 |
+| | | | | | | Ultra | |
+| | | | | | | Odroid-N2L | |
+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
| UART | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
@@ -105,6 +107,8 @@
odroid-c2
odroid-c4
odroid-n2
+ odroid-n2l
+ odroid-go-ultra
p200
p201
p212
diff --git a/doc/board/amlogic/odroid-go-ultra.rst b/doc/board/amlogic/odroid-go-ultra.rst
new file mode 100644
index 0000000..8df9e0c
--- /dev/null
+++ b/doc/board/amlogic/odroid-go-ultra.rst
@@ -0,0 +1,34 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for ODROID-GO-ULTRA
+==========================
+
+The Odroid Go Ultra is a portable gaming device with the following
+characteristics:
+
+ - Amlogic S922X SoC
+ - RK817 & RK818 PMICs
+ - 2GiB LPDDR4
+ - On board 16GiB eMMC
+ - Micro SD Card slot
+ - 5inch 854×480 MIPI-DSI TFT LCD
+ - Earphone stereo jack, 0.5Watt 8Ω Mono speaker
+ - Li-Polymer 3.7V/4000mAh Battery
+ - USB-A 2.0 Host Connector
+ - x16 GPIO Input Buttons
+ - 2x ADC Analog Joysticks
+ - USB-C Port for USB2 Device and Charging
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make odroid-go-ultra_defconfig
+ $ make
+
+Image creation
+--------------
+
+Pleaser refer to :doc:`pre-generated-fip` with codename `odroid-go-ultra`
diff --git a/doc/board/amlogic/odroid-n2l.rst b/doc/board/amlogic/odroid-n2l.rst
new file mode 100644
index 0000000..afd4409
--- /dev/null
+++ b/doc/board/amlogic/odroid-n2l.rst
@@ -0,0 +1,31 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for ODROID-N2L
+=====================
+
+ODROID-N2L is a single board computer manufactured by Hardkernel
+Co. Ltd with the following specifications:
+
+ - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
+ - 4GB DDR4 SDRAM
+ - HDMI 2.1 4K/60Hz display
+ - 40-pin GPIO header
+ - 1 x USB 3.0 Host, 1 x USB USB 2.0 Host
+ - eMMC, microSD
+ - MIPI DSI Port
+
+Schematics are available on the manufacturer website.
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make odroid-n2l_defconfig
+ $ make
+
+Image creation
+--------------
+
+For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `odroid-n2l`
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index 16fb4a6..746bd96 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -50,8 +50,7 @@
* U-Boot v2023.01 was released on Mon 09 January 2023.
-* The Merge Window for the next release (v2023.04) is **open** until -rc1
- release on Mon 30 January 2023.
+* The Merge Window for the next release (v2023.04) is **closed**.
* Release "v2023.04" is scheduled for 03 April 2023.
@@ -61,9 +60,9 @@
.. The following commented out dates are for when release candidates are
planned to be tagged.
-.. For the next scheduled release, release candidates were made on::
+For the next scheduled release, release candidates were made on::
-.. * U-Boot v2023.04-rc1 was released on Mon 30 January 2023.
+* U-Boot v2023.04-rc1 was released on Mon 30 January 2023.
.. * U-Boot v2023.04-rc2 was released on Mon 13 February 2023.
diff --git a/doc/usage/cmd/sm.rst b/doc/usage/cmd/sm.rst
new file mode 100644
index 0000000..f6524a1
--- /dev/null
+++ b/doc/usage/cmd/sm.rst
@@ -0,0 +1,48 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+sm command
+==========
+
+Synopis
+-------
+
+::
+
+ sm serial <address>
+ sm reboot_reason [name]
+ sm efuseread <offset> <size> <address>
+ sm efusewrite <offset> <size> <address>
+ sm efusedump <offset> <size>
+
+Description
+-----------
+
+The sm command is used to request services from the secure monitor. User
+can call secure monitor to request special TEE function, for example chip
+serial number info, reboot reason, etc.
+
+sm serial
+ Retrieve chip unique serial number from sm and write it to memory on
+ appropriate address.
+
+sm reboot_reason
+ Print reboot reason to the console, if parameter [name] isn't specified.
+ If parameter specified, set reboot reason string to environment variable
+ with this name.
+
+sm efuseread
+ Read <size> bytes starting from <offset> from efuse memory bank and write
+ result to the address <address>.
+
+sm efusewrite
+ Write into efuse memory bank, starting from <offset>, the <size> bytes
+ of data, located at address <address>.
+
+sm efusedump
+ Read <size> bytes starting from <offset> from efuse memory bank and print
+ them to the console.
+
+Configuration
+-------------
+
+To use the sm command you must specify CONFIG_CMD_MESON=y
diff --git a/doc/usage/index.rst b/doc/usage/index.rst
index 2c95471..3804046 100644
--- a/doc/usage/index.rst
+++ b/doc/usage/index.rst
@@ -80,6 +80,7 @@
cmd/sleep
cmd/sound
cmd/source
+ cmd/sm
cmd/temperature
cmd/tftpput
cmd/true
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 210703e..afbc497 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -3127,9 +3127,10 @@
#endif
#ifdef CONFIG_CMD_BKOPS_ENABLE
-int mmc_set_bkops_enable(struct mmc *mmc)
+int mmc_set_bkops_enable(struct mmc *mmc, bool autobkops, bool enable)
{
int err;
+ u32 bit = autobkops ? BIT(1) : BIT(0);
ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
err = mmc_send_ext_csd(mmc, ext_csd);
@@ -3143,18 +3144,21 @@
return -EMEDIUMTYPE;
}
- if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
+ if (enable && (ext_csd[EXT_CSD_BKOPS_EN] & bit)) {
puts("Background operations already enabled\n");
return 0;
}
- err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN,
+ enable ? bit : 0);
if (err) {
- puts("Failed to enable manual background operations\n");
+ printf("Failed to %sable manual background operations\n",
+ enable ? "en" : "dis");
return err;
}
- puts("Enabled manual background operations\n");
+ printf("%sabled %s background operations\n",
+ enable ? "En" : "Dis", autobkops ? "auto" : "manual");
return 0;
}
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index a80ad83..c6b250b 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -396,6 +396,14 @@
}
}
+ if (host->ops && host->ops->config_dll) {
+ ret = host->ops->config_dll(host, clock, false);
+ if (ret) {
+ printf("%s: Error while configuring dll\n", __func__);
+ return ret;
+ }
+ }
+
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
/*
* Check if the Host Controller supports Programmable Clock
@@ -439,6 +447,14 @@
if (host->ops && host->ops->set_clock)
host->ops->set_clock(host, div);
+ if (host->ops && host->ops->config_dll) {
+ ret = host->ops->config_dll(host, clock, true);
+ if (ret) {
+ printf("%s: Error while configuring dll\n", __func__);
+ return ret;
+ }
+ }
+
clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
<< SDHCI_DIVIDER_HI_SHIFT;
@@ -979,6 +995,10 @@
cfg->host_caps |= MMC_CAP(UHS_SDR50);
}
+ if ((host->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_HS400) &&
+ (caps_1 & SDHCI_SUPPORT_HS400))
+ cfg->host_caps |= MMC_CAP(MMC_HS_400);
+
if (caps_1 & SDHCI_SUPPORT_DDR50)
cfg->host_caps |= MMC_CAP(UHS_DDR50);
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index be4075c..91e309d2 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2013 - 2015 Xilinx, Inc.
+ * (C) Copyright 2013 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022, Advanced Micro Devices, Inc.
*
* Xilinx Zynq SD Host Controller Interface
*/
@@ -16,6 +17,7 @@
#include <dm/device_compat.h>
#include <linux/err.h>
#include <linux/libfdt.h>
+#include <linux/iopoll.h>
#include <asm/types.h>
#include <linux/math64.h>
#include <asm/cache.h>
@@ -48,6 +50,41 @@
#define SD0_OTAPDLYSEL_MASK GENMASK(5, 0)
#define SD1_OTAPDLYSEL_MASK GENMASK(21, 16)
+#define MIN_PHY_CLK_HZ 50000000
+
+#define PHY_CTRL_REG1 0x270
+#define PHY_CTRL_ITAPDLY_ENA_MASK BIT(0)
+#define PHY_CTRL_ITAPDLY_SEL_MASK GENMASK(5, 1)
+#define PHY_CTRL_ITAPDLY_SEL_SHIFT 1
+#define PHY_CTRL_ITAP_CHG_WIN_MASK BIT(6)
+#define PHY_CTRL_OTAPDLY_ENA_MASK BIT(8)
+#define PHY_CTRL_OTAPDLY_SEL_MASK GENMASK(15, 12)
+#define PHY_CTRL_OTAPDLY_SEL_SHIFT 12
+#define PHY_CTRL_STRB_SEL_MASK GENMASK(23, 16)
+#define PHY_CTRL_STRB_SEL_SHIFT 16
+#define PHY_CTRL_TEST_CTRL_MASK GENMASK(31, 24)
+
+#define PHY_CTRL_REG2 0x274
+#define PHY_CTRL_EN_DLL_MASK BIT(0)
+#define PHY_CTRL_DLL_RDY_MASK BIT(1)
+#define PHY_CTRL_FREQ_SEL_MASK GENMASK(6, 4)
+#define PHY_CTRL_FREQ_SEL_SHIFT 4
+#define PHY_CTRL_SEL_DLY_TX_MASK BIT(16)
+#define PHY_CTRL_SEL_DLY_RX_MASK BIT(17)
+#define FREQSEL_200M_170M 0x0
+#define FREQSEL_170M_140M 0x1
+#define FREQSEL_140M_110M 0x2
+#define FREQSEL_110M_80M 0x3
+#define FREQSEL_80M_50M 0x4
+#define FREQSEL_275M_250M 0x5
+#define FREQSEL_250M_225M 0x6
+#define FREQSEL_225M_200M 0x7
+#define PHY_DLL_TIMEOUT_MS 100
+
+#define VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN 39
+#define VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL 146
+#define VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL 0X77
+
struct arasan_sdhci_clk_data {
int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
@@ -64,6 +101,7 @@
u32 node_id;
u8 bank;
u8 no_1p8;
+ bool internal_phy_reg;
struct reset_ctl_bulk resets;
};
@@ -84,7 +122,7 @@
return 1;
}
-#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
+#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET)
/* Default settings for ZynqMP Clock Phases */
static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0,
0, 183, 54, 0, 0};
@@ -97,6 +135,12 @@
static const u32 versal_oclk_phases[] = {0, 60, 48, 0, 48, 72,
90, 36, 60, 90, 0};
+/* Default settings for versal-net eMMC Clock Phases */
+static const u32 versal_net_emmc_iclk_phases[] = {0, 0, 0, 0, 0, 0, 0, 0, 39,
+ 0, 0};
+static const u32 versal_net_emmc_oclk_phases[] = {0, 113, 0, 0, 0, 0, 0, 0,
+ 113, 79, 45};
+
static const u8 mode2timing[] = {
[MMC_LEGACY] = MMC_TIMING_LEGACY,
[MMC_HS] = MMC_TIMING_MMC_HS,
@@ -109,8 +153,124 @@
[UHS_DDR50] = MMC_TIMING_UHS_DDR50,
[UHS_SDR104] = MMC_TIMING_UHS_SDR104,
[MMC_HS_200] = MMC_TIMING_MMC_HS200,
+ [MMC_HS_400] = MMC_TIMING_MMC_HS400,
};
+#if defined(CONFIG_ARCH_VERSAL_NET)
+/**
+ * arasan_phy_set_delaychain - Set eMMC delay chain based Input/Output clock
+ *
+ * @host: Pointer to the sdhci_host structure
+ * @enable: Enable or disable Delay chain based Tx and Rx clock
+ * Return: None
+ *
+ * Enable or disable eMMC delay chain based Input and Output clock in
+ * PHY_CTRL_REG2
+ */
+static void arasan_phy_set_delaychain(struct sdhci_host *host, bool enable)
+{
+ u32 reg;
+
+ reg = sdhci_readw(host, PHY_CTRL_REG2);
+ if (enable)
+ reg |= PHY_CTRL_SEL_DLY_TX_MASK | PHY_CTRL_SEL_DLY_RX_MASK;
+ else
+ reg &= ~(PHY_CTRL_SEL_DLY_TX_MASK | PHY_CTRL_SEL_DLY_RX_MASK);
+
+ sdhci_writew(host, reg, PHY_CTRL_REG2);
+}
+
+/**
+ * arasan_phy_set_dll - Set eMMC DLL clock
+ *
+ * @host: Pointer to the sdhci_host structure
+ * @enable: Enable or disable DLL clock
+ * Return: 0 if success or timeout error
+ *
+ * Enable or disable eMMC DLL clock in PHY_CTRL_REG2. When DLL enable is
+ * set, wait till DLL is locked
+ */
+static int arasan_phy_set_dll(struct sdhci_host *host, bool enable)
+{
+ u32 reg;
+
+ reg = sdhci_readw(host, PHY_CTRL_REG2);
+ if (enable)
+ reg |= PHY_CTRL_EN_DLL_MASK;
+ else
+ reg &= ~PHY_CTRL_EN_DLL_MASK;
+
+ sdhci_writew(host, reg, PHY_CTRL_REG2);
+
+ /* If DLL is disabled return success */
+ if (!enable)
+ return 0;
+
+ /* If DLL is enabled wait till DLL loop is locked, which is
+ * indicated by dll_rdy bit(bit1) in PHY_CTRL_REG2
+ */
+ return readl_relaxed_poll_timeout(host->ioaddr + PHY_CTRL_REG2, reg,
+ (reg & PHY_CTRL_DLL_RDY_MASK),
+ 1000 * PHY_DLL_TIMEOUT_MS);
+}
+
+/**
+ * arasan_phy_dll_set_freq - Select frequency range of DLL for eMMC
+ *
+ * @host: Pointer to the sdhci_host structure
+ * @clock: clock value
+ * Return: None
+ *
+ * Set frequency range bits based on the selected clock for eMMC
+ */
+static void arasan_phy_dll_set_freq(struct sdhci_host *host, int clock)
+{
+ u32 reg, freq_sel, freq;
+
+ freq = DIV_ROUND_CLOSEST(clock, 1000000);
+ if (freq <= 200 && freq > 170)
+ freq_sel = FREQSEL_200M_170M;
+ else if (freq <= 170 && freq > 140)
+ freq_sel = FREQSEL_170M_140M;
+ else if (freq <= 140 && freq > 110)
+ freq_sel = FREQSEL_140M_110M;
+ else if (freq <= 110 && freq > 80)
+ freq_sel = FREQSEL_110M_80M;
+ else
+ freq_sel = FREQSEL_80M_50M;
+
+ reg = sdhci_readw(host, PHY_CTRL_REG2);
+ reg &= ~PHY_CTRL_FREQ_SEL_MASK;
+ reg |= (freq_sel << PHY_CTRL_FREQ_SEL_SHIFT);
+ sdhci_writew(host, reg, PHY_CTRL_REG2);
+}
+
+static int arasan_sdhci_config_dll(struct sdhci_host *host, unsigned int clock, bool enable)
+{
+ struct mmc *mmc = (struct mmc *)host->mmc;
+ struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
+
+ if (enable) {
+ if (priv->internal_phy_reg && clock >= MIN_PHY_CLK_HZ && enable)
+ arasan_phy_set_dll(host, 1);
+ return 0;
+ }
+
+ if (priv->internal_phy_reg && clock >= MIN_PHY_CLK_HZ) {
+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+ arasan_phy_set_dll(host, 0);
+ arasan_phy_set_delaychain(host, 0);
+ arasan_phy_dll_set_freq(host, clock);
+ return 0;
+ }
+
+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+ arasan_phy_set_delaychain(host, 1);
+
+ return 0;
+}
+#endif
+
static inline int arasan_zynqmp_set_in_tapdelay(u32 node_id, u32 itap_delay)
{
int ret;
@@ -585,6 +745,101 @@
return 0;
}
+/**
+ * sdhci_versal_net_emmc_sdcardclk_set_phase - Set eMMC Output Clock Tap Delays
+ *
+ * @host: Pointer to the sdhci_host structure.
+ * @degrees: The clock phase shift between 0 - 359.
+ * Return: 0
+ *
+ * Set eMMC Output Clock Tap Delays for Output path
+ */
+static int sdhci_versal_net_emmc_sdcardclk_set_phase(struct sdhci_host *host, int degrees)
+{
+ struct mmc *mmc = (struct mmc *)host->mmc;
+ int timing = mode2timing[mmc->selected_mode];
+ u8 tap_delay, tap_max = 0;
+ u32 regval;
+
+ switch (timing) {
+ case MMC_TIMING_MMC_HS:
+ case MMC_TIMING_MMC_DDR52:
+ tap_max = 16;
+ break;
+ case MMC_TIMING_MMC_HS200:
+ case MMC_TIMING_MMC_HS400:
+ /* For 200MHz clock, 32 Taps are available */
+ tap_max = 32;
+ break;
+ default:
+ break;
+ }
+
+ tap_delay = (degrees * tap_max) / 360;
+ /* Set the Clock Phase */
+ if (tap_delay) {
+ regval = sdhci_readl(host, PHY_CTRL_REG1);
+ regval |= PHY_CTRL_OTAPDLY_ENA_MASK;
+ sdhci_writel(host, regval, PHY_CTRL_REG1);
+ regval &= ~PHY_CTRL_OTAPDLY_SEL_MASK;
+ regval |= tap_delay << PHY_CTRL_OTAPDLY_SEL_SHIFT;
+ sdhci_writel(host, regval, PHY_CTRL_REG1);
+ }
+
+ return 0;
+}
+
+/**
+ * sdhci_versal_net_emmc_sampleclk_set_phase - Set eMMC Input Clock Tap Delays
+ *
+ * @host: Pointer to the sdhci_host structure.
+ * @degrees: The clock phase shift between 0 - 359.
+ * Return: 0
+ *
+ * Set eMMC Input Clock Tap Delays for Input path. If HS400 is selected,
+ * set strobe90 and strobe180 in PHY_CTRL_REG1.
+ */
+static int sdhci_versal_net_emmc_sampleclk_set_phase(struct sdhci_host *host, int degrees)
+{
+ struct mmc *mmc = (struct mmc *)host->mmc;
+ int timing = mode2timing[mmc->selected_mode];
+ u8 tap_delay, tap_max = 0;
+ u32 regval;
+
+ switch (timing) {
+ case MMC_TIMING_MMC_HS:
+ case MMC_TIMING_MMC_DDR52:
+ tap_max = 32;
+ break;
+ case MMC_TIMING_MMC_HS400:
+ /* Strobe select tap point for strb90 and strb180 */
+ regval = sdhci_readl(host, PHY_CTRL_REG1);
+ regval &= ~PHY_CTRL_STRB_SEL_MASK;
+ regval |= VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL << PHY_CTRL_STRB_SEL_SHIFT;
+ sdhci_writel(host, regval, PHY_CTRL_REG1);
+ break;
+ default:
+ break;
+ }
+
+ tap_delay = (degrees * tap_max) / 360;
+ /* Set the Clock Phase */
+ if (tap_delay) {
+ regval = sdhci_readl(host, PHY_CTRL_REG1);
+ regval |= PHY_CTRL_ITAP_CHG_WIN_MASK;
+ sdhci_writel(host, regval, PHY_CTRL_REG1);
+ regval |= PHY_CTRL_ITAPDLY_ENA_MASK;
+ sdhci_writel(host, regval, PHY_CTRL_REG1);
+ regval &= ~PHY_CTRL_ITAPDLY_SEL_MASK;
+ regval |= tap_delay << PHY_CTRL_ITAPDLY_SEL_SHIFT;
+ sdhci_writel(host, regval, PHY_CTRL_REG1);
+ regval &= ~PHY_CTRL_ITAP_CHG_WIN_MASK;
+ sdhci_writel(host, regval, PHY_CTRL_REG1);
+ }
+
+ return 0;
+}
+
static int arasan_sdhci_set_tapdelay(struct sdhci_host *host)
{
struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
@@ -616,6 +871,19 @@
ret = sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
if (ret)
return ret;
+ } else if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) &&
+ device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) {
+ if (mmc->clock >= MIN_PHY_CLK_HZ)
+ if (iclk_phase == VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN)
+ iclk_phase = VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL;
+
+ ret = sdhci_versal_net_emmc_sampleclk_set_phase(host, iclk_phase);
+ if (ret)
+ return ret;
+
+ ret = sdhci_versal_net_emmc_sdcardclk_set_phase(host, oclk_phase);
+ if (ret)
+ return ret;
}
return 0;
@@ -678,6 +946,14 @@
}
}
+ if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) &&
+ device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) {
+ for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
+ clk_data->clk_phase_in[i] = versal_net_emmc_iclk_phases[i];
+ clk_data->clk_phase_out[i] = versal_net_emmc_oclk_phases[i];
+ }
+ }
+
arasan_dt_read_clk_phase(dev, MMC_TIMING_LEGACY,
"clk-phase-legacy");
arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS,
@@ -706,6 +982,9 @@
.platform_execute_tuning = &arasan_sdhci_execute_tuning,
.set_delay = &arasan_sdhci_set_tapdelay,
.set_control_reg = &sdhci_set_control_reg,
+#if defined(CONFIG_ARCH_VERSAL_NET)
+ .config_dll = &arasan_sdhci_config_dll,
+#endif
};
#endif
@@ -822,6 +1101,8 @@
}
}
#endif
+ if (device_is_compatible(dev, "xlnx,versal-net-5.1-emmc"))
+ priv->internal_phy_reg = true;
ret = clk_get_by_index(dev, 0, &clk);
if (ret < 0) {
@@ -853,6 +1134,10 @@
if (priv->no_1p8)
host->quirks |= SDHCI_QUIRK_NO_1_8_V;
+ if (CONFIG_IS_ENABLED(ARCH_VERSAL_NET) &&
+ device_is_compatible(dev, "xlnx,versal-net-5.1-emmc"))
+ host->quirks |= SDHCI_QUIRK_CAPS_BIT63_FOR_HS400;
+
plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
ret = mmc_of_parse(dev, &plat->cfg);
@@ -905,7 +1190,7 @@
priv->host->name = dev->name;
-#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
+#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET)
priv->host->ops = &arasan_ops;
arasan_dt_parse_clk_phases(dev);
#endif
@@ -933,6 +1218,7 @@
static const struct udevice_id arasan_sdhci_ids[] = {
{ .compatible = "arasan,sdhci-8.9a" },
+ { .compatible = "xlnx,versal-net-5.1-emmc" },
{ }
};
diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c
index 90418dd..c62e42d 100644
--- a/drivers/usb/dwc3/dwc3-meson-g12a.c
+++ b/drivers/usb/dwc3/dwc3-meson-g12a.c
@@ -455,6 +455,22 @@
return dm_scan_fdt_dev(dev);
}
+static int dwc3_meson_g12a_child_pre_probe(struct udevice *dev)
+{
+ if (ofnode_device_is_compatible(dev_ofnode(dev), "amlogic,meson-g12a-usb"))
+ return dwc3_meson_g12a_force_mode(dev->parent, USB_DR_MODE_PERIPHERAL);
+
+ return 0;
+}
+
+static int dwc3_meson_g12a_child_post_remove(struct udevice *dev)
+{
+ if (ofnode_device_is_compatible(dev_ofnode(dev), "amlogic,meson-g12a-usb"))
+ return dwc3_meson_g12a_force_mode(dev->parent, USB_DR_MODE_HOST);
+
+ return 0;
+}
+
static const struct udevice_id dwc3_meson_g12a_ids[] = {
{ .compatible = "amlogic,meson-g12a-usb-ctrl" },
{ }
@@ -466,6 +482,8 @@
.of_match = dwc3_meson_g12a_ids,
.probe = dwc3_meson_g12a_probe,
.remove = dwc3_meson_g12a_remove,
+ .child_pre_probe = dwc3_meson_g12a_child_pre_probe,
+ .child_post_remove = dwc3_meson_g12a_child_post_remove,
.plat_auto = sizeof(struct dwc3_meson_g12a),
};
diff --git a/drivers/usb/dwc3/dwc3-meson-gxl.c b/drivers/usb/dwc3/dwc3-meson-gxl.c
index 6c6d463..d56f274 100644
--- a/drivers/usb/dwc3/dwc3-meson-gxl.c
+++ b/drivers/usb/dwc3/dwc3-meson-gxl.c
@@ -408,6 +408,22 @@
return dm_scan_fdt_dev(dev);
}
+static int dwc3_meson_gxl_child_pre_probe(struct udevice *dev)
+{
+ if (ofnode_device_is_compatible(dev_ofnode(dev), "amlogic,meson-g12a-usb"))
+ return dwc3_meson_gxl_force_mode(dev->parent, USB_DR_MODE_PERIPHERAL);
+
+ return 0;
+}
+
+static int dwc3_meson_gxl_child_post_remove(struct udevice *dev)
+{
+ if (ofnode_device_is_compatible(dev_ofnode(dev), "amlogic,meson-g12a-usb"))
+ return dwc3_meson_gxl_force_mode(dev->parent, USB_DR_MODE_HOST);
+
+ return 0;
+}
+
static const struct udevice_id dwc3_meson_gxl_ids[] = {
{ .compatible = "amlogic,meson-axg-usb-ctrl" },
{ .compatible = "amlogic,meson-gxl-usb-ctrl" },
@@ -421,6 +437,8 @@
.of_match = dwc3_meson_gxl_ids,
.probe = dwc3_meson_gxl_probe,
.remove = dwc3_meson_gxl_remove,
+ .child_pre_probe = dwc3_meson_gxl_child_pre_probe,
+ .child_post_remove = dwc3_meson_gxl_child_post_remove,
.plat_auto = sizeof(struct dwc3_meson_gxl),
};
diff --git a/include/configs/jethub.h b/include/configs/jethub.h
index 35f8509..e22db49 100644
--- a/include/configs/jethub.h
+++ b/include/configs/jethub.h
@@ -12,6 +12,7 @@
#define BOOTENV_DEV_RESCUE(devtypeu, devtypel, instance) \
"bootcmd_rescue=" \
"if gpio input 10; then " \
+ "run bootcmd_mmc0; " \
"run bootcmd_usb0;" \
"fi;\0"
#else
diff --git a/include/mmc.h b/include/mmc.h
index 571fa62..36dd841 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -892,9 +892,17 @@
int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen,
void *rsp, unsigned long rsplen);
-#ifdef CONFIG_CMD_BKOPS_ENABLE
-int mmc_set_bkops_enable(struct mmc *mmc);
-#endif
+/**
+ * mmc_set_bkops_enable() - enable background operations
+ * @param mmc Pointer to a MMC device struct
+ * @param autobkops Enable automatic bkops, not manual bkops
+ * @param enable Enable bkops, not disable
+ *
+ * Enable or disable automatic or manual background operation of the eMMC.
+ *
+ * Return: 0 on success, <0 on error.
+ */
+int mmc_set_bkops_enable(struct mmc *mmc, bool autobkops, bool enable);
/**
* Start device initialization and return immediately; it does not block on
diff --git a/include/power/act8846_pmic.h b/include/power/act8846_pmic.h
index acd0fd6..84845c7 100644
--- a/include/power/act8846_pmic.h
+++ b/include/power/act8846_pmic.h
@@ -9,7 +9,7 @@
#include <asm/gpio.h>
-#define ACT8846_NUM_OF_REGS 12
+#define ACT8846_NUM_OF_REGS 0xf6
#define BUCK_VOL_MASK 0x3f
#define LDO_VOL_MASK 0x3f
diff --git a/include/sdhci.h b/include/sdhci.h
index 24b4599..70fefca 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -189,6 +189,7 @@
#define SDHCI_SUPPORT_SDR50 0x00000001
#define SDHCI_SUPPORT_SDR104 0x00000002
#define SDHCI_SUPPORT_DDR50 0x00000004
+#define SDHCI_SUPPORT_HS400 BIT(31)
#define SDHCI_USE_SDR50_TUNING 0x00002000
#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
@@ -248,6 +249,8 @@
#define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
#define SDHCI_QUIRK_NO_1_8_V (1 << 9)
#define SDHCI_QUIRK_SUPPORT_SINGLE (1 << 10)
+/* Capability register bit-63 indicates HS400 support */
+#define SDHCI_QUIRK_CAPS_BIT63_FOR_HS400 BIT(11)
/* to make gcc happy */
struct sdhci_host;
@@ -272,6 +275,8 @@
void (*set_clock)(struct sdhci_host *host, u32 div);
int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
int (*set_delay)(struct sdhci_host *host);
+ /* Callback function to set DLL clock configuration */
+ int (*config_dll)(struct sdhci_host *host, u32 clock, bool enable);
int (*deferred_probe)(struct sdhci_host *host);
/**