qe: add u-qe support to arm board
ls1021 is arm-core and support qe which is u-qe.
add u-qe init for arm board.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
[York Sun: Fix compiling error caused by u_qe_init()]
Reviewed-by: York Sun <yorksun@freescale.com>
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index f2c9687..fc6a475 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -72,6 +72,10 @@
#define DCU_LAYER_MAX_NUM 16
+#define QE_MURAM_SIZE 0x6000UL
+#define MAX_QE_RISC 1
+#define QE_NUM_OF_SNUM 28
+
#define CONFIG_SYS_FSL_SRDS_1
#ifdef CONFIG_LS102XA
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index c69d064..438f128 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -17,6 +17,14 @@
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
#endif
+
+#if defined(CONFIG_U_QE)
+ u32 qe_clk;
+ u32 brg_clk;
+ uint mp_alloc_base;
+ uint mp_alloc_top;
+#endif /* CONFIG_U_QE */
+
#ifdef CONFIG_AT91FAMILY
/* "static data" needed by at91's clock.c */
unsigned long cpu_clk_rate_hz;
diff --git a/drivers/Makefile b/drivers/Makefile
index 33227c8..3c96524 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -16,6 +16,7 @@
obj-y += video/
obj-y += watchdog/
obj-$(CONFIG_QE) += qe/
+obj-$(CONFIG_U_QE) += qe/
obj-y += memory/
obj-y += pwm/
obj-y += input/
diff --git a/drivers/qe/Makefile b/drivers/qe/Makefile
index 7f1bd06..8fa4866 100644
--- a/drivers/qe/Makefile
+++ b/drivers/qe/Makefile
@@ -4,5 +4,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := qe.o uccf.o uec.o uec_phy.o
+obj-$(CONFIG_QE) += qe.o uccf.o uec.o uec_phy.o
+obj-$(CONFIG_U_QE) += qe.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/drivers/qe/fdt.c b/drivers/qe/fdt.c
index d9a7d82..dfae4bf 100644
--- a/drivers/qe/fdt.c
+++ b/drivers/qe/fdt.c
@@ -12,6 +12,7 @@
#include <fdt_support.h>
#include "qe.h"
+#ifdef CONFIG_QE
DECLARE_GLOBAL_DATA_PTR;
/*
@@ -72,3 +73,4 @@
"clock-frequency", gd->arch.qe_clk / 2, 1);
fdt_fixup_qe_firmware(blob);
}
+#endif
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 4358a91..b545ec9 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -40,6 +40,7 @@
return;
}
+#ifdef CONFIG_QE
uint qe_muram_alloc(uint size, uint align)
{
uint retloc;
@@ -70,6 +71,7 @@
return retloc;
}
+#endif
void *qe_muram_addr(uint offset)
{
@@ -180,6 +182,17 @@
qe_snums_init();
}
+#ifdef CONFIG_U_QE
+void u_qe_init(void)
+{
+ uint qe_base = CONFIG_SYS_IMMR + 0x01400000; /* QE immr base */
+ qe_immr = (qe_map_t *)qe_base;
+
+ qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
+ out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
+}
+#endif
+
void qe_reset(void)
{
qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
@@ -212,6 +225,7 @@
#define BRG_CLK (gd->arch.brg_clk)
+#ifdef CONFIG_QE
int qe_set_brg(uint brg, uint rate)
{
volatile uint *bp;
@@ -239,6 +253,7 @@
return 0;
}
+#endif
/* Set ethernet MII clock master
*/
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index ebb7c5f..30484b8 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -275,6 +275,7 @@
int qe_get_snum(void);
void qe_put_snum(u8 snum);
void qe_init(uint qe_base);
+void u_qe_init(void);
void qe_reset(void);
void qe_assign_page(uint snum, uint para_ram_base);
int qe_set_brg(uint brg, uint rate);