tree df783cf7d54f509c2202875f506c937509822947
parent a5f77dcaba97403bccbe933abe14ffc82eb50c6a
author ebony.zhu@freescale.com <ebony.zhu@freescale.com> 1166430315 +0800
committer Andrew Fleming-AFLEMING <afleming@freescale.com> 1177376307 -0500

u-boot: Disables MPC8548CDS 2T_TIMING for DDR by default

This patch disables MPC8548CDS 2T_TIMING for DDR by default.

Signed-off-by:Ebony Zhu <ebony.zhu@freescale.com>