* Patch by Daniel Engström, 13 Nov 2002:
Add support for i386 architecture and AMD SC520 board
* Patch by Pierre Aubert, 12 Nov 2002:
Add support for DOS filesystem and booting from DOS floppy disk
diff --git a/lib_i386/ic/ali512x.c b/lib_i386/ic/ali512x.c
new file mode 100644
index 0000000..4537095
--- /dev/null
+++ b/lib_i386/ic/ali512x.c
@@ -0,0 +1,442 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Based on sc520cdp.c from rolo 1.6:
+ *----------------------------------------------------------------------
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions GmbH
+ * Klein-Winternheim, Germany
+ *----------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/ic/ali512x.h>
+
+
+/* ALI M5123 Logical device numbers:
+ * 0 FDC
+ * 1 unused?
+ * 2 unused?
+ * 3 lpt
+ * 4 UART1
+ * 5 UART2
+ * 6 RTC
+ * 7 mouse/kbd
+ * 8 CIO
+ */
+
+/*
+ ************************************************************
+ * Some access primitives for the ALi chip: *
+ ************************************************************
+ */
+
+static void ali_write(u8 index, u8 value)
+{
+ /* write an arbirary register */
+ outb(index, ALI_INDEX);
+ outb(value, ALI_DATA);
+}
+
+static int ali_read(u8 index)
+{
+ outb(index, ALI_INDEX);
+ return inb(ALI_DATA);
+}
+
+#define ALI_OPEN() \
+ outb(0x51, ALI_DATA); \
+ outb(0x23, ALI_DATA)
+
+
+#define ALI_CLOSE() \
+ outb(0xbb, ALI_DATA)
+
+/* Select a logical device */
+#define ALI_SELDEV(dev) \
+ ali_write(0x07, dev)
+
+
+void ali512x_init(void)
+{
+ ALI_OPEN();
+
+ ali_write(0x02, 0x01); /* soft reset */
+ ali_write(0x03, 0x03); /* disable access to CIOs */
+ ali_write(0x22, 0x00); /* disable direct powerdown */
+ ali_write(0x23, 0x00); /* disable auto powerdown */
+ ali_write(0x24, 0x00); /* IR 8 is active hi, pin26 is PDIR */
+
+ ALI_CLOSE();
+}
+
+void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel)
+{
+ ALI_OPEN();
+ ALI_SELDEV(0);
+
+ ali_write(0x30, enabled?1:0);
+ if (enabled) {
+ ali_write(0x60, io >> 8);
+ ali_write(0x61, io & 0xff);
+ ali_write(0x70, irq);
+ ali_write(0x74, dma_channel);
+
+ /* AT mode, no drive swap */
+ ali_write(0xf0, 0x08);
+ ali_write(0xf1, 0x00);
+ ali_write(0xf2, 0xff);
+ ali_write(0xf4, 0x00);
+ }
+ ALI_CLOSE();
+}
+
+
+void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel)
+{
+ ALI_OPEN();
+ ALI_SELDEV(3);
+
+ ali_write(0x30, enabled?1:0);
+ if (enabled) {
+ ali_write(0x60, io >> 8);
+ ali_write(0x61, io & 0xff);
+ ali_write(0x70, irq);
+ ali_write(0x74, dma_channel);
+
+ /* mode: EPP 1.9, ECP FIFO threshold = 7, IRQ active low */
+ ali_write(0xf0, 0xbc);
+ /* 12 MHz, Burst DMA in ECP */
+ ali_write(0xf1, 0x05);
+ }
+ ALI_CLOSE();
+
+}
+
+void ali512x_set_uart(int enabled, int index, u16 io, u8 irq)
+{
+ ALI_OPEN();
+ ALI_SELDEV(index?5:4);
+
+ ali_write(0x30, enabled?1:0);
+ if (enabled) {
+ ali_write(0x60, io >> 8);
+ ali_write(0x61, io & 0xff);
+ ali_write(0x70, irq);
+
+ ali_write(0xf0, 0x00);
+ ali_write(0xf1, 0x00);
+
+ /* huh? write 0xf2 twice - a typo in rolo
+ * or some secret ali errata? Who knows?
+ */
+ if (index) {
+ ali_write(0xf2, 0x00);
+ }
+ ali_write(0xf2, 0x0c);
+ }
+ ALI_CLOSE();
+
+}
+
+void ali512x_set_uart2_irda(int enabled)
+{
+ ALI_OPEN();
+ ALI_SELDEV(5);
+
+ ali_write(0xf1, enabled?0x48:0x00); /* fullduplex IrDa */
+ ALI_CLOSE();
+
+}
+
+void ali512x_set_rtc(int enabled, u16 io, u8 irq)
+{
+ ALI_OPEN();
+ ALI_SELDEV(6);
+
+ ali_write(0x30, enabled?1:0);
+ if (enabled) {
+ ali_write(0x60, io >> 8);
+ ali_write(0x61, io & 0xff);
+ ali_write(0x70, irq);
+
+ ali_write(0xf0, 0x00);
+ }
+ ALI_CLOSE();
+}
+
+void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq)
+{
+ ALI_OPEN();
+ ALI_SELDEV(7);
+
+ ali_write(0x30, enabled?1:0);
+ if (enabled) {
+ ali_write(0x70, kbc_irq);
+ ali_write(0x72, mouse_irq);
+
+ ali_write(0xf0, 0x00);
+ }
+ ALI_CLOSE();
+}
+
+
+/* Common I/O
+ *
+ * (This descripotsion is base on several incompete sources
+ * since I have not been able to obtain any datasheet for the device
+ * there may be some mis-understandings burried in here.
+ * -- Daniel daniel@omicron.se)
+ *
+ * There are 22 CIO pins numbered
+ * 10-17
+ * 20-25
+ * 30-37
+ *
+ * 20-24 are dedicated CIO pins, the other 17 are muliplexed with
+ * other functions.
+ *
+ * Secondary
+ * CIO Pin Function Decription
+ * =======================================================
+ * CIO10 IRQIN1 Interrupt input 1?
+ * CIO11 IRQIN2 Interrupt input 2?
+ * CIO12 IRRX IrDa Receive
+ * CIO13 IRTX IrDa Transmit
+ * CIO14 P21 KBC P21 fucntion
+ * CIO15 P20 KBC P21 fucntion
+ * CIO16 I2C_CLK I2C Clock
+ * CIO17 I2C_DAT I2C Data
+ *
+ * CIO20 -
+ * CIO21 -
+ * CIO22 -
+ * CIO23 -
+ * CIO24 -
+ * CIO25 LOCK Keylock
+ *
+ * CIO30 KBC_CLK Keybaord Clock
+ * CIO31 CS0J General Chip Select decoder CS0J
+ * CIO32 CS1J General Chip Select decoder CS1J
+ * CIO33 ALT_KCLK Alternative Keyboard Clock
+ * CIO34 ALT_KDAT Alternative Keyboard Data
+ * CIO35 ALT_MCLK Alternative Mouse Clock
+ * CIO36 ALT_MDAT Alternative Mouse Data
+ * CIO37 ALT_KBC Alternative KBC select
+ *
+ * The CIO use a double indirect address scheme.
+ *
+ * Reigster 3 in the SIO is used to selectg where the CIO
+ * I/O registers show up under function 8. Note that these
+ * registers clash with the CIO function select regsters,
+ * below.
+ *
+ * SIO reigster 3 (CIO Address Selection) bit definitions:
+ * bit 7 CIO data register enabled
+ * bit 1-0 CIO indirect registers select
+ * 0 index = 0xE0 data = 0xE1
+ * 1 index = 0xE2 data = 0xE3
+ * 2 index = 0xE4 data = 0xE5
+ * 3 index = 0xEA data = 0xEB
+ *
+ * There are three CIO I/O register accessed via CIO index and CIO data
+ * 0x01 CIO 10-17 data
+ * 0x02 CIO 20-25 data (bits 7-6 unused)
+ * 0x03 CIO 30-37 data
+ *
+ *
+ * The pin function is accessed through normal
+ * SIO registers, each register have the same format:
+ *
+ * Bit Function Value
+ * 0 Input/output 1=input
+ * 1 Polarity of signal 1=inverted
+ * 2 Unused ??
+ * 3 Function (normal or special) 1=special
+ * 7-4 Unused
+ *
+ * SIO REG
+ * 0xe0 CIO 10 Config
+ * 0xe1 CIO 11 Config
+ * 0xe2 CIO 12 Config
+ * 0xe3 CIO 13 Config
+ * 0xe4 CIO 14 Config
+ * 0xe5 CIO 15 Config
+ * 0xe6 CIO 16 Config
+ * 0xe7 CIO 16 Config
+ *
+ * 0xe8 CIO 20 Config
+ * 0xe9 CIO 21 Config
+ * 0xea CIO 22 Config
+ * 0xeb CIO 23 Config
+ * 0xec CIO 24 Config
+ * 0xed CIO 25 Config
+ *
+ * 0xf5 CIO 30 Config
+ * 0xf6 CIO 31 Config
+ * 0xf7 CIO 32 Config
+ * 0xf8 CIO 33 Config
+ * 0xf9 CIO 34 Config
+ * 0xfa CIO 35 Config
+ * 0xfb CIO 36 Config
+ * 0xfc CIO 37 Config
+ *
+ */
+
+void ali512x_set_cio(int enabled)
+{
+ int i;
+
+ ALI_OPEN();
+ ali_write(0x3, 3); /* Disable CIO data register */
+
+ ALI_SELDEV(8);
+ ali_write(0x30, enabled?1:0);
+
+ /* set all pins to input to start with */
+ for (i=0xe0;i<0xee;i++) {
+ ali_write(i, 1);
+ }
+ for (i=0xf5;i<0xfe;i++) {
+ ali_write(i, 1);
+ }
+
+ ALI_CLOSE();
+}
+
+void ali512x_cio_function(int pin, int special, int inv, int input)
+{
+ u8 data;
+ u8 addr;
+
+
+ /* valid pins are 10-17, 20-25 and 30-37 */
+ if (pin >= 10 && pin <= 17) {
+ addr = 0xe0+(pin-10);
+ } else if (pin >= 20 && pin <= 25) {
+ addr = 0xe8+(pin-20);
+ } else if (pin >= 30 && pin <= 37) {
+ addr = 0xf5+(pin-30);
+ } else {
+ return;
+ }
+
+ ALI_OPEN();
+ ALI_SELDEV(8);
+
+ ali_write(0x03, 0x03); /* Disable CIO data register */
+
+ data=0;
+ if (special) {
+ data |= 0x08;
+ } else {
+ if (inv) {
+ data |= 0x02;
+ }
+ if (input) {
+ data |= 0x01;
+ }
+ }
+
+ ali_write(addr, data);
+
+ ALI_CLOSE();
+}
+
+void ali512x_cio_out(int pin, int value)
+{
+ u8 reg;
+ u8 data;
+ u8 bit;
+
+ /* valid pins are 10-17, 20-25 and 30-37 */
+ if (pin >= 10 && pin <= 17) {
+ reg = 1;
+ pin -= 10;
+ } else if (pin >= 20 && pin <= 25) {
+ reg = 2;
+ pin -= 20;
+ } else if (pin >= 30 && pin <= 37) {
+ reg = 3;
+ pin -= 30;
+ } else {
+ return;
+ }
+ bit = 1 << pin;
+
+ ALI_OPEN();
+ ALI_SELDEV(8);
+
+ ali_write(0x03, 0x83); /* Enable CIO data register, use data port at 0xea */
+
+ ali_write(0xea, reg); /* select I/O register */
+ data = ali_read(0xeb);
+ if (value) {
+ data |= bit;
+ } else {
+ data &= ~bit;
+ }
+ ali_write(0xeb, data);
+ ali_write(0xea, 0); /* select register 0 */
+ ali_write(0x03, 0x03); /* Disable CIO data register */
+ ALI_CLOSE();
+}
+
+int ali512x_cio_in(int pin)
+{
+ u8 reg;
+ u8 data;
+ u8 bit;
+
+ /* valid pins are 10-17, 20-25 and 30-37 */
+ if (pin >= 10 && pin <= 17) {
+ reg = 1;
+ pin -= 10;
+ } else if (pin >= 20 && pin <= 25) {
+ reg = 2;
+ pin -= 20;
+ } else if (pin >= 30 && pin <= 37) {
+ reg = 3;
+ pin -= 30;
+ } else {
+ return -1;
+ }
+ bit = 1 << pin;
+
+ ALI_OPEN();
+ ALI_SELDEV(8);
+
+ ali_write(0x03, 0x83); /* Enable CIO data register, use data port at 0xea */
+
+ ali_write(0xea, reg); /* select I/O register */
+ data = ali_read(0xeb);
+ ali_write(0xea, 0); /* select register 0 */
+ ali_write(0x03, 0x03); /* Disable CIO data register */
+ ALI_CLOSE();
+
+ return data & bit;
+}
+
+
diff --git a/lib_i386/ic/sc520.c b/lib_i386/ic/sc520.c
new file mode 100644
index 0000000..d202625
--- /dev/null
+++ b/lib_i386/ic/sc520.c
@@ -0,0 +1,348 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* stuff specific for the sc520,
+ * but idependent of implementation */
+
+
+#include <common.h>
+#include <config.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/ic/sc520.h>
+
+/*
+ * utility functions for boards based on the AMD sc520
+ *
+ * void write_mmcr_byte(u16 mmcr, u8 data)
+ * void write_mmcr_word(u16 mmcr, u16 data)
+ * void write_mmcr_long(u16 mmcr, u32 data)
+ *
+ * u8 read_mmcr_byte(u16 mmcr)
+ * u16 read_mmcr_word(u16 mmcr)
+ * u32 read_mmcr_long(u16 mmcr)
+ *
+ * void init_sc520(void)
+ * unsigned long init_sc520_dram(void)
+ * void pci_sc520_init(struct pci_controller *hose)
+ *
+ * void reset_timer(void)
+ * ulong get_timer(ulong base)
+ * void set_timer(ulong t)
+ * void udelay(unsigned long usec)
+ *
+ */
+
+static u32 mmcr_base= 0xfffef000;
+
+void write_mmcr_byte(u16 mmcr, u8 data)
+{
+ writeb(data, mmcr+mmcr_base);
+}
+
+void write_mmcr_word(u16 mmcr, u16 data)
+{
+ writew(data, mmcr+mmcr_base);
+}
+
+void write_mmcr_long(u16 mmcr, u32 data)
+{
+ writel(data, mmcr+mmcr_base);
+}
+
+u8 read_mmcr_byte(u16 mmcr)
+{
+ return readb(mmcr+mmcr_base);
+}
+
+u16 read_mmcr_word(u16 mmcr)
+{
+ return readw(mmcr+mmcr_base);
+}
+
+u32 read_mmcr_long(u16 mmcr)
+{
+ return readl(mmcr+mmcr_base);
+}
+
+
+void init_sc520(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /* Set the UARTxCTL register at it's slower,
+ * baud clock giving us a 1.8432 MHz reference
+ */
+ write_mmcr_byte(SC520_UART1CTL, 7);
+ write_mmcr_byte(SC520_UART2CTL, 7);
+
+ /* first set the timer pin mapping */
+ write_mmcr_byte(SC520_CLKSEL, 0x72); /* no clock frequency selected, use 1.1892MHz */
+
+ /* enable PCI bus arbitrer */
+ write_mmcr_byte(SC520_SYSARBCTL,0x02); /* enable concurrent mode */
+
+ write_mmcr_word(SC520_SYSARBMENB,0x1f); /* enable external grants */
+ write_mmcr_word(SC520_HBCTL,0x04); /* enable posted-writes */
+
+
+ if (CFG_SC520_HIGH_SPEED) {
+ write_mmcr_byte(SC520_CPUCTL, 0x2); /* set it to 133 MHz and write back */
+ gd->cpu_clk = 133000000;
+ printf("## CPU Speed set to 133MHz\n");
+ } else {
+ write_mmcr_byte(SC520_CPUCTL, 1); /* set CPU to 100 MHz and write back cache */
+ printf("## CPU Speed set to 100MHz\n");
+ gd->cpu_clk = 100000000;
+ }
+
+
+ /* wait at least one millisecond */
+ asm("movl $0x2000,%%ecx\n"
+ "wait_loop: pushl %%ecx\n"
+ "popl %%ecx\n"
+ "loop wait_loop\n": : : "ecx");
+
+ /* turn on the SDRAM write buffer */
+ write_mmcr_byte(SC520_DBCTL, 0x11);
+
+ /* turn on the cache and disable write through */
+ asm("movl %%cr0, %%eax\n"
+ "andl $0x9fffffff, %%eax\n"
+ "movl %%eax, %%cr0\n" : : : "eax");
+}
+
+unsigned long init_sc520_dram(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ bd_t *bd = gd->bd;
+
+ u32 dram_present=0;
+ u32 dram_ctrl;
+
+ int val;
+
+ int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY;
+ int refresh_rate = CFG_SDRAM_REFRESH_RATE;
+ int ras_cas_delay = CFG_SDRAM_RAS_CAS_DELAY;
+
+ /* set SDRAM speed here */
+
+ refresh_rate/=78;
+ if (refresh_rate<=1) {
+ val = 0; /* 7.8us */
+ } else if (refresh_rate==2) {
+ val = 1; /* 15.6us */
+ } else if (refresh_rate==3 || refresh_rate==4) {
+ val = 2; /* 31.2us */
+ } else {
+ val = 3; /* 62.4us */
+ }
+ write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
+
+ val = read_mmcr_byte(SC520_DRCTMCTL);
+ val &= 0xf0;
+
+ if (cas_precharge_delay==3) {
+ val |= 0x04; /* 3T */
+ } else if (cas_precharge_delay==4) {
+ val |= 0x08; /* 4T */
+ } else if (cas_precharge_delay>4) {
+ val |= 0x0c;
+ }
+
+ if (ras_cas_delay > 3) {
+ val |= 2;
+ } else {
+ val |= 1;
+ }
+ write_mmcr_byte(SC520_DRCTMCTL, val);
+
+
+ /* We read-back the configuration of the dram
+ * controller that the assembly code wrote */
+ dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
+
+
+ bd->bi_dram[0].start = 0;
+ if (dram_ctrl & 0x80) {
+ /* bank 0 enabled */
+ dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
+ bd->bi_dram[0].size = bd->bi_dram[1].start;
+
+ } else {
+ bd->bi_dram[0].size = 0;
+ bd->bi_dram[1].start = bd->bi_dram[0].start;
+ }
+
+ if (dram_ctrl & 0x8000) {
+ /* bank 1 enabled */
+ dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
+ bd->bi_dram[1].size = bd->bi_dram[2].start - bd->bi_dram[1].start;
+ } else {
+ bd->bi_dram[1].size = 0;
+ bd->bi_dram[2].start = bd->bi_dram[1].start;
+ }
+
+ if (dram_ctrl & 0x800000) {
+ /* bank 2 enabled */
+ dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
+ bd->bi_dram[2].size = bd->bi_dram[3].start - bd->bi_dram[2].start;
+ } else {
+ bd->bi_dram[2].size = 0;
+ bd->bi_dram[3].start = bd->bi_dram[2].start;
+ }
+
+ if (dram_ctrl & 0x80000000) {
+ /* bank 3 enabled */
+ dram_present = (dram_ctrl & 0x7f000000) >> 2;
+ bd->bi_dram[3].size = dram_present - bd->bi_dram[3].start;
+ } else {
+ bd->bi_dram[3].size = 0;
+ }
+
+
+#if 0
+ printf("Configured %d bytes of dram\n", dram_present);
+#endif
+ gd->ram_size = dram_present;
+
+ return dram_present;
+}
+
+
+#ifdef CONFIG_PCI
+
+
+
+void pci_sc520_init(struct pci_controller *hose)
+{
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ /* System memory space */
+ pci_set_region(hose->regions + 0,
+ SC520_PCI_MEMORY_BUS,
+ SC520_PCI_MEMORY_PHYS,
+ SC520_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 1,
+ SC520_PCI_MEM_BUS,
+ SC520_PCI_MEM_PHYS,
+ SC520_PCI_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* ISA/PCI memory space */
+ pci_set_region(hose->regions + 2,
+ SC520_ISA_MEM_BUS,
+ SC520_ISA_MEM_PHYS,
+ SC520_ISA_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* PCI I/O space */
+ pci_set_region(hose->regions + 3,
+ SC520_PCI_IO_BUS,
+ SC520_PCI_IO_PHYS,
+ SC520_PCI_IO_SIZE,
+ PCI_REGION_IO);
+
+ /* ISA/PCI I/O space */
+ pci_set_region(hose->regions + 4,
+ SC520_ISA_IO_BUS,
+ SC520_ISA_IO_PHYS,
+ SC520_ISA_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 5;
+
+ pci_setup_type1(hose,
+ SC520_REG_ADDR,
+ SC520_REG_DATA);
+
+ pci_register_hose(hose);
+
+ hose->last_busno = pci_hose_scan(hose);
+
+ /* enable target memory acceses on host brige */
+ pci_write_config_word(0, PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+}
+
+
+#endif
+
+#ifdef CFG_TIMER_SC520
+
+
+void reset_timer(void)
+{
+ write_mmcr_word(SC520_GPTMR0CNT, 0);
+ write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
+
+}
+
+ulong get_timer(ulong base)
+{
+ /* fixme: 30 or 33 */
+ return read_mmcr_word(SC520_GPTMR0CNT) / 33;
+}
+
+void set_timer(ulong t)
+{
+ /* FixMe: use two cascade coupled timers */
+ write_mmcr_word(SC520_GPTMR0CTL, 0x4001);
+ write_mmcr_word(SC520_GPTMR0CNT, t*33);
+ write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
+}
+
+
+void udelay(unsigned long usec)
+{
+ int m=0;
+ long u;
+
+ read_mmcr_word(SC520_SWTMRMILLI);
+ read_mmcr_word(SC520_SWTMRMICRO);
+
+#if 0
+ /* do not enable this line, udelay is used in the serial driver -> recursion */
+ printf("udelay: %ld m.u %d.%d tm.tu %d.%d\n", usec, m, u, tm, tu);
+#endif
+ while (1) {
+
+ m += read_mmcr_word(SC520_SWTMRMILLI);
+ u = read_mmcr_word(SC520_SWTMRMICRO) + (m * 1000);
+
+ if (usec <= u) {
+ break;
+ }
+ }
+}
+
+#endif
+
+
diff --git a/lib_i386/ic/sc520_asm.S b/lib_i386/ic/sc520_asm.S
new file mode 100644
index 0000000..72110c4
--- /dev/null
+++ b/lib_i386/ic/sc520_asm.S
@@ -0,0 +1,530 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This file is largely based on code obtned from AMD. AMD's original
+ * copyright is included below
+ */
+
+/*
+ * =============================================================================
+ *
+ * Copyright 1999 Advanced Micro Devices, Inc.
+ *
+ * This software is the property of Advanced Micro Devices, Inc (AMD) which
+ * specifically grants the user the right to modify, use and distribute this
+ * software provided this COPYRIGHT NOTICE is not removed or altered. All
+ * other rights are reserved by AMD.
+ *
+ * THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY
+ * OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF
+ * THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE.
+ * IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, LOSS OF INFORMAITON) ARISING OUT OF THE USE OF OR INABILITY
+ * TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGES. BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR
+ * LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
+ * LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors that may appear in
+ * the Materials nor any responsibility to support or update the Materials.
+ * AMD retains the right to make changes to its test specifications at any
+ * time, without notice.
+ *
+ * So that all may benefit from your experience, please report any problems
+ * or suggestions about this software back to AMD. Please include your name,
+ * company, telephone number, AMD product requiring support and question or
+ * problem encountered.
+ *
+ * Advanced Micro Devices, Inc. Worldwide support and contact
+ * Embedded Processor Division information available at:
+ * Systems Engineering epd.support@amd.com
+ * 5204 E. Ben White Blvd. -or-
+ * Austin, TX 78741 http://www.amd.com/html/support/techsup.html
+ * ============================================================================
+ */
+
+
+/*******************************************************************************
+ * AUTHOR : Buddy Fey - Original.
+ *******************************************************************************
+ */
+
+
+/*******************************************************************************
+ * FUNCTIONAL DESCRIPTION:
+ * This routine is called to autodetect the geometry of the DRAM.
+ *
+ * This routine is called to determine the number of column bits for the DRAM
+ * devices in this external bank. This routine assumes that the external bank
+ * has been configured for an 11-bit column and for 4 internal banks. This gives
+ * us the maximum address reach in memory. By writing a test value to the max
+ * address and locating where it aliases to, we can determine the number of valid
+ * column bits.
+ *
+ * This routine is called to determine the number of internal banks each DRAM
+ * device has. The external bank (under test) is configured for maximum reach
+ * with 11-bit columns and 4 internal banks. This routine will write to a max
+ * address (BA1 and BA0 = 1) and then read from an address with BA1=0 to see if
+ * that column is a "don't care". If BA1 does not affect write/read of data,
+ * then this device has only 2 internal banks.
+ *
+ * This routine is called to determine the ending address for this external
+ * bank of SDRAM. We write to a max address with a data value and then disable
+ * row address bits looking for "don't care" locations. Each "don't care" bit
+ * represents a dividing of the maximum density (128M) by 2. By dividing the
+ * maximum of 32 4M chunks in an external bank down by all the "don't care" bits
+ * determined during sizing, we set the proper density.
+ *
+ * WARNINGS.
+ * bp must be preserved because it is used for return linkage.
+ *
+ * EXIT
+ * nothing returned - but the memory subsystem is enabled
+ *******************************************************************************
+ */
+
+.section .text
+.equ DRCCTL, 0x0fffef010 /* DRAM control register */
+.equ DRCTMCTL, 0x0fffef012 /* DRAM timing control register */
+.equ DRCCFG, 0x0fffef014 /* DRAM bank configuration register */
+.equ DRCBENDADR, 0x0fffef018 /* DRAM bank ending address register */
+.equ ECCCTL, 0x0fffef020 /* DRAM ECC control register */
+.equ DBCTL, 0x0fffef040 /* DRAM buffer control register */
+
+.equ CACHELINESZ, 0x00000010 /* size of our cache line (read buffer) */
+.equ COL11_ADR, 0x0e001e00 /* 11 col addrs */
+.equ COL10_ADR, 0x0e000e00 /* 10 col addrs */
+.equ COL09_ADR, 0x0e000600 /* 9 col addrs */
+.equ COL08_ADR, 0x0e000200 /* 8 col addrs */
+.equ ROW14_ADR, 0x0f000000 /* 14 row addrs */
+.equ ROW13_ADR, 0x07000000 /* 13 row addrs */
+.equ ROW12_ADR, 0x03000000 /* 12 row addrs */
+.equ ROW11_ADR, 0x01000000 /* 11 row addrs/also bank switch */
+.equ ROW10_ADR, 0x00000000 /* 10 row addrs/also bank switch */
+.equ COL11_DATA, 0x0b0b0b0b /* 11 col addrs */
+.equ COL10_DATA, 0x0a0a0a0a /* 10 col data */
+.equ COL09_DATA, 0x09090909 /* 9 col data */
+.equ COL08_DATA, 0x08080808 /* 8 col data */
+.equ ROW14_DATA, 0x3f3f3f3f /* 14 row data (MASK) */
+.equ ROW13_DATA, 0x1f1f1f1f /* 13 row data (MASK) */
+.equ ROW12_DATA, 0x0f0f0f0f /* 12 row data (MASK) */
+.equ ROW11_DATA, 0x07070707 /* 11 row data/also bank switch (MASK) */
+.equ ROW10_DATA, 0xaaaaaaaa /* 10 row data/also bank switch (MASK) */
+
+
+ /*
+ * initialize dram controller registers
+ */
+.globl mem_init
+mem_init:
+ xorw %ax,%ax
+ movl $DBCTL, %edi
+fs movb %al, (%edi) /* disable write buffer */
+
+ movl $ECCCTL, %edi
+fs movb %al, (%edi) /* disable ECC */
+
+ movl $DRCTMCTL, %edi
+ movb $0x1E,%al /* Set SDRAM timing for slowest */
+fs movb %al, (%edi)
+
+ /*
+ * setup loop to do 4 external banks starting with bank 3
+ */
+ movl $0xff000000,%eax /* enable last bank and setup */
+ movl $DRCBENDADR, %edi /* ending address register */
+fs movl %eax, (%edi)
+
+ movl $DRCCFG, %edi /* setup */
+ movw $0xbbbb,%ax /* dram config register for */
+fs movw %ax, (%edi)
+
+ /*
+ * issue a NOP to all DRAMs
+ */
+ movl $DRCCTL, %edi /* setup DRAM control register with */
+ movb $0x1,%al /* Disable refresh,disable write buffer */
+fs movb %al, (%edi)
+ movl $CACHELINESZ, %esi /* just a dummy address to write for */
+fs movw %ax, (%esi)
+ /*
+ * delay for 100 usec? 200?
+ * ******this is a cludge for now *************
+ */
+ movw $100,%cx
+sizdelay:
+ loop sizdelay /* we need 100 usec here */
+ /***********************************************/
+
+ /*
+ * issue all banks precharge
+ */
+ movb $0x2,%al /* All banks precharge */
+fs movb %al, (%edi)
+fs movw %ax, (%esi)
+
+ /*
+ * issue 2 auto refreshes to all banks
+ */
+ movb $0x4,%al /* Auto refresh cmd */
+fs movb %al, (%edi)
+ movw $2,%cx
+refresh1:
+fs movw %ax, (%esi)
+ loop refresh1
+
+ /*
+ * issue LOAD MODE REGISTER command
+ */
+ movb $0x3,%al /* Load mode register cmd */
+fs movb %al, (%edi)
+fs movw %ax, (%esi)
+
+ /*
+ * issue 8 more auto refreshes to all banks
+ */
+ movb $0x4,%al /* Auto refresh cmd */
+fs movb %al, (%edi)
+ movw $8,%cx
+refresh2:
+fs movw %ax, (%esi)
+ loop refresh2
+
+ /*
+ * set control register to NORMAL mode
+ */
+ movb $0x0,%al /* Normal mode value */
+fs movb %al, (%edi)
+
+ /*
+ * size dram starting with external bank 3 moving to external bank 0
+ */
+ movl $0x3,%ecx /* start with external bank 3 */
+
+nextbank:
+
+ /*
+ * write col 11 wrap adr
+ */
+ movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
+ movl $COL11_DATA, %eax /* pattern for max supported columns(11) */
+fs movl %eax, (%esi) /* write max col pattern at max col adr */
+fs movl (%esi), %ebx /* optional read */
+ cmpl %ebx,%eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+ /*
+ * write col 10 wrap adr
+ */
+
+ movl $COL10_ADR, %esi /* set address to 10 col wrap address */
+ movl $COL10_DATA, %eax /* pattern for 10 col wrap */
+fs movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */
+fs movl (%esi), %ebx /* optional read */
+ cmpl %ebx,%eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+ /*
+ * write col 9 wrap adr
+ */
+ movl $COL09_ADR, %esi /* set address to 9 col wrap address */
+ movl $COL09_DATA, %eax /* pattern for 9 col wrap */
+fs movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */
+fs movl (%esi), %ebx /* optional read */
+ cmpl %ebx,%eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+ /*
+ * write col 8 wrap adr
+ */
+ movl $COL08_ADR, %esi /* set address to min(8) col wrap address */
+ movl $COL08_DATA, %eax /* pattern for min (8) col wrap */
+fs movl %eax, (%esi) /* write min col pattern @ min col adr */
+fs movl (%esi), %ebx /* optional read */
+ cmpl %ebx,%eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+ /*
+ * write row 14 wrap adr
+ */
+ movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */
+ movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */
+fs movl %eax, (%esi) /* write max row pattern at max row adr */
+fs movl (%esi), %ebx /* optional read */
+ cmpl %ebx,%eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+ /*
+ * write row 13 wrap adr
+ */
+ movl $ROW13_ADR, %esi /* set address to 13 row wrap address */
+ movl $ROW13_DATA, %eax /* pattern for 13 row wrap */
+fs movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */
+fs movl (%esi), %ebx /* optional read */
+ cmpl %ebx,%eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+ /*
+ * write row 12 wrap adr
+ */
+ movl $ROW12_ADR, %esi /* set address to 12 row wrap address */
+ movl $ROW12_DATA, %eax /* pattern for 12 row wrap */
+fs movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */
+fs movl (%esi), %ebx /* optional read */
+ cmpl %ebx,%eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+ /*
+ * write row 11 wrap adr
+ */
+ movl $ROW11_ADR, %edi /* set address to 11 row wrap address */
+ movl $ROW11_DATA, %eax /* pattern for 11 row wrap */
+fs movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */
+fs movl (%edi), %ebx /* optional read */
+ cmpl %ebx,%eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+ /*
+ * write row 10 wrap adr --- this write is really to determine number of banks
+ */
+ movl $ROW10_ADR, %edi /* set address to 10 row wrap address */
+ movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */
+fs movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */
+fs movl (%edi), %ebx /* optional read */
+ cmpl %ebx,%eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+ /*
+ * read data @ row 12 wrap adr to determine * banks,
+ * and read data @ row 14 wrap adr to determine * rows.
+ * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
+ * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
+ * if data @ row 12 wrap == 11 or 12, we have 4 banks,
+ */
+ xorw %di,%di /* value for 2 banks in DI */
+fs movl (%esi), %ebx /* read from 12 row wrap to check banks
+ * (esi is setup from the write to row 12 wrap) */
+ cmpl %ebx,%eax /* check for AA pattern (eax holds the aa pattern) */
+ jz only2 /* if pattern == AA, we only have 2 banks */
+
+ /* 4 banks */
+
+ movw $8,%di /* value for 4 banks in DI (BNK_CNT bit) */
+ cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */
+ jz only2
+ cmpl $ROW12_DATA, %ebx /* and 12 */
+ jnz bad_ram /* its bad if not 11 or 12! */
+
+ /* fall through */
+only2:
+ /*
+ * validate row mask
+ */
+ movl $ROW14_ADR, %esi /* set address back to max row wrap addr */
+fs movl (%esi), %eax /* read actual number of rows @ row14 adr */
+
+ cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */
+ jb bad_ram
+
+ cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */
+ ja bad_ram
+
+ cmpb %ah,%al /* verify all 4 bytes of dword same */
+ jnz bad_ram
+ movl %eax,%ebx
+ shrl $16,%ebx
+ cmpw %bx,%ax
+ jnz bad_ram
+ /*
+ * read col 11 wrap adr for real column data value
+ */
+ movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
+fs movl (%esi), %eax /* read real col number at max col adr */
+ /*
+ * validate column data
+ */
+ cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */
+ jb bad_ram
+
+ cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */
+ ja bad_ram
+
+ subl $COL08_DATA, %eax /* normalize column data to zero */
+ jc bad_ram
+ cmpb %ah,%al /* verify all 4 bytes of dword equal */
+ jnz bad_ram
+ movl %eax,%edx
+ shrl $16,%edx
+ cmpw %dx,%ax
+ jnz bad_ram
+ /*
+ * merge bank and col data together
+ */
+ addw %di,%dx /* merge of bank and col info in dl */
+ /*
+ * fix ending addr mask based upon col info
+ */
+ movb $3,%al
+ subb %dh,%al /* dh contains the overflow from the bank/col merge */
+ movb %bl,%dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */
+ xchgw %cx,%ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */
+ shrb %cl,%dh /* */
+ incb %dh /* ending addr is 1 greater than real end */
+ xchgw %cx,%ax /* cx is bank number again */
+ /*
+ * issue all banks precharge
+ */
+bad_reint:
+ movl $DRCCTL, %esi /* setup DRAM control register with */
+ movb $0x2,%al /* All banks precharge */
+fs movb %al, (%esi)
+ movl $CACHELINESZ, %esi /* address to init read buffer */
+fs movw %ax, (%esi)
+
+ /*
+ * update ENDING ADDRESS REGISTER
+ */
+ movl $DRCBENDADR, %edi /* DRAM ending address register */
+ movl %ecx,%ebx
+ addl %ebx, %edi
+fs movb %dh, (%edi)
+ /*
+ * update CONFIG REGISTER
+ */
+ xorb %dh,%dh
+ movw $0x00f,%bx
+ movw %cx,%ax
+ shlw $2,%ax
+ xchgw %cx,%ax
+ shlw %cl,%dx
+ shlw %cl,%bx
+ notw %bx
+ xchgw %cx,%ax
+ movl $DRCCFG, %edi
+fs mov (%edi), %ax
+ andw %bx,%ax
+ orw %dx,%ax
+fs movw %ax, (%edi)
+ jcxz cleanup
+
+ decw %cx
+ movl %ecx,%ebx
+ movl $DRCBENDADR, %edi /* DRAM ending address register */
+ movb $0xff,%al
+ addl %ebx, %edi
+fs movb %al, (%edi)
+ /*
+ * set control register to NORMAL mode
+ */
+ movl $DRCCTL, %esi /* setup DRAM control register with */
+ movb $0x0,%al /* Normal mode value */
+fs movb %al, (%esi)
+ movl $CACHELINESZ, %esi /* address to init read buffer */
+fs movw %ax, (%esi)
+ jmp nextbank
+
+cleanup:
+ movl $DRCBENDADR, %edi /* DRAM ending address register */
+ movw $4,%cx
+ xorw %ax,%ax
+cleanuplp:
+fs movb (%edi), %al
+ orb %al,%al
+ jz emptybank
+
+ addb %ah,%al
+ jns nottoomuch
+
+ movb $0x7f,%al
+nottoomuch:
+ movb %al,%ah
+ orb $0x80,%al
+fs movb %al, (%edi)
+emptybank:
+ incl %edi
+ loop cleanuplp
+
+#if defined(CFG_SDRAM_CAS_LATENCY_2T) || defined(CFG_SDRAM_CAS_LATENCY_3T)
+ /* set the CAS latency now since it is hard to do
+ * when we run from the RAM */
+ movl $DRCTMCTL, %edi /* DRAM timing register */
+ movb (%edi), %al
+#ifdef CFG_SDRAM_CAS_LATENCY_2T
+ andb $0xef, %al
+#endif
+#ifdef CFG_SDRAM_CAS_LATENCY_3T
+ orb $0x10, %al
+#endif
+ movb %al, (%edi)
+#endif
+ movl $DRCCTL, %edi /* DRAM Control register */
+ movb $0x3,%al /* Load mode register cmd */
+fs movb %al, (%edi)
+fs movw %ax, (%esi)
+
+
+ movl $DRCCTL, %edi /* DRAM Control register */
+ movb $0x18,%al /* Enable refresh and NORMAL mode */
+fs movb %al, (%edi)
+
+ jmp dram_done
+
+bad_ram:
+ xorl %edx,%edx
+ xorl %edi,%edi
+ jmp bad_reint
+
+dram_done:
+
+ /* readback DRCBENDADR and return the number
+ * of available ram bytes in %eax */
+
+ movl $DRCBENDADR, %edi /* DRAM ending address register */
+
+ movl (%edi), %eax
+ movl %eax, %ecx
+ andl $0x80000000, %ecx
+ jz bank2
+ andl $0x7f000000, %eax
+ shrl $2, %eax
+ movl %eax, %ebx
+
+bank2: movl (%edi), %eax
+ movl %eax, %ecx
+ andl $0x00800000, %ecx
+ jz bank1
+ andl $0x007f0000, %eax
+ shll $6, %eax
+ movl %eax, %ebx
+
+bank1: movl (%edi), %eax
+ movl %eax, %ecx
+ andl $0x00008000, %ecx
+ jz bank0
+ andl $0x00007f00, %eax
+ shll $14, %eax
+ movl %eax, %ebx
+
+bank0: movl (%edi), %eax
+ movl %eax, %ecx
+ andl $0x00000080, %ecx
+ jz done
+ andl $0x0000007f, %eax
+ shll $22, %eax
+ movl %eax, %ebx
+
+done: movl %ebx, %eax
+
+ jmp *%ebp