| commit | 317a47c385960886fb4a02aa7b2585fe7191b0e2 | [log] [tgz] |
|---|---|---|
| author | Thierry Reding <treding@nvidia.com> | Mon Apr 15 11:32:15 2019 +0200 |
| committer | Tom Warren <twarren@nvidia.com> | Wed Jun 05 09:16:32 2019 -0700 |
| tree | fa0f127fb8dae876ca8eb410a0c38b8575cab4d8 | |
| parent | f05618254a7f3a039484d45688ae0522609b9daf [diff] |
ARM: tegra: Fix mux type for disp1 and disp2 clocks on Tegra210 On Tegra210 the parents for the disp1 and disp2 clocks are slightly different from earlier chips. Only pll_p, pll_d_out0, pll_d2_out0 and clk_m are valid parents (technically pll_d_out is as well, but U-Boot doesn't know anything about it). Fix up the type name and the mux definition. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>