tree eb3579513553a870fac0ec44e5f9b6db0d88ef53
parent e5be4137309faf7f0ebd74eb9df9bafae7e7005e
author Akshay Saraswat <akshay.s@samsung.com> 1424419034 +0530
committer Minkyu Kang <mk7.kang@samsung.com> 1425114226 +0900

Exynos542x: Add workaround for ARM errata 799270

This patch adds workaround for the ARM errata 799270 which says
"If the L2 cache logic clock is stopped because of L2 inactivity,
setting or clearing the ACTLR.SMP bit might not be effective. The bit is
modified in the ACTLR, meaning a read of the register returns the
updated value. However the logic that uses that bit retains the previous
value."

Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>