diff --git a/cpu/mpc8260/bedbug_603e.c b/cpu/mpc8260/bedbug_603e.c
index 1ca057f..9c29b35 100644
--- a/cpu/mpc8260/bedbug_603e.c
+++ b/cpu/mpc8260/bedbug_603e.c
@@ -5,8 +5,7 @@
 #include <common.h>
 #include <command.h>
 #include <linux/ctype.h>
-
-#include <cmd_bedbug.h>
+#include <bedbug/type.h>
 #include <bedbug/bedbug.h>
 #include <bedbug/regs.h>
 #include <bedbug/ppc.h>
@@ -64,7 +63,7 @@
  * ====================================================================== */
 
 void bedbug603e_do_break (cmd_tbl_t *cmdtp, int flag, int argc,
-                         char *argv[])
+			 char *argv[])
 {
   long		addr;           /* Address to break at  */
   int		which_bp;       /* Breakpoint number    */
@@ -116,8 +115,8 @@
   /* Set a breakpoint at the address */
 
   if(!(( isdigit( argv[ 1 ][ 0 ] )) ||
-        (( argv[ 1 ][ 0 ] >= 'a' ) && ( argv[ 1 ][ 0 ] <= 'f' )) ||
-        (( argv[ 1 ][ 0 ] >= 'A' ) && ( argv[ 1 ][ 0 ] <= 'F' ))))
+	(( argv[ 1 ][ 0 ] >= 'a' ) && ( argv[ 1 ][ 0 ] <= 'f' )) ||
+	(( argv[ 1 ][ 0 ] >= 'A' ) && ( argv[ 1 ][ 0 ] <= 'F' ))))
   {
     printf ("Usage:\n%s\n", cmdtp->usage);
     return;
@@ -236,4 +235,3 @@
 
 /* ====================================================================== */
 #endif
-
diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c
index b8ba48c..7662fc6 100644
--- a/cpu/mpc8260/cpu.c
+++ b/cpu/mpc8260/cpu.c
@@ -180,7 +180,7 @@
 /* ------------------------------------------------------------------------- */
 
 int
-do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
+do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	ulong msr, addr;
 
diff --git a/cpu/mpc8260/cpu_init.c b/cpu/mpc8260/cpu_init.c
index d0545cf..fd09a8d 100644
--- a/cpu/mpc8260/cpu_init.c
+++ b/cpu/mpc8260/cpu_init.c
@@ -70,13 +70,13 @@
 			uint tpmsk = ~pmsk;
 
 			/*
-                         * the (somewhat confused) paragraph at the
-                         * bottom of page 35-5 warns that there might
-                         * be "unknown behaviour" when programming
-                         * PSORx and PDIRx, if PPARx = 1, so I
-                         * decided this meant I had to disable the
-                         * dedicated function first, and enable it
-                         * last.
+			 * the (somewhat confused) paragraph at the
+			 * bottom of page 35-5 warns that there might
+			 * be "unknown behaviour" when programming
+			 * PSORx and PDIRx, if PPARx = 1, so I
+			 * decided this meant I had to disable the
+			 * dedicated function first, and enable it
+			 * last.
 			 */
 			iop->ppar &= tpmsk;
 			iop->psor = (iop->psor & tpmsk) | psor;
diff --git a/cpu/mpc8260/ether_scc.c b/cpu/mpc8260/ether_scc.c
index 8b6af31..10133fa 100644
--- a/cpu/mpc8260/ether_scc.c
+++ b/cpu/mpc8260/ether_scc.c
@@ -43,31 +43,31 @@
 #  define CPM_CR_ENET_PAGE      CPM_CR_SCC1_PAGE
 #  define CPM_CR_ENET_SBLOCK    CPM_CR_SCC1_SBLOCK
 #  define CMXSCR_MASK          (CMXSCR_SC1          |\
-                                CMXSCR_RS1CS_MSK    |\
-                                CMXSCR_TS1CS_MSK)
+				CMXSCR_RS1CS_MSK    |\
+				CMXSCR_TS1CS_MSK)
 
 #elif (CONFIG_ETHER_INDEX == 2)
 #  define PROFF_ENET            PROFF_SCC2
 #  define CPM_CR_ENET_PAGE      CPM_CR_SCC2_PAGE
 #  define CPM_CR_ENET_SBLOCK    CPM_CR_SCC2_SBLOCK
 #  define CMXSCR_MASK          (CMXSCR_SC2          |\
-                                CMXSCR_RS2CS_MSK    |\
-                                CMXSCR_TS2CS_MSK)
+				CMXSCR_RS2CS_MSK    |\
+				CMXSCR_TS2CS_MSK)
 
 #elif (CONFIG_ETHER_INDEX == 3)
 #  define PROFF_ENET            PROFF_SCC3
 #  define CPM_CR_ENET_PAGE      CPM_CR_SCC3_PAGE
 #  define CPM_CR_ENET_SBLOCK    CPM_CR_SCC3_SBLOCK
 #  define CMXSCR_MASK          (CMXSCR_SC3          |\
-                                CMXSCR_RS3CS_MSK    |\
-                                CMXSCR_TS3CS_MSK)
+				CMXSCR_RS3CS_MSK    |\
+				CMXSCR_TS3CS_MSK)
 #elif (CONFIG_ETHER_INDEX == 4)
 #  define PROFF_ENET            PROFF_SCC4
 #  define CPM_CR_ENET_PAGE      CPM_CR_SCC4_PAGE
 #  define CPM_CR_ENET_SBLOCK    CPM_CR_SCC4_SBLOCK
 #  define CMXSCR_MASK          (CMXSCR_SC4          |\
-                                CMXSCR_RS4CS_MSK    |\
-                                CMXSCR_TS4CS_MSK)
+				CMXSCR_RS4CS_MSK    |\
+				CMXSCR_TS4CS_MSK)
 
 #endif
 
@@ -104,27 +104,27 @@
     int result = 0;
 
     if (length <= 0) {
-        printf("scc: bad packet size: %d\n", length);
-        goto out;
+	printf("scc: bad packet size: %d\n", length);
+	goto out;
     }
 
     for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
-        if (i >= TOUT_LOOP) {
-            printf("scc: tx buffer not ready\n");
-            goto out;
-        }
+	if (i >= TOUT_LOOP) {
+	    printf("scc: tx buffer not ready\n");
+	    goto out;
+	}
     }
 
     rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
     rtx->txbd[txIdx].cbd_datlen = length;
     rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |
-                                BD_ENET_TX_WRAP);
+				BD_ENET_TX_WRAP);
 
     for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
-        if (i >= TOUT_LOOP) {
-            printf("scc: tx error\n");
-            goto out;
-        }
+	if (i >= TOUT_LOOP) {
+	    printf("scc: tx error\n");
+	    goto out;
+	}
     }
 
     /* return only status bits */
@@ -141,37 +141,37 @@
 
     for (;;)
     {
-        if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
-            length = -1;
-            break;     /* nothing received - leave for() loop */
-        }
+	if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
+	    length = -1;
+	    break;     /* nothing received - leave for() loop */
+	}
 
-        length = rtx->rxbd[rxIdx].cbd_datlen;
+	length = rtx->rxbd[rxIdx].cbd_datlen;
 
-        if (rtx->rxbd[rxIdx].cbd_sc & 0x003f)
-        {
-            printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
-        }
-        else
-        {
-            /* Pass the packet up to the protocol layers. */
-            NetReceive(NetRxPackets[rxIdx], length - 4);
-        }
+	if (rtx->rxbd[rxIdx].cbd_sc & 0x003f)
+	{
+	    printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
+	}
+	else
+	{
+	    /* Pass the packet up to the protocol layers. */
+	    NetReceive(NetRxPackets[rxIdx], length - 4);
+	}
 
 
-        /* Give the buffer back to the SCC. */
-        rtx->rxbd[rxIdx].cbd_datlen = 0;
+	/* Give the buffer back to the SCC. */
+	rtx->rxbd[rxIdx].cbd_datlen = 0;
 
-        /* wrap around buffer index when necessary */
-        if ((rxIdx + 1) >= PKTBUFSRX) {
-            rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP |
-                                               BD_ENET_RX_EMPTY);
-            rxIdx = 0;
-        }
-        else {
-            rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
-            rxIdx++;
-        }
+	/* wrap around buffer index when necessary */
+	if ((rxIdx + 1) >= PKTBUFSRX) {
+	    rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP |
+					       BD_ENET_RX_EMPTY);
+	    rxIdx = 0;
+	}
+	else {
+	    rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
+	    rxIdx++;
+	}
     }
     return length;
 }
@@ -201,7 +201,7 @@
     /* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */
     immr->im_cpmux.cmx_uar = 0;
     immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) |
-                               CFG_CMXSCR_VALUE);
+			       CFG_CMXSCR_VALUE);
 
 
     /* 24.21 (6) write RBASE and TBASE to parameter RAM */
@@ -221,9 +221,9 @@
     /* 24.21 - (7): Write INIT RX AND TX PARAMETERS to CPCR */
     while(immr->im_cpm.cp_cpcr & CPM_CR_FLG);
     immr->im_cpm.cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE,
-                                     CPM_CR_ENET_SBLOCK,
-                                     0x0c,
-                                     CPM_CR_INIT_TRX) | CPM_CR_FLG;
+				     CPM_CR_ENET_SBLOCK,
+				     0x0c,
+				     CPM_CR_INIT_TRX) | CPM_CR_FLG;
 
     /* 24.21 - (8-18): Set up parameter RAM */
     pram_ptr->sen_crcec  = 0x0;           /* Error Counter CRC (unused) */
@@ -266,9 +266,9 @@
     /* 24.21 - (19): Initialize RxBD */
     for (i = 0; i < PKTBUFSRX; i++)
     {
-        rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
-        rtx->rxbd[i].cbd_datlen = 0;                  /* Reset */
-        rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
+	rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
+	rtx->rxbd[i].cbd_datlen = 0;                  /* Reset */
+	rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
     }
 
     rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
@@ -276,11 +276,11 @@
     /* 24.21 - (20): Initialize TxBD */
     for (i = 0; i < TX_BUF_CNT; i++)
     {
-        rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD  |
-                               BD_ENET_TX_LAST |
-                               BD_ENET_TX_TC);
-        rtx->txbd[i].cbd_datlen = 0;                  /* Reset */
-        rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
+	rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD  |
+			       BD_ENET_TX_LAST |
+			       BD_ENET_TX_TC);
+	rtx->txbd[i].cbd_datlen = 0;                  /* Reset */
+	rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
     }
 
     rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
@@ -290,8 +290,8 @@
 
     /* 24.21 - (22): Write to SCCM to enable TXE, RXF, TXB events */
     immr->im_scc[CONFIG_ETHER_INDEX-1].scc_sccm = (SCCE_ENET_TXE |
-                                                   SCCE_ENET_RXF |
-                                                   SCCE_ENET_TXB);
+						   SCCE_ENET_RXF |
+						   SCCE_ENET_TXB);
 
     /* 24.21 - (23): we don't use ethernet interrupts */
 
@@ -300,9 +300,9 @@
 
     /* 24.21 - (25): Clear GSMR_L to enable normal operations */
     immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl = (SCC_GSMRL_TCI        |
-                                                    SCC_GSMRL_TPL_48     |
-                                                    SCC_GSMRL_TPP_10     |
-                                                    SCC_GSMRL_MODE_ENET);
+						    SCC_GSMRL_TPL_48     |
+						    SCC_GSMRL_TPP_10     |
+						    SCC_GSMRL_MODE_ENET);
 
     /* 24.21 - (26): Initialize DSR */
     immr->im_scc[CONFIG_ETHER_INDEX-1].scc_dsr = 0xd555;
@@ -331,18 +331,17 @@
 
     /* 24.21 - (28): Write to GSMR_L to enable SCC */
     immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |
-                                                     SCC_GSMRL_ENT);
+						     SCC_GSMRL_ENT);
 
     return 0;
 }
 
 
-
 void eth_halt(void)
 {
     volatile immap_t *immr = (immap_t *)CFG_IMMR;
     immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR |
-                                                      SCC_GSMRL_ENT);
+						      SCC_GSMRL_ENT);
 }
 
 #if 0
@@ -350,9 +349,8 @@
 {
     volatile immap_t *immr = (immap_t *)CFG_IMMR;
     immr->im_cpm.cp_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |
-                                                            SCC_GSMRL_ENT);
+							    SCC_GSMRL_ENT);
 }
 #endif
 
 #endif  /* CONFIG_ETHER_ON_SCC && CFG_CMD_NET */
-
diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c
index 69ae535..789c514 100644
--- a/cpu/mpc8260/i2c.c
+++ b/cpu/mpc8260/i2c.c
@@ -223,7 +223,7 @@
 	volatile I2C_BD *rxbd, *txbd;
 	uint dpaddr;
 
-#ifdef CFG_I2C_INIT_BOARD        
+#ifdef CFG_I2C_INIT_BOARD
 	/* call board specific i2c bus reset routine before accessing the   */
 	/* environment, which might be in a chip on that bus. For details   */
 	/* about this problem see doc/I2C_Edge_Conditions.                  */
@@ -494,7 +494,7 @@
 	volatile iic_t *iip;
 	volatile i2c8260_t *i2c	= (i2c8260_t *)&immap->im_i2c;
 	volatile I2C_BD *txbd, *rxbd;
-        int  n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0;
+	int  n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0;
 	uint dpaddr;
 
 	PRINTD(("[I2C] i2c_doio\n"));
@@ -543,7 +543,7 @@
 
 		rxbd = ((I2C_BD*)state->rxbd) - n;
 		for (i = 0; i < n; i++) {
-        		rxtimeo += TOUT_LOOP * rxbd->length;
+			rxtimeo += TOUT_LOOP * rxbd->length;
 			rxbd++;
 		}
 
@@ -670,7 +670,7 @@
 	  * and the extra bits end up in the "chip address" bit slots.
 	  * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
 	  * chips.
-  	  *
+	  *
 	  * Note that we consider the length of the address field to still
 	  * be one byte because the extra address bits are hidden in the
 	  * chip address.
@@ -719,7 +719,7 @@
 	  * and the extra bits end up in the "chip address" bit slots.
 	  * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
 	  * chips.
-  	  *
+	  *
 	  * Note that we consider the length of the address field to still
 	  * be one byte because the extra address bits are hidden in the
 	  * chip address.
diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c
index ac77c16..b3a89f5 100644
--- a/cpu/mpc8260/pci.c
+++ b/cpu/mpc8260/pci.c
@@ -35,7 +35,7 @@
  *
  *   0x80000000 - 0xBFFFFFFF    CPU2PCI space              PCIBR0
  *   0xF4000000 - 0xF7FFFFFF    CPU2PCI space              PCIBR1
- *                       
+ *
  *   0x80000000 - 0x9FFFFFFF    0x80000000 - 0x9FFFFFFF   (Outbound ATU #1)
  *                              PCI Mem with prefetch
  *
@@ -44,7 +44,7 @@
  *
  *   0xF4000000 - 0xF7FFFFFF    0x00000000 - 0x03FFFFFF   (Outbound ATU #3)
  *                              32-bit PCI IO
- *                      
+ *
  *   PCI->Local map (from PCI)
  *   MPC826x slave window                                  controlled by
  *
@@ -52,15 +52,15 @@
  *                              MPC826x local memory
  */
 
-/* 
- * Slave window that allows PCI masters to access MPC826x local memory. 
+/*
+ * Slave window that allows PCI masters to access MPC826x local memory.
  * This window is set up using the first set of Inbound ATU registers
  */
 
-#ifndef CFG_PCI_SLV_MEM_LOCAL 
-#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE		/* Local base */ 
-#else 
-#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL 
+#ifndef CFG_PCI_SLV_MEM_LOCAL
+#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE		/* Local base */
+#else
+#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL
 #endif
 
 #ifndef CFG_PCI_SLV_MEM_BUS
@@ -71,22 +71,22 @@
 
 #ifndef CFG_PICMR0_MASK_ATTRIB
 #define PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
-                          	 PICMR_PREFETCH_EN)
+				 PICMR_PREFETCH_EN)
 #else
 #define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB
 #endif
 
-/* 
+/*
  * These are the windows that allow the CPU to access PCI address space.
- * All three PCI master windows, which allow the CPU to access PCI 
- * prefetch, non prefetch, and IO space (see below), must all fit within 
+ * All three PCI master windows, which allow the CPU to access PCI
+ * prefetch, non prefetch, and IO space (see below), must all fit within
  * these windows.
  */
 
 /* PCIBR0 */
 #ifndef CFG_PCI_MSTR0_LOCAL
-#define PCI_MSTR0_LOCAL		0x80000000		/* Local base */ 
-#else 
+#define PCI_MSTR0_LOCAL		0x80000000		/* Local base */
+#else
 #define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL
 #endif
 
@@ -98,9 +98,9 @@
 
 /* PCIBR1 */
 #ifndef CFG_PCI_MSTR1_LOCAL
-#define PCI_MSTR1_LOCAL		0xF4000000		/* Local base */ 
-#else 
-#define PCI_MSTR1_LOCAL		CFG_PCI_MSTR1_LOCAL 
+#define PCI_MSTR1_LOCAL		0xF4000000		/* Local base */
+#else
+#define PCI_MSTR1_LOCAL		CFG_PCI_MSTR1_LOCAL
 #endif
 
 #ifndef CFG_PCIMSK1_MASK
@@ -109,7 +109,7 @@
 #define  PCIMSK1_MASK		CFG_PCIMSK1_MASK
 #endif
 
-/* 
+/*
  * Master window that allows the CPU to access PCI Memory (prefetch).
  * This window will be setup with the first set of Outbound ATU registers
  * in the bridge.
@@ -145,34 +145,34 @@
 #define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB
 #endif
 
-/* 
+/*
  * Master window that allows the CPU to access PCI Memory (non-prefetch).
  * This window will be setup with the second set of Outbound ATU registers
  * in the bridge.
  */
 
-#ifndef CFG_PCI_MSTR_MEMIO_LOCAL 
-#define PCI_MSTR_MEMIO_LOCAL 0x90000000          /* Local base */ 
-#else 
-#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL 
+#ifndef CFG_PCI_MSTR_MEMIO_LOCAL
+#define PCI_MSTR_MEMIO_LOCAL 0x90000000          /* Local base */
+#else
+#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL
 #endif
 
-#ifndef CFG_PCI_MSTR_MEMIO_BUS 
-#define PCI_MSTR_MEMIO_BUS 0x90000000          /* PCI base   */ 
-#else 
-#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS 
+#ifndef CFG_PCI_MSTR_MEMIO_BUS
+#define PCI_MSTR_MEMIO_BUS 0x90000000          /* PCI base   */
+#else
+#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS
 #endif
 
-#ifndef CFG_CPU_PCI_MEMIO_START 
-#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL 
-#else 
-#define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START 
+#ifndef CFG_CPU_PCI_MEMIO_START
+#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
+#else
+#define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START
 #endif
 
-#ifndef CFG_PCI_MSTR_MEMIO_SIZE 
-#define PCI_MSTR_MEMIO_SIZE 0x10000000          /* 256 MB */ 
-#else 
-#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE 
+#ifndef CFG_PCI_MSTR_MEMIO_SIZE
+#define PCI_MSTR_MEMIO_SIZE 0x10000000          /* 256 MB */
+#else
+#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE
 #endif
 
 #ifndef CFG_POCMR1_MASK_ATTRIB
@@ -181,34 +181,34 @@
 #define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB
 #endif
 
-/* 
+/*
  * Master window that allows the CPU to access PCI IO space.
  * This window will be setup with the third set of Outbound ATU registers
  * in the bridge.
  */
 
-#ifndef CFG_PCI_MSTR_IO_LOCAL 
-#define PCI_MSTR_IO_LOCAL 0xA0000000          /* Local base */ 
-#else 
-#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL 
+#ifndef CFG_PCI_MSTR_IO_LOCAL
+#define PCI_MSTR_IO_LOCAL 0xA0000000          /* Local base */
+#else
+#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL
 #endif
 
-#ifndef CFG_PCI_MSTR_IO_BUS 
-#define PCI_MSTR_IO_BUS 0xA0000000          /* PCI base   */ 
-#else 
-#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS 
+#ifndef CFG_PCI_MSTR_IO_BUS
+#define PCI_MSTR_IO_BUS 0xA0000000          /* PCI base   */
+#else
+#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS
 #endif
 
-#ifndef CFG_CPU_PCI_IO_START 
-#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL 
-#else 
-#define CPU_PCI_IO_START CFG_CPU_PCI_IO_START 
+#ifndef CFG_CPU_PCI_IO_START
+#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
+#else
+#define CPU_PCI_IO_START CFG_CPU_PCI_IO_START
 #endif
 
-#ifndef CFG_PCI_MSTR_IO_SIZE 
-#define PCI_MSTR_IO_SIZE 0x10000000          /* 256MB */ 
-#else 
-#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE 
+#ifndef CFG_PCI_MSTR_IO_SIZE
+#define PCI_MSTR_IO_SIZE 0x10000000          /* 256MB */
+#else
+#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE
 #endif
 
 #ifndef CFG_POCMR2_MASK_ATTRIB
@@ -239,7 +239,7 @@
     pci_dev_t host_devno = PCI_BDF(0, 0, 0);
 
     pci_setup_indirect(hose, CFG_IMMR + PCI_CFG_ADDR_REG,
-	                         CFG_IMMR + PCI_CFG_DATA_REG);
+				 CFG_IMMR + PCI_CFG_DATA_REG);
 
     /*
      * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
@@ -248,23 +248,23 @@
     immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
 				   | SIUMCR_LBPC01;
 #else
-    /* 
-     * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), 
+    /*
+     * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
      * and local bus for PCI (SIUMCR [LBPC]).
      */
-    immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & 
-						  ~SIUMCR_LBPC11 & 
-						~SIUMCR_CS10PC11 & 
+    immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
+						  ~SIUMCR_LBPC11 &
+						~SIUMCR_CS10PC11 &
 						 ~SIUMCR_LBPC11) |
-				   SIUMCR_LBPC01 | 
-				   SIUMCR_CS10PC01 | 
+				   SIUMCR_LBPC01 |
+				   SIUMCR_CS10PC01 |
 				   SIUMCR_LBPC01;
 #endif
 
     /* Make PCI lowest priority */
-    /* Each 4 bits is a device bus request  and the MS 4bits 
+    /* Each 4 bits is a device bus request  and the MS 4bits
        is highest priority */
-    /* Bus               4bit value 
+    /* Bus               4bit value
 	   ---               ----------
        CPM high          0b0000
        CPM middle        0b0001
@@ -282,8 +282,8 @@
     /* Park bus on core while modifying PCI Bus accesses */
     immap->im_siu_conf.sc_ppc_acr = 0x6;
 
-    /* 
-     * Set up master windows that allow the CPU to access PCI space. These 
+    /*
+     * Set up master windows that allow the CPU to access PCI space. These
      * windows are set up using the two SIU PCIBR registers.
      */
     *(volatile unsigned long*)(immr_addr + M8265_PCIMSK0) = PCIMSK0_MASK;
@@ -294,40 +294,40 @@
     *(volatile unsigned long*)(immr_addr + M8265_PCIMSK1) = PCIMSK1_MASK;
     *(volatile unsigned long*)(immr_addr + M8265_PCIBR1) =
 	    PCI_MSTR1_LOCAL | PCIBR_ENABLE;
-#endif 
+#endif
 
     /* Release PCI RST (by default the PCI RST signal is held low)  */
     pci_outl (immr_addr | PCI_GCR_REG, PCIGCR_PCI_BUS_EN);
 
     /* give it some time */
     {
-#ifdef CONFIG_MPC8266ADS 
-		/* Give the PCI cards more time to initialize before query 
+#ifdef CONFIG_MPC8266ADS
+		/* Give the PCI cards more time to initialize before query
 			This might be good for other boards also
 		*/
-        int i;
-        for (i = 0; i < 1000; ++i)
+	int i;
+	for (i = 0; i < 1000; ++i)
 #endif
-            udelay(1000);
+	    udelay(1000);
     }
 
-    /* 
-     * Set up master window that allows the CPU to access PCI Memory (prefetch) 
+    /*
+     * Set up master window that allows the CPU to access PCI Memory (prefetch)
      * space. This window is set up using the first set of Outbound ATU registers.
      */
     pci_outl (immr_addr | POTAR_REG0, PCI_MSTR_MEM_BUS >> 12);      /* PCI base */
     pci_outl (immr_addr | POBAR_REG0, PCI_MSTR_MEM_LOCAL >> 12);    /* Local base */
     pci_outl (immr_addr | POCMR_REG0, POCMR0_MASK_ATTRIB);    /* Size & attribute */
 
-    /* 
-     * Set up master window that allows the CPU to access PCI Memory (non-prefetch) 
+    /*
+     * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
      * space. This window is set up using the second set of Outbound ATU registers.
      */
     pci_outl (immr_addr | POTAR_REG1, PCI_MSTR_MEMIO_BUS >> 12);    /* PCI base */
     pci_outl (immr_addr | POBAR_REG1, PCI_MSTR_MEMIO_LOCAL >> 12);  /* Local base */
     pci_outl (immr_addr | POCMR_REG1, POCMR1_MASK_ATTRIB);    /* Size & attribute */
-    
-    /* 
+
+    /*
      * Set up master window that allows the CPU to access PCI IO space. This window
      * is set up using the third set of Outbound ATU registers.
      */
@@ -335,8 +335,8 @@
     pci_outl (immr_addr | POBAR_REG2, PCI_MSTR_IO_LOCAL >> 12);     /* Local base */
     pci_outl (immr_addr | POCMR_REG2, POCMR2_MASK_ATTRIB);    /* Size & attribute */
 
-    /* 
-     * Set up slave window that allows PCI masters to access MPC826x local memory. 
+    /*
+     * Set up slave window that allows PCI masters to access MPC826x local memory.
      * This window is set up using the first set of Inbound ATU registers
      */
     pci_outl (immr_addr | PITAR_REG0, PCI_SLV_MEM_LOCAL >> 12);     /* Local base */
@@ -352,18 +352,18 @@
     /* Host mode - specify the bridge as a host-PCI bridge */
 
     pci_hose_write_config_byte(hose, host_devno, PCI_CLASS_CODE,
-	                           PCI_CLASS_BRIDGE_CTLR);
+				   PCI_CLASS_BRIDGE_CTLR);
 
     /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
     pci_hose_read_config_word(hose, host_devno, PCI_COMMAND, &tempShort);
     pci_hose_write_config_word(hose, host_devno, PCI_COMMAND,
-		         tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+			 tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 
 #ifdef CONFIG_MPC8266ADS
 	/* do some bridge init, should be done on all 8260 based bridges */
 	pci_hose_write_config_byte(hose, host_devno, PCI_CACHE_LINE_SIZE, 0x08);
 	pci_hose_write_config_byte(hose, host_devno, PCI_LATENCY_TIMER, 0xF8);
-#endif 
+#endif
 
     hose->first_busno = 0;
     hose->last_busno = 0xff;
diff --git a/cpu/mpc8260/serial_scc.c b/cpu/mpc8260/serial_scc.c
index ca76302..32016f2 100644
--- a/cpu/mpc8260/serial_scc.c
+++ b/cpu/mpc8260/serial_scc.c
@@ -82,7 +82,7 @@
 
 int serial_init (void)
 {
-        volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile immap_t *im = (immap_t *)CFG_IMMR;
 	volatile scc_t *sp;
 	volatile scc_uart_t *up;
 	volatile cbd_t *tbdf, *rbdf;
@@ -196,12 +196,12 @@
 {
 	volatile scc_uart_t	*up;
 	volatile cbd_t		*tbdf;
-        volatile immap_t	*im;
+	volatile immap_t	*im;
 
 	if (c == '\n')
 		serial_putc ('\r');
 
-        im = (immap_t *)CFG_IMMR;
+	im = (immap_t *)CFG_IMMR;
 	up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
 	tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase];
 
@@ -230,10 +230,10 @@
 {
 	volatile cbd_t		*rbdf;
 	volatile scc_uart_t	*up;
-        volatile immap_t	*im;
+	volatile immap_t	*im;
 	unsigned char		c;
 
-        im = (immap_t *)CFG_IMMR;
+	im = (immap_t *)CFG_IMMR;
 	up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
 	rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
 
@@ -255,9 +255,9 @@
 {
 	volatile cbd_t		*rbdf;
 	volatile scc_uart_t	*up;
-        volatile immap_t	*im;
+	volatile immap_t	*im;
 
-        im = (immap_t *)CFG_IMMR;
+	im = (immap_t *)CFG_IMMR;
 	up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
 	rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
 
@@ -321,7 +321,7 @@
 void
 kgdb_serial_init (void)
 {
-        volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile immap_t *im = (immap_t *)CFG_IMMR;
 	volatile scc_t *sp;
 	volatile scc_uart_t *up;
 	volatile cbd_t *tbdf, *rbdf;
@@ -435,12 +435,12 @@
 {
 	volatile scc_uart_t	*up;
 	volatile cbd_t		*tbdf;
-        volatile immap_t	*im;
+	volatile immap_t	*im;
 
 	if (c == '\n')
 		putDebugChar ('\r');
 
-        im = (immap_t *)CFG_IMMR;
+	im = (immap_t *)CFG_IMMR;
 	up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
 	tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase];
 
@@ -469,10 +469,10 @@
 {
 	volatile cbd_t		*rbdf;
 	volatile scc_uart_t	*up;
-        volatile immap_t	*im;
+	volatile immap_t	*im;
 	unsigned char		c;
 
-        im = (immap_t *)CFG_IMMR;
+	im = (immap_t *)CFG_IMMR;
 	up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
 	rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
 
diff --git a/cpu/mpc8260/serial_smc.c b/cpu/mpc8260/serial_smc.c
index b0e1ce4..0873319 100644
--- a/cpu/mpc8260/serial_smc.c
+++ b/cpu/mpc8260/serial_smc.c
@@ -74,7 +74,7 @@
 
 int serial_init (void)
 {
-        volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile immap_t *im = (immap_t *)CFG_IMMR;
 	volatile smc_t *sp;
 	volatile smc_uart_t *up;
 	volatile cbd_t *tbdf, *rbdf;
@@ -186,7 +186,7 @@
 	volatile cbd_t		*tbdf;
 	volatile char		*buf;
 	volatile smc_uart_t	*up;
-        volatile immap_t	*im = (immap_t *)CFG_IMMR;
+	volatile immap_t	*im = (immap_t *)CFG_IMMR;
 
 	if (c == '\n')
 		serial_putc ('\r');
@@ -220,7 +220,7 @@
 	volatile cbd_t		*rbdf;
 	volatile unsigned char	*buf;
 	volatile smc_uart_t	*up;
-        volatile immap_t	*im = (immap_t *)CFG_IMMR;
+	volatile immap_t	*im = (immap_t *)CFG_IMMR;
 	unsigned char		c;
 
 	up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
@@ -243,7 +243,7 @@
 {
 	volatile cbd_t		*rbdf;
 	volatile smc_uart_t	*up;
-        volatile immap_t	*im = (immap_t *)CFG_IMMR;
+	volatile immap_t	*im = (immap_t *)CFG_IMMR;
 
 	up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
 
@@ -289,7 +289,7 @@
 void
 kgdb_serial_init (void)
 {
-        volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile immap_t *im = (immap_t *)CFG_IMMR;
 	volatile smc_t *sp;
 	volatile smc_uart_t *up;
 	volatile cbd_t *tbdf, *rbdf;
@@ -401,7 +401,7 @@
 	volatile cbd_t		*tbdf;
 	volatile char		*buf;
 	volatile smc_uart_t	*up;
-        volatile immap_t	*im = (immap_t *)CFG_IMMR;
+	volatile immap_t	*im = (immap_t *)CFG_IMMR;
 
 	if (c == '\n')
 		putDebugChar ('\r');
@@ -435,7 +435,7 @@
 	volatile cbd_t		*rbdf;
 	volatile unsigned char	*buf;
 	volatile smc_uart_t	*up;
-        volatile immap_t	*im = (immap_t *)CFG_IMMR;
+	volatile immap_t	*im = (immap_t *)CFG_IMMR;
 	unsigned char		c;
 
 	up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]);
diff --git a/cpu/mpc8260/spi.c b/cpu/mpc8260/spi.c
index 6a2dc8f..c1a607c 100644
--- a/cpu/mpc8260/spi.c
+++ b/cpu/mpc8260/spi.c
@@ -213,12 +213,12 @@
 
 	/***********IMPORTANT******************/
 
-        /*
-         * Setting transmit and receive buffer descriptor pointers
-         * initially to rbase and tbase. Only the microcode patches
-         * documentation talks about initializing this pointer. This
-         * is missing from the sample I2C driver. If you dont
-         * initialize these pointers, the kernel hangs.
+	/*
+	 * Setting transmit and receive buffer descriptor pointers
+	 * initially to rbase and tbase. Only the microcode patches
+	 * documentation talks about initializing this pointer. This
+	 * is missing from the sample I2C driver. If you dont
+	 * initialize these pointers, the kernel hangs.
 	 */
 	spi->spi_rbptr = spi->spi_rbase;
 	spi->spi_tbptr = spi->spi_tbase;
diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S
index 2070ecc..d3fd865 100644
--- a/cpu/mpc8260/start.S
+++ b/cpu/mpc8260/start.S
@@ -966,8 +966,8 @@
 	/*
 	 * Relocation Function, r14 point to got2+0x8000
 	 *
-         * Adjust got2 pointers, no need to check for 0, this code
-         * already puts a few entries in the table.
+	 * Adjust got2 pointers, no need to check for 0, this code
+	 * already puts a few entries in the table.
 	 */
 	li	r0,__got2_entries@sectoff@l
 	la	r3,GOT(_GOT2_TABLE_)
@@ -981,7 +981,7 @@
 	bdnz	1b
 
 	/*
-         * Now adjust the fixups and the pointers to the fixups
+	 * Now adjust the fixups and the pointers to the fixups
 	 * in case we need to move ourselves again.
 	 */
 2:	li	r0,__fixup_entries@sectoff@l