diff --git a/board/bmw/Makefile b/board/bmw/Makefile
index 46fe791..621640b 100644
--- a/board/bmw/Makefile
+++ b/board/bmw/Makefile
@@ -31,7 +31,7 @@
 SOBJS	= early_init.o
 
 $(LIB):	.depend $(OBJS) $(SOBJS)
-	$(AR) crv $@ $^
+	$(AR) crv $@ $(OBJS) $(SOBJS)
 
 #########################################################################
 
diff --git a/board/bmw/README b/board/bmw/README
index 55ef56e..70bc813 100644
--- a/board/bmw/README
+++ b/board/bmw/README
@@ -20,39 +20,39 @@
 onboard the processor module are listed briefly below:
 
 0x00000000 - 0x40000000 - 64MB SDRAM SIMM
-                          (Unregistered PC-100 SDRAM DIMM Module)
+			  (Unregistered PC-100 SDRAM DIMM Module)
 
 0xFF000000 - 0xFF001FFF - M-Systems DiskOnChip (TM) 2000
-                          TSOP 16MB (MD2211-D16-V3)
+			  TSOP 16MB (MD2211-D16-V3)
 
 0x70000000 - 0x70001FFF - M-Systems DiskOnChip (TM) 2000
-                          DIP32 (Socketed 16MB - 1GB ) *
-                          NOTE: this is not populated on all systems.
+			  DIP32 (Socketed 16MB - 1GB ) *
+			  NOTE: this is not populated on all systems.
 
 0x7c000000 - 0x7c000000 - Reset Register
-                          (Write 0 to reset)
+			  (Write 0 to reset)
 
 0x7c000001 - 0x7c000001 - System LED
-                          (Clear Bit 7 to turn on, set to shut off)
+			  (Clear Bit 7 to turn on, set to shut off)
 
 0x7c000002 - 0x7c000002 - M48T59 Watchdog IRQ3
-                          (Clear bit 7 to reset, set to assert IRQ3)
+			  (Clear bit 7 to reset, set to assert IRQ3)
 
 0x7c000003 - 0x7c000003 - M48T59 Write-Protect Register
-                          (Clear bit 7 to make R/W, set to make R/O)
+			  (Clear bit 7 to make R/W, set to make R/O)
 
 0x7c002000 - 0x7c002003 - Infineon OSRAM DLR2416 4 Character
-                          5x7 Dot Matrix Alphanumeric Display
-                          (Each byte sets the appropriate character)
+			  5x7 Dot Matrix Alphanumeric Display
+			  (Each byte sets the appropriate character)
 
 0x7c004000 - 0x7c005FF0 - SGS-THOMSON M48T59Y 8K NVRAM/RTC
-                          NVRAM Memory Region
+			  NVRAM Memory Region
 
 0x7c005FF0 - 0x7c005FFF - SGS-THOMSON M48T59Y 8K NVRAM/RTC
-                          Realtime Clock Registers
+			  Realtime Clock Registers
 
 0xFFF00000 - 0xFFF80000 - 512K PLCC32 BootRom
-                          (AMD AM29F040, ST 29W040B)
+			  (AMD AM29F040, ST 29W040B)
 
 0xFFF00100 -              System Reset Vector
 
@@ -131,7 +131,6 @@
 - DOC Support - (underway)
 
 
-
 U-Boot 1.2.0 (Aug  6 2002 - 17:44:48)
 
 CPU:   MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache
@@ -167,15 +166,10 @@
 =>boot
 
 
-
-
-
-
-
 DevTools
 ========
 ELDK
-        DENX Embedded Linux Development Kit
+	DENX Embedded Linux Development Kit
 
 ROM Emulator
 	Grammar Engine PROMICE P1160-90-AI21E (2MBx8bit, 90ns access time)
@@ -187,7 +181,6 @@
 	WRS/EST VisionICE-II (PPC8240)
 
 
-
 =>reset
 
 
@@ -216,8 +209,8 @@
 Filename 'vmlinux.img'.
 Load address: 0x100000
 Loading: #################################################################
-         ####################################T #############################
-         ######################
+	 ####################################T #############################
+	 ######################
 done
 Bytes transferred = 777199 (bdbef hex)
 
@@ -317,7 +310,6 @@
 MPC8245/BMW
 
 
-
 switch-2 login: root
 Password:
 PAM_unix[49]: (login) session opened for user root by LOGIN(uid=0)
@@ -328,7 +320,6 @@
 MPC8245/BMW
 
 
-
 login[49]: ROOT LOGIN on `console'
 
 root@switch-2:~# cat /proc/cpuinfo
diff --git a/board/bmw/bmw.c b/board/bmw/bmw.c
index 2685662..f2d33fc 100644
--- a/board/bmw/bmw.c
+++ b/board/bmw/bmw.c
@@ -94,9 +94,6 @@
 }
 
 
-
-
-
 /*
  * Initialize PCI Devices, report devices found.
  */
diff --git a/board/bmw/bmw.h b/board/bmw/bmw.h
index 6b7571c..dd97569 100644
--- a/board/bmw/bmw.h
+++ b/board/bmw/bmw.h
@@ -46,13 +46,13 @@
 #define LED_REG_BASE		(XROM_BASE_ADDR | 0x2000)
 #define TOD_BASE		(XROM_BASE_ADDR | 0x4000)
 #define LED_REG(x)              (*(volatile unsigned char *) \
-                                  (LED_REG_BASE + (x)))
+				  (LED_REG_BASE + (x)))
 #define XROM_DEV_SIZE		0x00006000
 
 #define ENET_DEV_BASE		0x80000000
 
 #define PLD_REG(off)		(*(volatile unsigned char *)\
-                                  (PLD_REG_BASE + (off)))
+				  (PLD_REG_BASE + (off)))
 
 #define PLD_REVID_B1		0x7f	/* Fix me */
 #define PLD_REVID_B2		0x01	/* Fix me */
diff --git a/board/bmw/config.mk b/board/bmw/config.mk
index 7facadf..f991549 100644
--- a/board/bmw/config.mk
+++ b/board/bmw/config.mk
@@ -28,5 +28,5 @@
 TEXT_BASE = 0xFFF00000
 # NOTE: The flags below affect how the BCM570x driver is compiled
 PLATFORM_CPPFLAGS += -DEMBEDDED -DBIG_ENDIAN_HOST -DINCLUDE_5701_AX_FIX=1\
-                     -DDBG=0 -DT3_JUMBO_RCV_RCB_ENTRY_COUNT=256\
-                     -DTEXT_BASE=$(TEXT_BASE)
+		     -DDBG=0 -DT3_JUMBO_RCV_RCB_ENTRY_COUNT=256\
+		     -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/bmw/early_init.S b/board/bmw/early_init.S
index ec20a67..e6400c3 100644
--- a/board/bmw/early_init.S
+++ b/board/bmw/early_init.S
@@ -16,7 +16,7 @@
 	.global	iommu_setup
 	/* Initialize IO/MMU mappings via BAT method Ch. 7,
 	 * PPC Programming Reference
-         */
+	 */
 iommu_setup:
 
 /* initialize the BAT registers (SPRs 528 - 543 */
@@ -64,7 +64,7 @@
    BAT marked valid that is in an unknown or transient state
 */
 
-        addis   r5,0,0x0000
+	addis   r5,0,0x0000
 	mtibat0u(r5)
 	mtibat0l(r5)
 	mtibat1u(r5)
@@ -81,106 +81,106 @@
 	mtdbat2l(r5)
 	mtdbat3u(r5)
 	mtdbat3l(r5)
-        isync
+	isync
 
 /*
  *  Set up I/D BAT0
  */
-        lis     r4, CFG_DBAT0L@h
-        ori     r4, r4, CFG_DBAT0L@l
-        lis     r3, CFG_DBAT0U@h
-        ori     r3, r3, CFG_DBAT0U@l
+	lis     r4, CFG_DBAT0L@h
+	ori     r4, r4, CFG_DBAT0L@l
+	lis     r3, CFG_DBAT0U@h
+	ori     r3, r3, CFG_DBAT0U@l
 
-        mtdbat0l(r4)
-        isync
-        mtdbat0u(r3)
-        isync
-        sync
+	mtdbat0l(r4)
+	isync
+	mtdbat0u(r3)
+	isync
+	sync
 
-        lis     r4, CFG_IBAT0L@h
-        ori     r4, r4, CFG_IBAT0L@l
-        lis     r3, CFG_IBAT0U@h
-        ori     r3, r3, CFG_IBAT0U@l
+	lis     r4, CFG_IBAT0L@h
+	ori     r4, r4, CFG_IBAT0L@l
+	lis     r3, CFG_IBAT0U@h
+	ori     r3, r3, CFG_IBAT0U@l
 
-        isync
-        mtibat0l(r4)
-        isync
+	isync
+	mtibat0l(r4)
+	isync
 	mtibat0u(r3)
-        isync
+	isync
 
 /*
  *  Set up I/D BAT1
  */
-        lis     r4, CFG_IBAT1L@h
-        ori     r4, r4, CFG_IBAT1L@l
-        lis     r3, CFG_IBAT1U@h
-        ori     r3, r3, CFG_IBAT1U@l
+	lis     r4, CFG_IBAT1L@h
+	ori     r4, r4, CFG_IBAT1L@l
+	lis     r3, CFG_IBAT1U@h
+	ori     r3, r3, CFG_IBAT1U@l
 
-        isync
-        mtibat1l(r4)
-        isync
-        mtibat1u(r3)
-        isync
-        mtdbat1l(r4)
-        isync
-        mtdbat1u(r3)
-        isync
-        sync
+	isync
+	mtibat1l(r4)
+	isync
+	mtibat1u(r3)
+	isync
+	mtdbat1l(r4)
+	isync
+	mtdbat1u(r3)
+	isync
+	sync
 
 /*
  *  Set up I/D BAT2
  */
-        lis     r4, CFG_IBAT2L@h
-        ori     r4, r4, CFG_IBAT2L@l
-        lis     r3, CFG_IBAT2U@h
-        ori     r3, r3, CFG_IBAT2U@l
+	lis     r4, CFG_IBAT2L@h
+	ori     r4, r4, CFG_IBAT2L@l
+	lis     r3, CFG_IBAT2U@h
+	ori     r3, r3, CFG_IBAT2U@l
 
-        isync
-        mtibat2l(r4)
-        isync
-        mtibat2u(r3)
-        isync
-        mtdbat2l(r4)
-        isync
-        mtdbat2u(r3)
-        isync
-        sync
+	isync
+	mtibat2l(r4)
+	isync
+	mtibat2u(r3)
+	isync
+	mtdbat2l(r4)
+	isync
+	mtdbat2u(r3)
+	isync
+	sync
 
 /*
  *  Setup I/D BAT3
  */
-        lis     r4, CFG_IBAT3L@h
-        ori     r4, r4, CFG_IBAT3L@l
-        lis     r3, CFG_IBAT3U@h
-        ori     r3, r3, CFG_IBAT3U@l
+	lis     r4, CFG_IBAT3L@h
+	ori     r4, r4, CFG_IBAT3L@l
+	lis     r3, CFG_IBAT3U@h
+	ori     r3, r3, CFG_IBAT3U@l
 
-        isync
-        mtibat3l(r4)
-        isync
-        mtibat3u(r3)
-        isync
-        mtdbat3l(r4)
-        isync
-        mtdbat3u(r3)
-        isync
-        sync
+	isync
+	mtibat3l(r4)
+	isync
+	mtibat3u(r3)
+	isync
+	mtdbat3l(r4)
+	isync
+	mtdbat3u(r3)
+	isync
+	sync
 
 
 /*
  *  Invalidate all 64 TLB's
  */
-        lis     r3, 0
-        mtctr   r3
-        lis     r5, 4
+	lis     r3, 0
+	mtctr   r3
+	lis     r5, 4
 
 tlblp:
-        tlbie   r3
-        sync
-        addi    r3, r3, 0x1000
-        cmplw   r3, r5
-        blt     tlblp
+	tlbie   r3
+	sync
+	addi    r3, r3, 0x1000
+	cmplw   r3, r5
+	blt     tlblp
 
-        sync
+	sync
 
 /*
  *  Enable Data Translation
@@ -193,7 +193,7 @@
 	isync
 	sync
 
-        blr
+	blr
 
 
 #ifdef USE_V2_INIT
@@ -213,8 +213,8 @@
 /* MPC8245/BMW CPCI System Init
  * Jimmy Blair, Broadcom Corp, 2002.
  */
-        mflr    r11
- 	/* Zero-out registers */
+	mflr    r11
+	/* Zero-out registers */
 
 	addis	r0,r0,0
 	mtspr	SPRG0,r0
@@ -244,7 +244,7 @@
 	/* Set MPU/MSR to a known state. Turn off FP */
 
 #if 1	/* Turn off floating point (remove to keep FP on) */
-        andi.	r3, r3, 0
+	andi.	r3, r3, 0
 	sync
 	mtmsr 	r3
 	isync
@@ -368,10 +368,10 @@
 	rlwinm	r3, r4, 0, 21, 19	/* clear the ICFI bit */
 
 	/*
-         * The setting of the instruction cache enable (ICE) bit must be
-         * preceded by an isync instruction to prevent the cache from being
-         * enabled or disabled while an instruction access is in progress.
-         */
+	 * The setting of the instruction cache enable (ICE) bit must be
+	 * preceded by an isync instruction to prevent the cache from being
+	 * enabled or disabled while an instruction access is in progress.
+	 */
 	isync
 writeReg4:
 	mtspr	HID0, r4		/* Enable Instr Cache & Inval cache */
@@ -397,13 +397,13 @@
 	cmp	0,0,r3,r7
 	beq	cr0, X4_KAHLUA_START
 
-        /* It's not an 8240, is it an 8245? */
+	/* It's not an 8240, is it an 8245? */
 
 	LOADPTR (r7, KAHLUA2_ID)	/* Kahlua PCI controller ID */
 	cmp	0,0,r3,r7
 	beq	cr0, X4_KAHLUA_START
 
-        /* Save the PCI controller type in r7 */
+	/* Save the PCI controller type in r7 */
 	mr	r7, r3
 
 	LOADPTR (r5, PREP_REG_ADDR)
@@ -433,33 +433,33 @@
 
 	LOADPTR (r3, PROC_INT2_ADR)	/* Processor I/F Config 2 reg. */
 	stwbrx	r3,0,r5
-        lis	r4, 0x2000		/* Flush PCI config writes */
+	lis	r4, 0x2000		/* Flush PCI config writes */
 	stwbrx	r4,0,r6
 
 	LOADPTR (r9, KAHLUA2_ID)
-        cmpl	0, 0, r7, r9
-        bne     L1not8245
+	cmpl	0, 0, r7, r9
+	bne     L1not8245
 
-        /* MIOCR1 -- turn on bit for DLL delay */
+	/* MIOCR1 -- turn on bit for DLL delay */
 
 	LOADPTR (r3, MIOCR1_ADR_X)
 	stwbrx	r3,0,r5
-        li      r4, 0x04
+	li      r4, 0x04
 	stb	r4, MIOCR1_SHIFT(r6)
 
-        /* For the MPC8245, set register 77 to %00100000 (see Errata #15) */
-        /* SDRAM_CLK_DEL (0x77)*/
+	/* For the MPC8245, set register 77 to %00100000 (see Errata #15) */
+	/* SDRAM_CLK_DEL (0x77)*/
 
 	LOADPTR (r3, MIOCR2_ADR_X)
 	stwbrx	r3,0,r5
-        li      r4, 0x10
+	li      r4, 0x10
 	stb	r4, MIOCR2_SHIFT(r6)
 
-        /* PMCR2 -- set PCI hold delay to <10>b for 33 MHz */
+	/* PMCR2 -- set PCI hold delay to <10>b for 33 MHz */
 
 	LOADPTR (r3, PMCR2_ADR_X)
 	stwbrx	r3,0,r5
-        li      r4, 0x20
+	li      r4, 0x20
 	stb	r4, PMCR2_SHIFT(r6)
 
 	/* Initialize EUMBBAR early since 8245 has internal UART in EUMB */
@@ -471,21 +471,21 @@
 
 L1not8245:
 
-        /* Toggle the DLL reset bit in AMBOR */
+	/* Toggle the DLL reset bit in AMBOR */
 
 	LOADPTR (r3, AMBOR)
 	stwbrx	r3,0,r5
 	lbz	r4, 0(r6)
 
-        andi.   r4, r4, 0xdf
+	andi.   r4, r4, 0xdf
 	stb	r4, 0(r6)		/* Clear DLL_RESET */
-        sync
+	sync
 
-        ori     r4, r4, 0x20		/* Set DLL_RESET */
+	ori     r4, r4, 0x20		/* Set DLL_RESET */
 	stb	r4, 0(r6)
-        sync
+	sync
 
-        andi.   r4, r4, 0xdf
+	andi.   r4, r4, 0xdf
 	stb	r4, 0(r6)		/* Clear DLL_RESET */
 
 
@@ -533,10 +533,10 @@
 		MC1_MEMGO << 19 | MC1_SREN << 18 | \
 		MC1_RAM_TYPE << 17 | MC1_PCKEN << 16 )
 	li	r3, MC1_BANKBITS
-        cmpl	0, 0, r7, r9		/* Check for Kahlua2 */
-        bne     BankBitsAdd
-        cmpli   0, 0, r3, 0x5555
-        beq     K2BankBitsHack		/* On 8245, 5555 ==> 0 */
+	cmpl	0, 0, r7, r9		/* Check for Kahlua2 */
+	bne     BankBitsAdd
+	cmpli   0, 0, r3, 0x5555
+	beq     K2BankBitsHack		/* On 8245, 5555 ==> 0 */
 BankBitsAdd:
 	ori	r4, r3, 0
 K2BankBitsHack:
@@ -569,9 +569,9 @@
 		MC2_INLRD_PARECC_CHK_EN << 18 | \
 		MC2_ECC_EN << 17 | MC2_EDO << 16 | \
 		MC2_REFINT << 2 | MC2_RSV_PG << 1 | MC2_RMW_PAR)
-        cmpl	0, 0, r7, r9		/* Check for Kahlua2 */
-        bne     notK2
-        /* clear Kahlua2 reserved bits */
+	cmpl	0, 0, r7, r9		/* Check for Kahlua2 */
+	bne     notK2
+	/* clear Kahlua2 reserved bits */
 	LOADPTR (r3, 0xfffcffff)
 	and	r4, r4, r3
 notK2:
@@ -599,9 +599,9 @@
 		MC3_RDLAT << 20 | MC3_CPX << 19 | \
 		MC3_RAS6P << 15 | MC3_CAS5 << 12 | MC3_CP4 << 9 | \
 		MC3_CAS3 << 6 | MC3_RCD2 << 3 | MC3_RP1)
-        cmpl	0, 0, r7, r9              /* Check for Kahlua2 */
-        bne     notK2b
-        /* clear Kahlua2 reserved bits */
+	cmpl	0, 0, r7, r9              /* Check for Kahlua2 */
+	bne     notK2b
+	/* clear Kahlua2 reserved bits */
 	LOADPTR (r3, 0xff000000)
 	and	r4, r4, r3
 notK2b:
@@ -633,9 +633,9 @@
 		MC4_REGDIMM << 15 | MC4_SDMODE_CAS << 12 | \
 		MC4_SDMODE_WRAP << 11 | MC4_SDMODE_BURST << 8 | \
 		MC4_ACTORW << 4 | MC4_BSTOPRE_L)
-        cmpl	0, 0, r7, r9                /* Check for Kahlua 2 */
-        bne     notK2c
-        /* Turn on Kahlua2 extended ROM space */
+	cmpl	0, 0, r7, r9                /* Check for Kahlua 2 */
+	bne     notK2c
+	/* Turn on Kahlua2 extended ROM space */
 	LOADPTR (r3, 0x00200000)
 	or	r4, r4, r3
 notK2c:
@@ -745,13 +745,12 @@
 
 	sync
 	eieio
-        mtlr    r11
+	mtlr    r11
 	blr
 
 #else /* USE_V2_INIT */
 
 
-
 /* U-Boot works, but memory will not run reliably for all address ranges.
  * Early U-Boot Working init, but 2.4.19 kernel will crash since memory is not
  * initialized correctly. Could work if debugged.
@@ -898,106 +897,106 @@
 .globl  early_init_f
 
 early_init_f:
-        mflr    r11
-        lis     r10, 0x8000
+	mflr    r11
+	lis     r10, 0x8000
 
-        /* PCI Latency Timer */
-        li      r4, 0x0d
-        ori     r3, r10, PLTR@l
-        bl      __pci_config_write_8
+	/* PCI Latency Timer */
+	li      r4, 0x0d
+	ori     r3, r10, PLTR@l
+	bl      __pci_config_write_8
 
-        /* Cache Line Size */
-        li      r4, 0x08
-        ori     r3, r10, PCLSR@l
-        bl      __pci_config_write_8
+	/* Cache Line Size */
+	li      r4, 0x08
+	ori     r3, r10, PCLSR@l
+	bl      __pci_config_write_8
 
-        /* PCI Cmd */
-        li      r4, 6
-        ori     r3, r10, PCICR@l
-        bl      __pci_config_write_16
+	/* PCI Cmd */
+	li      r4, 6
+	ori     r3, r10, PCICR@l
+	bl      __pci_config_write_16
 
 #if 1
-        /* PCI Stat */
-        ori     r3, r10, PCISR@l
-        bl      __pci_config_read_16
-        ori     r4, r4, 0xffff
-        ori     r3, r10, PCISR@l
-        bl      __pci_config_write_16
+	/* PCI Stat */
+	ori     r3, r10, PCISR@l
+	bl      __pci_config_read_16
+	ori     r4, r4, 0xffff
+	ori     r3, r10, PCISR@l
+	bl      __pci_config_write_16
 #endif
 
-        /* PICR1 */
-        lis     r4, 0xff14
-        ori     r4, r4, 0x1b98
-        ori     r3, r10, PICR1@l
-        bl      __pci_config_write_32
+	/* PICR1 */
+	lis     r4, 0xff14
+	ori     r4, r4, 0x1b98
+	ori     r3, r10, PICR1@l
+	bl      __pci_config_write_32
 
 
-        /* PICR2 */
-        lis     r4, 0x0404
-        ori     r4, r4, 0x0004
-        ori     r3, r10, PICR2@l
-        bl      __pci_config_write_32
+	/* PICR2 */
+	lis     r4, 0x0404
+	ori     r4, r4, 0x0004
+	ori     r3, r10, PICR2@l
+	bl      __pci_config_write_32
 
 	/* MIOCR1 */
-        li      r4, 0x04
-        ori     r3, r10, MIOCR1@l
-        bl      __pci_config_write_8
+	li      r4, 0x04
+	ori     r3, r10, MIOCR1@l
+	bl      __pci_config_write_8
 
 	/* For the MPC8245, set register 77 to %00100000 (see Errata #15) */
 	/* SDRAM_CLK_DEL (0x77)*/
-        li      r4, 0x10
-        ori     r3, r10, MIOCR2@l
-        bl      __pci_config_write_8
+	li      r4, 0x10
+	ori     r3, r10, MIOCR2@l
+	bl      __pci_config_write_8
 
-        /* EUMBBAR */
-        lis     r4, 0xfc00
-        ori     r3, r10, EUMBBAR@l
-        bl      __pci_config_write_32
+	/* EUMBBAR */
+	lis     r4, 0xfc00
+	ori     r3, r10, EUMBBAR@l
+	bl      __pci_config_write_32
 
 	/* AMBOR */
 
        /* Even if Address Map B is not being used (though it should),
-        * the memory DLL needs to be cleared/set/cleared before using memory.
+	* the memory DLL needs to be cleared/set/cleared before using memory.
 	*/
 
-        ori     r3, r10, AMBOR@l
-        bl      __pci_config_read_8	/* get Current bits */
+	ori     r3, r10, AMBOR@l
+	bl      __pci_config_read_8	/* get Current bits */
 
-        andi.   r4, r4, 0xffdf
-        ori     r3, r10, AMBOR@l
-        bl      __pci_config_write_16	/* Clear DLL_RESET */
+	andi.   r4, r4, 0xffdf
+	ori     r3, r10, AMBOR@l
+	bl      __pci_config_write_16	/* Clear DLL_RESET */
 
-        ori    r4, r4, 0x0020
-        ori     r3, r10, AMBOR@l
-        bl      __pci_config_write_16	/* Set DLL_RESET */
+	ori    r4, r4, 0x0020
+	ori     r3, r10, AMBOR@l
+	bl      __pci_config_write_16	/* Set DLL_RESET */
 
-        andi.   r4, r4, 0xffdf
-        ori     r3, r10, AMBOR@l
-        bl      __pci_config_write_16	/* Clear DLL_RESET */
+	andi.   r4, r4, 0xffdf
+	ori     r3, r10, AMBOR@l
+	bl      __pci_config_write_16	/* Clear DLL_RESET */
 
-        /* ERCR1 */
-        lis     r4, 0x8040		/* Enable RCS2, use supplied timings */
-        ori     r4, r4, 0x8000
-        ori     r3, r10, ERCR1@l
-        bl      __pci_config_write_32
+	/* ERCR1 */
+	lis     r4, 0x8040		/* Enable RCS2, use supplied timings */
+	ori     r4, r4, 0x8000
+	ori     r3, r10, ERCR1@l
+	bl      __pci_config_write_32
 
-        /* ERCR2 */
-        lis     r4, 0x0000		/* Disable RCS3 parms */
-        ori     r4, r4, 0x0000
-        ori     r3, r10, ERCR2@l
-        bl      __pci_config_write_32
+	/* ERCR2 */
+	lis     r4, 0x0000		/* Disable RCS3 parms */
+	ori     r4, r4, 0x0000
+	ori     r3, r10, ERCR2@l
+	bl      __pci_config_write_32
 
-        /* ERCR3 */
-        lis     r4, 0x0000		/* RCS3 at 0x70000000, 64K bytes */
-        ori     r4, r4, 0x0004
-        ori     r3, r10, ERCR2@l
-        bl      __pci_config_write_32
+	/* ERCR3 */
+	lis     r4, 0x0000		/* RCS3 at 0x70000000, 64K bytes */
+	ori     r4, r4, 0x0004
+	ori     r3, r10, ERCR2@l
+	bl      __pci_config_write_32
 
 	/* Preserve memgo bit */
-        /* MCCR1 */
+	/* MCCR1 */
 
 /*	lis     r4, 0x75a8		/  Safe Local ROM = 11+3 clocks */
-  	lis     r4, 0x75a0              /* Safe Local ROM = 11+3 clocks */
+	lis     r4, 0x75a0              /* Safe Local ROM = 11+3 clocks */
 /*      lis     r4, 0x73a0              /  Fast Local ROM = 7+3 clocks */
 /*      oris    r4, r4, 0x0010          /  Burst ROM/Flash enable */
 /*      oris    r4, r4, 0x0004          /  Self-refresh enable */
@@ -1005,17 +1004,17 @@
 /*      ori     r4,r4,0xFFFF            /  16Mbit  2bank SDRAM */
 /*      ori     r4,r4,0xAAAA            /  256Mbit 4bank SDRAM (8245 only) */
 /*      ori     r4,r4,0x5555            /  64Mbit  2bank SDRAM */
-        ori     r4,r4,0x0000            /* 64Mbit  4bank SDRAM */
+	ori     r4,r4,0x0000            /* 64Mbit  4bank SDRAM */
 
-        ori     r3, r10, MCCR1@l
-        bl      __pci_config_write_32
+	ori     r3, r10, MCCR1@l
+	bl      __pci_config_write_32
 
-        /* MCCR2 */
+	/* MCCR2 */
 
-        lis     r4,0x0000
+	lis     r4,0x0000
 /*      oris    r4,r4,0x4000            /  TS_WAIT_TIMER = 3 clocks */
-        oris    r4,r4,0x1000            /* ASRISE = 8 clocks */
-        oris    r4,r4,0x0080            /* ASFALL = 8 clocks */
+	oris    r4,r4,0x1000            /* ASRISE = 8 clocks */
+	oris    r4,r4,0x0080            /* ASFALL = 8 clocks */
 /*      oris    r4,r4,0x0010            /  SDRAM Parity (else ECC) */
 /*      oris    r4,r4,0x0008            /  Write parity check */
 /*      oris    r4,r4,0x0004            /  SDRAM inline reads */
@@ -1030,143 +1029,142 @@
 /*      ori     r4,r4,0x150c            /  100 MHz mem bus        = 1347 */
 /*      ori     r4,r4,0x10fc            /   83 MHz mem bus        = 1087 */
 /*      ori     r4,r4,0x0cc4            /   66 MHz mem bus        =  817 */
-        ori     r4,r4,0x04cc            /*  33 MHz mem bus (SAFE) =  307 */
+	ori     r4,r4,0x04cc            /*  33 MHz mem bus (SAFE) =  307 */
 /*      ori     r4,r4,0x0002            /  Reserve a page */
 /*      ori     r4,r4,0x0001            /  RWM parity */
 
-        ori     r3, r10, MCCR2@l
-        bl      __pci_config_write_32
+	ori     r3, r10, MCCR2@l
+	bl      __pci_config_write_32
 
 
-        /* MCCR3 */
-        lis     r4,0x0000               /* BSTOPRE_M = 7 (see A/N) */
-        oris    r4,r4,0x0500            /* REFREC    = 8 clocks */
-        ori     r3, r10, MCCR3@l
-        bl      __pci_config_write_32
+	/* MCCR3 */
+	lis     r4,0x0000               /* BSTOPRE_M = 7 (see A/N) */
+	oris    r4,r4,0x0500            /* REFREC    = 8 clocks */
+	ori     r3, r10, MCCR3@l
+	bl      __pci_config_write_32
 
-        /* MCCR4 */                     /* Turn on registered buffer mode */
-        lis     r4, 0x2000              /* PRETOACT = 3 clocks */
-        oris    r4,r4,0x0400            /* ACTOPRE  = 5 clocks */
+	/* MCCR4 */                     /* Turn on registered buffer mode */
+	lis     r4, 0x2000              /* PRETOACT = 3 clocks */
+	oris    r4,r4,0x0400            /* ACTOPRE  = 5 clocks */
 /*      oris    r4,r4,0x0080            /  Enable 8-beat burst (32-bit bus) */
 /*      oris    r4,r4,0x0040            /  Enable Inline ECC/Parity */
-        oris    r4,r4,0x0020            /* EXTROM enabled */
-        oris    r4,r4,0x0010            /* Registered buffers */
+	oris    r4,r4,0x0020            /* EXTROM enabled */
+	oris    r4,r4,0x0010            /* Registered buffers */
 /*      oris    r4,r4,0x0000            /  BSTOPRE_U = 0 (see A/N) */
-        oris    r4,r4,0x0002            /* DBUS_SIZ[2] (8 bit on RCS1) */
+	oris    r4,r4,0x0002            /* DBUS_SIZ[2] (8 bit on RCS1) */
 
 /*      ori     r4,r4,0x8000            /  Registered DIMMs */
-        ori     r4,r4,0x2000            /*CAS Latency (CL=3) (see RDLAT) */
+	ori     r4,r4,0x2000            /*CAS Latency (CL=3) (see RDLAT) */
 /*      ori     r4,r4,0x2000            /  CAS Latency (CL=2) (see RDLAT) */
 /*      ori     r4,r4,0x0300            /  Sequential wrap/8-beat burst */
-        ori     r4,r4,0x0200            /* Sequential wrap/4-beat burst */
-        ori     r4,r4,0x0030            /* ACTORW  = 3 clocks */
-        ori     r4,r4,0x0009            /* BSTOPRE_L = 9 (see A/N) */
+	ori     r4,r4,0x0200            /* Sequential wrap/4-beat burst */
+	ori     r4,r4,0x0030            /* ACTORW  = 3 clocks */
+	ori     r4,r4,0x0009            /* BSTOPRE_L = 9 (see A/N) */
 
-        ori     r3, r10, MCCR4@l
-        bl      __pci_config_write_32
+	ori     r3, r10, MCCR4@l
+	bl      __pci_config_write_32
 
 	/* MSAR1 */
-        lis     r4, 0xc0804000@h
-        ori     r4, r4, 0xc0804000@l
-        ori     r3, r10, MSAR1@l
-        bl      __pci_config_write_32
+	lis     r4, 0xc0804000@h
+	ori     r4, r4, 0xc0804000@l
+	ori     r3, r10, MSAR1@l
+	bl      __pci_config_write_32
 
 	/* MSAR2 */
-        lis     r4, 0xc0804000@h
-        ori     r4, r4, 0xc0804000@l
-        ori     r3, r10, MSAR2@l
-        bl      __pci_config_write_32
+	lis     r4, 0xc0804000@h
+	ori     r4, r4, 0xc0804000@l
+	ori     r3, r10, MSAR2@l
+	bl      __pci_config_write_32
 
 	/* MESAR1 */
-        lis     r4, 0x00000000@h
-        ori     r4, r4, 0x00000000@l
-        ori     r3, r10, EMSAR1@l
-        bl      __pci_config_write_32
+	lis     r4, 0x00000000@h
+	ori     r4, r4, 0x00000000@l
+	ori     r3, r10, EMSAR1@l
+	bl      __pci_config_write_32
 
 	/* MESAR2 */
-        lis     r4, 0x01010101@h
-        ori     r4, r4, 0x01010101@l
-        ori     r3, r10, EMSAR2@l
-        bl      __pci_config_write_32
+	lis     r4, 0x01010101@h
+	ori     r4, r4, 0x01010101@l
+	ori     r3, r10, EMSAR2@l
+	bl      __pci_config_write_32
 
 	/* MEAR1 */
-        lis     r4, 0xffbf7f3f@h
-        ori     r4, r4, 0xffbf7f3f@l
-        ori     r3, r10, MEAR1@l
-        bl      __pci_config_write_32
+	lis     r4, 0xffbf7f3f@h
+	ori     r4, r4, 0xffbf7f3f@l
+	ori     r3, r10, MEAR1@l
+	bl      __pci_config_write_32
 
 	/* MEAR2 */
-        lis     r4, 0xffbf7f3f@h
-        ori     r4, r4, 0xffbf7f3f@l
-        ori     r3, r10, MEAR2@l
-        bl      __pci_config_write_32
+	lis     r4, 0xffbf7f3f@h
+	ori     r4, r4, 0xffbf7f3f@l
+	ori     r3, r10, MEAR2@l
+	bl      __pci_config_write_32
 
 	/* MEEAR1 */
-        lis     r4, 0x00000000@h
-        ori     r4, r4, 0x00000000@l
-        ori     r3, r10, EMEAR1@l
-        bl      __pci_config_write_32
+	lis     r4, 0x00000000@h
+	ori     r4, r4, 0x00000000@l
+	ori     r3, r10, EMEAR1@l
+	bl      __pci_config_write_32
 
 	/* MEEAR2 */
-        lis     r4, 0x01010101@h
-        ori     r4, r4, 0x01010101@l
-        ori     r3, r10, EMEAR2@l
-        bl      __pci_config_write_32
+	lis     r4, 0x01010101@h
+	ori     r4, r4, 0x01010101@l
+	ori     r3, r10, EMEAR2@l
+	bl      __pci_config_write_32
 
 	/* ODCR */
-        li      r4, 0x7f
-        ori     r3, r10, ODCR@l
-        bl      __pci_config_write_8
+	li      r4, 0x7f
+	ori     r3, r10, ODCR@l
+	bl      __pci_config_write_8
 
 	/* MBER */
-        li      r4, 0x01
-        ori     r3, r10, MBER@l
-        bl      __pci_config_write_8
+	li      r4, 0x01
+	ori     r3, r10, MBER@l
+	bl      __pci_config_write_8
 
-        /* Page CTR aka PGMAX */
-        li      r4, 0x32
-        ori     r3, r10, 0x70
-        bl      __pci_config_write_8
+	/* Page CTR aka PGMAX */
+	li      r4, 0x32
+	ori     r3, r10, 0x70
+	bl      __pci_config_write_8
 
 #if 0
 	/* CLK Drive */
-        ori     r4, r10, 0xfc01 /* Top bit will be ignored */
-        ori     r3, r10, 0x74
-        bl      __pci_config_write_16
+	ori     r4, r10, 0xfc01 /* Top bit will be ignored */
+	ori     r3, r10, 0x74
+	bl      __pci_config_write_16
 #endif
 
 	/* delay */
-        lis     r7, 1
-        mtctr   r7
+	lis     r7, 1
+	mtctr   r7
 label1: 	bdnz    label1
 
-        /* Set memgo bit */
-        /* MCCR1 */
-        ori     r3, r10, MCCR1@l
-        bl      __pci_config_read_32
-        lis	r7, 0x0008
-        or	r4, r3, r7
-        ori     r3, r10, MCCR1@l
-        bl      __pci_config_write_32
+	/* Set memgo bit */
+	/* MCCR1 */
+	ori     r3, r10, MCCR1@l
+	bl      __pci_config_read_32
+	lis	r7, 0x0008
+	or	r4, r3, r7
+	ori     r3, r10, MCCR1@l
+	bl      __pci_config_write_32
 
 	/* delay again */
-        lis     r7, 1
-        mtctr   r7
+	lis     r7, 1
+	mtctr   r7
 label2: 	bdnz    label2
 #if 0
 /* DEBUG: Infinite loop, write then read */
 loop:
-        lis     r7, 0xffff
-        mtctr   r7
-        li	r3, 0x5004
-        lis	r4, 0xa0a0
-        ori	r4, r4, 0x5050
+	lis     r7, 0xffff
+	mtctr   r7
+	li	r3, 0x5004
+	lis	r4, 0xa0a0
+	ori	r4, r4, 0x5050
 	bl write_32_ne
-        li	r3, 0x5004
+	li	r3, 0x5004
 	bl read_32_ne
-      	bdnz    loop
+	bdnz    loop
 #endif
-        mtlr    r11
-        blr
+	mtlr    r11
+	blr
 #endif
-
diff --git a/board/bmw/flash.c b/board/bmw/flash.c
index be62274..e04af97 100644
--- a/board/bmw/flash.c
+++ b/board/bmw/flash.c
@@ -91,7 +91,6 @@
 #endif /* 0 */
 
 
-
 static unsigned long
 flash_id(unsigned char mfct, unsigned char chip)
 {
@@ -135,7 +134,6 @@
 }
 
 
-
 unsigned long
 flash_init(void)
 {
@@ -181,9 +179,9 @@
     switch(pflinfo->flash_id & FLASH_TYPEMASK)
     {
       case FLASH_AM040:
-        pflinfo->size = 0x00080000;
+	pflinfo->size = 0x00080000;
 	pflinfo->sector_count = 8;
-        for(j = 0; j < 8; j++)
+	for(j = 0; j < 8; j++)
 	{
 	  pflinfo->start[j] = base_address + 0x00010000 * j;
 	  pflinfo->protect[j] = flash[(j << 16) | 0x2];
@@ -201,16 +199,16 @@
 	  pflinfo->start[j+3] = base_address + 0x00010000 * j;
 	}
 #if 0
-        /* check for protected sectors */
-        for (j = 0; j < pflinfo->sector_count; j++) {
-          /* read sector protection at sector address, (A7 .. A0) = 0x02 */
-          /* D0 = 1 if protected */
-          addr2 = (volatile FLASH_WORD_SIZE *)(pflinfo->start[j]);
-            if (pflinfo->flash_id & FLASH_MAN_SST)
-              pflinfo->protect[j] = 0;
-            else
-              pflinfo->protect[j] = addr2[2] & 1;
-        }
+	/* check for protected sectors */
+	for (j = 0; j < pflinfo->sector_count; j++) {
+	  /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	  /* D0 = 1 if protected */
+	  addr2 = (volatile FLASH_WORD_SIZE *)(pflinfo->start[j]);
+	    if (pflinfo->flash_id & FLASH_MAN_SST)
+	      pflinfo->protect[j] = 0;
+	    else
+	      pflinfo->protect[j] = addr2[2] & 1;
+	}
 #endif
 	break;
     }
@@ -245,30 +243,30 @@
     int i;
 
     /* set up sector start address table */
-        if (info->flash_id & FLASH_MAN_SST)
-          {
-            for (i = 0; i < info->sector_count; i++)
-              info->start[i] = base + (i * 0x00010000);
-          }
-        else
+	if (info->flash_id & FLASH_MAN_SST)
+	  {
+	    for (i = 0; i < info->sector_count; i++)
+	      info->start[i] = base + (i * 0x00010000);
+	  }
+	else
     if (info->flash_id & FLASH_BTYPE) {
-        /* set sector offsets for bottom boot block type    */
-        info->start[0] = base + 0x00000000;
-        info->start[1] = base + 0x00004000;
-        info->start[2] = base + 0x00006000;
-        info->start[3] = base + 0x00008000;
-        for (i = 4; i < info->sector_count; i++) {
-            info->start[i] = base + (i * 0x00010000) - 0x00030000;
-        }
+	/* set sector offsets for bottom boot block type    */
+	info->start[0] = base + 0x00000000;
+	info->start[1] = base + 0x00004000;
+	info->start[2] = base + 0x00006000;
+	info->start[3] = base + 0x00008000;
+	for (i = 4; i < info->sector_count; i++) {
+	    info->start[i] = base + (i * 0x00010000) - 0x00030000;
+	}
     } else {
-        /* set sector offsets for top boot block type       */
-        i = info->sector_count - 1;
-        info->start[i--] = base + info->size - 0x00004000;
-        info->start[i--] = base + info->size - 0x00006000;
-        info->start[i--] = base + info->size - 0x00008000;
-        for (; i >= 0; i--) {
-            info->start[i] = base + i * 0x00010000;
-        }
+	/* set sector offsets for top boot block type       */
+	i = info->sector_count - 1;
+	info->start[i--] = base + info->size - 0x00004000;
+	info->start[i--] = base + info->size - 0x00006000;
+	info->start[i--] = base + info->size - 0x00008000;
+	for (; i >= 0; i--) {
+	    info->start[i] = base + i * 0x00010000;
+	}
     }
 
 }
@@ -367,7 +365,7 @@
    short i;
     FLASH_WORD_SIZE value;
     ulong base = (ulong)addr;
-        volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
 
     printf("flash_get_size: \n");
     /* Write auto select command: read Manufacturer ID */
@@ -379,123 +377,123 @@
 
     switch (value) {
     case (FLASH_WORD_SIZE)AMD_MANUFACT:
-        info->flash_id = FLASH_MAN_AMD;
-        break;
+	info->flash_id = FLASH_MAN_AMD;
+	break;
     case (FLASH_WORD_SIZE)FUJ_MANUFACT:
-        info->flash_id = FLASH_MAN_FUJ;
-        break;
+	info->flash_id = FLASH_MAN_FUJ;
+	break;
     case (FLASH_WORD_SIZE)SST_MANUFACT:
-        info->flash_id = FLASH_MAN_SST;
-        break;
+	info->flash_id = FLASH_MAN_SST;
+	break;
     default:
-        info->flash_id = FLASH_UNKNOWN;
-        info->sector_count = 0;
-        info->size = 0;
-        return (0);         /* no or unknown flash  */
+	info->flash_id = FLASH_UNKNOWN;
+	info->sector_count = 0;
+	info->size = 0;
+	return (0);         /* no or unknown flash  */
     }
     printf("recognised manufacturer");
 
     value = addr2[ADDR3];          /* device ID        */
-        debug ("\ndev_code=%x\n", value);
+	debug ("\ndev_code=%x\n", value);
 
     switch (value) {
     case (FLASH_WORD_SIZE)AMD_ID_LV400T:
-        info->flash_id += FLASH_AM400T;
-        info->sector_count = 11;
-        info->size = 0x00080000;
-        break;              /* => 0.5 MB        */
+	info->flash_id += FLASH_AM400T;
+	info->sector_count = 11;
+	info->size = 0x00080000;
+	break;              /* => 0.5 MB        */
 
     case (FLASH_WORD_SIZE)AMD_ID_LV400B:
-        info->flash_id += FLASH_AM400B;
-        info->sector_count = 11;
-        info->size = 0x00080000;
-        break;              /* => 0.5 MB        */
+	info->flash_id += FLASH_AM400B;
+	info->sector_count = 11;
+	info->size = 0x00080000;
+	break;              /* => 0.5 MB        */
 
     case (FLASH_WORD_SIZE)AMD_ID_LV800T:
-        info->flash_id += FLASH_AM800T;
-        info->sector_count = 19;
-        info->size = 0x00100000;
-        break;              /* => 1 MB      */
+	info->flash_id += FLASH_AM800T;
+	info->sector_count = 19;
+	info->size = 0x00100000;
+	break;              /* => 1 MB      */
 
     case (FLASH_WORD_SIZE)AMD_ID_LV800B:
-        info->flash_id += FLASH_AM800B;
-        info->sector_count = 19;
-        info->size = 0x00100000;
-        break;              /* => 1 MB      */
+	info->flash_id += FLASH_AM800B;
+	info->sector_count = 19;
+	info->size = 0x00100000;
+	break;              /* => 1 MB      */
 
     case (FLASH_WORD_SIZE)AMD_ID_LV160T:
-        info->flash_id += FLASH_AM160T;
-        info->sector_count = 35;
-        info->size = 0x00200000;
-        break;              /* => 2 MB      */
+	info->flash_id += FLASH_AM160T;
+	info->sector_count = 35;
+	info->size = 0x00200000;
+	break;              /* => 2 MB      */
 
     case (FLASH_WORD_SIZE)AMD_ID_LV160B:
-        info->flash_id += FLASH_AM160B;
-        info->sector_count = 35;
-        info->size = 0x00200000;
-        break;              /* => 2 MB      */
+	info->flash_id += FLASH_AM160B;
+	info->sector_count = 35;
+	info->size = 0x00200000;
+	break;              /* => 2 MB      */
 
     case (FLASH_WORD_SIZE)SST_ID_xF800A:
-        info->flash_id += FLASH_SST800A;
-        info->sector_count = 16;
-        info->size = 0x00100000;
-        break;              /* => 1 MB      */
+	info->flash_id += FLASH_SST800A;
+	info->sector_count = 16;
+	info->size = 0x00100000;
+	break;              /* => 1 MB      */
 
     case (FLASH_WORD_SIZE)SST_ID_xF160A:
-        info->flash_id += FLASH_SST160A;
-        info->sector_count = 32;
-        info->size = 0x00200000;
-        break;              /* => 2 MB      */
+	info->flash_id += FLASH_SST160A;
+	info->sector_count = 32;
+	info->size = 0x00200000;
+	break;              /* => 2 MB      */
 
     case (FLASH_WORD_SIZE)AMD_ID_F040B:
-        info->flash_id += FLASH_AM040;
-        info->sector_count = 8;
-        info->size = 0x00080000;
-        break;              /* => 0.5 MB      */
+	info->flash_id += FLASH_AM040;
+	info->sector_count = 8;
+	info->size = 0x00080000;
+	break;              /* => 0.5 MB      */
 
     default:
-        info->flash_id = FLASH_UNKNOWN;
-        return (0);         /* => no or unknown flash */
+	info->flash_id = FLASH_UNKNOWN;
+	return (0);         /* => no or unknown flash */
 
     }
 
     printf("flash id %lx; sector count %x, size %lx\n", info->flash_id,info->sector_count,info->size);
     /* set up sector start address table */
-        if (info->flash_id & FLASH_MAN_SST)
-          {
-            for (i = 0; i < info->sector_count; i++)
-              info->start[i] = base + (i * 0x00010000);
-          }
-        else
+	if (info->flash_id & FLASH_MAN_SST)
+	  {
+	    for (i = 0; i < info->sector_count; i++)
+	      info->start[i] = base + (i * 0x00010000);
+	  }
+	else
     if (info->flash_id & FLASH_BTYPE) {
-        /* set sector offsets for bottom boot block type    */
-        info->start[0] = base + 0x00000000;
-        info->start[1] = base + 0x00004000;
-        info->start[2] = base + 0x00006000;
-        info->start[3] = base + 0x00008000;
-        for (i = 4; i < info->sector_count; i++) {
-            info->start[i] = base + (i * 0x00010000) - 0x00030000;
-        }
+	/* set sector offsets for bottom boot block type    */
+	info->start[0] = base + 0x00000000;
+	info->start[1] = base + 0x00004000;
+	info->start[2] = base + 0x00006000;
+	info->start[3] = base + 0x00008000;
+	for (i = 4; i < info->sector_count; i++) {
+	    info->start[i] = base + (i * 0x00010000) - 0x00030000;
+	}
     } else {
-        /* set sector offsets for top boot block type       */
-        i = info->sector_count - 1;
-        info->start[i--] = base + info->size - 0x00004000;
-        info->start[i--] = base + info->size - 0x00006000;
-        info->start[i--] = base + info->size - 0x00008000;
-        for (; i >= 0; i--) {
-            info->start[i] = base + i * 0x00010000;
-        }
+	/* set sector offsets for top boot block type       */
+	i = info->sector_count - 1;
+	info->start[i--] = base + info->size - 0x00004000;
+	info->start[i--] = base + info->size - 0x00006000;
+	info->start[i--] = base + info->size - 0x00008000;
+	for (; i >= 0; i--) {
+	    info->start[i] = base + i * 0x00010000;
+	}
     }
 
     /* check for protected sectors */
     for (i = 0; i < info->sector_count; i++) {
-        /* read sector protection at sector address, (A7 .. A0) = 0x02 */
-        /* D0 = 1 if protected */
-        addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
-                if (info->flash_id & FLASH_MAN_SST)
-                  info->protect[i] = 0;
-                else
-                  info->protect[i] = addr2[2] & 1;
+	/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	/* D0 = 1 if protected */
+	addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		if (info->flash_id & FLASH_MAN_SST)
+		  info->protect[i] = 0;
+		else
+		  info->protect[i] = addr2[2] & 1;
     }
 
     /*
@@ -503,7 +501,7 @@
      */
     if (info->flash_id != FLASH_UNKNOWN) {
        addr2 = (FLASH_WORD_SIZE *)info->start[0];
-        *addr2 = (FLASH_WORD_SIZE)0x00F000F0;   /* reset bank */
+	*addr2 = (FLASH_WORD_SIZE)0x00F000F0;   /* reset bank */
     }
 
     return (info->size);
@@ -521,32 +519,32 @@
     unsigned char sh8b;
 
     if ((s_first < 0) || (s_first > s_last)) {
-        if (info->flash_id == FLASH_UNKNOWN) {
-            printf ("- missing\n");
-        } else {
-            printf ("- no sectors to erase\n");
-        }
-        return 1;
+	if (info->flash_id == FLASH_UNKNOWN) {
+	    printf ("- missing\n");
+	} else {
+	    printf ("- no sectors to erase\n");
+	}
+	return 1;
     }
 
     if ((info->flash_id == FLASH_UNKNOWN) ||
-        (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
-        printf ("Can't erase unknown flash type - aborted\n");
-        return 1;
+	(info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
+	printf ("Can't erase unknown flash type - aborted\n");
+	return 1;
     }
 
     prot = 0;
     for (sect=s_first; sect<=s_last; ++sect) {
-        if (info->protect[sect]) {
-            prot++;
-        }
+	if (info->protect[sect]) {
+	    prot++;
+	}
     }
 
     if (prot) {
-        printf ("- Warning: %d protected sectors will not be erased!\n",
-            prot);
+	printf ("- Warning: %d protected sectors will not be erased!\n",
+	    prot);
     } else {
-        printf ("\n");
+	printf ("\n");
     }
 
     l_sect = -1;
@@ -568,28 +566,28 @@
 
     /* Start erase on unprotected sectors */
     for (sect = s_first; sect<=s_last; sect++) {
-        if (info->protect[sect] == 0) { /* not protected */
-            addr = (FLASH_WORD_SIZE *)(info->start[0] + (
+	if (info->protect[sect] == 0) { /* not protected */
+	    addr = (FLASH_WORD_SIZE *)(info->start[0] + (
 				(info->start[sect] - info->start[0]) << sh8b));
-                        if (info->flash_id & FLASH_MAN_SST)
-                          {
-                            addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
-                            addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
-                            addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080;
-                            addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
-                            addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
-                            addr[0] = (FLASH_WORD_SIZE)0x00500050;  /* block erase */
-                            udelay(30000);  /* wait 30 ms */
-                          }
-                        else
-                          addr[0] = (FLASH_WORD_SIZE)0x00300030;  /* sector erase */
-            l_sect = sect;
-        }
+			if (info->flash_id & FLASH_MAN_SST)
+			  {
+			    addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+			    addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080;
+			    addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+			    addr[0] = (FLASH_WORD_SIZE)0x00500050;  /* block erase */
+			    udelay(30000);  /* wait 30 ms */
+			  }
+			else
+			  addr[0] = (FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+	    l_sect = sect;
+	}
     }
 
     /* re-enable interrupts if necessary */
     if (flag)
-        enable_interrupts();
+	enable_interrupts();
 
     /* wait at least 80us - let's wait 1 ms */
     udelay (1000);
@@ -598,22 +596,22 @@
      * We wait for the last triggered sector
      */
     if (l_sect < 0)
-        goto DONE;
+	goto DONE;
 
     start = get_timer (0);
     last  = start;
     addr = (FLASH_WORD_SIZE *)(info->start[0] + (
 			(info->start[l_sect] - info->start[0]) << sh8b));
     while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
-        if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
-            printf ("Timeout\n");
-            return 1;
-        }
-        /* show that we're waiting */
-        if ((now - last) > 1000) {  /* every second */
-            serial_putc ('.');
-            last = now;
-        }
+	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return 1;
+	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {  /* every second */
+	    serial_putc ('.');
+	    last = now;
+	}
     }
 
 DONE:
@@ -643,42 +641,42 @@
      * handle unaligned start bytes
      */
     if ((l = addr - wp) != 0) {
-        data = 0;
-        for (i=0, cp=wp; i<l; ++i, ++cp) {
-            data = (data << 8) | (*(uchar *)cp);
-        }
-        for (; i<4 && cnt>0; ++i) {
-            data = (data << 8) | *src++;
-            --cnt;
-            ++cp;
-        }
-        for (; cnt==0 && i<4; ++i, ++cp) {
-            data = (data << 8) | (*(uchar *)cp);
-        }
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+	for (; i<4 && cnt>0; ++i) {
+	    data = (data << 8) | *src++;
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<4; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
 
-        if ((rc = write_word(info, wp, data)) != 0) {
-            return (rc);
-        }
-        wp += 4;
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
     }
 
     /*
      * handle word aligned part
      */
     while (cnt >= 4) {
-        data = 0;
-        for (i=0; i<4; ++i) {
-            data = (data << 8) | *src++;
-        }
-        if ((rc = write_word(info, wp, data)) != 0) {
-            return (rc);
-        }
-        wp  += 4;
-        cnt -= 4;
+	data = 0;
+	for (i=0; i<4; ++i) {
+	    data = (data << 8) | *src++;
+	}
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp  += 4;
+	cnt -= 4;
     }
 
     if (cnt == 0) {
-        return (0);
+	return (0);
     }
 
     /*
@@ -686,11 +684,11 @@
      */
     data = 0;
     for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-        data = (data << 8) | *src++;
-        --cnt;
+	data = (data << 8) | *src++;
+	--cnt;
     }
     for (; i<4; ++i, ++cp) {
-        data = (data << 8) | (*(uchar *)cp);
+	data = (data << 8) | (*(uchar *)cp);
     }
 
     return (write_word(info, wp, data));
@@ -704,12 +702,12 @@
  */
 static int write_word (flash_info_t *info, ulong dest, ulong data)
 {
-        volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)info->start[0];
-        volatile FLASH_WORD_SIZE *dest2;
-        volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)info->start[0];
+	volatile FLASH_WORD_SIZE *dest2;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
     ulong start;
     int flag;
-        int i;
+	int i;
     unsigned char sh8b;
 
     /* Check the ROM CS */
@@ -723,32 +721,32 @@
 
     /* Check if Flash is (sufficiently) erased */
     if ((*dest2 & (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
-        return (2);
+	return (2);
     }
     /* Disable interrupts which might cause a timeout here */
     flag = disable_interrupts();
 
-        for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
-          {
-            addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
-            addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
-            addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00A000A0;
+	for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
+	  {
+	    addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+	    addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+	    addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00A000A0;
 
-            dest2[i << sh8b] = data2[i];
+	    dest2[i << sh8b] = data2[i];
 
-            /* re-enable interrupts if necessary */
-            if (flag)
-              enable_interrupts();
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	      enable_interrupts();
 
-            /* data polling for D7 */
-            start = get_timer (0);
-            while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) !=
-                   (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
-              if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
-                return (1);
-              }
-            }
-          }
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) !=
+		   (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
+	      if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		return (1);
+	      }
+	    }
+	  }
 
     return (0);
 }
diff --git a/board/bmw/m48t59y.c b/board/bmw/m48t59y.c
index 469f1ad..d72c861 100644
--- a/board/bmw/m48t59y.c
+++ b/board/bmw/m48t59y.c
@@ -320,4 +320,3 @@
 {
   m48_tod_init();
 }
-
diff --git a/board/bmw/ns16550.c b/board/bmw/ns16550.c
index b6b6f4c..b1c28eb 100644
--- a/board/bmw/ns16550.c
+++ b/board/bmw/ns16550.c
@@ -55,6 +55,3 @@
 {
  return ((com_port->lsr & LSR_DR) != 0);
 }
-
-
-
diff --git a/board/bmw/ns16550.h b/board/bmw/ns16550.h
index b80ac02..0b7b389 100644
--- a/board/bmw/ns16550.h
+++ b/board/bmw/ns16550.h
@@ -78,4 +78,3 @@
 unsigned char NS16550_getc(volatile struct NS16550 *com_port);
 int NS16550_tstc(volatile struct NS16550 *com_port);
 void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor);
-
diff --git a/board/bmw/u-boot.lds b/board/bmw/u-boot.lds
index 5ba99b1..98584dc 100644
--- a/board/bmw/u-boot.lds
+++ b/board/bmw/u-boot.lds
@@ -103,6 +103,11 @@
   _edata  =  .;
   PROVIDE (edata = .);
 
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
   __start___ex_table = .;
   __ex_table : { *(__ex_table) }
   __stop___ex_table = .;
@@ -126,4 +131,3 @@
   _end = . ;
   PROVIDE (end = .);
 }
-