* Code cleanup:
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
diff --git a/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
index 1d6ca81..0934e1b 100644
--- a/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
+++ b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
@@ -30,47 +30,47 @@
#include "via686.h"
__asm(" .globl send_kb \n
- send_kb: \n
- lis r9, 0xfe00 \n
- \n
- li r4, 0x10 # retries \n
- mtctr r4 \n
- \n
- idle: \n
- lbz r4, 0x64(r9) \n
- andi. r4, r4, 0x02 \n
- bne idle \n
- \n
- ready: \n
- stb r3, 0x60(r9) \n
- \n
- check: \n
- lbz r4, 0x64(r9) \n
- andi. r4, r4, 0x01 \n
- beq check \n
- \n
- lbz r4, 0x60(r9) \n
- cmpwi r4, 0xfa \n
- beq done \n
- \n
- bdnz idle \n
- \n
- li r3, 0 \n
- blr \n
- \n
- done: \n
- li r3, 1 \n
- blr \n
- \n
- .globl test_kb \n
- test_kb: \n
- mflr r10 \n
- li r3, 0xed \n
- bl send_kb \n
- li r3, 0x01 \n
- bl send_kb \n
- mtlr r10 \n
- blr \n
+ send_kb: \n
+ lis r9, 0xfe00 \n
+ \n
+ li r4, 0x10 # retries \n
+ mtctr r4 \n
+ \n
+ idle: \n
+ lbz r4, 0x64(r9) \n
+ andi. r4, r4, 0x02 \n
+ bne idle \n
+ \n
+ ready: \n
+ stb r3, 0x60(r9) \n
+ \n
+ check: \n
+ lbz r4, 0x64(r9) \n
+ andi. r4, r4, 0x01 \n
+ beq check \n
+ \n
+ lbz r4, 0x60(r9) \n
+ cmpwi r4, 0xfa \n
+ beq done \n
+ \n
+ bdnz idle \n
+ \n
+ li r3, 0 \n
+ blr \n
+ \n
+ done: \n
+ li r3, 1 \n
+ blr \n
+ \n
+ .globl test_kb \n
+ test_kb: \n
+ mflr r10 \n
+ li r3, 0xed \n
+ bl send_kb \n
+ li r3, 0x01 \n
+ bl send_kb \n
+ mtlr r10 \n
+ blr \n
");
@@ -86,7 +86,6 @@
}
-
void after_reloc (ulong dest_addr, gd_t *gd)
{
/* HJF: DECLARE_GLOBAL_DATA_PTR; */
diff --git a/board/MAI/AmigaOneG3SE/Makefile b/board/MAI/AmigaOneG3SE/Makefile
index 785f01f..b1247fe 100644
--- a/board/MAI/AmigaOneG3SE/Makefile
+++ b/board/MAI/AmigaOneG3SE/Makefile
@@ -33,14 +33,14 @@
AOBJS = board_asm_init.o memio.o
-OBJS = $(COBJS) $(AOBJS)
+OBJS = $(COBJS) $(AOBJS)
EMUDIR = ../bios_emulator/scitech/src/x86emu/
EMUOBJ = $(EMUDIR)decode.o $(EMUDIR)ops2.o $(EMUDIR)fpu.o $(EMUDIR)prim_ops.o \
$(EMUDIR)ops.o $(EMUDIR)sys.o
EMUSRC = $(EMUOBJ:.o=.c)
-$(LIB): .depend $(OBJS) $(EMUSRC)
+$(LIB): .depend $(OBJS) $(EMUSRC)
make libx86emu.a -C ../bios_emulator/scitech/src/x86emu -f makefile.uboot CROSS_COMPILE=$(CROSS_COMPILE)
-rm $(LIB)
$(AR) crv $@ $(OBJS) $(EMUOBJ)
diff --git a/board/MAI/AmigaOneG3SE/articiaS.c b/board/MAI/AmigaOneG3SE/articiaS.c
index 5eddfc6..9fd6b95 100644
--- a/board/MAI/AmigaOneG3SE/articiaS.c
+++ b/board/MAI/AmigaOneG3SE/articiaS.c
@@ -1,6 +1,6 @@
/*
* (C) Copyright 2002
- * Hyperion Entertainment, ThomasF@hyperion-entertainment.com
+ * Hyperion Entertainment, ThomasF@hyperion-entertainment.com
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -572,7 +572,7 @@
if (banks[3].used)
burst_support = banks[3].burst_len;
- /*
+ /*
** Mode register:
** Bits Use
** 0-2 Burst len
diff --git a/board/MAI/AmigaOneG3SE/articiaS.h b/board/MAI/AmigaOneG3SE/articiaS.h
index 158d70a..ce20d03 100644
--- a/board/MAI/AmigaOneG3SE/articiaS.h
+++ b/board/MAI/AmigaOneG3SE/articiaS.h
@@ -99,14 +99,14 @@
#define XDBCR_HWTOXD (1<<0)
#define XDBCR_KBTOXD (1<<1)
#define XDBCR_RTCTOXD (1<<2)
-#define XDBCR_SCALE_1_1 (0x0<<3)
-#define XDBCR_SCALE_2_2 (0x1<<3)
-#define XDBCR_SCALE_3_2 (0x2<<3)
-#define XDBCR_SCALE_4_4 (0x3<<3)
-#define XDBCR_SCALE_5_8 (0x4<<3)
-#define XDBCR_SCALE_6_8 (0x5<<3)
-#define XDBCR_SCALE_8_8 (0x6<<3)
-#define XDBCR_SCALE_0_16 (0x7<<3)
+#define XDBCR_SCALE_1_1 (0x0<<3)
+#define XDBCR_SCALE_2_2 (0x1<<3)
+#define XDBCR_SCALE_3_2 (0x2<<3)
+#define XDBCR_SCALE_4_4 (0x3<<3)
+#define XDBCR_SCALE_5_8 (0x4<<3)
+#define XDBCR_SCALE_6_8 (0x5<<3)
+#define XDBCR_SCALE_8_8 (0x6<<3)
+#define XDBCR_SCALE_0_16 (0x7<<3)
#define XDBCR_XDPROM (1<<7)
@@ -134,7 +134,6 @@
#define ARTICIAS_ISAIO_PHYS 0xfe002000
-
/* Prototypes */
long articiaS_ram_init(void);
void articiaS_pci_init(void);
diff --git a/board/MAI/AmigaOneG3SE/articiaS_pci.c b/board/MAI/AmigaOneG3SE/articiaS_pci.c
index 2a7763d..d2e9f29 100644
--- a/board/MAI/AmigaOneG3SE/articiaS_pci.c
+++ b/board/MAI/AmigaOneG3SE/articiaS_pci.c
@@ -123,14 +123,14 @@
{
{ 0, 0, 0, 0xff}, /* Articia S host bridge */
{ 0, 1, 0, 0xff}, /* Articia S AGP bridge */
-// { 0, 6, 0, 0x05}, /* 3COM ethernet */
+/* { 0, 6, 0, 0x05}, /###* 3COM ethernet */
{ 0, 7, 0, 0xff}, /* VIA southbridge */
{ 0, 7, 1, 0x0e}, /* IDE controller in legacy mode */
-// { 0, 7, 2, 0x05}, /* First USB controller */
-// { 0, 7, 3, 0x0c}, /* Second USB controller (shares interrupt with ethernet) */
+/* { 0, 7, 2, 0x05}, /###* First USB controller */
+/* { 0, 7, 3, 0x0c}, /###* Second USB controller (shares interrupt with ethernet) */
{ 0, 7, 4, 0xff}, /* ACPI Power Management */
-// { 0, 7, 5, 0x08}, /* AC97 */
-// { 0, 7, 6, 0x08}, /* MC97 */
+/* { 0, 7, 5, 0x08}, /###* AC97 */
+/* { 0, 7, 6, 0x08}, /###* MC97 */
{ 0xff, 0xff, 0xff, 0xff}
};
@@ -287,7 +287,7 @@
PRINTF("atriciaS_pci_init\n");
- // Why aren't these relocated??
+ /* Why aren't these relocated?? */
for (i=0; config_table[i].config_device; i++)
{
switch((int)config_table[i].config_device)
@@ -335,7 +335,6 @@
PCI_REGION_IO);
-
articiaS_hose.region_count = 4;
pci_setup_indirect(&articiaS_hose, ARTICIAS_PCI_CFGADDR, ARTICIAS_PCI_CFGDATA);
@@ -410,8 +409,8 @@
pci_hose_read_config_byte(hose, dev, 0x0B, &c1);
pci_hose_read_config_byte(hose, dev, 0x0A, &c2);
class = c1<<8 | c2;
- //printf("At %02x:%02x:%02x: class %x\n",
- // PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), class);
+ /*printf("At %02x:%02x:%02x: class %x\n", */
+ /* PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), class); */
if (class == find_class)
{
if (index == 0)
@@ -441,7 +440,7 @@
if (hose == NULL) hose = &articiaS_hose;
- if (busnr < hose->first_busno || busnr > hose->last_busno) return PCI_ANY_ID; // Not in range
+ if (busnr < hose->first_busno || busnr > hose->last_busno) return PCI_ANY_ID; /* Not in range */
/*
* The bridge must be on a lower bus number
@@ -467,7 +466,7 @@
if (!PCI_FUNC(dev))
found_multi = header_type & 0x80;
- if (header_type == 1) // Bridge device header
+ if (header_type == 1) /* Bridge device header */
{
pci_hose_read_config_byte(hose, dev, PCI_SECONDARY_BUS, &secondary_bus);
if ((int)secondary_bus == busnr) return dev;
@@ -512,7 +511,7 @@
PRINTF("Searching for class 0x%x on bus %d\n", classes[classnr], busnr);
/* Find the first of this class on this bus */
dev = pci_hose_find_class(&articiaS_hose, busnr, classes[classnr], 0);
- if (dev != ~0)
+ if (dev != ~0)
{
PRINTF("Found VGA Card at %02x:%02x:%02x\n", PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
break;
diff --git a/board/MAI/AmigaOneG3SE/board_asm_init.S b/board/MAI/AmigaOneG3SE/board_asm_init.S
index a421c5d..086b19c 100644
--- a/board/MAI/AmigaOneG3SE/board_asm_init.S
+++ b/board/MAI/AmigaOneG3SE/board_asm_init.S
@@ -1,14 +1,13 @@
- #include "macros.h"
-
-
+#include "macros.h"
-#define GLOBALINFO0 0x50
+
+#define GLOBALINFO0 0x50
#define GLOBALINFO0_BO (1<<7)
#define GLOBALINFO2_B1ARBITER (1<<6)
#define HBUSACR0 0x5c
#define HBUSACR2_BURST (1<<0)
#define HBUSACR2_LAT (1<<1)
-
+
#define RECEIVER_HOLDING 0
#define TRANSMITTER_HOLDING 0
#define INTERRUPT_ENABLE 1
@@ -35,9 +34,9 @@
#define SUPERIO_1 ((7 << 3) | (0))
#define SUPERIO_2 ((7 << 3) | (1))
-
+
.globl board_asm_init
-
+
board_asm_init:
mflr r29
/* Set 'Must-set' register */
@@ -77,7 +76,7 @@
li r5, 0x47
bl pci_write_cfg_byte*/
-
+
/* Enable NVRAM for environment */
li r3, 0
li r4, 0
@@ -91,7 +90,7 @@
siowb 0x40, 0x08
siowb 0x41, 0x01
siowb 0x45, 0x80
- siowb 0x46, 0x60
+ siowb 0x46, 0x60
siowb 0x47, 0x20
siowb 0x48, 0x01
siowb 0x4a, 0xc4
@@ -103,7 +102,7 @@
siowb 0x56, 0x99
siowb 0x57, 0x90
siowb 0x85, 0x01
-
+
/* Enable configuration mode for SuperIO */
li r3, 0
li r4, (7<<3)
@@ -128,7 +127,7 @@
ori r3, r3, 0x0c
outb 0x3f0, 0xe2
outbr 0x3f1, r3
-
+
/* Disable configuration mode */
li r3, 0
li r4, (7<<3)
@@ -145,7 +144,7 @@
mtlr r29
blr
-
+
.globl new_reset
.globl new_reset_end
new_reset:
@@ -153,5 +152,5 @@
oris r0, r0, 0xFFF0
mtlr r0
blr
-
-new_reset_end:
\ No newline at end of file
+
+new_reset_end:
diff --git a/board/MAI/AmigaOneG3SE/cmd_boota.c b/board/MAI/AmigaOneG3SE/cmd_boota.c
index 140aaff..db1ecfc 100644
--- a/board/MAI/AmigaOneG3SE/cmd_boota.c
+++ b/board/MAI/AmigaOneG3SE/cmd_boota.c
@@ -1,6 +1,5 @@
#include <common.h>
#include <command.h>
-#include <cmd_boota.h>
#include "../disk/part_amiga.h"
#include <asm/cache.h>
@@ -121,3 +120,10 @@
return 0;
}
+#if defined(CONFIG_AMIGAONEG3SE) && (CONFIG_COMMANDS & CFG_CMD_BSP)
+cmd_tbl_t U_BOOT_CMD(BOOTA) = MK_CMD_ENTRY(
+ "boota", 3, 1, do_boota,
+ "boota - boot an Amiga kernel\n",
+ "address disk"
+);
+#endif /* _CMD_BOOTA_H */
diff --git a/board/MAI/AmigaOneG3SE/config.mk b/board/MAI/AmigaOneG3SE/config.mk
index d7d0e6b..930a793 100644
--- a/board/MAI/AmigaOneG3SE/config.mk
+++ b/board/MAI/AmigaOneG3SE/config.mk
@@ -29,5 +29,4 @@
TEXT_BASE = 0xfff00000
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -Wa,-mregnames -DEASTEREGG $(X86EMU) -Dprintk=printf #-DDEBUG
-
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -Wa,-mregnames -DEASTEREGG $(X86EMU) -Dprintk=printf #-DDEBUG
diff --git a/board/MAI/AmigaOneG3SE/enet.c b/board/MAI/AmigaOneG3SE/enet.c
index 0aaa8bf..d4be889 100644
--- a/board/MAI/AmigaOneG3SE/enet.c
+++ b/board/MAI/AmigaOneG3SE/enet.c
@@ -36,45 +36,45 @@
/* 3Com Ethernet PCI definitions*/
-// #define PCI_VENDOR_ID_3COM 0x10B7
+/* #define PCI_VENDOR_ID_3COM 0x10B7 */
#define PCI_DEVICE_ID_3COM_3C905C 0x9200
/* 3Com Commands, top 5 bits are command and bottom 11 bits are parameters */
-#define TotalReset (0<<11)
+#define TotalReset (0<<11)
#define SelectWindow (1<<11)
#define StartCoax (2<<11)
-#define RxDisable (3<<11)
-#define RxEnable (4<<11)
+#define RxDisable (3<<11)
+#define RxEnable (4<<11)
#define RxReset (5<<11)
-#define UpStall (6<<11)
+#define UpStall (6<<11)
#define UpUnstall (6<<11)+1
-#define DownStall (6<<11)+2
+#define DownStall (6<<11)+2
#define DownUnstall (6<<11)+3
#define RxDiscard (8<<11)
#define TxEnable (9<<11)
-#define TxDisable (10<<11)
+#define TxDisable (10<<11)
#define TxReset (11<<11)
-#define FakeIntr (12<<11)
-#define AckIntr (13<<11)
+#define FakeIntr (12<<11)
+#define AckIntr (13<<11)
#define SetIntrEnb (14<<11)
-#define SetStatusEnb (15<<11)
+#define SetStatusEnb (15<<11)
#define SetRxFilter (16<<11)
#define SetRxThreshold (17<<11)
-#define SetTxThreshold (18<<11)
+#define SetTxThreshold (18<<11)
#define SetTxStart (19<<11)
#define StartDMAUp (20<<11)
#define StartDMADown (20<<11)+1
#define StatsEnable (21<<11)
-#define StatsDisable (22<<11)
+#define StatsDisable (22<<11)
#define StopCoax (23<<11)
#define SetFilterBit (25<<11)
/* The SetRxFilter command accepts the following classes */
-#define RxStation 1
-#define RxMulticast 2
-#define RxBroadcast 4
+#define RxStation 1
+#define RxMulticast 2
+#define RxBroadcast 4
#define RxProm 8
/* 3Com status word defnitions */
@@ -83,12 +83,12 @@
#define HostError 0x0002
#define TxComplete 0x0004
#define TxAvailable 0x0008
-#define RxComplete 0x0010
+#define RxComplete 0x0010
#define RxEarly 0x0020
#define IntReq 0x0040
#define StatsFull 0x0080
#define DMADone (1<<8)
-#define DownComplete (1<<9)
+#define DownComplete (1<<9)
#define UpComplete (1<<10)
#define DMAInProgress (1<<11) /* DMA controller is still busy.*/
#define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/
@@ -114,31 +114,31 @@
/* EEPROM locations. */
-#define PhysAddr01 0
+#define PhysAddr01 0
#define PhysAddr23 1
-#define PhysAddr45 2
+#define PhysAddr45 2
#define ModelID 3
-#define EtherLink3ID 7
-#define IFXcvrIO 8
+#define EtherLink3ID 7
+#define IFXcvrIO 8
#define IRQLine 9
-#define NodeAddr01 10
-#define NodeAddr23 11
+#define NodeAddr01 10
+#define NodeAddr23 11
#define NodeAddr45 12
-#define DriverTune 13
+#define DriverTune 13
#define Checksum 15
/* Register window 1 offsets, the window used in normal operation */
-#define TX_FIFO 0x10
-#define RX_FIFO 0x10
+#define TX_FIFO 0x10
+#define RX_FIFO 0x10
#define RxErrors 0x14
-#define RxStatus 0x18
-#define Timer 0x1A
+#define RxStatus 0x18
+#define Timer 0x1A
#define TxStatus 0x1B
#define TxFree 0x1C /* Remaining free bytes in Tx buffer. */
/* Register Window 2 */
-
+
#define Wn2_ResetOptions 12
/* Register Window 3: MAC/config bits */
@@ -148,11 +148,11 @@
#define Wn3_Options 8
#define BFEXT(value, offset, bitcount) \
- ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
+ ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
#define BFINS(lhs, rhs, offset, bitcount) \
- (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
- (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
+ (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
+ (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
#define RAM_SIZE(v) BFEXT(v, 0, 3)
#define RAM_WIDTH(v) BFEXT(v, 3, 1)
@@ -163,7 +163,7 @@
#define AUTOSELECT(v) BFEXT(v, 24, 1)
/* Register Window 4: Xcvr/media bits */
-
+
#define Wn4_FIFODiag 4
#define Wn4_NetDiag 6
#define Wn4_PhysicalMgmt 8
@@ -196,28 +196,28 @@
#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
struct rx_desc_3com {
- u32 next; /* Last entry points to 0 */
- u32 status; /* FSH -> Frame Start Header */
- u32 addr; /* Up to 63 addr/len pairs possible */
- u32 length; /* Set LAST_FRAG to indicate last pair */
+ u32 next; /* Last entry points to 0 */
+ u32 status; /* FSH -> Frame Start Header */
+ u32 addr; /* Up to 63 addr/len pairs possible */
+ u32 length; /* Set LAST_FRAG to indicate last pair */
};
/* Values for the Rx status entry. */
#define RxDComplete 0x00008000
#define RxDError 0x4000
-#define IPChksumErr (1<<25)
-#define TCPChksumErr (1<<26)
+#define IPChksumErr (1<<25)
+#define TCPChksumErr (1<<26)
#define UDPChksumErr (1<<27)
-#define IPChksumValid (1<<29)
+#define IPChksumValid (1<<29)
#define TCPChksumValid (1<<30)
#define UDPChksumValid (1<<31)
struct tx_desc_3com {
- u32 next; /* Last entry points to 0 */
- u32 status; /* bits 0:12 length, others see below */
- u32 addr;
- u32 length;
+ u32 next; /* Last entry points to 0 */
+ u32 status; /* bits 0:12 length, others see below */
+ u32 addr;
+ u32 length;
};
/* Values for the Tx status entry. */
@@ -232,9 +232,9 @@
/* XCVR Types */
#define XCVR_10baseT 0
-#define XCVR_AUI 1
+#define XCVR_AUI 1
#define XCVR_10baseTOnly 2
-#define XCVR_10base2 3
+#define XCVR_10base2 3
#define XCVR_100baseTx 4
#define XCVR_100baseFx 5
#define XCVR_MII 6
@@ -243,10 +243,10 @@
#define XCVR_Default 10 /* I don't think this is correct -> should have been 0x10 if Auto Negotiate */
struct descriptor { /* A generic descriptor. */
- u32 next; /* Last entry points to 0 */
- u32 status; /* FSH -> Frame Start Header */
- u32 addr; /* Up to 63 addr/len pairs possible */
- u32 length; /* Set LAST_FRAG to indicate last pair */
+ u32 next; /* Last entry points to 0 */
+ u32 status; /* FSH -> Frame Start Header */
+ u32 addr; /* Up to 63 addr/len pairs possible */
+ u32 length; /* Set LAST_FRAG to indicate last pair */
};
/* Misc. definitions */
@@ -338,7 +338,7 @@
static inline void ETH_CMD(struct eth_device* dev, int command)
{
- *(volatile u16 *)io_to_phys(EL3_CMD + dev->iobase) = cpu_to_le16(command);
+ *(volatile u16 *)io_to_phys(EL3_CMD + dev->iobase) = cpu_to_le16(command);
__asm volatile ("eieio");
}
@@ -348,24 +348,24 @@
static int issue_and_wait(struct eth_device* dev, int command)
{
- int i, status;
+ int i, status;
ETH_CMD(dev, command);
- for (i = 0; i < 2000; i++) {
- status = ETH_STATUS(dev);
- //printf ("Issue: status 0x%4x.\n", status);
+ for (i = 0; i < 2000; i++) {
+ status = ETH_STATUS(dev);
+ /*printf ("Issue: status 0x%4x.\n", status); */
if (!(status & CmdInProgress))
- return 1;
- }
+ return 1;
+ }
- /* OK, that didn't work. Do it the slow way. One second */
- for (i = 0; i < 100000; i++) {
- status = ETH_STATUS(dev);
- //printf ("Issue: status 0x%4x.\n", status);
- return 1;
- udelay(10);
- }
- PRINTF("Ethernet command: 0x%4x did not complete! Status: 0x%4x\n", command, ETH_STATUS(dev) );
+ /* OK, that didn't work. Do it the slow way. One second */
+ for (i = 0; i < 100000; i++) {
+ status = ETH_STATUS(dev);
+ /*printf ("Issue: status 0x%4x.\n", status); */
+ return 1;
+ udelay(10);
+ }
+ PRINTF("Ethernet command: 0x%4x did not complete! Status: 0x%4x\n", command, ETH_STATUS(dev) );
return 0;
}
@@ -378,7 +378,7 @@
EL3WINDOW(dev, 1);
- // Wait for Auto negotiation to complete
+ /* Wait for Auto negotiation to complete */
for (i = 0; i <= 1000; i++)
{
if (ETH_INW(dev, 2) & 0x04)
@@ -391,7 +391,6 @@
return 0;
}
}
-
return 1;
@@ -430,10 +429,10 @@
int eth_3com_initialize(bd_t *bis)
{
- u32 eth_iobase = 0, status;
- int card_number = 0, ret;
- struct eth_device* dev;
- pci_dev_t devno;
+ u32 eth_iobase = 0, status;
+ int card_number = 0, ret;
+ struct eth_device* dev;
+ pci_dev_t devno;
char *s;
s = getenv("3com_base");
@@ -453,10 +452,10 @@
}
ret = pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, ð_iobase);
- eth_iobase &= ~0xf;
+ eth_iobase &= ~0xf;
PRINTF("eth: 3Com Found at Address: 0x%x\n", eth_iobase);
-
+
pci_write_config_dword(devno, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
/* Check if I/O accesses and Bus Mastering are enabled */
@@ -481,28 +480,28 @@
goto Done;
}
- dev = (struct eth_device*) malloc(sizeof(*dev)); //struct eth_device));
+ dev = (struct eth_device*) malloc(sizeof(*dev)); /*struct eth_device)); */
- sprintf(dev->name, "3Com 3c920c#%d", card_number);
- dev->iobase = eth_iobase;
- dev->priv = (void*) devno;
- dev->init = eth_3com_init;
- dev->halt = eth_3com_halt;
- dev->send = eth_3com_send;
- dev->recv = eth_3com_recv;
+ sprintf(dev->name, "3Com 3c920c#%d", card_number);
+ dev->iobase = eth_iobase;
+ dev->priv = (void*) devno;
+ dev->init = eth_3com_init;
+ dev->halt = eth_3com_halt;
+ dev->send = eth_3com_send;
+ dev->recv = eth_3com_recv;
- eth_register(dev);
+ eth_register(dev);
/* { */
/* char interrupt; */
/* devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0); */
/* pci_read_config_byte(devno, PCI_INTERRUPT_LINE, &interrupt); */
-
+
/* printf("Installing eth0 interrupt handler to %d\n", interrupt); */
/* irq_install_handler(interrupt, eth_interrupt, dev); */
/* } */
- card_number++;
+ card_number++;
/* Set the latency timer for value */
s = getenv("3com_latency");
@@ -532,13 +531,13 @@
PRINTF ("Cannot allocate memory for RX_RING.....\n");
goto Done;
}
-
+
if (!(tx_ring = memalign(sizeof(struct tx_desc_3com) * NUM_TX_DESC, 16)))
{
PRINTF ("Cannot allocate memory for TX_RING.....\n");
goto Done;
}
-
+
Done:
return status;
}
@@ -552,7 +551,7 @@
struct descriptor *ias_cmd;
/* Determine what type of network the machine is connected to */
- /* presently drops the connect to 10Mbps */
+ /* presently drops the connect to 10Mbps */
if (!auto_negotiate(dev))
{
@@ -560,43 +559,43 @@
goto Done;
}
- issue_and_wait(dev, TxReset);
- issue_and_wait(dev, RxReset|0x04);
+ issue_and_wait(dev, TxReset);
+ issue_and_wait(dev, RxReset|0x04);
- /* Switch to register set 7 for normal use. */
- EL3WINDOW(dev, 7);
+ /* Switch to register set 7 for normal use. */
+ EL3WINDOW(dev, 7);
/* Initialize Rx and Tx rings */
init_rx_ring(dev);
purge_tx_ring(dev);
- ETH_CMD(dev, SetRxFilter | RxStation | RxBroadcast | RxProm);
+ ETH_CMD(dev, SetRxFilter | RxStation | RxBroadcast | RxProm);
- issue_and_wait(dev,SetTxStart|0x07ff);
+ issue_and_wait(dev,SetTxStart|0x07ff);
- /* Below sets which indication bits to be seen. */
+ /* Below sets which indication bits to be seen. */
- status_enable = SetStatusEnb | HostError | DownComplete | UpComplete | (1<<6);
- ETH_CMD(dev, status_enable);
+ status_enable = SetStatusEnb | HostError | DownComplete | UpComplete | (1<<6);
+ ETH_CMD(dev, status_enable);
/* Below sets no bits are to cause an interrupt since this is just polling */
- intr_enable = SetIntrEnb;
-// intr_enable = SetIntrEnb | (1<<9) | (1<<10) | (1<<6);
- ETH_CMD(dev, intr_enable);
+ intr_enable = SetIntrEnb;
+/* intr_enable = SetIntrEnb | (1<<9) | (1<<10) | (1<<6); */
+ ETH_CMD(dev, intr_enable);
ETH_OUTB(dev, 127, UpPoll);
- /* Ack all pending events, and set active indicator mask */
+ /* Ack all pending events, and set active indicator mask */
- ETH_CMD(dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq);
- ETH_CMD(dev, intr_enable);
+ ETH_CMD(dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq);
+ ETH_CMD(dev, intr_enable);
/* Tell the adapter where the RX ring is located */
issue_and_wait(dev,UpStall); /* Stall and set the UplistPtr */
ETH_OUTL(dev, (u32)&rx_ring[rx_next], UpListPtr);
- ETH_CMD(dev, RxEnable); /* Enable the receiver. */
+ ETH_CMD(dev, RxEnable); /* Enable the receiver. */
issue_and_wait(dev,UpUnstall);
/* Send the Individual Address Setup frame */
@@ -612,7 +611,7 @@
/* Tell the adapter where the TX ring is located */
- ETH_CMD(dev, TxEnable); /* Enable transmitter. */
+ ETH_CMD(dev, TxEnable); /* Enable transmitter. */
issue_and_wait(dev, DownStall); /* Stall and set the DownListPtr. */
ETH_OUTL(dev, (u32)&tx_ring[tx_cur], DownListPtr);
issue_and_wait(dev, DownUnstall);
@@ -627,13 +626,13 @@
}
if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */
{
- ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */
- issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */
+ ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */
+ issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */
ETH_OUTL(dev, 0, DownListPtr);
issue_and_wait(dev, DownUnstall);
}
status = 1;
-
+
Done:
return status;
}
@@ -673,8 +672,8 @@
}
if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */
{
- ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */
- issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */
+ ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */
+ issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */
ETH_OUTL(dev, 0, DownListPtr);
issue_and_wait(dev, DownUnstall);
}
@@ -710,15 +709,15 @@
status = le32_to_cpu(rx_ring[rx_next].status); /* packet status */
while (status & (1<<15))
- {
+ {
/* A packet has been received */
- if (status & (1<<15))
+ if (status & (1<<15))
{
/* A valid frame received */
-
+
length = le32_to_cpu(rx_ring[rx_next].status) & 0x1fff; /* length is in bits 0 - 12 */
-
+
/* Pass the packet up to the protocol layers */
NetReceive((uchar *)le32_to_cpu(rx_ring[rx_next].addr), length);
@@ -748,7 +747,7 @@
void eth_3com_halt(struct eth_device* dev)
{
- if (!(dev->iobase))
+ if (!(dev->iobase))
{
goto Done;
}
@@ -758,14 +757,14 @@
issue_and_wait(dev, RxDisable);
issue_and_wait(dev, TxDisable);
-// free(tx_ring); /* release memory allocated to the DPD and UPD rings */
-// free(rx_ring);
+/* free(tx_ring); /###* release memory allocated to the DPD and UPD rings */
+/* free(rx_ring); */
Done:
return;
}
-static void init_rx_ring(struct eth_device* dev)
+static void init_rx_ring(struct eth_device* dev)
{
int i;
@@ -782,7 +781,7 @@
rx_next = 0;
}
-static void purge_tx_ring(struct eth_device* dev)
+static void purge_tx_ring(struct eth_device* dev)
{
int i;
@@ -799,39 +798,39 @@
}
}
-static void read_hw_addr(struct eth_device* dev, bd_t *bis)
+static void read_hw_addr(struct eth_device* dev, bd_t *bis)
{
u8 hw_addr[ETH_ALEN];
unsigned int eeprom[0x40];
unsigned int checksum = 0;
int i, j, timer;
- /* Read the station address from the EEPROM. */
+ /* Read the station address from the EEPROM. */
- EL3WINDOW(dev, 0);
+ EL3WINDOW(dev, 0);
for (i = 0; i < 0x40; i++)
{
- ETH_OUTW(dev, EEPROM_Read + i, Wn0EepromCmd);
- /* Pause for at least 162 us. for the read to take place. */
- for (timer = 10; timer >= 0; timer--)
+ ETH_OUTW(dev, EEPROM_Read + i, Wn0EepromCmd);
+ /* Pause for at least 162 us. for the read to take place. */
+ for (timer = 10; timer >= 0; timer--)
{
- udelay(162);
- if ((ETH_INW(dev, Wn0EepromCmd) & 0x8000) == 0)
- break;
- }
- eeprom[i] = ETH_INW(dev, Wn0EepromData);
- }
+ udelay(162);
+ if ((ETH_INW(dev, Wn0EepromCmd) & 0x8000) == 0)
+ break;
+ }
+ eeprom[i] = ETH_INW(dev, Wn0EepromData);
+ }
/* Checksum calculation. I'm not sure about this part and there seems to be a bug on the 3com side of things */
- for (i = 0; i < 0x21; i++)
- checksum ^= eeprom[i];
- checksum = (checksum ^ (checksum >> 8)) & 0xff;
+ for (i = 0; i < 0x21; i++)
+ checksum ^= eeprom[i];
+ checksum = (checksum ^ (checksum >> 8)) & 0xff;
- if (checksum != 0xbb)
- printf(" *** INVALID EEPROM CHECKSUM %4.4x *** \n", checksum);
+ if (checksum != 0xbb)
+ printf(" *** INVALID EEPROM CHECKSUM %4.4x *** \n", checksum);
- for (i = 0, j = 0; i < 3; i++)
+ for (i = 0, j = 0; i < 3; i++)
{
hw_addr[j++] = (u8)((eeprom[i+10] >> 8) & 0xff);
hw_addr[j++] = (u8)(eeprom[i+10] & 0xff);
@@ -839,9 +838,9 @@
/* MAC Address is in window 2, write value from EEPROM to window 2 */
- EL3WINDOW(dev, 2);
- for (i = 0; i < 6; i++)
- ETH_OUTB(dev, hw_addr[i], i);
+ EL3WINDOW(dev, 2);
+ for (i = 0; i < 6; i++)
+ ETH_OUTB(dev, hw_addr[i], i);
for (j = 0; j < ETH_ALEN; j+=2)
{
@@ -849,9 +848,9 @@
hw_addr[j+1] = (u8)((ETH_INW(dev, j) >> 8) & 0xff);
}
- for (i=0;i<ETH_ALEN;i++)
+ for (i=0;i<ETH_ALEN;i++)
{
- if (hw_addr[i] != bis->bi_enetaddr[i])
+ if (hw_addr[i] != bis->bi_enetaddr[i])
{
/* printf("Warning: HW address don't match:\n"); */
/* printf("Address in 3Com Window 2 is " */
@@ -870,9 +869,9 @@
bis->bi_enetaddr[4] == 0 && bis->bi_enetaddr[5] == 0)
{
- sprintf(buffer, "%02X:%02X:%02X:%02X:%02X:%02X",
- hw_addr[0], hw_addr[1], hw_addr[2],
- hw_addr[3], hw_addr[4], hw_addr[5]);
+ sprintf(buffer, "%02X:%02X:%02X:%02X:%02X:%02X",
+ hw_addr[0], hw_addr[1], hw_addr[2],
+ hw_addr[3], hw_addr[4], hw_addr[5]);
setenv("ethaddr", buffer);
}
}
@@ -883,4 +882,3 @@
Done:
return;
}
-
diff --git a/board/MAI/AmigaOneG3SE/flash_new.c b/board/MAI/AmigaOneG3SE/flash_new.c
index 3fb9f12..d46bf46 100644
--- a/board/MAI/AmigaOneG3SE/flash_new.c
+++ b/board/MAI/AmigaOneG3SE/flash_new.c
@@ -27,11 +27,10 @@
#include <common.h>
#include <flash.h>
#include <asm/io.h>
-#include "memio.h"
+#include "memio.h"
/*---------------------------------------------------------------------*/
#undef DEBUG_FLASH
-//#define DEBUG_FLASH
#ifdef DEBUG_FLASH
#define DEBUGF(fmt,args...) printf(fmt ,##args)
@@ -68,7 +67,7 @@
unsigned char x;
flash_xd_nest --;
-
+
if (flash_xd_nest == 0)
{
DEBUGF("Flash on memory bus\n");
@@ -327,7 +326,7 @@
/* set sector offsets for uniform sector type */
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + i * info->size /
- info->sector_count;
+ info->sector_count;
}
break;
default:
@@ -478,7 +477,7 @@
}
if ((rc = write_word(info, wp, data)) != 0) {
- flash_to_mem();
+ flash_to_mem();
return (rc);
}
wp += 4;
@@ -493,7 +492,7 @@
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
- flash_to_mem();
+ flash_to_mem();
return (rc);
}
wp += 4;
@@ -582,7 +581,7 @@
*/
static void flash_reset (ulong addr)
{
- flash_to_xd();
+ flash_to_xd();
out8(addr, 0xF0); /* reset bank */
iobarrier_rw();
flash_to_mem();
@@ -633,10 +632,10 @@
info->size / 0x100000, info->sector_count);
} else if (info->size % 0x400 == 0) {
printf (" Size: %ld KB in %d Sectors\n",
- info->size / 0x400, info->sector_count);
+ info->size / 0x400, info->sector_count);
} else {
printf (" Size: %ld B in %d Sectors\n",
- info->size, info->sector_count);
+ info->size, info->sector_count);
}
printf (" Sector Start Addresses:");
diff --git a/board/MAI/AmigaOneG3SE/i8259.c b/board/MAI/AmigaOneG3SE/i8259.c
index 6cdfc60..34f489f 100644
--- a/board/MAI/AmigaOneG3SE/i8259.c
+++ b/board/MAI/AmigaOneG3SE/i8259.c
@@ -75,16 +75,16 @@
char dummy;
PRINTF("Initializing Interrupt controller\n");
/* init master interrupt controller */
- out8(0x20, 0x11); //0x19); // was: 0x11); /* Start init sequence */
+ out8(0x20, 0x11); /* 0x19); /###* Start init sequence */
out8(0x21, 0x00); /* Vector base */
out8(0x21, 0x04); /* edge tiggered, Cascade (slave) on IRQ2 */
- out8(0x21, 0x11); // was: 0x01); /* Select 8086 mode */
+ out8(0x21, 0x11); /* was: 0x01); /###* Select 8086 mode */
/* init slave interrupt controller */
- out8(0xA0, 0x11); //0x19); // was: 0x11); /* Start init sequence */
+ out8(0xA0, 0x11); /* 0x19); /###* Start init sequence */
out8(0xA1, 0x08); /* Vector base */
out8(0xA1, 0x02); /* edge triggered, Cascade (slave) on IRQ2 */
- out8(0xA1, 0x11); // was: 0x01); /* Select 8086 mode */
+ out8(0xA1, 0x11); /* was: 0x01); /###* Select 8086 mode */
/* always read ISR */
out8(0x20, 0x0B);
diff --git a/board/MAI/AmigaOneG3SE/interrupts.c b/board/MAI/AmigaOneG3SE/interrupts.c
index bb93ea0..5b314a8 100644
--- a/board/MAI/AmigaOneG3SE/interrupts.c
+++ b/board/MAI/AmigaOneG3SE/interrupts.c
@@ -73,7 +73,7 @@
static __inline__ void
set_msr(unsigned long msr)
{
- asm volatile("mtmsr %0" : : "r" (msr));
+ asm volatile("mtmsr %0" : : "r" (msr));
}
static __inline__ unsigned long
@@ -89,7 +89,7 @@
static __inline__ void
set_dec(unsigned long val)
{
- asm volatile("mtdec %0" : : "r" (val));
+ asm volatile("mtdec %0" : : "r" (val));
}
@@ -167,8 +167,8 @@
int irq, unmask = 1;
- irq = i8259_irq(); //i8259_get_irq(regs);
-// printf("irq = %d, handler at %p ack=%d\n", irq, irq_handlers[irq].handler, *(volatile unsigned char *)0xFEF00000);
+ irq = i8259_irq(); /*i8259_get_irq(regs); */
+/* printf("irq = %d, handler at %p ack=%d\n", irq, irq_handlers[irq].handler, *(volatile unsigned char *)0xFEF00000); */
i8259_mask_and_ack(irq);
if (irq_handlers[irq].handler != NULL)
@@ -264,5 +264,3 @@
{
puts("IRQ related functions are unimplemented currently.\n");
}
-
-
diff --git a/board/MAI/AmigaOneG3SE/macros.h b/board/MAI/AmigaOneG3SE/macros.h
index 0fbe39b..6020d7e 100644
--- a/board/MAI/AmigaOneG3SE/macros.h
+++ b/board/MAI/AmigaOneG3SE/macros.h
@@ -5,20 +5,20 @@
/*
** Load a long integer into a register
*/
- .macro liw reg, value
- lis \reg, \value@h
- ori \reg, \reg, \value@l
- .endm
+ .macro liw reg, value
+ lis \reg, \value@h
+ ori \reg, \reg, \value@l
+ .endm
- /*
+ /*
** Generate config_addr request
** This macro expects the values in registers:
** r3 - bus
** r4 - devfn
** r5 - offset
*/
- .macro config_addr
+ .macro config_addr
rlwinm r9, r5, 24, 0, 6
rlwinm r8, r4, 16, 0, 31
rlwinm r7, r3, 8, 0, 31
@@ -31,7 +31,7 @@
sync
.endm
-
+
/*
** Generate config_data address
*/
@@ -45,40 +45,40 @@
/*
** Write a byte value to an output port
*/
- .macro outb port, value
- lis r2, 0xfe00
- li r0, \value
- stb r0, \port(r2)
- .endm
+ .macro outb port, value
+ lis r2, 0xfe00
+ li r0, \value
+ stb r0, \port(r2)
+ .endm
/*
** Write a register byte value to an output port
*/
- .macro outbr port, value
- lis r2, 0xfe00
- stb \value, \port(r2)
- .endm
+ .macro outbr port, value
+ lis r2, 0xfe00
+ stb \value, \port(r2)
+ .endm
- /*
+ /*
** Read a byte value from a port into a specified register
*/
- .macro inb reg, port
- lis r2, 0xfe00
- lbz \reg, \port(r2)
- .endm
+ .macro inb reg, port
+ lis r2, 0xfe00
+ lbz \reg, \port(r2)
+ .endm
/*
** Write a byte to the SuperIO config area
*/
- .macro siowb offset, value
- li r3, 0
- li r4, (7<<3)
- li r5, \offset
- li r6, \value
- bl pci_write_cfg_byte
- .endm
+ .macro siowb offset, value
+ li r3, 0
+ li r4, (7<<3)
+ li r5, \offset
+ li r6, \value
+ bl pci_write_cfg_byte
+ .endm
#endif
diff --git a/board/MAI/AmigaOneG3SE/memio.S b/board/MAI/AmigaOneG3SE/memio.S
index c4a09aa..980d343 100644
--- a/board/MAI/AmigaOneG3SE/memio.S
+++ b/board/MAI/AmigaOneG3SE/memio.S
@@ -1,9 +1,8 @@
#include "macros.h"
-
.globl pci_read_cfg_byte
-
+
pci_read_cfg_byte:
config_addr
config_data 3
@@ -12,11 +11,10 @@
lbz r3, 0(r9)
blr
-
.globl pci_write_cfg_byte
-
-pci_write_cfg_byte:
+
+pci_write_cfg_byte:
config_addr
config_data 3
stb r6, 0(r9)
@@ -25,9 +23,8 @@
blr
-
.globl pci_read_cfg_word
-
+
pci_read_cfg_word:
config_addr
config_data 2
@@ -37,9 +34,8 @@
blr
-
.globl pci_write_cfg_word
-
+
pci_write_cfg_word:
config_addr
config_data 2
@@ -48,10 +44,9 @@
sync
blr
-
.globl pci_read_cfg_long
-
+
pci_read_cfg_long:
config_addr
config_data 0
@@ -61,9 +56,8 @@
blr
-
.globl pci_write_cfg_long
-
+
pci_write_cfg_long:
config_addr
config_data 0
@@ -71,4 +65,3 @@
eieio
sync
blr
-
diff --git a/board/MAI/AmigaOneG3SE/memio.h b/board/MAI/AmigaOneG3SE/memio.h
index df0839f..f5ce303 100644
--- a/board/MAI/AmigaOneG3SE/memio.h
+++ b/board/MAI/AmigaOneG3SE/memio.h
@@ -2,7 +2,7 @@
* Memory mapped IO
*
* (C) Copyright 2002
- * Hyperion Entertainment, ThomasF@hyperion-entertainment.com
+ * Hyperion Entertainment, ThomasF@hyperion-entertainment.com
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -15,9 +15,9 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
- */
+ */
#ifndef _MEMIO_H
#define _MEMIO_H
@@ -97,8 +97,8 @@
#define CONFIG_ADDR(bus, devfn, offset) \
write_long_big((uint32 *)0xFEC00CF8, \
- ((offset & 0xFC)<<24) | (devfn << 16) \
- | (bus<<8) | 0x80);
+ ((offset & 0xFC)<<24) | (devfn << 16) \
+ | (bus<<8) | 0x80);
#define CONFIG_DATA(offset,mask) ((void *)(0xFEE00CFC+(offset & mask)))
diff --git a/board/MAI/AmigaOneG3SE/nvram.c b/board/MAI/AmigaOneG3SE/nvram.c
index 5dde15b..d37eec1 100644
--- a/board/MAI/AmigaOneG3SE/nvram.c
+++ b/board/MAI/AmigaOneG3SE/nvram.c
@@ -1,6 +1,6 @@
/*
* (C) Copyright 2002
- * Thomas Frieden, Hyperion Entertainment
+ * Thomas Frieden, Hyperion Entertainment
* ThomasF@hyperion-entertainment.com
*
* See file CREDITS for list of people who contributed to this
@@ -34,4 +34,3 @@
{
pci_write_cfg_byte(0, 0, 0x56, 0x0);
}
-
diff --git a/board/MAI/AmigaOneG3SE/ps2kbd.c b/board/MAI/AmigaOneG3SE/ps2kbd.c
index a6d67be..bfe5eb3 100644
--- a/board/MAI/AmigaOneG3SE/ps2kbd.c
+++ b/board/MAI/AmigaOneG3SE/ps2kbd.c
@@ -1,7 +1,7 @@
/*
* (C) Copyright 2002
* John W. Linville, linville@tuxdriver.com
- *
+ *
* Modified from code for support of MIP405 and PIP405 boards. Previous
* copyright follows.
*
@@ -48,7 +48,6 @@
#undef KBG_DEBUG
-//#define KBG_DEBUG
#ifdef KBG_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
@@ -143,8 +142,6 @@
#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */
-
-
static volatile char kbd_buffer[KBD_BUFFER_LEN];
static volatile int in_pointer = 0;
static volatile int out_pointer = 0;
@@ -172,7 +169,7 @@
'2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */
'\r',0xff,0xff
};
-
+
static unsigned char kbd_shift_xlate[] = {
0xff,0x1b, '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', '+','\b','\t', /* 0x00 - 0x0f */
'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', 'P', '{', '}','\r',0xff, 'A', 'S', /* 0x10 - 0x1f */
@@ -194,7 +191,7 @@
};
/******************************************************************
- * Init
+ * Init
******************************************************************/
int isa_kbd_init(void)
@@ -252,7 +249,7 @@
error=console_assign(stdin,DEVNAME);
if(error==0)
return 1;
- else
+ else
return error;
}
return 1;
@@ -261,7 +258,7 @@
}
/******************************************************************
- * Queue handling
+ * Queue handling
******************************************************************/
/* puts character in the queue and sets up the in and out pointer */
void kbd_put_queue(char data)
@@ -287,7 +284,7 @@
if(in_pointer==out_pointer)
return(0); /* no data */
else
- return(1);
+ return(1);
}
/* gets the character from the queue */
int kbd_getc(void)
@@ -295,13 +292,13 @@
char c;
while(in_pointer==out_pointer);
- if((out_pointer+1)==KBD_BUFFER_LEN)
+ if((out_pointer+1)==KBD_BUFFER_LEN)
out_pointer=0;
else
out_pointer++;
c=kbd_buffer[out_pointer];
return (int)c;
-
+
}
@@ -324,7 +321,7 @@
kbd_send_data(KBD_CMD_SET_LEDS);
kbd_send_data(leds);
}
-
+
void handle_keyboard_event(unsigned char scancode)
{
@@ -381,11 +378,11 @@
console_changed = 1;
}
return;
- case 0x2A:
+ case 0x2A:
case 0x36: /* shift pressed */
shift=1;
return; /* do nothing else */
- case 0xAA:
+ case 0xAA:
case 0xB6: /* shift released */
shift=0;
return; /* do nothing else */
@@ -408,15 +405,15 @@
case 0x3A: /* capslock pressed */
caps_lock=~caps_lock;
kbd_set_leds();
- return;
+ return;
case 0x45: /* numlock pressed */
num_lock=~num_lock;
kbd_set_leds();
- return;
+ return;
case 0xC6: /* scroll lock released */
case 0xC5: /* num lock released */
case 0xBA: /* caps lock released */
- return; /* just swallow */
+ return; /* just swallow */
}
if((scancode&0x80)==0x80) /* key released */
return;
@@ -456,7 +453,7 @@
PRINTF("unkown scancode %X\n",scancode);
return; /* swallow unknown codes */
}
-
+
kbd_put_queue(keycode);
PRINTF("%x\n",keycode);
}
@@ -494,30 +491,29 @@
}
-
/******************************************************************************
* Lowlevel Part of keyboard section
- */
+ */
unsigned char kbd_read_status(void)
{
return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT));
-}
-
+}
+
unsigned char kbd_read_input(void)
{
return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT));
-}
+}
void kbd_write_command(unsigned char cmd)
{
out8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd);
-}
-
+}
+
void kbd_write_output(unsigned char data)
{
out8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data);
-}
-
+}
+
int kbd_read_data(void)
{
int val;
@@ -537,7 +533,7 @@
{
unsigned long timeout;
int val;
-
+
timeout = KBD_TIMEOUT;
val=kbd_read_data();
while(val < 0)
@@ -602,7 +598,7 @@
* If the test is successful a x55 is placed in the input buffer.
*/
kbd_write_command_w(KBD_CCMD_SELF_TEST);
- if (kbd_wait_for_input() != 0x55)
+ if (kbd_wait_for_input() != 0x55)
return "Kbd: failed self test";
/*
* Perform a keyboard interface test. This causes the controller
@@ -610,7 +606,7 @@
* test are placed in the input buffer.
*/
kbd_write_command_w(KBD_CCMD_KBD_TEST);
- if (kbd_wait_for_input() != 0x00)
+ if (kbd_wait_for_input() != 0x00)
return "Kbd: interface failed self test";
/*
* Enable the keyboard by allowing the keyboard clock to run.
@@ -628,7 +624,7 @@
do {
kbd_write_output_w(KBD_CMD_RESET);
status = kbd_wait_for_input();
- if (status == KBD_REPLY_ACK)
+ if (status == KBD_REPLY_ACK)
break;
if (status != KBD_REPLY_RESEND)
{
@@ -692,8 +688,3 @@
{
handle_kbd_event();
}
-
-
-
-/* eof */
-
diff --git a/board/MAI/AmigaOneG3SE/ps2kbd.h b/board/MAI/AmigaOneG3SE/ps2kbd.h
index 95fc14d..fc5c422 100644
--- a/board/MAI/AmigaOneG3SE/ps2kbd.h
+++ b/board/MAI/AmigaOneG3SE/ps2kbd.h
@@ -1,7 +1,7 @@
/*
* (C) Copyright 2002
* John W. Linville, linville@tuxdriver.com
- *
+ *
* Modified from code for support of MIP405 and PIP405 boards. Previous
* copyright follows.
*
@@ -30,7 +30,7 @@
#ifndef _KBD_H_
#define _KBD_H_
-
+
extern int kbd_testc(void);
extern int kbd_getc(void);
extern void kbd_interrupt(void);
diff --git a/board/MAI/AmigaOneG3SE/short_types.h b/board/MAI/AmigaOneG3SE/short_types.h
index 22df3c9..1840d28 100644
--- a/board/MAI/AmigaOneG3SE/short_types.h
+++ b/board/MAI/AmigaOneG3SE/short_types.h
@@ -2,7 +2,7 @@
* short type names
*
* (C) Copyright 2002
- * Hyperion Entertainment, ThomasF@hyperion-entertainment.com
+ * Hyperion Entertainment, ThomasF@hyperion-entertainment.com
*
* See file CREDITS for list of people who contributed to this
* project.
diff --git a/board/MAI/AmigaOneG3SE/smbus.c b/board/MAI/AmigaOneG3SE/smbus.c
index 616005e..de13977 100644
--- a/board/MAI/AmigaOneG3SE/smbus.c
+++ b/board/MAI/AmigaOneG3SE/smbus.c
@@ -26,18 +26,18 @@
{
int i;
int level;
-
+
out_byte(0xA539, 0x00);
level = 0;
for (i=0; i<8; i++)
{
- if ((writeme & 0x80) == (level<<7))
- {
+ if ((writeme & 0x80) == (level<<7))
+ {
/* Bit did not change, rewrite strobe */
out_byte(0xA539, level | 0x02);
- out_byte(0xA539, level);
+ out_byte(0xA539, level);
}
else
{
@@ -68,7 +68,7 @@
}
return retme;
-}
+}
int sm_get_ack(void)
{
@@ -106,36 +106,36 @@
int sm_read_byte_from_device(uint8 addr, uint8 reg, uint8 *storage)
{
- // S Addr Wr
+ /* S Addr Wr */
sm_write_mode();
sm_send_start();
sm_write_byte((addr<<1));
-
- // [A]
+
+ /* [A] */
sm_read_mode();
if (sm_get_ack() == FALSE) return FALSE;
- // Comm
+ /* Comm */
sm_write_mode();
sm_write_byte(reg);
-
- // [A]
+
+ /* [A] */
sm_read_mode();
if (sm_get_ack() == FALSE) return FALSE;
- // S Addr Rd
+ /* S Addr Rd */
sm_write_mode();
sm_send_start();
sm_write_byte((addr<<1)|1);
-
- // [A]
+
+ /* [A] */
sm_read_mode();
if (sm_get_ack() == FALSE) return FALSE;
- // [Data]
+ /* [Data] */
*storage = sm_read_byte();
-
- // NA
+
+ /* NA */
sm_write_mode();
sm_write_nack();
sm_send_stop();
@@ -144,10 +144,10 @@
}
void sm_init(void)
-{
+{
/* Switch to PMC mode */
pci_write_cfg_byte(0, 0, REG_GROUP, (uint8)(REG_GROUP_SPECIAL|REG_GROUP_POWER));
-
+
/* Set GPIO Base */
pci_write_cfg_long(0, 0, 0x40, 0xa500);
@@ -155,12 +155,12 @@
pci_write_cfg_byte(0, 0, 0x44, 0x11);
/* Set both GPIO 0 and 1 as output */
- out_byte(0xA53A, 0x03);
+ out_byte(0xA53A, 0x03);
}
void sm_term(void)
-{
+{
/* Switch to normal mode */
pci_write_cfg_byte(0, 0, REG_GROUP, 0);
}
@@ -173,7 +173,7 @@
#if 0
/* Switch to PMC mode */
pci_write_cfg_byte(0, 0, REG_GROUP, (uint8)(REG_GROUP_SPECIAL|REG_GROUP_POWER));
-
+
/* Set GPIO Base */
pci_write_cfg_long(0, 0, 0x40, 0xa500);
@@ -181,7 +181,7 @@
pci_write_cfg_byte(0, 0, 0x44, 0x11);
/* Set both GPIO 0 and 1 as output */
- out_byte(0xA53A, 0x03);
+ out_byte(0xA53A, 0x03);
#endif
sm_init();
diff --git a/board/MAI/AmigaOneG3SE/start.txt b/board/MAI/AmigaOneG3SE/start.txt
index 5c7b541..e421462 100644
--- a/board/MAI/AmigaOneG3SE/start.txt
+++ b/board/MAI/AmigaOneG3SE/start.txt
@@ -1,201 +1,198 @@
-
- /*------------------------------------------------------*/
- /* TERON Articia / SDRAM Init */
- /*------------------------------------------------------*/
-
-* XD_CTL = 0x81000000 (0x74)
-
-* HBUS_ACC_CTL_0 &= 0xFFFFFDFF (0x5c)
- /* host bus access ctl reg 2(5e) */
- /* set - CPU read from memory data one clock after data is latched */
-
-* GLOBL_INFO_0 |= 0x00004000 (0x50)
- /* global info register 2 (52), AGP/PCI bus 1 arbiter is addressed in Articia S */
-
- PCI_1_SB_CONFIG_0 |= 0x00000400 (0x80d0)
- /* PCI1 side band config reg 2 (d2), enable read acces while write buffer not empty */
-
- MEM_RAS_CTL_0 |= 0x3f000000 (0xcc)
- &= 0x3fffffff
- /* RAS park control reg 0(cc), park access enable is set */
-
- HOST_RDBUF_CTL |= 0x10000000 (0x70)
- &= 0x10ffffff
- /* host read buffer control reg, enable prefetch for CPU read from DRAM control */
-
- HBUS_ACC_CTL_0 |= 0x0100001f (0x5c)
- &= 0xf1ffffff
- /* host bus access control register, enable CPU address bus pipe control */
- /* two outstanding requests, *** changed to 2 from 3 */
- /* enable line merge write control for CPU write to system memory, PCI 1 */
- /* and PCI 0 bus memory; enable page merge write control for write to */
- /* PCI bus 0 & bus 1 memory */
-
- SRAM_CTL |= 0x00004000 (0xc8)
- &= 0xffbff7ff
- /* DRAM detail timing control register 1 (ca), bit 3 set to 0 */
- /* DRAM start access latency control - wait for one clock */
- /* ff9f changed to ffbf */
-
- DIM0_TIM_CTL_0 = 0x737d737d (0xc9)
- /* DRAM timing control for dimm0 & dimm1; set wait one clock */
- /* cycle for next data access */
-
- DIM2_TIM_CTL_0 = 0x737d737d (0xca)
- /* DRAM timing control for dimm2 & dimm3; set wait one clock */
- /* cycle for next data access */
-
- DIM0_BNK0_CTL_0 = BNK0_RAM_SIZ_128MB (0x90)
- /* set dimm0 bank0 for 128 MB */
-
- DIM0_BNK1_CTL_0 = BNK1_RAM_SIZ_128MB (0x94)
- /* set dimm0 for bank1 */
-
- DIM0_TIM_CTL_0 = 0xf3bf0000 (0xc9)
- /* dimm0 timing control register; RAS - CAS latency - 4 clock */
- /* CAS access latency - 3 wait; pre-charge latency - 3 wait */
- /* pre-charge command period control - 5 clock; wait one clock */
- /* cycle for next data access; read to write access latency control */
- /* - 2 clock cycles */
-
- DRAM_GBL_CTL_0 |= 0x00000100 (0xc0)
- &= 0xffff01ff
- /* memory global control register - support buffer sdram on bank 0 */
-
- DRAM_ECC_CTL_0 |= 0x00260000 (0xc4)
- &= 0xff26ffff
- /* enable ECC; enable read, modify, write control */
-
- DRAM_REF_CTL_0 = DRAM_REF_DATA (0xb8)
- /* set DRAM refresh parameters *** changed to 00940100 */
-
- nop
- nop
- nop
- nop
- nop
-
- DRAM_ECC_CTL_0 |= 0x20243280 (0xc4)
- /* turn off ecc */
- /* for SDRAM bank 0 */
-
- DRAM_ECC_CTL_0 |= 0x20243290 (0xc4) ?
- /* for SDRAM bank 1 */
-
-
-/* Additional Stuff...*/
-
- GLOBL_CTRL |= 0x20000b00 (0x54)
-
- PCI_0_SB_CONFIG |= 0x04100007 (0xd0)
- /* PCI 0 Side band config reg*/
-
- 0x8000083c |= 0x00080000
- /* Disable VGA decode on PCI Bus 1 */
-
-
-/*End Additional Stuff..*/
-
- /*--------------------------------------------------------------*/
- /* TERON serial port initialization code */
- /*--------------------------------------------------------------*/
-
- 0x84380080 |= 0x00030000
- /* enable super IO configuration VIA chip Register 85 */
- /* Enable super I/O config mode */
-
- 0xfe0003f0 = 0xe2
- bl delay1
-
- 0xfe0003f1 = 0x0f
- bl delay1
- /* enable com1 & com2, parallel port disabled */
-
- 0xfe0003f0 = 0xe7
- bl delay1
- /* let's make com1 base as 0x3f8 */
-
- 0xfe0003f1 = 0xfe
- bl delay1
-
- 0xfe0003f0 = 0xe8
- bl delay1
- /* let's make com2 base as 0x2f8 */
-
- 0xfe0003f1 = 0xbe
-
- 0x84380080 &= 0xfffdffff
- /* closing super IO configuration VIA chip Register 85 */
-
-
-/* -------------------------------*/
-
- 0xfe0003fb = 0x83
- bl delay1
- /*latch enable word length -8 bit */ /* set mslab bit */
- 0xfe0003f8 = 0x0c
- bl delay1
- /* set baud rate lsb for 9600 baud */
- 0xfe0003f9 = 0x0
- bl delay1
- /* set baud rate msb for 9600 baud */
- 0xfe0003fb = 0x03
- bl delay1
- /* reset mslab */
-
- /*--------------------------------------------------------------*/
- /* END TERON Serial Port Initialization Code */
- /*--------------------------------------------------------------*/
-
-
-
- /*--------------------------------------------------------------*/
- /* END TERON Articia / SDRAM Initialization code */
- /*--------------------------------------------------------------*/
-
-Proposed from Documentation:
-
-write dmem 0xfec00cf8 0x50000080
-write dmem 0xfee00cfc 0xc0305411
-
- Writes to index 0x50-0x53.
- 0x50: Global Information Register 0
- 0xC0 = Little Endian CPU, Sequential order Burst
- 0x51: Global Information Register 1
- Read only, 0x30 = Provides PowerPC and X86 support
- 0x52: Global Information Register 2
- 0x05 = 64/128 bit CPU bus support
- 0x53: Global Information Register 3
- 0x80 = PCI Bus 0 grant active time is 1 clock after REQ# deasserted
-
-write dmem 0xfec00cf8 0x5c000080
-write dmem 0xfee00cfc 0xb300011F
-
-write dmem 0xfec00cf8 0xc8000080
-write dmem 0xfee00cfc 0x0020f100
-
-write dmem 0xfec00cf8 0x90000080
-write dmem 0xfee00cfc 0x007fe700
-
-write dmem 0xfec00cf8 0x9400080
-write dmem 0xfee00cfc 0x007fe700
-
-write dmem 0xfec00cf8 0xb0000080
-write dmem 0xfee00cfc 0x737d737d
-
-write dmem 0xfec00cf8 0xb4000080
-write dmem 0xfee00cfc 0x737d737d
-
-write dmem 0xfec00cf8 0xc0000080
-write dmem 0xfee00cfc 0x40005500
-
-write dmem 0xfec00cf8 0xb8000080
-write dmem 0xfee00cfc 0x00940100
-
-write dmem 0xfec00cf8 0xc4000080
-write dmem 0xfee00cfc 0x00003280
-
-write dmem 0xfec00cf8 0xc4000080
-write dmem 0xfee00cfc 0x00003290
-
-
+
+ /*------------------------------------------------------*/
+ /* TERON Articia / SDRAM Init */
+ /*------------------------------------------------------*/
+
+* XD_CTL = 0x81000000 (0x74)
+
+* HBUS_ACC_CTL_0 &= 0xFFFFFDFF (0x5c)
+ /* host bus access ctl reg 2(5e) */
+ /* set - CPU read from memory data one clock after data is latched */
+
+* GLOBL_INFO_0 |= 0x00004000 (0x50)
+ /* global info register 2 (52), AGP/PCI bus 1 arbiter is addressed in Articia S */
+
+ PCI_1_SB_CONFIG_0 |= 0x00000400 (0x80d0)
+ /* PCI1 side band config reg 2 (d2), enable read acces while write buffer not empty */
+
+ MEM_RAS_CTL_0 |= 0x3f000000 (0xcc)
+ &= 0x3fffffff
+ /* RAS park control reg 0(cc), park access enable is set */
+
+ HOST_RDBUF_CTL |= 0x10000000 (0x70)
+ &= 0x10ffffff
+ /* host read buffer control reg, enable prefetch for CPU read from DRAM control */
+
+ HBUS_ACC_CTL_0 |= 0x0100001f (0x5c)
+ &= 0xf1ffffff
+ /* host bus access control register, enable CPU address bus pipe control */
+ /* two outstanding requests, *** changed to 2 from 3 */
+ /* enable line merge write control for CPU write to system memory, PCI 1 */
+ /* and PCI 0 bus memory; enable page merge write control for write to */
+ /* PCI bus 0 & bus 1 memory */
+
+ SRAM_CTL |= 0x00004000 (0xc8)
+ &= 0xffbff7ff
+ /* DRAM detail timing control register 1 (ca), bit 3 set to 0 */
+ /* DRAM start access latency control - wait for one clock */
+ /* ff9f changed to ffbf */
+
+ DIM0_TIM_CTL_0 = 0x737d737d (0xc9)
+ /* DRAM timing control for dimm0 & dimm1; set wait one clock */
+ /* cycle for next data access */
+
+ DIM2_TIM_CTL_0 = 0x737d737d (0xca)
+ /* DRAM timing control for dimm2 & dimm3; set wait one clock */
+ /* cycle for next data access */
+
+ DIM0_BNK0_CTL_0 = BNK0_RAM_SIZ_128MB (0x90)
+ /* set dimm0 bank0 for 128 MB */
+
+ DIM0_BNK1_CTL_0 = BNK1_RAM_SIZ_128MB (0x94)
+ /* set dimm0 for bank1 */
+
+ DIM0_TIM_CTL_0 = 0xf3bf0000 (0xc9)
+ /* dimm0 timing control register; RAS - CAS latency - 4 clock */
+ /* CAS access latency - 3 wait; pre-charge latency - 3 wait */
+ /* pre-charge command period control - 5 clock; wait one clock */
+ /* cycle for next data access; read to write access latency control */
+ /* - 2 clock cycles */
+
+ DRAM_GBL_CTL_0 |= 0x00000100 (0xc0)
+ &= 0xffff01ff
+ /* memory global control register - support buffer sdram on bank 0 */
+
+ DRAM_ECC_CTL_0 |= 0x00260000 (0xc4)
+ &= 0xff26ffff
+ /* enable ECC; enable read, modify, write control */
+
+ DRAM_REF_CTL_0 = DRAM_REF_DATA (0xb8)
+ /* set DRAM refresh parameters *** changed to 00940100 */
+
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ DRAM_ECC_CTL_0 |= 0x20243280 (0xc4)
+ /* turn off ecc */
+ /* for SDRAM bank 0 */
+
+ DRAM_ECC_CTL_0 |= 0x20243290 (0xc4) ?
+ /* for SDRAM bank 1 */
+
+
+/* Additional Stuff...*/
+
+ GLOBL_CTRL |= 0x20000b00 (0x54)
+
+ PCI_0_SB_CONFIG |= 0x04100007 (0xd0)
+ /* PCI 0 Side band config reg*/
+
+ 0x8000083c |= 0x00080000
+ /* Disable VGA decode on PCI Bus 1 */
+
+
+/*End Additional Stuff..*/
+
+ /*--------------------------------------------------------------*/
+ /* TERON serial port initialization code */
+ /*--------------------------------------------------------------*/
+
+ 0x84380080 |= 0x00030000
+ /* enable super IO configuration VIA chip Register 85 */
+ /* Enable super I/O config mode */
+
+ 0xfe0003f0 = 0xe2
+ bl delay1
+
+ 0xfe0003f1 = 0x0f
+ bl delay1
+ /* enable com1 & com2, parallel port disabled */
+
+ 0xfe0003f0 = 0xe7
+ bl delay1
+ /* let's make com1 base as 0x3f8 */
+
+ 0xfe0003f1 = 0xfe
+ bl delay1
+
+ 0xfe0003f0 = 0xe8
+ bl delay1
+ /* let's make com2 base as 0x2f8 */
+
+ 0xfe0003f1 = 0xbe
+
+ 0x84380080 &= 0xfffdffff
+ /* closing super IO configuration VIA chip Register 85 */
+
+
+/* -------------------------------*/
+
+ 0xfe0003fb = 0x83
+ bl delay1
+ /*latch enable word length -8 bit */ /* set mslab bit */
+ 0xfe0003f8 = 0x0c
+ bl delay1
+ /* set baud rate lsb for 9600 baud */
+ 0xfe0003f9 = 0x0
+ bl delay1
+ /* set baud rate msb for 9600 baud */
+ 0xfe0003fb = 0x03
+ bl delay1
+ /* reset mslab */
+
+ /*--------------------------------------------------------------*/
+ /* END TERON Serial Port Initialization Code */
+ /*--------------------------------------------------------------*/
+
+
+ /*--------------------------------------------------------------*/
+ /* END TERON Articia / SDRAM Initialization code */
+ /*--------------------------------------------------------------*/
+
+Proposed from Documentation:
+
+write dmem 0xfec00cf8 0x50000080
+write dmem 0xfee00cfc 0xc0305411
+
+ Writes to index 0x50-0x53.
+ 0x50: Global Information Register 0
+ 0xC0 = Little Endian CPU, Sequential order Burst
+ 0x51: Global Information Register 1
+ Read only, 0x30 = Provides PowerPC and X86 support
+ 0x52: Global Information Register 2
+ 0x05 = 64/128 bit CPU bus support
+ 0x53: Global Information Register 3
+ 0x80 = PCI Bus 0 grant active time is 1 clock after REQ# deasserted
+
+write dmem 0xfec00cf8 0x5c000080
+write dmem 0xfee00cfc 0xb300011F
+
+write dmem 0xfec00cf8 0xc8000080
+write dmem 0xfee00cfc 0x0020f100
+
+write dmem 0xfec00cf8 0x90000080
+write dmem 0xfee00cfc 0x007fe700
+
+write dmem 0xfec00cf8 0x9400080
+write dmem 0xfee00cfc 0x007fe700
+
+write dmem 0xfec00cf8 0xb0000080
+write dmem 0xfee00cfc 0x737d737d
+
+write dmem 0xfec00cf8 0xb4000080
+write dmem 0xfee00cfc 0x737d737d
+
+write dmem 0xfec00cf8 0xc0000080
+write dmem 0xfee00cfc 0x40005500
+
+write dmem 0xfec00cf8 0xb8000080
+write dmem 0xfee00cfc 0x00940100
+
+write dmem 0xfec00cf8 0xc4000080
+write dmem 0xfee00cfc 0x00003280
+
+write dmem 0xfec00cf8 0xc4000080
+write dmem 0xfee00cfc 0x00003290
diff --git a/board/MAI/AmigaOneG3SE/u-boot.lds b/board/MAI/AmigaOneG3SE/u-boot.lds
index 10c0c3d..2281d35 100644
--- a/board/MAI/AmigaOneG3SE/u-boot.lds
+++ b/board/MAI/AmigaOneG3SE/u-boot.lds
@@ -63,7 +63,7 @@
cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
- common/environment.o(.text)
+ common/environment.o(.text)
*(.text)
*(.fixup)
@@ -87,7 +87,7 @@
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ *(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
@@ -108,6 +108,11 @@
_edata = .;
PROVIDE (edata = .);
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
diff --git a/board/MAI/AmigaOneG3SE/usb_uhci.c b/board/MAI/AmigaOneG3SE/usb_uhci.c
index fd8cb4e..14e8043 100644
--- a/board/MAI/AmigaOneG3SE/usb_uhci.c
+++ b/board/MAI/AmigaOneG3SE/usb_uhci.c
@@ -83,7 +83,7 @@
#define USB_MAX_TEMP_INT_TD 32 /* number of temporary TDs for Interrupt transfers */
-//#define USB_UHCI_DEBUG
+/*#define USB_UHCI_DEBUG */
#ifdef USB_UHCI_DEBUG
#define USB_UHCI_PRINTF(fmt,args...) printf (fmt ,##args)
@@ -599,7 +599,7 @@
printf("Error USB UHCI (%04X,%04X) not found\n",USB_UHCI_VEND_ID,USB_UHCI_DEV_ID);
return -1;
}
-
+
#if 1
s = getenv("usb_irq");
if (s)
@@ -1115,7 +1115,6 @@
#endif
-
#ifdef USB_UHCI_DEBUG
static int usb_display_td(uhci_td_t *td)
diff --git a/board/MAI/AmigaOneG3SE/usb_uhci.h b/board/MAI/AmigaOneG3SE/usb_uhci.h
index 7fda60b..3387157 100644
--- a/board/MAI/AmigaOneG3SE/usb_uhci.h
+++ b/board/MAI/AmigaOneG3SE/usb_uhci.h
@@ -190,5 +190,3 @@
#endif /* _USB_UHCI_H_ */
-
-
diff --git a/board/MAI/AmigaOneG3SE/via686.c b/board/MAI/AmigaOneG3SE/via686.c
index 0483ca9..c797e47 100644
--- a/board/MAI/AmigaOneG3SE/via686.c
+++ b/board/MAI/AmigaOneG3SE/via686.c
@@ -211,18 +211,18 @@
__asm (" .globl via_calibrate_time_base \n"
"via_calibrate_time_base: \n"
- " lis 9, 0xfe00 \n"
- " li 0, 0x00 \n"
+ " lis 9, 0xfe00 \n"
+ " li 0, 0x00 \n"
" mttbu 0 \n"
" mttbl 0 \n"
"ctb_loop: \n"
- " lbz 0, 0x61(9) \n"
- " eieio \n"
- " andi. 0, 0, 0x20 \n"
- " beq ctb_loop \n"
- "ctb_done: \n"
- " mftb 3 \n"
- " blr");
+ " lbz 0, 0x61(9) \n"
+ " eieio \n"
+ " andi. 0, 0, 0x20 \n"
+ " beq ctb_loop \n"
+ "ctb_done: \n"
+ " mftb 3 \n"
+ " blr");
extern unsigned long via_calibrate_time_base(void);
diff --git a/board/MAI/AmigaOneG3SE/video.c b/board/MAI/AmigaOneG3SE/video.c
index e80288b..36e3c62 100644
--- a/board/MAI/AmigaOneG3SE/video.c
+++ b/board/MAI/AmigaOneG3SE/video.c
@@ -1,6 +1,6 @@
/*
* (C) Copyright 2002
- * Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com
+ * Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -100,7 +100,7 @@
video_inited = 1;
video_init();
memset (&vgadev, 0, sizeof(vgadev));
-
+
strcpy(vgadev.name, VIDEO_NAME);
vgadev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM;
vgadev.putc = video_putc;
@@ -108,7 +108,7 @@
vgadev.getc = NULL;
vgadev.tstc = NULL;
vgadev.start = video_start;
-
+
error = device_register (&vgadev);
if (error == 0)
@@ -129,11 +129,11 @@
int video_init(void)
{
- cursor_position = VIDEO_BASE; // Color text display base
+ cursor_position = VIDEO_BASE; /* Color text display base */
cursor_row = 0;
cursor_col = 0;
- current_attr = video_get_attr(); // Currently selected value for attribute.
-// video_test();
+ current_attr = video_get_attr(); /* Currently selected value for attribute. */
+/* video_test(); */
video_set_color(current_attr);
return 0;
@@ -283,7 +283,7 @@
void video_draw_box(int style, int attr, char *title, int separate, int x, int y, int w, int h)
{
- unsigned char *fb, *fb2;
+ unsigned char *fb, *fb2;
unsigned char *st = (style == SINGLE_BOX)?video_single_box : video_double_box;
unsigned char *ti = (style == SINGLE_BOX)?video_single_title : video_double_title;
int i;
@@ -324,11 +324,11 @@
*fb = st[3];
*(fb+1) = attr; fb += 2*VIDEO_COLS;
- *fb2 = st[4];
+ *fb2 = st[4];
*(fb2+1) = attr; fb2 += 2*VIDEO_COLS;
}
-
- // Draw title
+
+ /* Draw title */
if (title)
{
if (separate == 0)
@@ -370,7 +370,7 @@
fb += 2;
}
fb = video_addr(x+2, y+1);
-
+
while (*title)
{
*fb = *title;
@@ -414,7 +414,7 @@
}
void video_restore_rect(int x, int y, int w, int h, void *save_area)
-{
+{
unsigned char *save = (unsigned char *)save_area;
unsigned char *fb = video_addr(x,y);
int i,j;
@@ -484,7 +484,7 @@
int i;
char *s;
int maxdev;
-
+
if (video_inited == 0) return;
#ifdef EASTEREGG