commit 5735fe18665d83433f46cd386d23e874dafc919e
author Prabhakar Kushwaha <prabhakar@freescale.com> Sun Apr 29 23:56:56 2012 +0000
committer Andy Fleming <afleming@freescale.com> Fri Jul 06 17:30:30 2012 -0500
tree 75f144255460f301c270d845420a4a1f5c58450e
parent bc8d57c24e188eb1763722bc669c4f1997fbbc3c

powerpc/85xx:Fix NAND code base to support debugger

Update NAND code base to ovecome e500 and e500v2's second limitation i.e. IVPR
+ IVOR15 should be valid fetchable OP code address.

As NAND SPL does not compile vector table so making sure IVOR + IVOR15 points to
any fetchable valid data

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>

arch/powerpc/cpu/mpc85xx/start.S

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 4267196..6aabc30 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -182,7 +182,7 @@
 	andi.	r1,r3,L1CSR0_DCE@l
 	beq	2b
 
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
 /*
  * TLB entry for debuggging in AS1
  * Create temporary TLB entry in AS0 to handle debug exception