| commit | 56fd85df5488fb1a228930f65a06975737ff215e | [log] [tgz] |
|---|---|---|
| author | Ye Li <ye.li@nxp.com> | Mon Jan 07 03:18:06 2019 +0000 |
| committer | Peng Fan <peng.fan@nxp.com> | Fri May 03 20:03:41 2019 +0800 |
| tree | 311a4c938f6fb4afd4623f8f4179aa75757471f0 | |
| parent | dd6f126edc06e912a2d79d2a760afa9c40cd3323 [diff] |
mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode, the output clock rate is half of the internal clock rate. This patch set the DDR_EN bit first for DDR mode, hardware divide the usdhc clock automatically, then follow the original sdr clock setting method. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>