diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c
index 0c2114a..94c157f 100644
--- a/cpu/mpc5xxx/pci_mpc5200.c
+++ b/cpu/mpc5xxx/pci_mpc5200.c
@@ -115,7 +115,7 @@
 
 	/* Map MBAR to PCI space */
 	*(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR;
-	*(vu_long *)MPC5XXX_PCI_TBATR1 = CFG_MBAR | 1;
+	*(vu_long *)MPC5XXX_PCI_TBATR0 = CFG_MBAR | 1;
 
 	/* Map RAM to PCI space */
 	*(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S
index 26811e1..6f0b269 100644
--- a/cpu/mpc5xxx/start.S
+++ b/cpu/mpc5xxx/start.S
@@ -145,6 +145,8 @@
 	lis	r3, CFG_MBAR@h
 	ori	r3, r3, CFG_MBAR@l
 #if defined(CONFIG_MPC5200)
+	/* MBAR is mirrored into the MBAR SPR */
+	mtspr	MBAR,r3
 	rlwinm	r3, r3, 16, 16, 31
 #endif
 #if defined(CONFIG_MGT5100)
diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c
index b3a89f5..dc077ed 100644
--- a/cpu/mpc8260/pci.c
+++ b/cpu/mpc8260/pci.c
@@ -28,28 +28,28 @@
 #include <pci.h>
 #include <mpc8260.h>
 #include <asm/m8260_pci.h>
-
+#include <asm/io.h>
 /*
- *   Local->PCI map (from CPU)                             controlled by
+ *   Local->PCI map (from CPU)				   controlled by
  *   MPC826x master window
  *
- *   0x80000000 - 0xBFFFFFFF    CPU2PCI space              PCIBR0
- *   0xF4000000 - 0xF7FFFFFF    CPU2PCI space              PCIBR1
+ *   0x80000000 - 0xBFFFFFFF	CPU2PCI space		   PCIBR0
+ *   0xF4000000 - 0xF7FFFFFF	CPU2PCI space		   PCIBR1
  *
- *   0x80000000 - 0x9FFFFFFF    0x80000000 - 0x9FFFFFFF   (Outbound ATU #1)
- *                              PCI Mem with prefetch
+ *   0x80000000 - 0x9FFFFFFF	0x80000000 - 0x9FFFFFFF	  (Outbound ATU #1)
+ *				PCI Mem with prefetch
  *
- *   0xA0000000 - 0xBFFFFFFF    0xA0000000 - 0xBFFFFFFF   (Outbound ATU #2)
- *                              PCI Mem w/o  prefetch
+ *   0xA0000000 - 0xBFFFFFFF	0xA0000000 - 0xBFFFFFFF	  (Outbound ATU #2)
+ *				PCI Mem w/o  prefetch
  *
- *   0xF4000000 - 0xF7FFFFFF    0x00000000 - 0x03FFFFFF   (Outbound ATU #3)
- *                              32-bit PCI IO
+ *   0xF4000000 - 0xF7FFFFFF	0x00000000 - 0x03FFFFFF	  (Outbound ATU #3)
+ *				32-bit PCI IO
  *
  *   PCI->Local map (from PCI)
- *   MPC826x slave window                                  controlled by
+ *   MPC826x slave window				   controlled by
  *
- *   0x00000000 - 0x1FFFFFFF    0x00000000 - 0x1FFFFFFF   (Inbound ATU #1)
- *                              MPC826x local memory
+ *   0x00000000 - 0x1FFFFFFF	0x00000000 - 0x1FFFFFFF	  (Inbound ATU #1)
+ *				MPC826x local memory
  */
 
 /*
@@ -58,13 +58,13 @@
  */
 
 #ifndef CFG_PCI_SLV_MEM_LOCAL
-#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE		/* Local base */
+#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE	/* Local base */
 #else
 #define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL
 #endif
 
 #ifndef CFG_PCI_SLV_MEM_BUS
-#define PCI_SLV_MEM_BUS 0x00000000		/* PCI base */
+#define PCI_SLV_MEM_BUS 0x00000000	/* PCI base */
 #else
 #define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS
 #endif
@@ -85,28 +85,28 @@
 
 /* PCIBR0 */
 #ifndef CFG_PCI_MSTR0_LOCAL
-#define PCI_MSTR0_LOCAL		0x80000000		/* Local base */
+#define PCI_MSTR0_LOCAL		0x80000000	/* Local base */
 #else
 #define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL
 #endif
 
 #ifndef CFG_PCIMSK0_MASK
-#define PCIMSK0_MASK		PCIMSK_1GB		/* Size of window */
+#define PCIMSK0_MASK		PCIMSK_1GB	/* Size of window */
 #else
 #define PCIMSK0_MASK	CFG_PCIMSK0_MASK
 #endif
 
 /* PCIBR1 */
 #ifndef CFG_PCI_MSTR1_LOCAL
-#define PCI_MSTR1_LOCAL		0xF4000000		/* Local base */
+#define PCI_MSTR1_LOCAL		0xF4000000	/* Local base */
 #else
 #define PCI_MSTR1_LOCAL		CFG_PCI_MSTR1_LOCAL
 #endif
 
 #ifndef CFG_PCIMSK1_MASK
-#define  PCIMSK1_MASK		PCIMSK_64MB		/* Size of window */
+#define	 PCIMSK1_MASK		PCIMSK_64MB	/* Size of window */
 #else
-#define  PCIMSK1_MASK		CFG_PCIMSK1_MASK
+#define	 PCIMSK1_MASK		CFG_PCIMSK1_MASK
 #endif
 
 /*
@@ -116,13 +116,13 @@
  */
 
 #ifndef CFG_PCI_MSTR_MEM_LOCAL
-#define PCI_MSTR_MEM_LOCAL 0x80000000          /* Local base */
+#define PCI_MSTR_MEM_LOCAL 0x80000000	/* Local base */
 #else
 #define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL
 #endif
 
 #ifndef CFG_PCI_MSTR_MEM_BUS
-#define PCI_MSTR_MEM_BUS 0x80000000          /* PCI base   */
+#define PCI_MSTR_MEM_BUS 0x80000000	/* PCI base   */
 #else
 #define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS
 #endif
@@ -134,7 +134,7 @@
 #endif
 
 #ifndef CFG_PCI_MSTR_MEM_SIZE
-#define PCI_MSTR_MEM_SIZE 0x10000000          /* 256MB */
+#define PCI_MSTR_MEM_SIZE 0x10000000	/* 256MB */
 #else
 #define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE
 #endif
@@ -152,13 +152,13 @@
  */
 
 #ifndef CFG_PCI_MSTR_MEMIO_LOCAL
-#define PCI_MSTR_MEMIO_LOCAL 0x90000000          /* Local base */
+#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
 #else
 #define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL
 #endif
 
 #ifndef CFG_PCI_MSTR_MEMIO_BUS
-#define PCI_MSTR_MEMIO_BUS 0x90000000          /* PCI base   */
+#define PCI_MSTR_MEMIO_BUS 0x90000000	/* PCI base   */
 #else
 #define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS
 #endif
@@ -170,13 +170,13 @@
 #endif
 
 #ifndef CFG_PCI_MSTR_MEMIO_SIZE
-#define PCI_MSTR_MEMIO_SIZE 0x10000000          /* 256 MB */
+#define PCI_MSTR_MEMIO_SIZE 0x10000000	/* 256 MB */
 #else
 #define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE
 #endif
 
 #ifndef CFG_POCMR1_MASK_ATTRIB
-#define POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
+#define POCMR1_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE)
 #else
 #define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB
 #endif
@@ -188,13 +188,13 @@
  */
 
 #ifndef CFG_PCI_MSTR_IO_LOCAL
-#define PCI_MSTR_IO_LOCAL 0xA0000000          /* Local base */
+#define PCI_MSTR_IO_LOCAL 0xA0000000	/* Local base */
 #else
 #define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL
 #endif
 
 #ifndef CFG_PCI_MSTR_IO_BUS
-#define PCI_MSTR_IO_BUS 0xA0000000          /* PCI base   */
+#define PCI_MSTR_IO_BUS 0xA0000000	/* PCI base   */
 #else
 #define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS
 #endif
@@ -206,13 +206,13 @@
 #endif
 
 #ifndef CFG_PCI_MSTR_IO_SIZE
-#define PCI_MSTR_IO_SIZE 0x10000000          /* 256MB */
+#define PCI_MSTR_IO_SIZE 0x10000000	/* 256MB */
 #else
 #define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE
 #endif
 
 #ifndef CFG_POCMR2_MASK_ATTRIB
-#define POCMR2_MASK_ATTRIB      (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
+#define POCMR2_MASK_ATTRIB	(POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
 #else
 #define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB
 #endif
@@ -223,193 +223,198 @@
 #define PCI_CLASS_BRIDGE_CTLR	0x06
 
 
-static inline void  pci_outl(u32 addr, u32 data)
+static inline void pci_outl (u32 addr, u32 data)
 {
-    *(volatile u32 *) addr = cpu_to_le32(data);
+	*(volatile u32 *) addr = cpu_to_le32 (data);
 }
 
-void pci_mpc8250_init(struct pci_controller *hose)
+void pci_mpc8250_init (struct pci_controller *hose)
 {
 #ifdef CONFIG_MPC8266ADS
-    DECLARE_GLOBAL_DATA_PTR;
+	DECLARE_GLOBAL_DATA_PTR;
 #endif
-    u16 tempShort;
-    u32 immr_addr = CFG_IMMR;
-    volatile immap_t *immap = (immap_t *) CFG_IMMR;
-    pci_dev_t host_devno = PCI_BDF(0, 0, 0);
+	u16 tempShort;
+
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	pci_dev_t host_devno = PCI_BDF (0, 0, 0);
 
-    pci_setup_indirect(hose, CFG_IMMR + PCI_CFG_ADDR_REG,
-				 CFG_IMMR + PCI_CFG_DATA_REG);
+	pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG,
+			    CFG_IMMR + PCI_CFG_DATA_REG);
 
-    /*
-     * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
-     */
+	/*
+	 * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
+	 */
 #ifdef CONFIG_MPC8266ADS
-    immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
-				   | SIUMCR_LBPC01;
+	immap->im_siu_conf.sc_siumcr =
+		(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
+		| SIUMCR_LBPC01;
 #else
-    /*
-     * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
-     * and local bus for PCI (SIUMCR [LBPC]).
-     */
-    immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
-						  ~SIUMCR_LBPC11 &
+	/*
+	 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
+	 * and local bus for PCI (SIUMCR [LBPC]).
+	 */
+	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
+						~SIUMCR_LBPC11 &
 						~SIUMCR_CS10PC11 &
-						 ~SIUMCR_LBPC11) |
-				   SIUMCR_LBPC01 |
-				   SIUMCR_CS10PC01 |
-				   SIUMCR_LBPC01;
+						~SIUMCR_LBPC11) |
+					SIUMCR_LBPC01 |
+					SIUMCR_CS10PC01 |
+					SIUMCR_APPC10;
 #endif
 
-    /* Make PCI lowest priority */
-    /* Each 4 bits is a device bus request  and the MS 4bits
-       is highest priority */
-    /* Bus               4bit value
-	   ---               ----------
-       CPM high          0b0000
-       CPM middle        0b0001
-	   CPM low           0b0010
-       PCI reguest       0b0011
-       Reserved          0b0100
-       Reserved          0b0101
-       Internal Core     0b0110
-       External Master 1 0b0111
-       External Master 2 0b1000
-       External Master 3 0b1001
-       The rest are reserved */
-    immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
+	/* Make PCI lowest priority */
+	/* Each 4 bits is a device bus request	and the MS 4bits
+	   is highest priority */
+	/* Bus		     4bit value
+	   ---		     ----------
+	   CPM high	     0b0000
+	   CPM middle	     0b0001
+	   CPM low	     0b0010
+	   PCI reguest	     0b0011
+	   Reserved	     0b0100
+	   Reserved	     0b0101
+	   Internal Core     0b0110
+	   External Master 1 0b0111
+	   External Master 2 0b1000
+	   External Master 3 0b1001
+	   The rest are reserved */
+	immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
 
-    /* Park bus on core while modifying PCI Bus accesses */
-    immap->im_siu_conf.sc_ppc_acr = 0x6;
+	/* Park bus on core while modifying PCI Bus accesses */
+	immap->im_siu_conf.sc_ppc_acr = 0x6;
 
-    /*
-     * Set up master windows that allow the CPU to access PCI space. These
-     * windows are set up using the two SIU PCIBR registers.
-     */
-    *(volatile unsigned long*)(immr_addr + M8265_PCIMSK0) = PCIMSK0_MASK;
-    *(volatile unsigned long*)(immr_addr + M8265_PCIBR0) =
-	    PCI_MSTR0_LOCAL | PCIBR_ENABLE;
+	/*
+	 * Set up master windows that allow the CPU to access PCI space. These
+	 * windows are set up using the two SIU PCIBR registers.
+	 */
+	immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
+	immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;
 
 #ifdef CONFIG_MPC8266ADS
-    *(volatile unsigned long*)(immr_addr + M8265_PCIMSK1) = PCIMSK1_MASK;
-    *(volatile unsigned long*)(immr_addr + M8265_PCIBR1) =
-	    PCI_MSTR1_LOCAL | PCIBR_ENABLE;
+	immap->im_memctl.memc_pcimsk0 = PCIMSK1_MASK;
+	immap->im_memctl.memc_pcibr0 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
 #endif
 
-    /* Release PCI RST (by default the PCI RST signal is held low)  */
-    pci_outl (immr_addr | PCI_GCR_REG, PCIGCR_PCI_BUS_EN);
+	/* Release PCI RST (by default the PCI RST signal is held low)	*/
+	immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);
 
-    /* give it some time */
-    {
+	/* give it some time */
+	{
 #ifdef CONFIG_MPC8266ADS
 		/* Give the PCI cards more time to initialize before query
-			This might be good for other boards also
-		*/
-	int i;
-	for (i = 0; i < 1000; ++i)
+		   This might be good for other boards also
+		 */
+		int i;
+
+		for (i = 0; i < 1000; ++i)
 #endif
-	    udelay(1000);
-    }
+			udelay (1000);
+	}
 
-    /*
-     * Set up master window that allows the CPU to access PCI Memory (prefetch)
-     * space. This window is set up using the first set of Outbound ATU registers.
-     */
-    pci_outl (immr_addr | POTAR_REG0, PCI_MSTR_MEM_BUS >> 12);      /* PCI base */
-    pci_outl (immr_addr | POBAR_REG0, PCI_MSTR_MEM_LOCAL >> 12);    /* Local base */
-    pci_outl (immr_addr | POCMR_REG0, POCMR0_MASK_ATTRIB);    /* Size & attribute */
+	/*
+	 * Set up master window that allows the CPU to access PCI Memory (prefetch)
+	 * space. This window is set up using the first set of Outbound ATU registers.
+	 */
+	immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12);	/* PCI base */
+	immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12);	/* Local base */
+	immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB);	/* Size & attribute */
 
-    /*
-     * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
-     * space. This window is set up using the second set of Outbound ATU registers.
-     */
-    pci_outl (immr_addr | POTAR_REG1, PCI_MSTR_MEMIO_BUS >> 12);    /* PCI base */
-    pci_outl (immr_addr | POBAR_REG1, PCI_MSTR_MEMIO_LOCAL >> 12);  /* Local base */
-    pci_outl (immr_addr | POCMR_REG1, POCMR1_MASK_ATTRIB);    /* Size & attribute */
+	/*
+	 * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
+	 * space. This window is set up using the second set of Outbound ATU registers.
+	 */
+	immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12);	/* PCI base */
+	immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12);	/* Local base */
+	immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB);	/* Size & attribute */
 
-    /*
-     * Set up master window that allows the CPU to access PCI IO space. This window
-     * is set up using the third set of Outbound ATU registers.
-     */
-    pci_outl (immr_addr | POTAR_REG2, PCI_MSTR_IO_BUS >> 12);       /* PCI base */
-    pci_outl (immr_addr | POBAR_REG2, PCI_MSTR_IO_LOCAL >> 12);     /* Local base */
-    pci_outl (immr_addr | POCMR_REG2, POCMR2_MASK_ATTRIB);    /* Size & attribute */
+	/*
+	 * Set up master window that allows the CPU to access PCI IO space. This window
+	 * is set up using the third set of Outbound ATU registers.
+	 */
+	immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
+	immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12);	/* Local base */
+	immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB);	/* Size & attribute */
 
-    /*
-     * Set up slave window that allows PCI masters to access MPC826x local memory.
-     * This window is set up using the first set of Inbound ATU registers
-     */
-    pci_outl (immr_addr | PITAR_REG0, PCI_SLV_MEM_LOCAL >> 12);     /* Local base */
-    pci_outl (immr_addr | PIBAR_REG0, PCI_SLV_MEM_BUS >> 12);       /* PCI base */
-    pci_outl (immr_addr | PICMR_REG0, PICMR0_MASK_ATTRIB);    /* Size & attribute */
+	/*
+	 * Set up slave window that allows PCI masters to access MPC826x local memory.
+	 * This window is set up using the first set of Inbound ATU registers
+	 */
+	immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12);	/* PCI base */
+	immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
+	immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB);	/* Size & attribute */
 
-     /* See above for description - puts PCI request as highest priority */
-    immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
+	/* See above for description - puts PCI request as highest priority */
+	immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
 
-    /* Park the bus on the PCI */
-    immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
+	/* Park the bus on the PCI */
+	immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
 
-    /* Host mode - specify the bridge as a host-PCI bridge */
+	/* Host mode - specify the bridge as a host-PCI bridge */
 
-    pci_hose_write_config_byte(hose, host_devno, PCI_CLASS_CODE,
-				   PCI_CLASS_BRIDGE_CTLR);
+	pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
+				    PCI_CLASS_BRIDGE_CTLR);
 
-    /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
-    pci_hose_read_config_word(hose, host_devno, PCI_COMMAND, &tempShort);
-    pci_hose_write_config_word(hose, host_devno, PCI_COMMAND,
-			 tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+	/* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
+	pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
+	pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
+				    tempShort | PCI_COMMAND_MASTER |
+				    PCI_COMMAND_MEMORY);
 
-#ifdef CONFIG_MPC8266ADS
 	/* do some bridge init, should be done on all 8260 based bridges */
-	pci_hose_write_config_byte(hose, host_devno, PCI_CACHE_LINE_SIZE, 0x08);
-	pci_hose_write_config_byte(hose, host_devno, PCI_LATENCY_TIMER, 0xF8);
-#endif
+	pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
+				    0x08);
+	pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
+				    0xF8);
 
-    hose->first_busno = 0;
-    hose->last_busno = 0xff;
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
 
-    /* System memory space */
+	/* System memory space */
 #ifdef CONFIG_MPC8266ADS
-    pci_set_region(hose->regions + 0,
-		       PCI_SLV_MEM_BUS,
-		       PCI_SLV_MEM_LOCAL,
-		       gd->ram_size,
-		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+	pci_set_region (hose->regions + 0,
+			PCI_SLV_MEM_BUS,
+			PCI_SLV_MEM_LOCAL,
+			gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
 #else
-    pci_set_region(hose->regions + 0,
-		       CFG_SDRAM_BASE,
-		       CFG_SDRAM_BASE,
-		       0x4000000,
-		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+	pci_set_region (hose->regions + 0,
+			CFG_SDRAM_BASE,
+			CFG_SDRAM_BASE,
+			0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
 #endif
 
-    /* PCI memory space */
+	/* PCI memory space */
 #ifdef CONFIG_MPC8266ADS
-    pci_set_region(hose->regions + 1,
-		       PCI_MSTR_MEMIO_BUS,
-		       PCI_MSTR_MEMIO_LOCAL,
-		       PCI_MSTR_MEMIO_SIZE,
-		       PCI_REGION_MEM);
+	pci_set_region (hose->regions + 1,
+			PCI_MSTR_MEMIO_BUS,
+			PCI_MSTR_MEMIO_LOCAL,
+			PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
 #else
-    pci_set_region(hose->regions + 1,
-		       PCI_MSTR_MEM_BUS,
-		       PCI_MSTR_MEM_LOCAL,
-		       PCI_MSTR_MEM_SIZE,
-		       PCI_REGION_MEM);
+	pci_set_region (hose->regions + 1,
+			PCI_MSTR_MEM_BUS,
+			PCI_MSTR_MEM_LOCAL,
+			PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
 #endif
 
+	/* PCI I/O space */
+	pci_set_region (hose->regions + 2,
+			PCI_MSTR_IO_BUS,
+			PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);
+
-    /* PCI I/O space */
-    pci_set_region(hose->regions + 2,
-		       PCI_MSTR_IO_BUS,
-		       PCI_MSTR_IO_LOCAL,
-		       PCI_MSTR_IO_SIZE,
-		       PCI_REGION_IO);
+	hose->region_count = 3;
 
-    hose->region_count = 3;
+	pci_register_hose (hose);
+	/* Mask off master abort machine checks */
+	immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
+	eieio ();
 
-    pci_register_hose(hose);
+	hose->last_busno = pci_hose_scan (hose);
 
-    hose->last_busno = pci_hose_scan(hose);
+
+	/* clear the error in the error status register */
+	immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
+
+	/* unmask master abort machine checks */
+	immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
 }
 
-#endif	/* CONFIG_PCI */
+#endif /* CONFIG_PCI */
diff --git a/cpu/mpc8260/traps.c b/cpu/mpc8260/traps.c
index a7f6f7e..deab808 100644
--- a/cpu/mpc8260/traps.c
+++ b/cpu/mpc8260/traps.c
@@ -35,6 +35,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/processor.h>
+#include <asm/m8260_pci.h>
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 int (*debugger_exception_handler)(struct pt_regs *) = 0;
@@ -86,14 +87,12 @@
 
 	printf("\n");
 	for (i = 0;  i < 32;  i++) {
-		if ((i % 8) == 0)
-		{
+		if ((i % 8) == 0) {
 			printf("GPR%02d: ", i);
 		}
 
 		printf("%08lX ", regs->gpr[i]);
-		if ((i % 8) == 7)
-		{
+		if ((i % 8) == 7) {
 			printf("\n");
 		}
 	}
@@ -108,6 +107,24 @@
 	panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
 }
 
+#ifdef CONFIG_PCI
+void dump_pci (void)
+{
+
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+	printf ("PCI: err status %x err mask %x err ctrl %x\n",
+		le32_to_cpu (immap->im_pci.pci_esr),
+		le32_to_cpu (immap->im_pci.pci_emr),
+		le32_to_cpu (immap->im_pci.pci_ecr));
+	printf ("     error address %x error data %x ctrl %x\n",
+		le32_to_cpu (immap->im_pci.pci_eacr),
+		le32_to_cpu (immap->im_pci.pci_edcr),
+		le32_to_cpu (immap->im_pci.pci_eccr));
+
+}
+#endif
+
 void
 MachineCheckException(struct pt_regs *regs)
 {
@@ -117,6 +134,17 @@
 	 * when a device is not present.  Catch it and return to
 	 * the PCI exception handler.
 	 */
+#ifdef CONFIG_PCI
+	volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+#ifdef DEBUG
+	dump_pci();
+#endif
+	/* clear the error in the error status register */
+	if(immap->im_pci.pci_esr && cpu_to_le32(PCI_ERROR_PCI_NO_RSP)) {
+		immap->im_pci.pci_esr = cpu_to_le32(PCI_ERROR_PCI_NO_RSP);
+		return;
+	}
+#endif
 	if ((fixup = search_exception_table(regs->nip)) != 0) {
 		regs->nip = fixup;
 		return;
@@ -130,8 +158,7 @@
 	printf("Machine check in kernel mode.\n");
 	printf("Caused by (from msr): ");
 	printf("regs %p ",regs);
-	switch( regs->msr & 0x0000F000)
-	{
+	switch( regs->msr & 0x0000F000) {
 	case (1<<12) :
 		printf("Machine check signal - probably due to mm fault\n"
 			"with mmu off\n");
@@ -150,6 +177,9 @@
 	}
 	show_regs(regs);
 	print_backtrace((unsigned long *)regs->gpr[1]);
+#ifdef CONFIG_PCI
+	dump_pci();
+#endif
 	panic("machine check");
 }
 
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index d3f6b23..c9e2e9c 100644
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -411,15 +411,23 @@
 
 	/*--------------------------------------------------------------------------+
 	 * The PCI initialization sequence enable bit must be set ... if not abort
-     * pci setup since updating the bit requires chip reset.
+	 * pci setup since updating the bit requires chip reset.
 	 *--------------------------------------------------------------------------*/
-    strap = mfdcr(cpc0_strp1);
-    if( (strap & 0x00040000) == 0 ){
-	printf("PCI: CPC0_STRP1[PISE] not set.\n");
-	printf("PCI: Configuration aborted.\n");
-	return;
-    }
-
+#if defined (CONFIG_440_GX)
+	mfsdr(sdr_sdstp1,strap);
+	if ( (strap & 0x00010000) == 0 ){
+		printf("PCI: SDR0_STRP1[PISE] not set.\n");
+		printf("PCI: Configuration aborted.\n");
+		return;
+	}
+#else
+	strap = mfdcr(cpc0_strp1);
+	if( (strap & 0x00040000) == 0 ){
+		printf("PCI: CPC0_STRP1[PISE] not set.\n");
+		printf("PCI: Configuration aborted.\n");
+		return;
+	}
+#endif
 	/*--------------------------------------------------------------------------+
 	 * PCI controller init
 	 *--------------------------------------------------------------------------*/
@@ -463,8 +471,13 @@
     out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
 #endif
 
-    out32r( PCIX0_BRDGOPT1, 0x10000060 );               /* PLB Rq pri highest   */
-    out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config   */
+#if defined(CONFIG_440_GX)
+	out32r( PCIX0_BRDGOPT1, 0x04000060 );               /* PLB Rq pri highest   */
+	out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1  */
+#else
+	out32r( PCIX0_BRDGOPT1, 0x10000060 );               /* PLB Rq pri highest   */
+	out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config   */
+#endif
 
 	/*--------------------------------------------------------------------------+
 	 * PCI master init: default is one 256MB region for PCI memory:
diff --git a/cpu/ppc4xx/440gx_enet.c b/cpu/ppc4xx/440gx_enet.c
index 617a174..4502085 100644
--- a/cpu/ppc4xx/440gx_enet.c
+++ b/cpu/ppc4xx/440gx_enet.c
@@ -116,6 +116,10 @@
 
 #undef INFO_440_ENET
 
+#define BI_PHYMODE_NONE  0
+#define BI_PHYMODE_ZMII  1
+#define BI_PHYMODE_RGMII 2
+
 /*-----------------------------------------------------------------------------+
  * Global variables. TX and RX descriptors and buffers.
  *-----------------------------------------------------------------------------*/
@@ -316,11 +320,12 @@
 		break;
 	}
 
+	bis->bi_phynum[devnum] = reg;
+
 	/* Reset the phy */
 	miiphy_reset (reg);
 
 	/* Start/Restart autonegotiation */
-/*	miiphy_write(reg, PHY_BMCR, 0x9340); */
 	phy_setup_aneg (reg);
 	udelay (1000);
 
@@ -579,13 +584,6 @@
 		irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
 				     (interrupt_handler_t *) enetInt, dev);
 	}
-#if 0				/* done by irq_install_handler */
-	/* set up interrupt handler */
-	/* setup interrupt controller to take interrupts from the MAL &
-	   EMAC */
-	mtdcr (uicsr, 0xffffffff);	/* clear pending interrupts */
-	mtdcr (uicer, mfdcr (uicer) | MAL_UIC_DEF | EMAC_UIC_DEF);
-#endif
 
 	mtmsr (msr);		/* enable interrupts again */
 
@@ -1027,33 +1025,49 @@
 	pfc1 &= ~(0x01e00000);
 	pfc1 |= 0x01200000;
 	mtsdr (sdr_pfc1, pfc1);
+	/* set phy num and mode */
+	bis->bi_phynum[0] = CONFIG_PHY_ADDR;
+	bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
+	bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
+	bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
+	bis->bi_phymode[0] = 0;
+	bis->bi_phymode[1] = 0;
+	bis->bi_phymode[2] = 2;
+	bis->bi_phymode[3] = 2;
 
 	for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
 
 		/* See if we can actually bring up the interface, otherwise, skip it */
 		switch (eth_num) {
 		case 0:
-			if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0)
+			if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
+				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
 				continue;
+			}
 			break;
 		case 1:
-			if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) ==
-			    0)
+			if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
+				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
 				continue;
+			}
 			break;
 		case 2:
-			if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) ==
-			    0)
+			if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
+				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
 				continue;
+			}
 			break;
 		case 3:
-			if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) ==
-			    0)
+			if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
+				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
 				continue;
+			}
 			break;
 		default:
-			if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0)
+			if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
+				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
 				continue;
+			}
 			break;
 		}