clk: qcom: add clk_phy_mux_enable() for PCIe PIPE clock
The PCIe PIPE clock requires a special setup function to
mux & enable the clock from the PCIe PHY before the PHY
has enabled the clock.
Import the clk_phy_mux_enable() from the Linux driver to
use the same implementation regarding the PIPE clock.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241125-topic-pcie-clk-v1-1-4315d1e4e164@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index 78d9b1d..ff336de 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -6,6 +6,7 @@
#define _CLOCK_QCOM_H
#include <asm/io.h>
+#include <linux/bitfield.h>
#define CFG_CLK_SRC_CXO (0 << 8)
#define CFG_CLK_SRC_GPLL0 (1 << 8)
@@ -102,6 +103,7 @@
int div, int m, int n, int source, u8 mnd_width);
void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
int source);
+void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled);
static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
{