arm: pxa: Remove CONFIG_CPU_PXA25X
There are no platforms that set this, remove the code.
Signed-off-by: Tom Rini <trini@konsulko.com>
diff --git a/arch/arm/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile
index 263d9dd..fab7732 100644
--- a/arch/arm/cpu/pxa/Makefile
+++ b/arch/arm/cpu/pxa/Makefile
@@ -5,7 +5,6 @@
extra-y = start.o
-obj-$(CONFIG_CPU_PXA25X) += pxa2xx.o
obj-$(CONFIG_CPU_PXA27X) += pxa2xx.o
obj-y += cpuinfo.o
diff --git a/arch/arm/cpu/pxa/cpuinfo.c b/arch/arm/cpu/pxa/cpuinfo.c
index 0d9542f..549b61d 100644
--- a/arch/arm/cpu/pxa/cpuinfo.c
+++ b/arch/arm/cpu/pxa/cpuinfo.c
@@ -11,12 +11,6 @@
#include <errno.h>
#include <linux/compiler.h>
-#ifdef CONFIG_CPU_PXA25X
-#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
-#error "Init SP address must be set to 0xfffff800 for PXA250"
-#endif
-#endif
-
#define CPU_MASK_PXA_PRODID 0x000003f0
#define CPU_MASK_PXA_REVID 0x0000000f
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index 896e05f..ab7bcb4 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -49,9 +49,6 @@
bl cpu_init_crit
#endif
-#ifdef CONFIG_CPU_PXA25X
- bl lock_cache_for_stack
-#endif
#ifdef CONFIG_CPU_PXA27X
/*
* enable clock for SRAM
@@ -67,20 +64,7 @@
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
-
-#ifdef CONFIG_CPU_PXA25X
- /*
- * Unlock (actually, disable) the cache now that board_init_f
- * is done. We could do this earlier but we would need to add
- * a new C runtime hook, whereas c_runtime_cpu_setup already
- * exists.
- * As this routine is just a call to cpu_init_crit, let us
- * tail-optimize and do a simple branch here.
- */
- b cpu_init_crit
-#else
bx lr
-#endif
/*
*************************************************************************
@@ -92,7 +76,7 @@
*
*************************************************************************
*/
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
cpu_init_crit:
/*
* flush v4 I/D caches
@@ -111,95 +95,4 @@
mcr p15, 0, r0, c1, c0, 0
mov pc, lr /* back to my caller */
-#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || CONFIG_CPU_PXA25X */
-
-/*
- * Enable MMU to use DCache as DRAM.
- *
- * This is useful on PXA25x and PXA26x in early bootstages, where there is no
- * other possible memory available to hold stack.
- */
-#ifdef CONFIG_CPU_PXA25X
-.macro CPWAIT reg
- mrc p15, 0, \reg, c2, c0, 0
- mov \reg, \reg
- sub pc, pc, #4
-.endm
-lock_cache_for_stack:
- /* Domain access -- enable for all CPs */
- ldr r0, =0x0000ffff
- mcr p15, 0, r0, c3, c0, 0
-
- /* Point TTBR to MMU table */
- ldr r0, =mmutable
- mcr p15, 0, r0, c2, c0, 0
-
- /* Kick in MMU, ICache, DCache, BTB */
- mrc p15, 0, r0, c1, c0, 0
- bic r0, #0x1b00
- bic r0, #0x0087
- orr r0, #0x1800
- orr r0, #0x0005
- mcr p15, 0, r0, c1, c0, 0
- CPWAIT r0
-
- /* Unlock Icache, Dcache */
- mcr p15, 0, r0, c9, c1, 1
- mcr p15, 0, r0, c9, c2, 1
-
- /* Flush Icache, Dcache, BTB */
- mcr p15, 0, r0, c7, c7, 0
-
- /* Unlock I-TLB, D-TLB */
- mcr p15, 0, r0, c10, c4, 1
- mcr p15, 0, r0, c10, c8, 1
-
- /* Flush TLB */
- mcr p15, 0, r0, c8, c7, 0
-
- /* Allocate 4096 bytes of Dcache as RAM */
-
- /* Drain pending loads and stores */
- mcr p15, 0, r0, c7, c10, 4
-
- mov r4, #0x00
- mov r5, #0x00
- mov r2, #0x01
- mcr p15, 0, r0, c9, c2, 0
- CPWAIT r0
-
- /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
- mov r0, #128
- ldr r1, =0xfffff000
-
-alloc:
- mcr p15, 0, r1, c7, c2, 5
- /* Drain pending loads and stores */
- mcr p15, 0, r0, c7, c10, 4
- strd r4, [r1], #8
- strd r4, [r1], #8
- strd r4, [r1], #8
- strd r4, [r1], #8
- subs r0, #0x01
- bne alloc
- /* Drain pending loads and stores */
- mcr p15, 0, r0, c7, c10, 4
- mov r2, #0x00
- mcr p15, 0, r2, c9, c2, 0
- CPWAIT r0
-
- mov pc, lr
-
-.section .mmutable, "a"
-mmutable:
- .align 14
- /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
- .set __base, 0
- .rept 0xfff
- .word (__base << 20) | 0xc12
- .set __base, __base + 1
- .endr
-
- /* 0xfff00000 : 1:1, cached mapping */
- .word (0xfff << 20) | 0x1c1e
-#endif /* CONFIG_CPU_PXA25X */
+#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
diff --git a/arch/arm/include/asm/arch-pxa/config.h b/arch/arm/include/asm/arch-pxa/config.h
index 75b0e49..11effd4 100644
--- a/arch/arm/include/asm/arch-pxa/config.h
+++ b/arch/arm/include/asm/arch-pxa/config.h
@@ -13,8 +13,6 @@
*/
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define CONFIG_SYS_TIMER_RATE 3250000
-#elif defined(CONFIG_CPU_PXA25X)
-#define CONFIG_SYS_TIMER_RATE 3686400
#else
#error "Timer frequency unknown - please config PXA CPU type"
#endif
diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h
index 14860d8..26f1877 100644
--- a/arch/arm/include/asm/config.h
+++ b/arch/arm/include/asm/config.h
@@ -11,7 +11,6 @@
#if defined(CONFIG_ARCH_LS1021A) || \
defined(CONFIG_CPU_PXA27X) || \
defined(CONFIG_CPU_MONAHANS) || \
- defined(CONFIG_CPU_PXA25X) || \
defined(CONFIG_FSL_LAYERSCAPE)
#include <asm/arch/config.h>
#endif