commit 56af659b15728ac5943860bde0f483a56c380f40
author Tom Rini <trini@konsulko.com> Wed Nov 16 13:10:33 2022 -0500
committer Tom Rini <trini@konsulko.com> Mon Dec 05 16:06:07 2022 -0500
tree 6fade563d93ccb2dc3c774bdcc3d2f5cf5b6403c
parent 7ea43c580c00ba8c85fbdeb4fa4ec340282724f2

global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI*

The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and
CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many
cases they likely should come from the device tree instead. Move these
out of CONFIG namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

arch/arm/include/asm/arch-fsl-layerscape/cpu.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 4db4791..20f9671 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -35,17 +35,17 @@
 #define CONFIG_SYS_FSL_QBMAN_SIZE	0x8000000
 #define CONFIG_SYS_FSL_QBMAN_SIZE_1	0x4000000
 #ifdef CONFIG_ARCH_LS2080A
-#define CONFIG_SYS_PCIE1_PHYS_SIZE	0x200000000
-#define CONFIG_SYS_PCIE2_PHYS_SIZE	0x200000000
-#define CONFIG_SYS_PCIE3_PHYS_SIZE	0x200000000
-#define CONFIG_SYS_PCIE4_PHYS_SIZE	0x200000000
+#define CFG_SYS_PCIE1_PHYS_SIZE	0x200000000
+#define CFG_SYS_PCIE2_PHYS_SIZE	0x200000000
+#define CFG_SYS_PCIE3_PHYS_SIZE	0x200000000
+#define CFG_SYS_PCIE4_PHYS_SIZE	0x200000000
 #else
-#define CONFIG_SYS_PCIE1_PHYS_SIZE	0x800000000
-#define CONFIG_SYS_PCIE2_PHYS_SIZE	0x800000000
-#ifndef CONFIG_SYS_PCIE3_PHYS_SIZE
-#define CONFIG_SYS_PCIE3_PHYS_SIZE	0x800000000
+#define CFG_SYS_PCIE1_PHYS_SIZE	0x800000000
+#define CFG_SYS_PCIE2_PHYS_SIZE	0x800000000
+#ifndef CFG_SYS_PCIE3_PHYS_SIZE
+#define CFG_SYS_PCIE3_PHYS_SIZE	0x800000000
 #endif
-#define CONFIG_SYS_PCIE4_PHYS_SIZE	0x800000000
+#define CFG_SYS_PCIE4_PHYS_SIZE	0x800000000
 #define SYS_PCIE5_PHYS_SIZE		0x800000000
 #define SYS_PCIE6_PHYS_SIZE		0x800000000
 #endif
@@ -83,9 +83,9 @@
 #define CONFIG_SYS_FSL_QBMAN_SIZE	0x10000000
 #define CONFIG_SYS_FSL_DRAM_BASE2	0x880000000
 #define CONFIG_SYS_FSL_DRAM_SIZE2	0x780000000	/* 30GB */
-#define CONFIG_SYS_PCIE1_PHYS_SIZE	0x800000000
-#define CONFIG_SYS_PCIE2_PHYS_SIZE	0x800000000
-#define CONFIG_SYS_PCIE3_PHYS_SIZE	0x800000000
+#define CFG_SYS_PCIE1_PHYS_SIZE	0x800000000
+#define CFG_SYS_PCIE2_PHYS_SIZE	0x800000000
+#define CFG_SYS_PCIE3_PHYS_SIZE	0x800000000
 #define CONFIG_SYS_FSL_DRAM_BASE3	0x8800000000
 #define CONFIG_SYS_FSL_DRAM_SIZE3	0x7800000000	/* 480GB */
 #endif