dts/upstream/src/arm64/amlogic/amlogic-t7.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/amlogic,t7-pwrc.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <0x2>;
		#size-cells = <0x0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu100>;
				};
				core1 {
					cpu = <&cpu101>;
				};
				core2 {
					cpu = <&cpu102>;
				};
				core3 {
					cpu = <&cpu103>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};
		};

		cpu100: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x100>;
			enable-method = "psci";
		};

		cpu101: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x101>;
			enable-method = "psci";
		};

		cpu102: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x102>;
			enable-method = "psci";
		};

		cpu103: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x103>;
			enable-method = "psci";
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x0 0x0>;
			enable-method = "psci";
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x0 0x1>;
			enable-method = "psci";
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x0 0x2>;
			enable-method = "psci";
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x0 0x3>;
			enable-method = "psci";
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	sm: secure-monitor {
		compatible = "amlogic,meson-gxbb-sm";

		pwrc: power-controller {
			compatible = "amlogic,t7-pwrc";
			#power-domain-cells = <1>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gic: interrupt-controller@fff01000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x0 0xfff01000 0 0x1000>,
			      <0x0 0xfff02000 0 0x0100>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		apb4: bus@fe000000 {
			compatible = "simple-bus";
			reg = <0x0 0xfe000000 0x0 0x480000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;

			watchdog@2100 {
				compatible = "amlogic,t7-wdt";
				reg = <0x0 0x2100 0x0 0x10>;
				clocks = <&xtal>;
			};

			periphs_pinctrl: pinctrl@4000 {
				compatible = "amlogic,t7-periphs-pinctrl";
				#address-cells = <2>;
				#size-cells = <2>;
				ranges;

				gpio: bank@4000 {
					reg = <0x0 0x4000 0x0 0x0064>,
					      <0x0 0x40c0 0x0 0x0220>;
					reg-names = "mux", "gpio";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&periphs_pinctrl 0 0 157>;
				};
			};

			gpio_intc: interrupt-controller@4080 {
				compatible = "amlogic,t7-gpio-intc",
					     "amlogic,meson-gpio-intc";
				reg = <0x0 0x4080 0x0 0x20>;
				interrupt-controller;
				#interrupt-cells = <2>;
				amlogic,channel-interrupts =
					<10 11 12 13 14 15 16 17 18 19 20 21>;
			};

			uart_a: serial@78000 {
				compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart";
				reg = <0x0 0x78000 0x0 0x18>;
				interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};
		};

	};
};