clk: renesas: Implement R8A779H0 V4M PLL7 support
Add PLL7 support to Gen3/Gen4 common clock driver. Add initial PLL7
multiplier and divider values into table in R8A779H0 V4M clock driver.
The PLL7 is new PLL added in R8A779H0 V4M SoC. Only integer multiplication
mode is supported by PLL7. The PLL reference clock are either 16.66 MHz or
20 MHz on R8A779H0 V4M SoC, and the output frequency must be 2000 MHz. The
multiplier values fitting this requirement are calculated to 120 or 100.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index 196903e..b840242 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -306,6 +306,12 @@
gen4_pll_config->pll6_div,
"PLL6");
+ case CLK_TYPE_GEN4_PLL7:
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
+ 0, gen4_pll_config->pll7_mult,
+ gen4_pll_config->pll7_div,
+ "PLL7");
+
case CLK_TYPE_FF:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
0, core->mult, core->div,