| commit | 1b07ef1090ad73a031d26a75351342b8c15cd6b9 | [log] [tgz] |
|---|---|---|
| author | York Sun <yorksun@freescale.com> | Tue Dec 02 11:18:09 2014 -0800 |
| committer | York Sun <yorksun@freescale.com> | Mon Dec 15 09:15:12 2014 -0800 |
| tree | 8102d1ed2cb0ef18f642c606d4ade71219c62f64 | |
| parent | 69f44b8262e30c466b83d6b514f50c1e140fbf47 [diff] |
driver/ddr/fsl: Fix MRC_CYC calculation for DDR3 For DDR controller version 4.7 or newer, MRC_CYC (mode register set cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD is max(12nCK, 15ns) according to JEDEC spec. DDR4 is not affected by this change. Signed-off-by: York Sun <yorksun@freescale.com>