tree 6649bffbc1673264e11cd66d362c74e53508a289
parent 8b4ee5f75cb9826f15cb82f67836c0001b320b39
author Rick Chen <rick@andestech.com> 1573710747 +0800
committer Andes <uboot@andestech.com> 1575937390 +0800

riscv: Fix clear bss loop in the start-up code

For RV64, it will use sd instruction to clear t0
register, and the increament will be 8 bytes. So
if the difference between__bss_strat and __bss_end
was not 8 bytes aligned, the clear bss loop will
overflow and acks like system hang.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>