net: mscc: servalt: Add ethernet nodes for ServalT

Add ethernet nodes for ServalT SoCs family. Currently there is only one
pcb(pcb116) in this family.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
diff --git a/arch/mips/dts/mscc,servalt.dtsi b/arch/mips/dts/mscc,servalt.dtsi
index 4beb7a3..45ae2de 100644
--- a/arch/mips/dts/mscc,servalt.dtsi
+++ b/arch/mips/dts/mscc,servalt.dtsi
@@ -145,5 +145,45 @@
 			#gpio-cells = <2>;
 			gpio-ranges = <&sgpio 0 0 128>;
 		};
+
+		switch: switch@1010000 {
+			compatible = "mscc,vsc7437-switch";
+			reg = <0x01030000 0x0100>,   // VTSS_TO_DEV_0
+			      <0x01040000 0x0100>,   // VTSS_TO_DEV_1
+			      <0x01f00000 0x100000>, // ANA_AC
+			      <0x01d00000 0x100000>, // ANA_CL
+			      <0x01e00000 0x100000>, // ANA_L2
+			      <0x01120000 0x10000>,  // ASM
+			      <0x01130000 0x00000>,  // LRN
+			      <0x017d0000 0x10000>,  // QFWD
+			      <0x01020000 0x20000>,  // QS
+			      <0x017e0000 0x10000>,  // QSYS
+			      <0x01b00000 0x80000>;  // REW
+			reg-names = "port0", "port1",
+				    "ana_ac", "ana_cl", "ana_l2", "asm", "lrn",
+				    "qfwd", "qs", "qsys", "rew";
+			status = "okay";
+
+			ethernet-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		mdio0: mdio@010100c4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "mscc,jr2-miim";
+			reg = <0x010100c4 0x24>;
+			status = "disabled";
+		};
+
+		mdio1: mdio@010100e8 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "mscc,jr2-miim";
+			reg = <0x010100e8 0x24>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/arch/mips/dts/servalt_pcb116.dts b/arch/mips/dts/servalt_pcb116.dts
index fb33312..9d49215 100644
--- a/arch/mips/dts/servalt_pcb116.dts
+++ b/arch/mips/dts/servalt_pcb116.dts
@@ -54,3 +54,28 @@
 	status = "okay";
 	sgpio-ports = <0x0000fe7f>;
 };
+
+&mdio0 {
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+	};
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
+&switch {
+	ethernet-ports {
+
+		port0: port@0 {
+			reg = <0>;
+			phy-handle = <&phy0>;
+		};
+		port1: port@1 {
+			reg = <1>;
+			phy-handle = <&phy1>;
+		};
+	};
+};