Merge git://git.denx.de/u-boot-sh
- Enable -ffunction-sections / -fdata-sections --gc-sections to SH
- RCar Gen3 updates
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 480ef4c..12ec6c7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -374,16 +374,27 @@
ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
ls1021a-iot-duart.dtb ls1021a-tsn.dtb
dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
+ fsl-ls2080a-qds-42-x.dtb \
fsl-ls2080a-rdb.dtb \
fsl-ls2081a-rdb.dtb \
fsl-ls2088a-rdb-qspi.dtb \
fsl-ls1088a-rdb.dtb \
fsl-ls1088a-qds.dtb \
+ fsl-ls1088a-qds-21-x.dtb \
+ fsl-ls1088a-qds-29-x.dtb \
fsl-ls1028a-rdb.dtb \
fsl-ls1028a-qds-duart.dtb \
fsl-ls1028a-qds-lpuart.dtb \
fsl-lx2160a-rdb.dtb \
- fsl-lx2160a-qds.dtb
+ fsl-lx2160a-qds.dtb \
+ fsl-lx2160a-qds-3-x-x.dtb \
+ fsl-lx2160a-qds-3-11-x.dtb \
+ fsl-lx2160a-qds-7-x-x.dtb \
+ fsl-lx2160a-qds-7-11-x.dtb \
+ fsl-lx2160a-qds-19-x-x.dtb \
+ fsl-lx2160a-qds-19-11-x.dtb \
+ fsl-lx2160a-qds-20-x-x.dtb \
+ fsl-lx2160a-qds-20-11-x.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
diff --git a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
index fecef88..6402cf5 100644
--- a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
+++ b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
@@ -21,14 +21,13 @@
};
&qspi {
- bus-num = <0>;
status = "okay";
- qflash0: s25fl128s@0 {
+ s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
- spi-max-frequency = <20000000>;
+ spi-max-frequency = <50000000>;
reg = <0>;
};
};
diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dtsi b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
index a357793..88aa24a 100644
--- a/arch/arm/dts/fsl-ls1012a-frdm.dtsi
+++ b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
@@ -15,14 +15,13 @@
};
&qspi {
- bus-num = <0>;
status = "okay";
- qflash0: s25fl128s@0 {
+ s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
- spi-max-frequency = <20000000>;
+ spi-max-frequency = <50000000>;
reg = <0>;
};
};
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi
index a330597..910d2a5 100644
--- a/arch/arm/dts/fsl-ls1012a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi
@@ -43,14 +43,13 @@
};
&qspi {
- bus-num = <0>;
status = "okay";
- qflash0: s25fl128s@0 {
+ s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
- spi-max-frequency = <20000000>;
+ spi-max-frequency = <50000000>;
reg = <0>;
};
};
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
index 55155fd..3757051 100644
--- a/arch/arm/dts/fsl-ls1012a-rdb.dtsi
+++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
@@ -19,14 +19,13 @@
};
&qspi {
- bus-num = <0>;
status = "okay";
- qflash0: s25fl128s@0 {
+ s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
- spi-max-frequency = <20000000>;
+ spi-max-frequency = <50000000>;
reg = <0>;
};
};
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 1125e57..2d70c82 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -107,14 +107,12 @@
};
qspi: quadspi@1550000 {
- compatible = "fsl,vf610-qspi";
+ compatible = "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x1550000 0x0 0x10000>,
<0x0 0x40000000 0x0 0x4000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
- num-cs = <1>;
- big-endian;
status = "disabled";
};
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi b/arch/arm/dts/fsl-ls1043a-qds.dtsi
index 70e1a6a..884bdad 100644
--- a/arch/arm/dts/fsl-ls1043a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi
@@ -53,14 +53,13 @@
};
&qspi {
- bus-num = <0>;
status = "okay";
- qflash0: s25fl128s@0 {
+ s25fl128s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
- spi-max-frequency = <20000000>;
+ spi-max-frequency = <50000000>;
reg = <0>;
};
};
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 0a959f0..f7db44c 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -210,14 +210,12 @@
status = "disabled";
};
qspi: quadspi@1550000 {
- compatible = "fsl,vf610-qspi";
+ compatible = "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x1550000 0x0 0x10000>,
- <0x0 0x40000000 0x0 0x4000000>;
+ <0x0 0x40000000 0x0 0x1000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
- num-cs = <2>;
- big-endian;
status = "disabled";
};
diff --git a/arch/arm/dts/fsl-ls1046a-frwy.dts b/arch/arm/dts/fsl-ls1046a-frwy.dts
index d391593..cda0541 100644
--- a/arch/arm/dts/fsl-ls1046a-frwy.dts
+++ b/arch/arm/dts/fsl-ls1046a-frwy.dts
@@ -19,13 +19,12 @@
};
&qspi {
- bus-num = <0>;
status = "okay";
- qflash0: mt25qu512abb8esf@0 {
+ mt25qu512a0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "spi-flash";
+ compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
};
diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi
index 76dc397..fec5c8d 100644
--- a/arch/arm/dts/fsl-ls1046a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi
@@ -53,14 +53,13 @@
};
&qspi {
- bus-num = <0>;
status = "okay";
- qflash0: s25fl128s@0 {
+ s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
- spi-max-frequency = <20000000>;
+ spi-max-frequency = <50000000>;
reg = <0>;
};
};
diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
index cac65a7..4641292 100644
--- a/arch/arm/dts/fsl-ls1046a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -21,10 +21,9 @@
};
&qspi {
- bus-num = <0>;
status = "okay";
- qflash0: s25fs512s@0 {
+ s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -32,7 +31,7 @@
reg = <0>;
};
- qflash1: s25fs512s@1 {
+ s25fs512s1: flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 4e91d5c..8673a5d 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -211,14 +211,12 @@
};
qspi: quadspi@1550000 {
- compatible = "fsl,vf610-qspi";
+ compatible = "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x1550000 0x0 0x10000>,
<0x0 0x40000000 0x0 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
- num-cs = <4>;
- big-endian;
status = "disabled";
};
diff --git a/arch/arm/dts/fsl-ls1088a-qds-21-x.dts b/arch/arm/dts/fsl-ls1088a-qds-21-x.dts
new file mode 100644
index 0000000..a877964
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1088a-qds-21-x.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1088AQDS device tree source for SERDES protocol 21.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1088a-qds-sd1-21.dtsi"
+
+/ {
+ model = "NXP Layerscape 1088a QDS Board (DTS 21-x)";
+ compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
+};
diff --git a/arch/arm/dts/fsl-ls1088a-qds-29-x.dts b/arch/arm/dts/fsl-ls1088a-qds-29-x.dts
new file mode 100644
index 0000000..29c4ec5
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1088a-qds-29-x.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1088AQDS device tree source for SERDES protocol 29.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1088a-qds-sd1-29.dtsi"
+
+/ {
+ model = "NXP Layerscape 1088a QDS Board (DTS 29-x)";
+ compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
+};
diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi
new file mode 100644
index 0000000..e0a6c04
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1088AQDS device tree source for SERDES block #1 - protocol 21 (0x15)
+ *
+ * Copyright 2020 NXP
+ */
+
+#include "fsl-ls1088a-qds.dtsi"
+
+&dpmac1 {
+ status = "okay";
+ phy-connection-type = "xfi";
+};
+
+&dpmac2 {
+ status = "okay";
+ phy-connection-type = "xfi";
+};
+
+&dpmac4 {
+ status = "okay";
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+};
+
+&dpmac5 {
+ status = "okay";
+ phy-handle = <&rgmii_phy2>;
+ phy-connection-type = "rgmii-id";
+};
diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi
new file mode 100644
index 0000000..65e95300
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1088AQDS device tree source for SERDES block #1 - protocol 29 (0x1d)
+ *
+ * Copyright 2020 NXP
+ */
+
+#include "fsl-ls1088a-qds.dtsi"
+
+&dpmac1 {
+ status = "okay";
+ phy-connection-type = "xfi";
+};
+
+&dpmac2 {
+ status = "okay";
+ phy-connection-type = "xfi";
+};
diff --git a/arch/arm/dts/fsl-ls1088a-qds.dts b/arch/arm/dts/fsl-ls1088a-qds.dts
index f07d0c6..8e64e71 100644
--- a/arch/arm/dts/fsl-ls1088a-qds.dts
+++ b/arch/arm/dts/fsl-ls1088a-qds.dts
@@ -1,133 +1,15 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * NXP ls1088a QDS board device tree source
+ * NXP ls1088a QDS default board device tree source
*
- * Copyright 2017 NXP
+ * Copyright 2020 NXP
*/
/dts-v1/;
-#include "fsl-ls1088a.dtsi"
+#include "fsl-ls1088a-qds.dtsi"
/ {
model = "NXP Layerscape 1088a QDS Board";
compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
- aliases {
- spi0 = &qspi;
- spi1 = &dspi;
- };
-};
-
-&i2c0 {
- status = "okay";
- u-boot,dm-pre-reloc;
-
- i2c-mux@77 {
- compatible = "nxp,pca9547";
- reg = <0x77>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x3>;
-
- rtc@51 {
- compatible = "pcf2127-rtc";
- reg = <0x51>;
- };
- };
- };
-};
-
-&ifc {
- #address-cells = <2>;
- #size-cells = <1>;
- /* NOR, NAND Flashes and FPGA on board */
- ranges = <0 0 0x5 0x80000000 0x08000000
- 2 0 0x5 0x30000000 0x00010000
- 3 0 0x5 0x20000000 0x00010000>;
- status = "okay";
-
- nor@0,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "cfi-flash";
- reg = <0x0 0x0 0x8000000>;
- bank-width = <2>;
- device-width = <1>;
- };
-
- nand@2,0 {
- compatible = "fsl,ifc-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x1 0x0 0x10000>;
- };
-
- fpga: board-control@3,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus", "fsl,ls1088aqds-fpga",
- "fsl,fpga-qixis";
- reg = <0x2 0x0 0x0000100>;
- bank-width = <1>;
- device-width = <1>;
- ranges = <0 2 0 0x100>;
- };
-};
-
-&dspi {
- bus-num = <0>;
- status = "okay";
-
- dflash0: n25q128a {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <1000000>; /* input clock */
- };
-
- dflash1: sst25wf040b {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <3500000>;
- reg = <1>;
- };
-
- dflash2: en25s64 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <3500000>;
- reg = <2>;
- };
-};
-
-&qspi {
- bus-num = <0>;
- status = "okay";
-
- qflash0: s25fs512s@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <0>;
- };
-
- qflash1: s25fs512s@1 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <1>;
- };
-};
-
-&sata {
- status = "okay";
};
diff --git a/arch/arm/dts/fsl-ls1088a-qds.dtsi b/arch/arm/dts/fsl-ls1088a-qds.dtsi
new file mode 100644
index 0000000..a7d0edc
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1088a-qds.dtsi
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP ls1088a QDS common board device tree source
+ *
+ * Copyright 2017-2020 NXP
+ */
+
+#include "fsl-ls1088a.dtsi"
+
+/ {
+ aliases {
+ spi0 = &qspi;
+ spi1 = &dspi;
+ };
+};
+
+&emdio1 {
+ status = "okay";
+};
+
+&emdio2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ fpga@66 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "simple-mfd";
+ reg = <0x66>;
+
+ mux-mdio@54 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mdio-mux-i2creg";
+ reg = <0x54>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x54 0xe0>; // reg 0x54, bits 7:5
+ mdio-parent-bus = <&emdio1>;
+
+ mdio@00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x00>;
+
+ rgmii_phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ };
+ mdio@20 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x20>;
+
+ rgmii_phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+ };
+
+ emdio1_slot1: mdio@40 { /* I/O Slot #1 */
+ reg = <0x40>;
+ device-name = "emdio1_slot1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emdio1_slot3: mdio@60 { /* I/O Slot #3 */
+ reg = <0x60>;
+ device-name = "emdio1_slot3";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
+ i2c-mux@77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ rtc@51 {
+ compatible = "pcf2127-rtc";
+ reg = <0x51>;
+ };
+ };
+ };
+};
+
+&ifc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* NOR, NAND Flashes and FPGA on board */
+ ranges = <0 0 0x5 0x80000000 0x08000000
+ 2 0 0x5 0x30000000 0x00010000
+ 3 0 0x5 0x20000000 0x00010000>;
+ status = "okay";
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand@2,0 {
+ compatible = "fsl,ifc-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x1 0x0 0x10000>;
+ };
+
+ fpga: board-control@3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus", "fsl,ls1088aqds-fpga",
+ "fsl,fpga-qixis";
+ reg = <0x2 0x0 0x0000100>;
+ bank-width = <1>;
+ device-width = <1>;
+ ranges = <0 2 0 0x100>;
+ };
+};
+
+&dspi {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash0: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <1000000>; /* input clock */
+ };
+
+ dflash1: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <3500000>;
+ reg = <1>;
+ };
+
+ dflash2: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <3500000>;
+ reg = <2>;
+ };
+};
+
+&qspi {
+ status = "okay";
+
+ s25fs512s0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+
+ s25fs512s1: flash@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <1>;
+ };
+};
+
+&sata {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1088a-rdb.dts b/arch/arm/dts/fsl-ls1088a-rdb.dts
index 46a5780..de92bf2 100644
--- a/arch/arm/dts/fsl-ls1088a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1088a-rdb.dts
@@ -143,10 +143,9 @@
};
&qspi {
- bus-num = <0>;
status = "okay";
- qflash0: s25fs512s@0 {
+ s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -154,7 +153,7 @@
reg = <0>;
};
- qflash1: s25fs512s@1 {
+ s25fs512s1: flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index 133cacb..bf303c6 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -92,7 +92,7 @@
};
qspi: quadspi@1550000 {
- compatible = "fsl,vf610-qspi";
+ compatible = "fsl,ls1088a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c0000 0x0 0x10000>,
diff --git a/arch/arm/dts/fsl-ls2080a-qds-42-x.dts b/arch/arm/dts/fsl-ls2080a-qds-42-x.dts
new file mode 100644
index 0000000..bd46c39
--- /dev/null
+++ b/arch/arm/dts/fsl-ls2080a-qds-42-x.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS2080AQDS device tree source for SERDES protocol 42.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-ls2080a-qds-sd1-42.dtsi"
+
+/ {
+ model = "NXP Layerscape LS2080AQDS Board (DTS 42-x)";
+ compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
+};
diff --git a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi
new file mode 100644
index 0000000..ccbb5de
--- /dev/null
+++ b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS2080aQDS device tree source for SERDES block #1 - protocol 42 (0x2a)
+ *
+ * Copyright 2020 NXP
+ */
+
+#include "fsl-ls2080a-qds.dtsi"
+
+&dpmac1 {
+ status = "okay";
+ phy-connection-type = "xfi";
+};
+
+&dpmac2 {
+ status = "okay";
+ phy-connection-type = "xfi";
+};
+
+&dpmac3 {
+ status = "okay";
+ phy-connection-type = "xfi";
+};
+
+&dpmac4 {
+ status = "okay";
+ phy-connection-type = "xfi";
+};
+
+&dpmac5 {
+ status = "okay";
+ phy-connection-type = "xfi";
+};
+
+&dpmac6 {
+ status = "okay";
+ phy-connection-type = "xfi";
+};
+
+&dpmac7 {
+ status = "okay";
+ phy-connection-type = "xfi";
+};
+
+&dpmac8 {
+ status = "okay";
+ phy-connection-type = "xfi";
+};
diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts
index 13461b5..a1196f9 100644
--- a/arch/arm/dts/fsl-ls2080a-qds.dts
+++ b/arch/arm/dts/fsl-ls2080a-qds.dts
@@ -1,13 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Freescale ls2080a QDS board device tree source
+ * Freescale ls2080a QDS defaul board device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*/
/dts-v1/;
-#include "fsl-ls2080a.dtsi"
+#include "fsl-ls2080a-qds.dtsi"
/ {
model = "Freescale Layerscape 2080a QDS Board";
@@ -18,72 +18,3 @@
spi1 = &dspi;
};
};
-
-&i2c0 {
- status = "okay";
- pca9547@77 {
- compatible = "nxp,pca9547";
- reg = <0x77>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x00>;
- rtc@68 {
- compatible = "dallas,ds3232";
- reg = <0x68>;
- };
- };
- };
-};
-
-&dspi {
- bus-num = <0>;
- status = "okay";
-
- dflash0: n25q128a {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <3000000>;
- spi-cpol;
- spi-cpha;
- reg = <0>;
- };
- dflash1: sst25wf040b {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <3000000>;
- spi-cpol;
- spi-cpha;
- reg = <1>;
- };
- dflash2: en25s64 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <3000000>;
- spi-cpol;
- spi-cpha;
- reg = <2>;
- };
-};
-
-&qspi {
- bus-num = <0>;
- status = "okay";
-
- qflash0: s25fs256s@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <20000000>;
- reg = <0>;
- };
-};
-
-&sata {
- status = "okay";
-};
diff --git a/arch/arm/dts/fsl-ls2080a-qds.dtsi b/arch/arm/dts/fsl-ls2080a-qds.dtsi
new file mode 100644
index 0000000..cb7851f
--- /dev/null
+++ b/arch/arm/dts/fsl-ls2080a-qds.dtsi
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Freescale ls2080a QDS common device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
+ */
+
+#include "fsl-ls2080a.dtsi"
+
+&i2c0 {
+ status = "okay";
+ pca9547@77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x00>;
+ rtc@68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+ };
+ };
+ };
+};
+
+&dspi {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash0: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+ dflash1: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ };
+ dflash2: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ };
+};
+
+&qspi {
+ status = "okay";
+
+ s25fs256s0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+};
+
+&sata {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index fb5777e..90a0a3f 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -96,13 +96,13 @@
};
qspi: quadspi@1550000 {
- compatible = "fsl,vf610-qspi";
+ compatible = "fsl,ls2080a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c0000 0x0 0x10000>,
<0x0 0x20000000 0x0 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
- num-cs = <4>;
+ status = "disabled";
};
esdhc: esdhc@0 {
diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
index 16b9aee..179ed19 100644
--- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
+++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
@@ -125,10 +125,9 @@
};
&qspi {
- bus-num = <0>;
status = "okay";
- qflash0: s25fs512s@0 {
+ s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -136,7 +135,7 @@
reg = <0>;
};
- qflash1: s25fs512s@1 {
+ s25fs512s1: flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
diff --git a/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts b/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts
new file mode 100644
index 0000000..5857591
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for SERDES protocol 19.11.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a-qds-sd1-19.dtsi"
+
+#include "fsl-lx2160a-qds-sd2-11.dtsi"
+
+/ {
+ model = "NXP Layerscape LX2160AQDS Board (DTS 19.11.x)";
+ compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+
+};
diff --git a/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts b/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts
new file mode 100644
index 0000000..ebe1139
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for SERDES protocol 19.x.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a-qds-sd1-19.dtsi"
+
+/ {
+ model = "NXP Layerscape LX2160AQDS Board (DTS 19.x.x)";
+ compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+
+};
diff --git a/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts b/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts
new file mode 100644
index 0000000..d9f0918
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for SERDES protocol 20.11.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a-qds-sd1-20.dtsi"
+
+#include "fsl-lx2160a-qds-sd2-11.dtsi"
+
+/ {
+ model = "NXP Layerscape LX2160AQDS Board (DTS 20.11.x)";
+ compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+
+};
diff --git a/arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts b/arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts
new file mode 100644
index 0000000..735d440
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for SERDES protocol 20.x.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a-qds-sd1-20.dtsi"
+
+/ {
+ model = "NXP Layerscape LX2160AQDS Board (DTS 20.x.x)";
+ compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+
+};
diff --git a/arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts b/arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts
new file mode 100644
index 0000000..3b21c87
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for SERDES protocol 3.11.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a-qds-sd1-3.dtsi"
+
+#include "fsl-lx2160a-qds-sd2-11.dtsi"
+
+/ {
+ model = "NXP Layerscape LX2160AQDS Board (DTS 3.11.x)";
+ compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+
+};
diff --git a/arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts b/arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts
new file mode 100644
index 0000000..ede4056
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for SERDES protocol 3.x.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a-qds-sd1-3.dtsi"
+
+/ {
+ model = "NXP Layerscape LX2160AQDS Board (DTS 3.x.x)";
+ compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+
+};
diff --git a/arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts b/arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts
new file mode 100644
index 0000000..8100af4
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for SERDES protocol 7.11.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a-qds-sd1-7.dtsi"
+
+#include "fsl-lx2160a-qds-sd2-11.dtsi"
+
+/ {
+ model = "NXP Layerscape LX2160AQDS Board (DTS 7.11.x)";
+ compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+
+};
diff --git a/arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts b/arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts
new file mode 100644
index 0000000..15dee35
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for SERDES protocol 7.x.x
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a-qds-sd1-7.dtsi"
+
+/ {
+ model = "NXP Layerscape LX2160AQDS Board (DTS 7-x-x)";
+ compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+
+};
diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi
new file mode 100644
index 0000000..a31ff8a
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 19
+ *
+ * Some assumptions are made:
+ * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4)
+ * * mezzanine card M13 is connected to IO SLOT6 (25g-aui for DPMAC 5,6)
+ * * mezzanine card M7 is connected to IO SLOT2 (xlaui4 for DPMAC 2)
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+#include "fsl-lx2160a-qds.dtsi"
+
+&dpmac2 {
+ status = "okay";
+ phy-handle = <&cortina_phy0>;
+ phy-connection-type = "xlaui4";
+};
+
+&dpmac3 {
+ status = "okay";
+ phy-handle = <&aquantia_phy1>;
+ phy-connection-type = "usxgmii";
+};
+
+&dpmac4 {
+ status = "okay";
+ phy-handle = <&aquantia_phy2>;
+ phy-connection-type = "usxgmii";
+};
+
+&dpmac5 {
+ status = "okay";
+ phy-handle = <&inphi_phy0>;
+ phy-connection-type = "25g-aui";
+};
+
+&dpmac6 {
+ status = "okay";
+ phy-handle = <&inphi_phy1>;
+ phy-connection-type = "25g-aui";
+};
+
+&emdio1_slot1 {
+ aquantia_phy1: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+ };
+
+ aquantia_phy2: ethernet-phy@5 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x1>;
+ };
+};
+
+&emdio1_slot2 {
+ cortina_phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+ };
+};
+
+&emdio1_slot6 {
+ inphi_phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0210.7440";
+ reg = <0x0>;
+ };
+
+ inphi_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0210.7440";
+ reg = <0x1>;
+ };
+};
diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi
new file mode 100644
index 0000000..42e1496
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 20
+ *
+ * Some assumptions are made:
+ * * 2 mezzanine cards M13 are connected to IO SLOT1 and IO SLOT2
+ * (xlaui4 for DPMAC 1,2)
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+#include "fsl-lx2160a-qds.dtsi"
+
+&dpmac1 {
+ status = "okay";
+ phy-handle = <&cortina_phy1_0>;
+ phy-connection-type = "xlaui4";
+};
+
+&dpmac2 {
+ status = "okay";
+ phy-handle = <&cortina_phy2_0>;
+ phy-connection-type = "xlaui4";
+};
+
+&emdio1_slot1 {
+ cortina_phy1_0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+ };
+};
+
+&emdio1_slot2 {
+ cortina_phy2_0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+ };
+};
diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi
new file mode 100644
index 0000000..256d784
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 3
+ *
+ * Some assumptions are made:
+ * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4,5,6)
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+#include "fsl-lx2160a-qds.dtsi"
+
+&dpmac3 {
+ status = "okay";
+ phy-handle = <&aquantia_phy1>;
+ phy-connection-type = "usxgmii";
+};
+
+&dpmac4 {
+ status = "okay";
+ phy-handle = <&aquantia_phy2>;
+ phy-connection-type = "usxgmii";
+};
+
+&dpmac5 {
+ status = "okay";
+ phy-handle = <&aquantia_phy3>;
+ phy-connection-type = "usxgmii";
+};
+
+&dpmac6 {
+ status = "okay";
+ phy-handle = <&aquantia_phy4>;
+ phy-connection-type = "usxgmii";
+};
+
+&emdio1_slot1 {
+ aquantia_phy1: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+ };
+ aquantia_phy2: ethernet-phy@5 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x1>;
+ };
+ aquantia_phy3: ethernet-phy@6 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x2>;
+ };
+ aquantia_phy4: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x3>;
+ };
+};
diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi
new file mode 100644
index 0000000..5fcf846
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 7
+ *
+ * Some assumptions are made:
+ * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4,5,6)
+ * * mezzanine card M1/M4 is connected to IO SLOT2 (sgmii for DPMAC 7,8,9,10)
+ *
+ * Copyright 2020 NXP
+ *
+ */
+#include "fsl-lx2160a-qds.dtsi"
+
+&dpmac3 {
+ status = "okay";
+ phy-handle = <&aquantia_phy1>;
+ phy-connection-type = "usxgmii";
+};
+
+&dpmac4 {
+ status = "okay";
+ phy-handle = <&aquantia_phy2>;
+ phy-connection-type = "usxgmii";
+};
+
+&dpmac5 {
+ status = "okay";
+ phy-handle = <&aquantia_phy3>;
+ phy-connection-type = "usxgmii";
+};
+
+&dpmac6 {
+ status = "okay";
+ phy-handle = <&aquantia_phy4>;
+ phy-connection-type = "usxgmii";
+};
+
+&dpmac7 {
+ status = "okay";
+ phy-handle = <&sgmii_phy1>;
+ phy-connection-type = "sgmii";
+};
+
+&dpmac8 {
+ status = "okay";
+ phy-handle = <&sgmii_phy2>;
+ phy-connection-type = "sgmii";
+};
+
+&dpmac9 {
+ status = "okay";
+ phy-handle = <&sgmii_phy3>;
+ phy-connection-type = "sgmii";
+};
+
+&dpmac10 {
+ status = "okay";
+ phy-handle = <&sgmii_phy4>;
+ phy-connection-type = "sgmii";
+};
+
+&emdio1_slot1 {
+ aquantia_phy1: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+ };
+
+ aquantia_phy2: ethernet-phy@5 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x1>;
+ };
+
+ aquantia_phy3: ethernet-phy@6 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x2>;
+ };
+
+ aquantia_phy4: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x3>;
+ };
+};
+
+&emdio1_slot2 {
+ sgmii_phy1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+
+ sgmii_phy2: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+
+ sgmii_phy3: ethernet-phy@1e {
+ reg = <0x1e>;
+ };
+
+ sgmii_phy4: ethernet-phy@1f {
+ reg = <0x1f>;
+ };
+};
diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi
new file mode 100644
index 0000000..cf09f98
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for the SERDES block #2 - protocol 11
+ *
+ * Some assumptions are made:
+ * * 2 mezzanine cards M1/M4 are connected to IO SLOT 7 and IO SLOT 8
+ * (sgmii for DPMAC 12, 13, 14, 16, 17, 18)
+ *
+ * Copyright 2020 NXP
+ *
+ */
+#include "fsl-lx2160a-qds.dtsi"
+
+&dpmac12 {
+ status = "okay";
+ phy-handle = <&sgmii_phy7_2>;
+ phy-connection-type = "sgmii";
+};
+
+&dpmac17 {
+ status = "okay";
+ phy-handle = <&sgmii_phy7_3>;
+ phy-connection-type = "sgmii";
+};
+
+&dpmac18 {
+ status = "okay";
+ phy-handle = <&sgmii_phy7_4>;
+ phy-connection-type = "sgmii";
+};
+
+&dpmac16 {
+ status = "okay";
+ phy-handle = <&sgmii_phy8_2>;
+ phy-connection-type = "sgmii";
+};
+
+&dpmac13 {
+ status = "okay";
+ phy-handle = <&sgmii_phy8_3>;
+ phy-connection-type = "sgmii";
+};
+
+&dpmac14 {
+ status = "okay";
+ phy-handle = <&sgmii_phy8_4>;
+ phy-connection-type = "sgmii";
+};
+
+&emdio1_slot7 {
+ sgmii_phy7_2: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+
+ sgmii_phy7_3: ethernet-phy@1e {
+ reg = <0x1e>;
+ };
+
+ sgmii_phy7_4: ethernet-phy@1f {
+ reg = <0x1f>;
+ };
+};
+
+&emdio1_slot8 {
+ sgmii_phy8_2: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+
+ sgmii_phy8_3: ethernet-phy@1e {
+ reg = <0x1e>;
+ };
+
+ sgmii_phy8_4: ethernet-phy@1f {
+ reg = <0x1f>;
+ };
+};
diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts
index 592fd59..e0f5d5e 100644
--- a/arch/arm/dts/fsl-lx2160a-qds.dts
+++ b/arch/arm/dts/fsl-lx2160a-qds.dts
@@ -1,14 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * NXP LX2160AQDS device tree source
+ * NXP LX2160AQDS default device tree source
*
- * Copyright 2018-2019 NXP
+ * Copyright 2020 NXP
*
*/
/dts-v1/;
-#include "fsl-lx2160a.dtsi"
+#include "fsl-lx2160a-qds.dtsi"
/ {
model = "NXP Layerscape LX2160AQDS Board";
@@ -17,64 +17,3 @@
spi0 = &fspi;
};
};
-
-&esdhc0 {
- status = "okay";
-};
-
-&esdhc1 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
- u-boot,dm-pre-reloc;
-
- i2c-mux@77 {
- compatible = "nxp,pca9547";
- reg = <0x77>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x3>;
-
- rtc@51 {
- compatible = "pcf2127-rtc";
- reg = <0x51>;
- };
- };
- };
-};
-
-&fspi {
- status = "okay";
-
- mt35xu512aba0: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <0>;
- spi-rx-bus-width = <8>;
- spi-tx-bus-width = <1>;
- };
-};
-
-&sata0 {
- status = "okay";
-};
-
-&sata1 {
- status = "okay";
-};
-
-&sata2 {
- status = "okay";
-};
-
-&sata3 {
- status = "okay";
-};
diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi b/arch/arm/dts/fsl-lx2160a-qds.dtsi
new file mode 100644
index 0000000..129cf82
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS common device tree source
+ *
+ * Copyright 2018-2019 NXP
+ *
+ */
+
+#include "fsl-lx2160a.dtsi"
+
+&dpmac17 {
+ status = "okay";
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+};
+
+&dpmac18 {
+ status = "okay";
+ phy-handle = <&rgmii_phy2>;
+ phy-connection-type = "rgmii-id";
+};
+
+&emdio1 {
+ status = "okay";
+};
+
+&emdio2 {
+ status = "okay";
+};
+
+&esdhc0 {
+ status = "okay";
+};
+
+&esdhc1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ fpga@66 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "simple-mfd";
+ reg = <0x66>;
+
+ mux-mdio@54 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mdio-mux-i2creg";
+ reg = <0x54>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3
+ mdio-parent-bus = <&emdio1>;
+
+ mdio@00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x00>;
+
+ rgmii_phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ };
+ mdio@08 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x40>;
+
+ rgmii_phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+ };
+
+ emdio1_slot1: mdio@c0 { /* I/O Slot #1 */
+ reg = <0xC0>;
+ device-name = "emdio1_slot1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emdio1_slot2: mdio@c8 { /* I/O Slot #2 */
+ reg = <0xC8>;
+ device-name = "emdio1_slot2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emdio1_slot3: mdio@d0 { /* I/O Slot #3 */
+ reg = <0xD0>;
+ device-name = "emdio1_slot3";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emdio1_slot4: mdio@d8 { /* I/O Slot #4 */
+ reg = <0xD8>;
+ device-name = "emdio1_slot4";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emdio1_slot5: mdio@e0 { /* I/O Slot #5 */
+ reg = <0xE0>;
+ device-name = "emdio1_slot5";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emdio1_slot6: mdio@e8 { /* I/O Slot #6 */
+ reg = <0xE8>;
+ device-name = "emdio1_slot6";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emdio1_slot7: mdio@f0 { /* I/O Slot #7 */
+ reg = <0xF0>;
+ device-name = "emdio1_slot7";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emdio1_slot8: mdio@f8 { /* I/O Slot #8 */
+ reg = <0xF8>;
+ device-name = "emdio1_slot8";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ };
+
+ i2c-mux@77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ rtc@51 {
+ compatible = "pcf2127-rtc";
+ reg = <0x51>;
+ };
+ };
+ };
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 73d04db..1789da8 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -2,7 +2,7 @@
/*
* NXP lx2160a SOC common device tree source
*
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
*
*/
@@ -383,6 +383,18 @@
#address-cells = <1>;
#size-cells = <0>;
+ dpmac1: dpmac@1 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x1>;
+ status = "disabled";
+ };
+
+ dpmac2: dpmac@2 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x2>;
+ status = "disabled";
+ };
+
dpmac3: dpmac@3 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x3>;
@@ -395,6 +407,78 @@
status = "disabled";
};
+ dpmac5: dpmac@5 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x5>;
+ status = "disabled";
+ };
+
+ dpmac6: dpmac@6 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x6>;
+ status = "disabled";
+ };
+
+ dpmac7: dpmac@7 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x7>;
+ status = "disabled";
+ };
+
+ dpmac8: dpmac@8 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x8>;
+ status = "disabled";
+ };
+
+ dpmac9: dpmac@9 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x9>;
+ status = "disabled";
+ };
+
+ dpmac10: dpmac@a {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xa>;
+ status = "disabled";
+ };
+
+ dpmac11: dpmac@b {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xb>;
+ status = "disabled";
+ };
+
+ dpmac12: dpmac@c {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xc>;
+ status = "disabled";
+ };
+
+ dpmac13: dpmac@d {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xd>;
+ status = "disabled";
+ };
+
+ dpmac14: dpmac@e {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xe>;
+ status = "disabled";
+ };
+
+ dpmac15: dpmac@f {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xf>;
+ status = "disabled";
+ };
+
+ dpmac16: dpmac@10 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x10>;
+ status = "disabled";
+ };
+
dpmac17: dpmac@11 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x11>;
diff --git a/arch/arm/dts/ls1021a-twr.dtsi b/arch/arm/dts/ls1021a-twr.dtsi
index 27c96f9..bf96af7 100644
--- a/arch/arm/dts/ls1021a-twr.dtsi
+++ b/arch/arm/dts/ls1021a-twr.dtsi
@@ -24,14 +24,13 @@
};
&qspi {
- bus-num = <0>;
status = "okay";
- qflash0: n25q128a13@0 {
+ n25q128a130: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
- spi-max-frequency = <20000000>;
+ spi-max-frequency = <50000000>;
reg = <0>;
};
};
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index e419d9c..0eeec43 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -169,14 +169,12 @@
};
qspi: quadspi@1550000 {
- compatible = "fsl,vf610-qspi";
+ compatible = "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1550000 0x10000>,
- <0x40000000 0x4000000>;
+ <0x40000000 0x1000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
- num-cs = <2>;
- big-endian;
status = "disabled";
};
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 908d860..e13f4d8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -310,7 +310,6 @@
#define CONFIG_SYS_FSL_ESDHC_BE
#define CONFIG_SYS_FSL_WDOG_BE
#define CONFIG_SYS_FSL_DSPI_BE
-#define CONFIG_SYS_FSL_QSPI_BE
#define CONFIG_SYS_FSL_CCSR_GUR_BE
#define CONFIG_SYS_FSL_PEX_LUT_BE
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 9705378..3884948 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -94,7 +94,6 @@
#define CONFIG_SYS_FSL_ESDHC_BE
#define CONFIG_SYS_FSL_WDOG_BE
#define CONFIG_SYS_FSL_DSPI_BE
-#define CONFIG_SYS_FSL_QSPI_BE
#define CONFIG_SYS_FSL_DCU_BE
#define CONFIG_SYS_FSL_SEC_MON_LE
#define CONFIG_SYS_FSL_SFP_VER_3_2
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 5d76502..18808da 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -106,10 +106,6 @@
bool "Support kmcoge5ne"
select VENDOR_KM
-config TARGET_SUVD3
- bool "Support suvd3"
- select VENDOR_KM
-
config TARGET_KMTEGR1
bool "Support kmtegr1"
select VENDOR_KM
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index cefbcf6..49c75a0 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -127,16 +127,10 @@
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
ulong msr;
-#ifndef MPC83xx_RESET
- ulong addr;
-#endif
-
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
puts("Resetting the board.\n");
-#ifdef MPC83xx_RESET
-
/* Interrupts and MMU off */
msr = mfmsr();
msr &= ~(MSR_EE | MSR_IR | MSR_DR);
@@ -156,24 +150,6 @@
/* perform reset, only one bit */
immap->reset.rcr = RCR_SWHR;
-#else /* ! MPC83xx_RESET */
-
- immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
-
- /* Interrupts and MMU off */
- msr = mfmsr();
- msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
- mtmsr(msr);
-
- /*
- * Trying to execute the next instruction at a non-existing address
- * should cause a machine check, resulting in reset
- */
- addr = CONFIG_SYS_RESET_ADDRESS;
-
- ((void (*)(void)) addr) ();
-#endif /* MPC83xx_RESET */
-
return 1;
}
#endif
diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c
index 8371c1c..e5d9d94 100644
--- a/board/freescale/ls1088a/eth_ls1088aqds.c
+++ b/board/freescale/ls1088a/eth_ls1088aqds.c
@@ -26,6 +26,7 @@
#include "ls1088a_qixis.h"
+#ifndef CONFIG_DM_ETH
#ifdef CONFIG_FSL_MC_ENET
#define SFP_TX 0
@@ -737,6 +738,7 @@
error = pci_eth_init(bis);
return error;
}
+#endif // !CONFIG_DM_ETH
#if defined(CONFIG_RESET_PHY_R)
void reset_phy(void)
@@ -744,3 +746,90 @@
mc_env_boot();
}
#endif /* CONFIG_RESET_PHY_R */
+
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
+
+/* Structure to hold SERDES protocols supported in case of
+ * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
+ *
+ * @serdes_block: the index of the SERDES block
+ * @serdes_protocol: the decimal value of the protocol supported
+ * @dts_needed: DTS notes describing the current configuration are needed
+ *
+ * When dts_needed is true, the board_fit_config_name_match() function
+ * will try to exactly match the current configuration of the block with a DTS
+ * name provided.
+ */
+static struct serdes_configuration {
+ u8 serdes_block;
+ u32 serdes_protocol;
+ bool dts_needed;
+} supported_protocols[] = {
+ /* Serdes block #1 */
+ {1, 21, true},
+ {1, 29, true},
+};
+
+#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
+
+static bool protocol_supported(u8 serdes_block, u32 protocol)
+{
+ struct serdes_configuration serdes_conf;
+ int i;
+
+ for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+ serdes_conf = supported_protocols[i];
+ if (serdes_conf.serdes_block == serdes_block &&
+ serdes_conf.serdes_protocol == protocol)
+ return true;
+ }
+
+ return false;
+}
+
+static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
+{
+ struct serdes_configuration serdes_conf;
+ int i;
+
+ for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+ serdes_conf = supported_protocols[i];
+ if (serdes_conf.serdes_block == serdes_block &&
+ serdes_conf.serdes_protocol == protocol) {
+ if (serdes_conf.dts_needed == true)
+ sprintf(str, "%u", protocol);
+ else
+ sprintf(str, "x");
+ return;
+ }
+ }
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ char expected_dts[100];
+ char srds_s1_str[2];
+ u32 srds_s1, cfg;
+
+ cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
+ FSL_CHASSIS3_SRDS1_PRTCL_MASK;
+ cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
+ srds_s1 = serdes_get_number(FSL_SRDS_1, cfg);
+
+ /* Check for supported protocols. The default DTS will be used
+ * in this case
+ */
+ if (!protocol_supported(1, srds_s1))
+ return -1;
+
+ get_str_protocol(1, srds_s1, srds_s1_str);
+
+ sprintf(expected_dts, "fsl-ls1088a-qds-%s-x", srds_s1_str);
+
+ if (!strcmp(name, expected_dts))
+ return 0;
+
+ return -1;
+}
+#endif
diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index 81b5b9e..9171cb2 100644
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -26,6 +26,8 @@
#define MC_BOOT_ENV_VAR "mcinitcmd"
+#ifndef CONFIG_DM_ETH
+
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
/* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
* Bank 1 -> Lanes A, B, C, D, E, F, G, H
@@ -891,10 +893,11 @@
}
}
#endif
+#endif // !CONFIG_DM_ETH
int board_eth_init(bd_t *bis)
{
- int error;
+#ifndef CONFIG_DM_ETH
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
@@ -908,6 +911,7 @@
struct memac_mdio_info *memac_mdio1_info;
unsigned int i;
char *env_hwconfig;
+ int error;
env_hwconfig = env_get("hwconfig");
@@ -972,8 +976,13 @@
sgmii_configure_repeater(2);
}
#endif
+#endif // !CONFIG_DM_ETH
+
+#ifdef CONFIG_DM_ETH
+ return 0;
+#else
+ return pci_eth_init(bis);
+#endif
- error = pci_eth_init(bis);
- return error;
}
#if defined(CONFIG_RESET_PHY_R)
@@ -982,3 +991,100 @@
mc_env_boot();
}
#endif /* CONFIG_RESET_PHY_R */
+
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
+
+/* Structure to hold SERDES protocols supported in case of
+ * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
+ *
+ * @serdes_block: the index of the SERDES block
+ * @serdes_protocol: the decimal value of the protocol supported
+ * @dts_needed: DTS notes describing the current configuration are needed
+ *
+ * When dts_needed is true, the board_fit_config_name_match() function
+ * will try to exactly match the current configuration of the block with a DTS
+ * name provided.
+ */
+static struct serdes_configuration {
+ u8 serdes_block;
+ u32 serdes_protocol;
+ bool dts_needed;
+} supported_protocols[] = {
+ /* Serdes block #1 */
+ {1, 42, true},
+
+ /* Serdes block #2 */
+ {2, 65, false},
+};
+
+#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
+
+static bool protocol_supported(u8 serdes_block, u32 protocol)
+{
+ struct serdes_configuration serdes_conf;
+ int i;
+
+ for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+ serdes_conf = supported_protocols[i];
+ if (serdes_conf.serdes_block == serdes_block &&
+ serdes_conf.serdes_protocol == protocol)
+ return true;
+ }
+
+ return false;
+}
+
+static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
+{
+ struct serdes_configuration serdes_conf;
+ int i;
+
+ for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+ serdes_conf = supported_protocols[i];
+ if (serdes_conf.serdes_block == serdes_block &&
+ serdes_conf.serdes_protocol == protocol) {
+ if (serdes_conf.dts_needed == true)
+ sprintf(str, "%u", protocol);
+ else
+ sprintf(str, "x");
+ return;
+ }
+ }
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 rcw_status = in_le32(&gur->rcwsr[28]);
+ char srds_s1_str[2], srds_s2_str[2];
+ u32 srds_s1, srds_s2;
+ char expected_dts[100];
+
+ srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+ srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+ srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+ /* Check for supported protocols. The default DTS will be used
+ * in this case
+ */
+ if (!protocol_supported(1, srds_s1) ||
+ !protocol_supported(2, srds_s2))
+ return -1;
+
+ get_str_protocol(1, srds_s1, srds_s1_str);
+ get_str_protocol(2, srds_s2, srds_s2_str);
+
+ printf("expected_dts %s\n", expected_dts);
+ sprintf(expected_dts, "fsl-ls2080a-qds-%s-%s",
+ srds_s1_str, srds_s2_str);
+
+ if (!strcmp(name, expected_dts))
+ return 0;
+
+ printf("this is not!\n");
+ return -1;
+}
+
+#endif
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 5f95f3c..b9754f9 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -252,6 +252,10 @@
ppa_init();
#endif
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+ pci_init();
+#endif
+
return 0;
}
diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c b/board/freescale/lx2160a/eth_lx2160aqds.c
index 8240eaa..7794495 100644
--- a/board/freescale/lx2160a/eth_lx2160aqds.c
+++ b/board/freescale/lx2160a/eth_lx2160aqds.c
@@ -28,6 +28,7 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_DM_ETH
#define EMI_NONE 0
#define EMI1 1 /* Mdio Bus 1 */
#define EMI2 2 /* Mdio Bus 2 */
@@ -442,9 +443,11 @@
}
#endif
+#endif /* !CONFIG_DM_ETH */
int board_eth_init(bd_t *bis)
{
+#ifndef CONFIG_DM_ETH
#if defined(CONFIG_FSL_MC_ENET)
struct memac_mdio_info mdio_info;
struct memac_mdio_controller *regs;
@@ -567,6 +570,7 @@
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
+#endif /* !CONFIG_DM_ETH */
#ifdef CONFIG_PHY_AQUANTIA
/*
@@ -580,7 +584,12 @@
gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
#endif
+
+#ifdef CONFIG_DM_ETH
+ return 0;
+#else
return pci_eth_init(bis);
+#endif
}
#if defined(CONFIG_RESET_PHY_R)
@@ -592,6 +601,7 @@
}
#endif /* CONFIG_RESET_PHY_R */
+#ifndef CONFIG_DM_ETH
#if defined(CONFIG_FSL_MC_ENET)
int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
{
@@ -840,4 +850,113 @@
return ret;
}
#endif // CONFIG_FSL_MC_ENET
+#endif
+
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
+
+/* Structure to hold SERDES protocols supported in case of
+ * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
+ *
+ * @serdes_block: the index of the SERDES block
+ * @serdes_protocol: the decimal value of the protocol supported
+ * @dts_needed: DTS notes describing the current configuration are needed
+ *
+ * When dts_needed is true, the board_fit_config_name_match() function
+ * will try to exactly match the current configuration of the block with a DTS
+ * name provided.
+ */
+static struct serdes_configuration {
+ u8 serdes_block;
+ u32 serdes_protocol;
+ bool dts_needed;
+} supported_protocols[] = {
+ /* Serdes block #1 */
+ {1, 3, true},
+ {1, 7, true},
+ {1, 19, true},
+ {1, 20, true},
+
+ /* Serdes block #2 */
+ {2, 2, false},
+ {2, 3, false},
+ {2, 5, false},
+ {2, 11, true},
+
+ /* Serdes block #3 */
+ {3, 2, false},
+ {3, 3, false},
+};
+
+#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
+
+static bool protocol_supported(u8 serdes_block, u32 protocol)
+{
+ struct serdes_configuration serdes_conf;
+ int i;
+
+ for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+ serdes_conf = supported_protocols[i];
+ if (serdes_conf.serdes_block == serdes_block &&
+ serdes_conf.serdes_protocol == protocol)
+ return true;
+ }
+
+ return false;
+}
+static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
+{
+ struct serdes_configuration serdes_conf;
+ int i;
+
+ for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
+ serdes_conf = supported_protocols[i];
+ if (serdes_conf.serdes_block == serdes_block &&
+ serdes_conf.serdes_protocol == protocol) {
+ if (serdes_conf.dts_needed == true)
+ sprintf(str, "%u", protocol);
+ else
+ sprintf(str, "x");
+ return;
+ }
+ }
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 rcw_status = in_le32(&gur->rcwsr[28]);
+ char srds_s1_str[2], srds_s2_str[2], srds_s3_str[2];
+ u32 srds_s1, srds_s2, srds_s3;
+ char expected_dts[100];
+
+ srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+ srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+ srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+ srds_s3 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
+ srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
+
+ /* Check for supported protocols. The default DTS will be used
+ * in this case
+ */
+ if (!protocol_supported(1, srds_s1) ||
+ !protocol_supported(2, srds_s2) ||
+ !protocol_supported(3, srds_s3))
+ return -1;
+
+ get_str_protocol(1, srds_s1, srds_s1_str);
+ get_str_protocol(2, srds_s2, srds_s2_str);
+ get_str_protocol(3, srds_s3, srds_s3_str);
+
+ sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s-%s",
+ srds_s1_str, srds_s2_str, srds_s3_str);
+
+ if (!strcmp(name, expected_dts))
+ return 0;
+
+ return -1;
+}
+#endif
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 88eb66b..73e05ee 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -586,6 +586,9 @@
sec_init();
#endif
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
+ pci_init();
+#endif
return 0;
}
@@ -631,7 +634,9 @@
if (get_mc_boot_status() == 0 &&
(is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
fdt_status_okay(fdt, offset);
+#ifndef CONFIG_DM_ETH
fdt_fixup_board_phy(fdt);
+#endif
} else {
fdt_status_fail(fdt, offset);
}
diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig
index 1011cc8..94075ce 100644
--- a/board/keymile/km83xx/Kconfig
+++ b/board/keymile/km83xx/Kconfig
@@ -57,25 +57,6 @@
endif
-if TARGET_SUVD3
-
-config SYS_BOARD
- default "km83xx"
-
-config SYS_VENDOR
- default "keymile"
-
-config SYS_CONFIG_NAME
- default "suvd3"
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select ARCH_MPC832X
- imply CMD_CRAMFS
- imply FS_CRAMFS
-
-endif
-
if TARGET_TUXX1
config SYS_BOARD
diff --git a/board/keymile/km83xx/MAINTAINERS b/board/keymile/km83xx/MAINTAINERS
index d2af983..177c2c4 100644
--- a/board/keymile/km83xx/MAINTAINERS
+++ b/board/keymile/km83xx/MAINTAINERS
@@ -8,9 +8,7 @@
F: include/configs/tuxx1.h
F: configs/kmopti2_defconfig
F: configs/kmtepr2_defconfig
-F: include/configs/suvd3.h
F: configs/kmtegr1_defconfig
-F: configs/suvd3_defconfig
F: configs/tuge1_defconfig
F: configs/tuxx1_defconfig
diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index 29514d8..75c558a 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -100,27 +100,6 @@
{0, 0, 0, 0, QE_IOP_TAB_END},
};
-#if defined(CONFIG_SUVD3)
-const uint upma_table[] = {
- 0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */
- 0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */
- 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */
- 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */
- 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */
- 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */
- 0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */
- 0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
- 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */
- 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */
- 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */
- 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */
- 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */
- 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */
- 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */
- 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */
-};
-#endif
-
static int piggy_present(void)
{
struct km_bec_fpga __iomem *base =
@@ -138,11 +117,6 @@
{
struct km_bec_fpga *base =
(struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
-#if defined(CONFIG_SUVD3)
- immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- fsl_lbc_t *lbc = &immap->im_lbc;
- u32 *mxmr = &lbc->mamr;
-#endif
#if defined(CONFIG_ARCH_MPC8360)
unsigned short svid;
@@ -178,12 +152,6 @@
/* enable Application Buffer */
setbits_8(&base->oprtl, OPRTL_XBUFENA);
-#if defined(CONFIG_SUVD3)
- /* configure UPMA for APP1 */
- upmconfig(UPMA, (uint *) upma_table,
- sizeof(upma_table) / sizeof(uint));
- out_be32(mxmr, CONFIG_SYS_MAMR);
-#endif
return 0;
}
diff --git a/cmd/avb.c b/cmd/avb.c
index 398ad3b..88172a9 100644
--- a/cmd/avb.c
+++ b/cmd/avb.c
@@ -316,6 +316,9 @@
printf("Unknown error occurred\n");
}
+ if (out_data)
+ avb_slot_verify_data_free(out_data);
+
return res;
}
diff --git a/common/board_r.c b/common/board_r.c
index bce87cb..fa57fa9 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -373,11 +373,19 @@
}
#if defined(CONFIG_MTD_NOR_FLASH)
+__weak int is_flash_available(void)
+{
+ return 1;
+}
+
static int initr_flash(void)
{
ulong flash_size = 0;
bd_t *bd = gd->bd;
+ if (!is_flash_available())
+ return 0;
+
puts("Flash: ");
if (board_flash_wp_on())
diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig
index 18b72b4..07ba4d6 100644
--- a/configs/ls1012a2g5rdb_qspi_defconfig
+++ b/configs/ls1012a2g5rdb_qspi_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012A2G5RDB=y
CONFIG_SYS_TEXT_BASE=0x40100000
-CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
@@ -44,6 +44,7 @@
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig
index 4ca57d1..8999d01 100644
--- a/configs/ls1012a2g5rdb_tfa_defconfig
+++ b/configs/ls1012a2g5rdb_tfa_defconfig
@@ -2,7 +2,7 @@
CONFIG_TARGET_LS1012A2G5RDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
@@ -44,6 +44,7 @@
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
index 1a4cc37..541cbb0 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRDM=y
CONFIG_SYS_TEXT_BASE=0x40100000
-CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
@@ -41,6 +41,7 @@
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig
index 177fcd4..b5043d7 100644
--- a/configs/ls1012afrdm_tfa_defconfig
+++ b/configs/ls1012afrdm_tfa_defconfig
@@ -2,7 +2,7 @@
CONFIG_TARGET_LS1012AFRDM=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
@@ -41,6 +41,7 @@
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
index a702cc8..f105aaf 100644
--- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRWY=y
CONFIG_SYS_TEXT_BASE=0x40100000
-CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_DM_GPIO=y
CONFIG_FSL_LS_PPA=y
diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig
index 187015c..4922764 100644
--- a/configs/ls1012afrwy_qspi_defconfig
+++ b/configs/ls1012afrwy_qspi_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRWY=y
CONFIG_SYS_TEXT_BASE=0x40100000
-CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x1D0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
@@ -35,6 +35,7 @@
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x401D0000
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
index 5071bb7..9c89064 100644
--- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
@@ -2,7 +2,7 @@
CONFIG_TARGET_LS1012AFRWY=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_DM_GPIO=y
CONFIG_NR_DRAM_BANKS=2
diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig
index c5ed91a..2948fd5 100644
--- a/configs/ls1012afrwy_tfa_defconfig
+++ b/configs/ls1012afrwy_tfa_defconfig
@@ -2,7 +2,7 @@
CONFIG_TARGET_LS1012AFRWY=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x1D0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
@@ -34,7 +34,7 @@
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x401D0000
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index 1c3d7bc..65e8e5c 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012AQDS=y
CONFIG_SYS_TEXT_BASE=0x40100000
-CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
@@ -60,6 +60,7 @@
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
index 0833a2a..529cd08 100644
--- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
@@ -2,7 +2,7 @@
CONFIG_TARGET_LS1012AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_DM_GPIO=y
CONFIG_QSPI_AHB_INIT=y
@@ -49,6 +49,7 @@
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig
index 7fc9e15..79d196c 100644
--- a/configs/ls1012aqds_tfa_defconfig
+++ b/configs/ls1012aqds_tfa_defconfig
@@ -2,7 +2,7 @@
CONFIG_TARGET_LS1012AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
@@ -60,6 +60,7 @@
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
index b6110c0..1483e64 100644
--- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012ARDB=y
CONFIG_SYS_TEXT_BASE=0x40100000
-CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_DM_GPIO=y
CONFIG_FSL_LS_PPA=y
@@ -44,6 +44,7 @@
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_E1000=y
CONFIG_PCI=y
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
index 9c2a308..e39de4c 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012ARDB=y
CONFIG_SYS_TEXT_BASE=0x40100000
-CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
@@ -46,6 +46,7 @@
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
index 736810d..8b67798 100644
--- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
@@ -2,7 +2,7 @@
CONFIG_TARGET_LS1012ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_DM_GPIO=y
CONFIG_QSPI_AHB_INIT=y
@@ -43,6 +43,7 @@
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig
index fc3dc4a..e0d203d 100644
--- a/configs/ls1012ardb_tfa_defconfig
+++ b/configs/ls1012ardb_tfa_defconfig
@@ -2,7 +2,7 @@
CONFIG_TARGET_LS1012ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
@@ -35,7 +35,6 @@
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x40500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
@@ -46,6 +45,7 @@
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index 9ea003e..a018b22 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -44,6 +44,7 @@
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index c5887cc..a7252ac 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -58,6 +58,7 @@
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
index f10d4d9..3ee5d28 100644
--- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
@@ -48,6 +48,7 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
@@ -62,6 +63,7 @@
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig
index 4fcdca8..297788b 100644
--- a/configs/ls1043aqds_tfa_defconfig
+++ b/configs/ls1043aqds_tfa_defconfig
@@ -58,6 +58,7 @@
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig
index 48dc7ac..68271c3 100644
--- a/configs/ls1046afrwy_tfa_defconfig
+++ b/configs/ls1046afrwy_tfa_defconfig
@@ -32,6 +32,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x40500000
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig
index b98101d..00b3568 100644
--- a/configs/ls1046aqds_qspi_defconfig
+++ b/configs/ls1046aqds_qspi_defconfig
@@ -34,6 +34,7 @@
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_ADDR=0x40300000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
@@ -42,6 +43,7 @@
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig
index 616e420..a66b1bd 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -58,6 +58,7 @@
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
index 03cd17f..2b84a6b 100644
--- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
@@ -47,6 +47,7 @@
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig
index d50a8eb..e412c05 100644
--- a/configs/ls1046aqds_tfa_defconfig
+++ b/configs/ls1046aqds_tfa_defconfig
@@ -4,7 +4,7 @@
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
-CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
@@ -42,7 +42,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=0
-CONFIG_ENV_ADDR=0x60500000
+CONFIG_ENV_ADDR=0x40500000
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
@@ -57,6 +57,7 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_SF_DEFAULT_BUS=1
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
index 1f89222..f29e86b 100644
--- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
@@ -37,6 +37,7 @@
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig
index 8b1b695..5197868 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -30,6 +30,7 @@
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_ADDR=0x40300000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
@@ -40,6 +41,7 @@
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
index 140da79..7db5174 100644
--- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
@@ -37,6 +37,7 @@
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig
index eab34cd..06bedd6 100644
--- a/configs/ls1046ardb_tfa_defconfig
+++ b/configs/ls1046ardb_tfa_defconfig
@@ -33,6 +33,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x40500000
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
@@ -42,6 +43,7 @@
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig
index e66a61c..c184843 100644
--- a/configs/ls1088aqds_tfa_defconfig
+++ b/configs/ls1088aqds_tfa_defconfig
@@ -27,6 +27,7 @@
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
+CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@@ -35,11 +36,13 @@
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
+CONFIG_OF_LIST="fsl-ls1088a-qds-21-x fsl-ls1088a-qds-29-x"
+CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x80500000
+CONFIG_ENV_ADDR=0x20500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
@@ -66,8 +69,13 @@
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
CONFIG_E1000=y
CONFIG_MII=y
+CONFIG_MDIO_MUX_I2CREG=y
+CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig
index 1c36801..53b236c 100644
--- a/configs/ls1088ardb_tfa_defconfig
+++ b/configs/ls1088ardb_tfa_defconfig
@@ -39,7 +39,7 @@
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x80500000
+CONFIG_ENV_ADDR=0x20500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig
index 7c7bb34..ad17ef1 100644
--- a/configs/ls2088aqds_tfa_defconfig
+++ b/configs/ls2088aqds_tfa_defconfig
@@ -22,6 +22,7 @@
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -34,10 +35,13 @@
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_OF_LIST="fsl-ls2080a-qds-42-x"
+CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x80500000
+CONFIG_ENV_ADDR=0x20500000
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
@@ -61,9 +65,14 @@
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
+CONFIG_MDIO_MUX_I2CREG=y
+CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig
index d312cc9..f2eb8d7 100644
--- a/configs/ls2088ardb_qspi_defconfig
+++ b/configs/ls2088ardb_qspi_defconfig
@@ -32,6 +32,7 @@
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_ADDR=0x20300000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig
index 2a82fda..b64e3dc 100644
--- a/configs/ls2088ardb_tfa_defconfig
+++ b/configs/ls2088ardb_tfa_defconfig
@@ -39,7 +39,8 @@
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0x80500000
+CONFIG_ENV_ADDR=0x20500000
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
index cd7b413..51d5dc3 100644
--- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
@@ -21,6 +21,7 @@
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -31,6 +32,8 @@
CONFIG_OF_CONTROL=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
+CONFIG_OF_LIST="fsl-lx2160a-qds-3-x-x fsl-lx2160a-qds-7-x-x fsl-lx2160a-qds-19-x-x fsl-lx2160a-qds-20-x-x fsl-lx2160a-qds-3-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-19-11-x fsl-lx2160a-qds-20-11-x"
+CONFIG_MULTI_DTB_FIT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
@@ -53,7 +56,12 @@
CONFIG_PHY_CORTINA=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
CONFIG_E1000=y
+CONFIG_MDIO_MUX_I2CREG=y
+CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
index 9b6ce38..716c089 100644
--- a/configs/lx2160aqds_tfa_defconfig
+++ b/configs/lx2160aqds_tfa_defconfig
@@ -23,6 +23,7 @@
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@@ -33,6 +34,8 @@
CONFIG_OF_CONTROL=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
+CONFIG_OF_LIST="fsl-lx2160a-qds-3-x-x fsl-lx2160a-qds-7-x-x fsl-lx2160a-qds-19-x-x fsl-lx2160a-qds-20-x-x fsl-lx2160a-qds-3-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-19-11-x fsl-lx2160a-qds-20-11-x"
+CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x20500000
@@ -57,7 +60,12 @@
CONFIG_PHY_CORTINA=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
CONFIG_E1000=y
+CONFIG_MDIO_MUX_I2CREG=y
+CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig
deleted file mode 100644
index 9908ca0..0000000
--- a/configs/suvd3_defconfig
+++ /dev/null
@@ -1,184 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xF0000000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_SUVD3=y
-CONFIG_CORE_PLL_RATIO_25_1=y
-CONFIG_QUICC_MULT_FACTOR_3=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_INHIBITED=y
-CONFIG_BAT0_ICACHE_GUARDED=y
-CONFIG_BAT0_DCACHE_INHIBITED=y
-CONFIG_BAT0_DCACHE_GUARDED=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="IMMR"
-CONFIG_BAT1_BASE=0xE0000000
-CONFIG_BAT1_LENGTH_4_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
-CONFIG_BAT1_DCACHE_INHIBITED=y
-CONFIG_BAT1_DCACHE_GUARDED=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="KMBEC_FPGA"
-CONFIG_BAT2_BASE=0xE8000000
-CONFIG_BAT2_LENGTH_128_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="FLASH"
-CONFIG_BAT3_BASE=0xF0000000
-CONFIG_BAT3_LENGTH_256_MBYTES=y
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_DCACHE_INHIBITED=y
-CONFIG_BAT3_DCACHE_GUARDED=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT4=y
-CONFIG_BAT4_NAME="STACK_IN_DCACHE"
-CONFIG_BAT4_BASE=0xE6000000
-CONFIG_BAT4_ACCESS_RW=y
-CONFIG_BAT4_USER_MODE_VALID=y
-CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="APP1"
-CONFIG_BAT5_BASE=0xA0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="APP2"
-CONFIG_BAT6_BASE=0xB0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_INHIBITED=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xF0000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_256_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xE8000000
-CONFIG_LBLAW1_NAME="KMBEC_FPGA"
-CONFIG_LBLAW1_LENGTH_128_MBYTES=y
-CONFIG_LBLAW2=y
-CONFIG_LBLAW2_BASE=0xA0000000
-CONFIG_LBLAW2_NAME="APP1"
-CONFIG_LBLAW2_LENGTH_256_MBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xB0000000
-CONFIG_LBLAW3_NAME="APP2"
-CONFIG_LBLAW3_LENGTH_256_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF0000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_256_MBYTES=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
-CONFIG_BR1_OR1_BASE=0xE8000000
-CONFIG_OR1_AM_128_MBYTES=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="APP1"
-CONFIG_BR2_OR2_BASE=0xA0000000
-CONFIG_BR2_PORTSIZE_16BIT=y
-CONFIG_BR2_MACHINE_UPMA=y
-CONFIG_OR2_AM_256_MBYTES=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="APP2"
-CONFIG_BR3_OR3_BASE=0xB0000000
-CONFIG_BR3_PORTSIZE_16BIT=y
-CONFIG_OR3_AM_256_MBYTES=y
-CONFIG_OR3_SCY_3=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_ACR_APARK_MASTER=y
-CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_2=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SUVD3"
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_LAST_STAGE_INIT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=boot"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
-CONFIG_CMD_UBI=y
-# CONFIG_CMD_UBIFS is not set
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xF00C0000
-CONFIG_ENV_ADDR_REDUND=0xF00E0000
-CONFIG_DM=y
-CONFIG_BOOTCOUNT_LIMIT=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-# CONFIG_PCI is not set
-CONFIG_QE=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/drivers/crypto/rsa_mod_exp/mod_exp_sw.c b/drivers/crypto/rsa_mod_exp/mod_exp_sw.c
index 03b3d61..4ce85b3 100644
--- a/drivers/crypto/rsa_mod_exp/mod_exp_sw.c
+++ b/drivers/crypto/rsa_mod_exp/mod_exp_sw.c
@@ -32,6 +32,7 @@
.name = "mod_exp_sw",
.id = UCLASS_MOD_EXP,
.ops = &mod_exp_ops_sw,
+ .flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DEVICE(mod_exp_sw) = {
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 81a4cf2..62396d3 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -57,10 +57,10 @@
bus.priv = priv->mac->phyregs;
#else
bus.priv = priv->pcs_mdio;
-#endif
bus.read = memac_mdio_read;
bus.write = memac_mdio_write;
bus.reset = memac_mdio_reset;
+#endif
qsgmii_loop:
/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 1c03427..e516c3c 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2018, 2020 NXP
*/
#include <common.h>
#include <command.h>
@@ -320,7 +320,7 @@
void fdt_fsl_mc_fixup_iommu_map_entry(void *blob)
{
u32 *prop;
- u32 iommu_map[4];
+ u32 iommu_map[4], phandle;
int offset;
int lenp;
@@ -349,6 +349,21 @@
fdt_setprop_inplace(blob, offset, "iommu-map",
iommu_map, sizeof(iommu_map));
+
+ /* get phandle to MSI controller */
+ prop = (u32 *)fdt_getprop(blob, offset, "msi-parent", 0);
+ if (!prop) {
+ debug("\n%s: ERROR: missing msi-parent\n", __func__);
+ return;
+ }
+ phandle = fdt32_to_cpu(*prop);
+
+ /* also set msi-map property */
+ fdt_appendprop_u32(blob, offset, "msi-map", FSL_DPAA2_STREAM_ID_START);
+ fdt_appendprop_u32(blob, offset, "msi-map", phandle);
+ fdt_appendprop_u32(blob, offset, "msi-map", FSL_DPAA2_STREAM_ID_START);
+ fdt_appendprop_u32(blob, offset, "msi-map", FSL_DPAA2_STREAM_ID_END -
+ FSL_DPAA2_STREAM_ID_START + 1);
}
static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id,
@@ -466,8 +481,19 @@
/* fixup MAC addresses for dpmac ports */
nodeoffset = fdt_path_offset(blob, "/board_info/ports");
- if (nodeoffset < 0)
- goto out;
+ if (nodeoffset < 0) {
+ err = fdt_increase_size(blob, 512);
+ if (err) {
+ printf("fdt_increase_size: err=%s\n",
+ fdt_strerror(err));
+ goto out;
+ }
+ nodeoffset = fdt_path_offset(blob, "/board_info");
+ if (nodeoffset < 0)
+ nodeoffset = fdt_add_subnode(blob, 0, "board_info");
+
+ nodeoffset = fdt_add_subnode(blob, nodeoffset, "ports");
+ }
err = mc_fixup_mac_addrs(blob, MC_FIXUP_DPC);
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index e9baa2a..3bea9a9 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -34,26 +34,11 @@
#define CONFIG_LAYERSCAPE_NS_ACCESS
/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
/*SPI device */
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_TFABOOT)
#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_FSL_SPI_INTERFACE
-#define CONFIG_SF_DATAFLASH
-
-#define QSPI0_AMBA_BASE 0x40000000
-#define CONFIG_SPI_FLASH_SPANSION
-
-#define FSL_QSPI_FLASH_SIZE SZ_64M
-#define FSL_QSPI_FLASH_NUM 2
-
-/*
- * Environment
- */
-#define CONFIG_ENV_OVERWRITE
-#endif
+#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
/* SATA */
#define CONFIG_SCSI_AHCI_PLAT
diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h
index 97d3eb2..1ea6548 100644
--- a/include/configs/ls1012afrwy.h
+++ b/include/configs/ls1012afrwy.h
@@ -34,9 +34,6 @@
func(DHCP, dhcp, na)
#endif
-#undef FSL_QSPI_FLASH_SIZE
-#define FSL_QSPI_FLASH_SIZE SZ_16M
-
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index c9d116d..8fb7565 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -15,9 +15,6 @@
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
#define CONFIG_CMD_MEMINFO
-
-/* ENV */
-#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
/*
* I2C IO expander
*/
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
index 912345b..3eff1be 100644
--- a/include/configs/ls1021aiot.h
+++ b/include/configs/ls1021aiot.h
@@ -138,12 +138,6 @@
/* SPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SPI_FLASH_SPANSION
-
-/* QSPI */
-#define QSPI0_AMBA_BASE 0x40000000
-#define FSL_QSPI_FLASH_SIZE (1 << 24)
-#define FSL_QSPI_FLASH_NUM 2
-#define CONFIG_SPI_FLASH_SPANSION
#endif
/* DM SPI */
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 031bc6f..e069467 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -363,20 +363,9 @@
* MMC
*/
-/* SPI */
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-/* QSPI */
-#define QSPI0_AMBA_BASE 0x40000000
-#define FSL_QSPI_FLASH_SIZE (1 << 24)
-#define FSL_QSPI_FLASH_NUM 2
-
-/* DSPI */
-
/* DM SPI */
#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
#define CONFIG_DM_SPI_FLASH
-#define CONFIG_SPI_FLASH_DATAFLASH
-#endif
#endif
/*
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index cb56037..53a10ba 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -234,16 +234,6 @@
* MMC
*/
-/* SPI */
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-/* QSPI */
-#define QSPI0_AMBA_BASE 0x40000000
-#define FSL_QSPI_FLASH_SIZE (1 << 24)
-#define FSL_QSPI_FLASH_NUM 2
-
-/* DSPI */
-#endif
-
/* DM SPI */
#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
#define CONFIG_DM_SPI_FLASH
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 95bf5fa..46baeb0 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -376,16 +376,6 @@
#define VDD_MV_MIN 819
#define VDD_MV_MAX 1212
-/* QSPI device */
-#if defined(CONFIG_TFABOOT) || \
- (defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI))
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
-#define FSL_QSPI_FLASH_SIZE (1 << 24)
-#define FSL_QSPI_FLASH_NUM 2
-#endif
-#endif
-
/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h
index 4ccd3b0..44e7fc3 100644
--- a/include/configs/ls1046afrwy.h
+++ b/include/configs/ls1046afrwy.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
*/
#ifndef __LS1046AFRWY_H__
@@ -96,12 +96,17 @@
/*
* Environment
*/
-#define CONFIG_ENV_OVERWRITE
-
#define CONFIG_SYS_MMC_ENV_DEV 0
-
#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
+#ifndef CONFIG_SPL_BUILD
+#undef BOOT_TARGET_DEVICES
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0) \
+ func(DHCP, dhcp, na)
+#endif
+
/* FMan */
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
@@ -115,12 +120,6 @@
#define CONFIG_ETHPRIME "FM1@DTSEC3"
-#endif
-
-/* QSPI device */
-#ifdef CONFIG_FSL_QSPI
-#define FSL_QSPI_FLASH_SIZE SZ_64M
-#define FSL_QSPI_FLASH_NUM 1
#endif
#undef CONFIG_BOOTCOMMAND
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index ff0d5fa..969d2c5 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -41,16 +41,6 @@
#define CONFIG_SPI_FLASH_EON /* cs2 */
#endif
-/* QSPI */
-#if defined(CONFIG_TFABOOT) || \
- defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
-#define FSL_QSPI_FLASH_SIZE (1 << 24)
-#define FSL_QSPI_FLASH_NUM 2
-#endif
-#endif
-
#ifdef CONFIG_SYS_DPAA_FMAN
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2
@@ -419,16 +409,7 @@
/*
* Environment
*/
-#define CONFIG_ENV_OVERWRITE
-
-#ifdef CONFIG_TFABOOT
#define CONFIG_SYS_MMC_ENV_DEV 0
-#else
-#ifdef CONFIG_NAND_BOOT
-#elif defined(CONFIG_SD_BOOT)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-#endif
#define CONFIG_CMDLINE_TAG
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 1093761..fe8108d 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -153,19 +153,8 @@
/*
* Environment
*/
-#ifndef SPL_NO_ENV
-#define CONFIG_ENV_OVERWRITE
-#endif
-
-#ifdef CONFIG_TFABOOT
#define CONFIG_SYS_MMC_ENV_DEV 0
-
#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
-#else
-#if defined(CONFIG_SD_BOOT)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-#endif
#define AQR105_IRQ_MASK 0x80000000
/* FMan */
@@ -184,15 +173,6 @@
#define CONFIG_ETHPRIME "FM1@DTSEC3"
#endif
-#endif
-
-/* QSPI device */
-#ifndef SPL_NO_QSPI
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
-#define FSL_QSPI_FLASH_SIZE (1 << 26)
-#define FSL_QSPI_FLASH_NUM 2
-#endif
#endif
#ifndef SPL_NO_MISC
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index ab5b396..a737342 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -35,13 +35,7 @@
#endif
/* Link Definitions */
-#ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
-#else
-#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
-#endif
-#endif
#define CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index 3bfd1d2..2bc910a 100644
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h
@@ -358,14 +358,6 @@
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-/* QSPI device */
-#if defined(CONFIG_TFABOOT) || \
- defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define FSL_QSPI_FLASH_SIZE (1 << 26)
-#define FSL_QSPI_FLASH_NUM 2
-
-#endif
-
#ifdef CONFIG_FSL_DSPI
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_SST
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index dec1ff9..4752073 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -8,16 +8,7 @@
#include "ls1088a_common.h"
-#ifdef CONFIG_TFABOOT
#define CONFIG_SYS_MMC_ENV_DEV 0
-#else
-#if defined(CONFIG_QSPI_BOOT)
-#elif defined(CONFIG_SD_BOOT)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#endif
-#endif /* CONFIG_TFABOOT */
#if defined(CONFIG_TFABOOT) || \
defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
@@ -268,15 +259,6 @@
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#ifndef SPL_NO_QSPI
-/* QSPI device */
-#if defined(CONFIG_TFABOOT) || \
- defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define FSL_QSPI_FLASH_SIZE (1 << 26)
-#define FSL_QSPI_FLASH_NUM 2
-#endif
-#endif
-
#define CONFIG_CMD_MEMINFO
#ifdef CONFIG_SPL_BUILD
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 8ab892b..751325a 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -276,7 +276,6 @@
#define I2C_MUX_CH_DEFAULT 0x8
/* SPI */
-#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
#ifdef CONFIG_FSL_DSPI
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_SST
@@ -285,8 +284,6 @@
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION
-#define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */
-#define FSL_QSPI_FLASH_NUM 4
#endif
/*
* Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
@@ -295,8 +292,6 @@
*/
#define FSL_QIXIS_BRDCFG9_QSPI 0x1
-#endif
-
/*
* MMC
*/
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index c1819d2..006a4c9 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -273,13 +273,9 @@
#define I2C_MUX_CH_DEFAULT 0x8
/* SPI */
-#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
-#ifdef CONFIG_FSL_DSPI
+#if defined(CONFIG_FSL_DSPI)
#define CONFIG_SPI_FLASH_STMICRO
#endif
-#define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */
-#define FSL_QSPI_FLASH_NUM 2
-#endif
/*
* RTC configuration
@@ -321,11 +317,15 @@
#include <config_distro_bootcmd.h>
#ifdef CONFIG_TFABOOT
-#define QSPI_MC_INIT_CMD \
- "env exists secureboot && " \
- "esbc_validate 0x20640000 && " \
- "esbc_validate 0x20680000;" \
- "fsl_mc start mc 0x20a00000 0x20e00000 \0"
+#define QSPI_MC_INIT_CMD \
+ "sf probe 0:0; " \
+ "sf read 0x80640000 0x640000 0x80000; " \
+ "env exists secureboot && " \
+ "esbc_validate 0x80640000 && " \
+ "esbc_validate 0x80680000; " \
+ "sf read 0x80a00000 0xa00000 0x300000; " \
+ "sf read 0x80e00000 0xe00000 0x100000; " \
+ "fsl_mc start mc 0x80a00000 0x80e00000 \0"
#define SD_MC_INIT_CMD \
"mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \
"mmc read 0x80e00000 0x7000 0x800;" \
@@ -342,11 +342,15 @@
"fsl_mc start mc 0x580a00000 0x580e00000 \0"
#else
#ifdef CONFIG_QSPI_BOOT
-#define MC_INIT_CMD \
- "mcinitcmd=env exists secureboot && " \
- "esbc_validate 0x20640000 && " \
- "esbc_validate 0x20680000;" \
- "fsl_mc start mc 0x20a00000 0x20e00000 \0"
+#define MC_INIT_CMD \
+ "mcinitcmd=sf probe 0:0; " \
+ "sf read 0x80640000 0x640000 0x80000; " \
+ "env exists secureboot && " \
+ "esbc_validate 0x80640000 && " \
+ "esbc_validate 0x80680000; " \
+ "sf read 0x80a00000 0xa00000 0x300000; " \
+ "sf read 0x80e00000 0xe00000 0x100000; " \
+ "fsl_mc start mc 0x80a00000 0x80e00000 \0"
#elif defined(CONFIG_SD_BOOT)
#define MC_INIT_CMD \
"mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
@@ -500,10 +504,13 @@
#ifdef CONFIG_TFABOOT
#define QSPI_NOR_BOOTCOMMAND \
+ "sf probe 0:0; " \
+ "sf read 0x806c0000 0x6c0000 0x40000; " \
"env exists mcinitcmd && env exists secureboot "\
- "&& esbc_validate 0x206C0000; " \
+ "&& esbc_validate 0x806c0000; " \
+ "sf read 0x80d00000 0xd00000 0x100000; " \
"env exists mcinitcmd && " \
- "fsl_mc lazyapply dpl 0x20d00000; " \
+ "fsl_mc lazyapply dpl 0x80d00000; " \
"run distro_bootcmd;run qspi_bootcmd; " \
"env exists secureboot && esbc_halt;"
@@ -530,10 +537,13 @@
#ifdef CONFIG_QSPI_BOOT
/* Try to boot an on-QSPI kernel first, then do normal distro boot */
#define CONFIG_BOOTCOMMAND \
+ "sf probe 0:0; " \
+ "sf read 0x806c0000 0x6c0000 0x40000; " \
"env exists mcinitcmd && env exists secureboot "\
- "&& esbc_validate 0x206C0000; " \
+ "&& esbc_validate 0x806C0000; " \
+ "sf read 0x80d00000 0xd00000 0x100000; " \
"env exists mcinitcmd && " \
- "fsl_mc lazyapply dpl 0x20d00000; " \
+ "fsl_mc lazyapply dpl 0x80d00000; " \
"run distro_bootcmd;run qspi_bootcmd; " \
"env exists secureboot && esbc_halt;"
#elif defined(CONFIG_SD_BOOT)
diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
deleted file mode 100644
index d747079..0000000
--- a/include/configs/suvd3.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * Copyright (C) 2007 Logic Product Development, Inc.
- * Peter Barada <peterb@logicpd.com>
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- * Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * (C) Copyright 2010
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-
-#define CONFIG_HOSTNAME "suvd3"
-
-/* include common defines/options for all Keymile boards */
-#include "km/keymile-common.h"
-#include "km/km-powerpc.h"
-#include "km/km-mpc83xx.h"
-#include "km/km-mpc832x.h"
-
-#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
- 0x0000c000 | \
- MxMR_WLFx_2X)
-#endif /* __CONFIG_H */
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index c2a1853..ea67868 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -13,11 +13,6 @@
#endif
/*
- * MPC83xx cpu provide RCR register to do reset thing specially
- */
-#define MPC83xx_RESET
-
-/*
* System reset offset (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 6dde9bc..3f5e650 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -1733,7 +1733,6 @@
CONFIG_STV0991_HZ_CLOCK
CONFIG_ST_SMI
CONFIG_SUNXI_MAX_FB_SIZE
-CONFIG_SUVD3
CONFIG_SXNI855T
CONFIG_SYSFLAGS_ADDR
CONFIG_SYSFS
diff --git a/test/compression.c b/test/compression.c
index ad719dd..a2a4b9f 100644
--- a/test/compression.c
+++ b/test/compression.c
@@ -164,7 +164,7 @@
{
/* There is no bzip2 compression in u-boot, so fake it. */
ut_asserteq(in_size, strlen(plain));
- ut_asserteq(0, memcmp(plain, in, in_size));
+ ut_asserteq_mem(plain, in, in_size);
if (bzip2_compressed_size > out_max)
return -1;
@@ -199,7 +199,7 @@
{
/* There is no lzma compression in u-boot, so fake it. */
ut_asserteq(in_size, strlen(plain));
- ut_asserteq(0, memcmp(plain, in, in_size));
+ ut_asserteq_mem(plain, in, in_size);
if (lzma_compressed_size > out_max)
return -1;
@@ -233,7 +233,7 @@
{
/* There is no lzo compression in u-boot, so fake it. */
ut_asserteq(in_size, strlen(plain));
- ut_asserteq(0, memcmp(plain, in, in_size));
+ ut_asserteq_mem(plain, in, in_size);
if (lzo_compressed_size > out_max)
return -1;
@@ -268,7 +268,7 @@
{
/* There is no lz4 compression in u-boot, so fake it. */
ut_asserteq(in_size, strlen(plain));
- ut_asserteq(0, memcmp(plain, in, in_size));
+ ut_asserteq_mem(plain, in, in_size);
if (lz4_compressed_size > out_max)
return -1;
diff --git a/test/dm/acpi.c b/test/dm/acpi.c
index 176d207..4c46dd8 100644
--- a/test/dm/acpi.c
+++ b/test/dm/acpi.c
@@ -218,20 +218,20 @@
rsdp = buf + 16;
ut_asserteq_ptr(rsdp, ctx.rsdp);
- ut_assertok(memcmp(RSDP_SIG, rsdp->signature, sizeof(rsdp->signature)));
+ ut_asserteq_mem(RSDP_SIG, rsdp->signature, sizeof(rsdp->signature));
ut_asserteq(sizeof(*rsdp), rsdp->length);
ut_assertok(table_compute_checksum(rsdp, 20));
ut_assertok(table_compute_checksum(rsdp, sizeof(*rsdp)));
rsdt = PTR_ALIGN((void *)rsdp + sizeof(*rsdp), 16);
ut_asserteq_ptr(rsdt, ctx.rsdt);
- ut_assertok(memcmp("RSDT", rsdt->header.signature, ACPI_NAME_LEN));
+ ut_asserteq_mem("RSDT", rsdt->header.signature, ACPI_NAME_LEN);
ut_asserteq(sizeof(*rsdt), rsdt->header.length);
ut_assertok(table_compute_checksum(rsdt, sizeof(*rsdt)));
xsdt = PTR_ALIGN((void *)rsdt + sizeof(*rsdt), 16);
ut_asserteq_ptr(xsdt, ctx.xsdt);
- ut_assertok(memcmp("XSDT", xsdt->header.signature, ACPI_NAME_LEN));
+ ut_asserteq_mem("XSDT", xsdt->header.signature, ACPI_NAME_LEN);
ut_asserteq(sizeof(*xsdt), xsdt->header.length);
ut_assertok(table_compute_checksum(xsdt, sizeof(*xsdt)));
diff --git a/test/dm/axi.c b/test/dm/axi.c
index 289f07a..e1155a5 100644
--- a/test/dm/axi.c
+++ b/test/dm/axi.c
@@ -66,11 +66,11 @@
/* Test writing */
val = 0x55667788;
axi_write(store, 0, &val, AXI_SIZE_32);
- ut_asserteq(0, memcmp(data, tdata1, ARRAY_SIZE(tdata1)));
+ ut_asserteq_mem(data, tdata1, ARRAY_SIZE(tdata1));
val = 0xaabbccdd;
axi_write(store, 3, &val, AXI_SIZE_32);
- ut_asserteq(0, memcmp(data + 3, tdata2, ARRAY_SIZE(tdata1)));
+ ut_asserteq_mem(data + 3, tdata2, ARRAY_SIZE(tdata1));
return 0;
}
diff --git a/test/dm/dma.c b/test/dm/dma.c
index 12cba57..317ed4f 100644
--- a/test/dm/dma.c
+++ b/test/dm/dma.c
@@ -30,8 +30,8 @@
src_buf[i] = i;
ut_assertok(dma_memcpy(dst_buf, src_buf, len));
+ ut_asserteq_mem(src_buf, dst_buf, len);
- ut_assertok(memcmp(src_buf, dst_buf, len));
return 0;
}
DM_TEST(dm_test_dma_m2m, DM_TESTF_SCAN_FDT);
@@ -72,7 +72,7 @@
ut_assertok(dma_free(&dma_tx));
ut_assertok(dma_free(&dma_rx));
- ut_assertok(memcmp(src_buf, dst_buf, len));
+ ut_asserteq_mem(src_buf, dst_buf, len);
return 0;
}
@@ -117,7 +117,7 @@
ut_assertok(dma_free(&dma_tx));
ut_assertok(dma_free(&dma_rx));
- ut_assertok(memcmp(src_buf, dst_buf, len));
+ ut_asserteq_mem(src_buf, dst_buf, len);
return 0;
}
diff --git a/test/dm/eth.c b/test/dm/eth.c
index 99c1672..1fddcaa 100644
--- a/test/dm/eth.c
+++ b/test/dm/eth.c
@@ -282,17 +282,17 @@
ut_assert(arp_is_waiting());
/* Validate response */
- ut_assert(memcmp(eth->et_src, net_ethaddr, ARP_HLEN) == 0);
- ut_assert(memcmp(eth->et_dest, priv->fake_host_hwaddr, ARP_HLEN) == 0);
+ ut_asserteq_mem(eth->et_src, net_ethaddr, ARP_HLEN);
+ ut_asserteq_mem(eth->et_dest, priv->fake_host_hwaddr, ARP_HLEN);
ut_assert(eth->et_protlen == htons(PROT_ARP));
ut_assert(arp->ar_hrd == htons(ARP_ETHER));
ut_assert(arp->ar_pro == htons(PROT_IP));
ut_assert(arp->ar_hln == ARP_HLEN);
ut_assert(arp->ar_pln == ARP_PLEN);
- ut_assert(memcmp(&arp->ar_sha, net_ethaddr, ARP_HLEN) == 0);
+ ut_asserteq_mem(&arp->ar_sha, net_ethaddr, ARP_HLEN);
ut_assert(net_read_ip(&arp->ar_spa).s_addr == net_ip.s_addr);
- ut_assert(memcmp(&arp->ar_tha, priv->fake_host_hwaddr, ARP_HLEN) == 0);
+ ut_asserteq_mem(&arp->ar_tha, priv->fake_host_hwaddr, ARP_HLEN);
ut_assert(net_read_ip(&arp->ar_tpa).s_addr ==
string_to_ip("1.1.2.4").s_addr);
@@ -373,8 +373,8 @@
ut_assert(arp_is_waiting());
/* Validate response */
- ut_assert(memcmp(eth->et_src, net_ethaddr, ARP_HLEN) == 0);
- ut_assert(memcmp(eth->et_dest, priv->fake_host_hwaddr, ARP_HLEN) == 0);
+ ut_asserteq_mem(eth->et_src, net_ethaddr, ARP_HLEN);
+ ut_asserteq_mem(eth->et_dest, priv->fake_host_hwaddr, ARP_HLEN);
ut_assert(eth->et_protlen == htons(PROT_IP));
ut_assert(net_read_ip(&ip->ip_src).s_addr == net_ip.s_addr);
diff --git a/test/dm/i2c.c b/test/dm/i2c.c
index cadbb43..2025c42 100644
--- a/test/dm/i2c.c
+++ b/test/dm/i2c.c
@@ -51,10 +51,10 @@
ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
ut_assertok(i2c_get_chip(bus, chip, 1, &dev));
ut_assertok(dm_i2c_read(dev, 0, buf, 5));
- ut_assertok(memcmp(buf, "\0\0\0\0\0", sizeof(buf)));
+ ut_asserteq_mem(buf, "\0\0\0\0\0", sizeof(buf));
ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2));
ut_assertok(dm_i2c_read(dev, 0, buf, 5));
- ut_assertok(memcmp(buf, "\0\0AB\0", sizeof(buf)));
+ ut_asserteq_mem(buf, "\0\0AB\0", sizeof(buf));
return 0;
}
@@ -123,7 +123,7 @@
ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
ut_assertok(i2c_get_chip(bus, chip, 1, &dev));
ut_assertok(dm_i2c_read(dev, 0, buf, 5));
- ut_assertok(memcmp(buf, "\0\0\0\0\0", sizeof(buf)));
+ ut_asserteq_mem(buf, "\0\0\0\0\0", sizeof(buf));
/* Tell the EEPROM to only read/write one register at a time */
ut_assertok(uclass_first_device(UCLASS_I2C_EMUL, &eeprom));
@@ -132,34 +132,34 @@
/* Now we only get the first byte - the rest will be 0xff */
ut_assertok(dm_i2c_read(dev, 0, buf, 5));
- ut_assertok(memcmp(buf, "\0\xff\xff\xff\xff", sizeof(buf)));
+ ut_asserteq_mem(buf, "\0\xff\xff\xff\xff", sizeof(buf));
/* If we do a separate transaction for each byte, it works */
ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS));
ut_assertok(dm_i2c_read(dev, 0, buf, 5));
- ut_assertok(memcmp(buf, "\0\0\0\0\0", sizeof(buf)));
+ ut_asserteq_mem(buf, "\0\0\0\0\0", sizeof(buf));
/* This will only write A */
ut_assertok(i2c_set_chip_flags(dev, 0));
ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2));
ut_assertok(dm_i2c_read(dev, 0, buf, 5));
- ut_assertok(memcmp(buf, "\0\xff\xff\xff\xff", sizeof(buf)));
+ ut_asserteq_mem(buf, "\0\xff\xff\xff\xff", sizeof(buf));
/* Check that the B was ignored */
ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS));
ut_assertok(dm_i2c_read(dev, 0, buf, 5));
- ut_assertok(memcmp(buf, "\0\0A\0\0\0", sizeof(buf)));
+ ut_asserteq_mem(buf, "\0\0A\0\0\0", sizeof(buf));
/* Now write it again with the new flags, it should work */
ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_WR_ADDRESS));
ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2));
ut_assertok(dm_i2c_read(dev, 0, buf, 5));
- ut_assertok(memcmp(buf, "\0\xff\xff\xff\xff", sizeof(buf)));
+ ut_asserteq_mem(buf, "\0\xff\xff\xff\xff", sizeof(buf));
ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_WR_ADDRESS |
DM_I2C_CHIP_RD_ADDRESS));
ut_assertok(dm_i2c_read(dev, 0, buf, 5));
- ut_assertok(memcmp(buf, "\0\0AB\0\0", sizeof(buf)));
+ ut_asserteq_mem(buf, "\0\0AB\0\0", sizeof(buf));
/* Restore defaults */
sandbox_i2c_eeprom_set_test_mode(eeprom, SIE_TEST_MODE_NONE);
diff --git a/test/dm/misc.c b/test/dm/misc.c
index 4d4232a..26fd6ac 100644
--- a/test/dm/misc.c
+++ b/test/dm/misc.c
@@ -25,24 +25,24 @@
ut_asserteq(5, misc_write(dev, 4, "WRITE", 5));
ut_asserteq(9, misc_read(dev, 0, buf, 9));
- ut_assertok(memcmp(buf, "TESTWRITE", 9));
+ ut_asserteq_mem(buf, "TESTWRITE", 9);
/* Call tests */
id = 0;
ut_assertok(misc_call(dev, 0, &id, 4, buf, 16));
- ut_assertok(memcmp(buf, "Zero", 4));
+ ut_asserteq_mem(buf, "Zero", 4);
id = 2;
ut_assertok(misc_call(dev, 0, &id, 4, buf, 16));
- ut_assertok(memcmp(buf, "Two", 3));
+ ut_asserteq_mem(buf, "Two", 3);
ut_assertok(misc_call(dev, 1, &id, 4, buf, 16));
- ut_assertok(memcmp(buf, "Forty-two", 9));
+ ut_asserteq_mem(buf, "Forty-two", 9);
id = 1;
ut_assertok(misc_call(dev, 1, &id, 4, buf, 16));
- ut_assertok(memcmp(buf, "Forty-one", 9));
+ ut_asserteq_mem(buf, "Forty-one", 9);
/* IOCTL tests */
diff --git a/test/dm/osd.c b/test/dm/osd.c
index 6910690..5739dfa 100644
--- a/test/dm/osd.c
+++ b/test/dm/osd.c
@@ -71,27 +71,29 @@
ut_assertok(sandbox_osd_get_mem(dev, mem, memsize));
split(mem, memsize / 2, text, colors);
- ut_assertok(memcmp(text, " "
- " "
- " "
- " "
- " "
- " "
- " "
- " "
- " "
- " ", memsize / 2));
+ ut_asserteq_mem(text,
+ " "
+ " "
+ " "
+ " "
+ " "
+ " "
+ " "
+ " "
+ " "
+ " ", memsize / 2);
- ut_assertok(memcmp(colors, "kkkkkkkkkk"
- "kkkkkkkkkk"
- "kkkkkkkkkk"
- "kkkkkkkkkk"
- "kkkkkkkkkk"
- "kkkkkkkkkk"
- "kkkkkkkkkk"
- "kkkkkkkkkk"
- "kkkkkkkkkk"
- "kkkkkkkkkk", memsize / 2));
+ ut_asserteq_mem(colors,
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk", memsize / 2);
print_mem(mem, 10, 10);
@@ -100,27 +102,29 @@
ut_assertok(sandbox_osd_get_mem(dev, mem, memsize));
split(mem, memsize / 2, text, colors);
- ut_assertok(memcmp(text, " "
- " Blah "
- " "
- " "
- " "
- " "
- " "
- " "
- " "
- " ", memsize / 2));
+ ut_asserteq_mem(text,
+ " "
+ " Blah "
+ " "
+ " "
+ " "
+ " "
+ " "
+ " "
+ " "
+ " ", memsize / 2);
- ut_assertok(memcmp(colors, "kkkkkkkkkk"
- "krrrrkkkkk"
- "kkkkkkkkkk"
- "kkkkkkkkkk"
- "kkkkkkkkkk"
- "kkkkkkkkkk"
- "kkkkkkkkkk"
- "kkkkkkkkkk"
- "kkkkkkkkkk"
- "kkkkkkkkkk", memsize / 2));
+ ut_asserteq_mem(colors,
+ "kkkkkkkkkk"
+ "krrrrkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk", memsize / 2);
print_mem(mem, 10, 10);
@@ -152,17 +156,19 @@
ut_assertok(sandbox_osd_get_mem(dev, mem, memsize));
split(mem, memsize / 2, text, colors);
- ut_assertok(memcmp(text, " "
- " "
- " "
- " "
- " ", memsize / 2));
+ ut_asserteq_mem(text,
+ " "
+ " "
+ " "
+ " "
+ " ", memsize / 2);
- ut_assertok(memcmp(colors, "kkkkkkkkkkkkkkkkkkkk"
- "kkkkkkkkkkkkkkkkkkkk"
- "kkkkkkkkkkkkkkkkkkkk"
- "kkkkkkkkkkkkkkkkkkkk"
- "kkkkkkkkkkkkkkkkkkkk", memsize / 2));
+ ut_asserteq_mem(colors,
+ "kkkkkkkkkkkkkkkkkkkk"
+ "kkkkkkkkkkkkkkkkkkkk"
+ "kkkkkkkkkkkkkkkkkkkk"
+ "kkkkkkkkkkkkkkkkkkkk"
+ "kkkkkkkkkkkkkkkkkkkk", memsize / 2);
print_mem(mem, 20, 5);
@@ -192,17 +198,19 @@
print_mem(mem, 20, 5);
- ut_assertok(memcmp(text, "+---- OSD menu ----+"
- "| * Entry 1 |"
- "| (*) Entry 2 |"
- "| * Entry 3 |"
- "+------------------+", memsize / 2));
+ ut_asserteq_mem(text,
+ "+---- OSD menu ----+"
+ "| * Entry 1 |"
+ "| (*) Entry 2 |"
+ "| * Entry 3 |"
+ "+------------------+", memsize / 2);
- ut_assertok(memcmp(colors, "gggggggggggggggggggg"
- "gkbbbbbbbbbbbkkkkkkg"
- "gkbbbbbbbbbbbkkkkkkg"
- "gkbbbbbbbbbbbkkkkkkg"
- "gggggggggggggggggggg", memsize / 2));
+ ut_asserteq_mem(colors,
+ "gggggggggggggggggggg"
+ "gkbbbbbbbbbbbkkkkkkg"
+ "gkbbbbbbbbbbbkkkkkkg"
+ "gkbbbbbbbbbbbkkkkkkg"
+ "gggggggggggggggggggg", memsize / 2);
return 0;
}
diff --git a/test/dm/remoteproc.c b/test/dm/remoteproc.c
index 4067596..9511c7d 100644
--- a/test/dm/remoteproc.c
+++ b/test/dm/remoteproc.c
@@ -223,7 +223,7 @@
/* Load firmware in loaded_firmware, and verify it */
ut_assertok(rproc_elf32_load_image(dev, (ulong)valid_elf32, size));
- ut_assertok(memcmp(loaded_firmware, valid_elf32, loaded_firmware_size));
+ ut_asserteq_mem(loaded_firmware, valid_elf32, loaded_firmware_size);
ut_asserteq(rproc_elf_get_boot_addr(dev, (unsigned long)valid_elf32),
0x08000000);
unmap_physmem(loaded_firmware, MAP_NOCACHE);
@@ -243,8 +243,8 @@
&rsc_addr, &rsc_size));
ut_asserteq(rsc_addr, CONFIG_SYS_SDRAM_BASE);
ut_asserteq(rsc_size, rsc_table_size);
- ut_assertok(memcmp(loaded_firmware, valid_elf32 + shdr->sh_offset,
- shdr->sh_size));
+ ut_asserteq_mem(loaded_firmware, valid_elf32 + shdr->sh_offset,
+ shdr->sh_size);
unmap_physmem(loaded_firmware, MAP_NOCACHE);
/* Invalid ELF Magic */
diff --git a/test/dm/sf.c b/test/dm/sf.c
index 7805af7..55b8d15 100644
--- a/test/dm/sf.c
+++ b/test/dm/sf.c
@@ -35,7 +35,7 @@
dst = map_sysmem(0x20000 + full_size, full_size);
ut_assertok(spi_flash_read_dm(dev, 0, size, dst));
- ut_assertok(memcmp(src, dst, size));
+ ut_asserteq_mem(src, dst, size);
/* Erase */
ut_assertok(spi_flash_erase_dm(dev, 0, size));
@@ -48,7 +48,7 @@
src[i] = i;
ut_assertok(spi_flash_write_dm(dev, 0, size, src));
ut_assertok(spi_flash_read_dm(dev, 0, size, dst));
- ut_assertok(memcmp(src, dst, size));
+ ut_asserteq_mem(src, dst, size);
/* Try the write-protect stuff */
ut_assertok(uclass_first_device_err(UCLASS_SPI_EMUL, &emul));
diff --git a/test/unicode_ut.c b/test/unicode_ut.c
index 5f932bf..26d9633 100644
--- a/test/unicode_ut.c
+++ b/test/unicode_ut.c
@@ -67,8 +67,9 @@
u16 *copy = u16_strdup(c4);
ut_assert(copy != c4);
- ut_assert(!memcmp(copy, c4, sizeof(c4)));
+ ut_asserteq_mem(copy, c4, sizeof(c4));
free(copy);
+
return 0;
}
UNICODE_TEST(unicode_test_u16_strdup);
@@ -80,7 +81,8 @@
r = u16_strcpy(copy, c1);
ut_assert(r == copy);
- ut_assert(!memcmp(copy, c1, sizeof(c1)));
+ ut_asserteq_mem(copy, c1, sizeof(c1));
+
return 0;
}
UNICODE_TEST(unicode_test_u16_strcpy);