| commit | 54f4d076f674e22c4cf6f75a931686f1c85e4ab0 | [log] [tgz] |
|---|---|---|
| author | Michal Simek <michal.simek@xilinx.com> | Tue Feb 14 17:40:21 2017 +0100 |
| committer | Michal Simek <michal.simek@xilinx.com> | Wed Aug 02 09:11:51 2017 +0200 |
| tree | f43f64b13e373fef33bf6558be02171fb27c31e8 | |
| parent | d4ee68656112a7fd6864afd611f6426430535099 [diff] |
arm: zynq: Label whole PL part as fpga_full region This will simplify dt overlay structure for the whole PL. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>