tree 1c7affaf8b45a246101e92d149e5abc1c85267c1
parent bad1b5e1f305220c46a8fba21d089b3b7ead09f1
author Lukas Auer <lukas.auer@aisec.fraunhofer.de> 1542882372 +0100
committer Andes <uboot@andestech.com> 1543211849 +0800

riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I

RISC-V defines the base integer instruction sets as RV32I and RV64I.
Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to
match this convention.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>