riscv: mbv: Enable SPL and binman
Enable SPL and binman to generate u-boot.img (machine mode) and u-boot.itb
(supervisor mode). DTB is placed at fixed address to ensure that it is 8
byte aligned which is not ensured when dtb is attached behind SPL binary
that's why SPL and U-Boot are taking DTB from the same address.
Also align addresses for both defconfigs.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/85506bce5580d448f095f267d029e3932c5e9990.1707911544.git.michal.simek@amd.com
diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig
index 553c232..9d5ee65 100644
--- a/board/xilinx/mbv/Kconfig
+++ b/board/xilinx/mbv/Kconfig
@@ -15,12 +15,23 @@
config TEXT_BASE
default 0x21200000
+config SPL_TEXT_BASE
+ default 0x20000000
+
+config SPL_OPENSBI_LOAD_ADDR
+ hex
+ default 0x20200000
+
config BOARD_SPECIFIC_OPTIONS
def_bool y
select GENERIC_RISCV
+ select SUPPORT_SPL
imply BOARD_LATE_INIT
+ imply SPL_RAM_SUPPORT
+ imply SPL_RAM_DEVICE
imply CMD_SBI
imply CMD_PING
+ imply OF_HAS_PRIOR_STAGE
source "board/xilinx/Kconfig"
diff --git a/board/xilinx/mbv/board.c b/board/xilinx/mbv/board.c
index ccf4395..c478f7e 100644
--- a/board/xilinx/mbv/board.c
+++ b/board/xilinx/mbv/board.c
@@ -5,7 +5,17 @@
* Michal Simek <michal.simek@amd.com>
*/
+#include <spl.h>
+
int board_init(void)
{
return 0;
}
+
+#ifdef CONFIG_SPL
+u32 spl_boot_device(void)
+{
+ /* RISC-V QEMU only supports RAM as SPL boot device */
+ return BOOT_DEVICE_RAM;
+}
+#endif