clk: microchip: mpfs: support new syscon based devicetree configuration
Why get a devicetree description wrong once when you can get it wrong
twice? The original mistake, which the driver supports was failing to
describe the main PLL that the "cfg" and "periph" clocks parented by.
The second mistake was describing the "cfg" and "periph" clocks a
reg region within the clock controller, rather as two registers within
a syscon region that also contains pinctrl, interrupt muxing controls
and other functions.
Make up for lost time and describe these regions as they should have
been originally, preserving support for the existing two configurations
for the sake of existing systems with firmware-provided devicetrees.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff --git a/drivers/clk/microchip/mpfs_clk_cfg.c b/drivers/clk/microchip/mpfs_clk_cfg.c
index 5e8fb99..7da1fc7 100644
--- a/drivers/clk/microchip/mpfs_clk_cfg.c
+++ b/drivers/clk/microchip/mpfs_clk_cfg.c
@@ -9,6 +9,7 @@
#include <dm/device.h>
#include <dm/devres.h>
#include <dm/uclass.h>
+#include <regmap.h>
#include <dt-bindings/clock/microchip-mpfs-clock.h>
#include <linux/err.h>
@@ -57,7 +58,7 @@
*/
struct mpfs_cfg_hw_clock {
struct mpfs_cfg_clock cfg;
- void __iomem *sys_base;
+ struct regmap *regmap;
u32 prate;
struct clk hw;
};
@@ -68,11 +69,11 @@
{
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
- void __iomem *base_addr = cfg_hw->sys_base;
unsigned long rate;
u32 val;
- val = readl(base_addr + REG_CLOCK_CONFIG_CR) >> cfg->shift;
+ regmap_read(cfg_hw->regmap, REG_CLOCK_CONFIG_CR, &val);
+ val >>= cfg->shift;
val &= clk_div_mask(cfg->width);
rate = cfg_hw->prate / (1u << val);
hw->rate = rate;
@@ -84,7 +85,6 @@
{
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
- void __iomem *base_addr = cfg_hw->sys_base;
u32 val;
int divider_setting;
@@ -93,10 +93,10 @@
if (divider_setting < 0)
return divider_setting;
- val = readl(base_addr + REG_CLOCK_CONFIG_CR);
+ regmap_read(cfg_hw->regmap, REG_CLOCK_CONFIG_CR, &val);
val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift);
val |= divider_setting << cfg->shift;
- writel(val, base_addr + REG_CLOCK_CONFIG_CR);
+ regmap_write(cfg_hw->regmap, REG_CLOCK_CONFIG_CR, val);
return clk_get_rate(hw);
}
@@ -116,7 +116,7 @@
CLK_CFG(CLK_AHB, "clk_ahb", 4, 2, mpfs_div_ahb_table, 0),
};
-int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent)
+int mpfs_clk_register_cfgs(struct clk *parent, struct regmap *regmap)
{
int ret;
int i, id, num_clks;
@@ -126,7 +126,7 @@
num_clks = ARRAY_SIZE(mpfs_cfg_clks);
for (i = 0; i < num_clks; i++) {
hw = &mpfs_cfg_clks[i].hw;
- mpfs_cfg_clks[i].sys_base = base;
+ mpfs_cfg_clks[i].regmap = regmap;
mpfs_cfg_clks[i].prate = clk_get_rate(parent);
name = mpfs_cfg_clks[i].cfg.name;
ret = clk_register(hw, MPFS_CFG_CLOCK, name, parent->dev->name);