x86: qemu: Avoid accessing BSS too early
BSS is placed in DRAM which is actually available early with QEMU. But
it is cleared by the init sequence, so values stored there are lost.
Move the system-type flag into a function, instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 563f63e..e846ccd 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -15,14 +15,21 @@
#include <asm/arch/qemu.h>
#include <asm/u-boot-x86.h>
-static bool i440fx;
-
#if CONFIG_IS_ENABLED(QFW_PIO)
U_BOOT_DRVINFO(x86_qfw_pio) = {
.name = "qfw_pio",
};
#endif
+static bool is_i440fx(void)
+{
+ u16 device;
+
+ pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device);
+
+ return device == PCI_DEVICE_ID_INTEL_82441;
+}
+
static void enable_pm_piix(void)
{
u8 en;
@@ -50,16 +57,17 @@
void qemu_chipset_init(void)
{
- u16 device, xbcs;
+ bool i440fx;
+ u16 xbcs;
int pam, i;
+ i440fx = is_i440fx();
+
/*
* i440FX and Q35 chipset have different PAM register offset, but with
* the same bitfield layout. Here we determine the offset based on its
* PCI device ID.
*/
- pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device);
- i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
pam = i440fx ? I440FX_PAM : Q35_PAM;
/*
@@ -123,7 +131,7 @@
{
u8 irq;
- if (i440fx) {
+ if (is_i440fx()) {
/*
* Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not
* connected to I/O APIC INTPIN#16-19. Instead they are routed