diff --git a/CHANGELOG b/CHANGELOG
index b3d00fe..fa3bbfe 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,12 @@
 Changes since U-Boot 1.0.1:
 ======================================================================
 
+* Patch by Travis Sawyer, 30 Dec 2003:
+  Add support for IBM PPC440GX. Multiple EMAC Ethernet devices,
+  select MDI port based on enabled EMAC device.
+  Add support for XES Inc <http://www.xes-inc.com> XPedite1000 440GX
+  base PrPMC board.
+
 * Patch by Wolter Kamphuis, 15 Dec 2003:
   made CONFIG_SILENT_CONSOLE usable on all architectures
 
diff --git a/CREDITS b/CREDITS
index e46381c..047240d 100644
--- a/CREDITS
+++ b/CREDITS
@@ -276,6 +276,10 @@
 E: caret@c-side.com
 D: Author of LiMon-1.4.2, which contributed some ideas
 
+N: Travis B. Sawyer
+E: travis.sawyer@sandburst.com
+D: Support for IBM PPC440GX, XES XPedite1000 440GX PrPMC board.
+
 N: Paolo Scaffardi
 E: arsenio@tin.it
 D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more
diff --git a/MAKEALL b/MAKEALL
index 2e5b87f..f8cdcb9 100644
--- a/MAKEALL
+++ b/MAKEALL
@@ -64,6 +64,7 @@
 	ML2		OCRTC		ORSG		PCI405		\
 	PIP405		PLU405          PMC405          PPChameleonEVB	\
 	VOH405          W7OLMC		W7OLMG          WALNUT405	\
+	XPEDITE1K							\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index 0a5b470..5f4102e 100644
--- a/Makefile
+++ b/Makefile
@@ -635,6 +635,9 @@
 WALNUT405_config:unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx walnut405
 
+XPEDITE1K_config:unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx xpedite1k
+
 #########################################################################
 ## MPC824x Systems
 #########################################################################
diff --git a/README b/README
index 61d55d4..46171bf 100644
--- a/README
+++ b/README
@@ -141,7 +141,7 @@
 
 - cpu/74xx_7xx	Files specific to Motorola MPC74xx and 7xx CPUs
 - cpu/arm925t	Files specific to ARM	   925	   CPUs
-- cpu/arm926ejs	Files specific to ARM	926	CPUs
+- cpu/arm926ejs Files specific to ARM	926	CPUs
 - cpu/mpc5xx	Files specific to Motorola MPC5xx  CPUs
 - cpu/mpc8xx	Files specific to Motorola MPC8xx  CPUs
 - cpu/mpc824x	Files specific to Motorola MPC824x CPUs
@@ -150,22 +150,22 @@
 - cpu/ppc4xx	Files specific to IBM	   4xx	   CPUs
 
 
-- board/LEOX/   Files specific to boards manufactured by The LEOX team
+- board/LEOX/	Files specific to boards manufactured by The LEOX team
 - board/LEOX/elpt860	Files specific to ELPT860 boards
 - board/RPXClassic
 		Files specific to RPXClassic boards
-- board/RPXlite	Files specific to RPXlite    boards
+- board/RPXlite Files specific to RPXlite    boards
 - board/at91rm9200dk Files specific to AT91RM9200DK boards
 - board/c2mon	Files specific to c2mon	     boards
-- board/cmi	Files specific to cmi        boards
+- board/cmi	Files specific to cmi	     boards
 - board/cogent	Files specific to Cogent     boards
 		(need further configuration)
 		Files specific to CPCIISER4  boards
-- board/cpu86	Files specific to CPU86      boards
+- board/cpu86	Files specific to CPU86	     boards
 - board/cray/	Files specific to boards manufactured by Cray
-- board/cray/L1		Files specific to L1         boards
+- board/cray/L1		Files specific to L1	     boards
 - board/cu824	Files specific to CU824	     boards
-- board/ebony   Files specific to IBM Ebony board
+- board/ebony	Files specific to IBM Ebony board
 - board/eric	Files specific to ERIC	     boards
 - board/esd/	Files specific to boards manufactured by ESD
 - board/esd/adciop	Files specific to ADCIOP     boards
@@ -175,8 +175,8 @@
 - board/esd/cpciiser4	Files specific to CPCIISER4  boards
 - board/esd/common	Common files for ESD boards
 - board/esd/dasa_sim	Files specific to DASA_SIM   boards
-- board/esd/du405	Files specific to DU405      boards
-- board/esd/ocrtc	Files specific to OCRTC      boards
+- board/esd/du405	Files specific to DU405	     boards
+- board/esd/ocrtc	Files specific to OCRTC	     boards
 - board/esd/pci405	Files specific to PCI405     boards
 - board/esteem192e
 		Files specific to ESTEEM192E boards
@@ -211,17 +211,17 @@
 - board/mpl/common	Common files for MPL boards
 - board/mpl/pip405	Files specific to PIP405     boards
 - board/mpl/mip405	Files specific to MIP405     boards
-- board/mpl/vcma9	Files specific to VCMA9      boards
-- board/musenki	Files specific to MUSEKNI    boards
-- board/mvs1	Files specific to MVS1       boards
-- board/nx823   Files specific to NX823      boards
-- board/oxc	Files specific to OXC        boards
+- board/mpl/vcma9	Files specific to VCMA9	     boards
+- board/musenki Files specific to MUSEKNI    boards
+- board/mvs1	Files specific to MVS1	     boards
+- board/nx823	Files specific to NX823	     boards
+- board/oxc	Files specific to OXC	     boards
 - board/omap1510inn
 		Files specific to OMAP 1510 Innovator boards
 - board/omap1610inn
 		Files specific to OMAP 1610 Innovator boards
-- board/pcippc2	Files specific to PCIPPC2/PCIPPC6 boards
-- board/pm826	Files specific to PM826      boards
+- board/pcippc2 Files specific to PCIPPC2/PCIPPC6 boards
+- board/pm826	Files specific to PM826	     boards
 - board/ppmc8260
 		Files specific to PPMC8260   boards
 - board/snmc/qs850	Files specific to QS850/823  boards
@@ -232,24 +232,24 @@
 		Files specific to RSDproto   boards
 - board/sandpoint
 		Files specific to Sandpoint  boards
-- board/sbc8260	Files specific to SBC8260    boards
+- board/sbc8260 Files specific to SBC8260    boards
 - board/sacsng	Files specific to SACSng     boards
 - board/siemens Files specific to boards manufactured by Siemens AG
 - board/siemens/CCM	Files specific to CCM	     boards
 - board/siemens/IAD210	Files specific to IAD210     boards
-- board/siemens/SCM	Files specific to SCM        boards
+- board/siemens/SCM	Files specific to SCM	     boards
 - board/siemens/pcu_e	Files specific to PCU_E	     boards
 - board/sixnet	Files specific to SIXNET     boards
 - board/spd8xx	Files specific to SPD8xxTS   boards
 - board/tqm8260 Files specific to TQM8260    boards
 - board/tqm8xx	Files specific to TQM8xxL    boards
-- board/w7o	Files specific to W7O        boards
+- board/w7o	Files specific to W7O	     boards
 - board/walnut405
 		Files specific to Walnut405  boards
-- board/westel/	Files specific to boards manufactured by Westel Wireless
+- board/westel/ Files specific to boards manufactured by Westel Wireless
 - board/westel/amx860	Files specific to AMX860     boards
-- board/utx8245	Files specific to UTX8245   boards
-- board/zpc1900	Files specific to Zephyr Engineering ZPC.1900 board
+- board/utx8245 Files specific to UTX8245   boards
+- board/zpc1900 Files specific to Zephyr Engineering ZPC.1900 board
 
 Software Configuration:
 =======================
@@ -336,49 +336,49 @@
 		PowerPC based boards:
 		---------------------
 
-		CONFIG_ADCIOP,     CONFIG_ICU862      CONFIG_RPXsuper,
-		CONFIG_ADS860,     CONFIG_IP860,      CONFIG_SM850,
-		CONFIG_AMX860,     CONFIG_IPHASE4539, CONFIG_SPD823TS,
-		CONFIG_AR405,      CONFIG_IVML24,     CONFIG_SXNI855T,
-		CONFIG_BAB7xx,     CONFIG_IVML24_128, CONFIG_Sandpoint8240,
-		CONFIG_CANBT,      CONFIG_IVML24_256, CONFIG_Sandpoint8245,
-		CONFIG_CCM,        CONFIG_IVMS8,      CONFIG_TQM823L,
-		CONFIG_CPCI405,    CONFIG_IVMS8_128,  CONFIG_TQM850L,
+		CONFIG_ADCIOP,	   CONFIG_ICU862      CONFIG_RPXsuper,
+		CONFIG_ADS860,	   CONFIG_IP860,      CONFIG_SM850,
+		CONFIG_AMX860,	   CONFIG_IPHASE4539, CONFIG_SPD823TS,
+		CONFIG_AR405,	   CONFIG_IVML24,     CONFIG_SXNI855T,
+		CONFIG_BAB7xx,	   CONFIG_IVML24_128, CONFIG_Sandpoint8240,
+		CONFIG_CANBT,	   CONFIG_IVML24_256, CONFIG_Sandpoint8245,
+		CONFIG_CCM,	   CONFIG_IVMS8,      CONFIG_TQM823L,
+		CONFIG_CPCI405,	   CONFIG_IVMS8_128,  CONFIG_TQM850L,
 		CONFIG_CPCI4052,   CONFIG_IVMS8_256,  CONFIG_TQM855L,
 		CONFIG_CPCIISER4,  CONFIG_LANTEC,     CONFIG_TQM860L,
-		CONFIG_CPU86,      CONFIG_MBX,        CONFIG_TQM8260,
-		CONFIG_CRAYL1,     CONFIG_MBX860T,    CONFIG_TTTech,
-		CONFIG_CU824,      CONFIG_MHPC,       CONFIG_UTX8245,
+		CONFIG_CPU86,	   CONFIG_MBX,	      CONFIG_TQM8260,
+		CONFIG_CRAYL1,	   CONFIG_MBX860T,    CONFIG_TTTech,
+		CONFIG_CU824,	   CONFIG_MHPC,	      CONFIG_UTX8245,
 		CONFIG_DASA_SIM,   CONFIG_MIP405,     CONFIG_W7OLMC,
-		CONFIG_DU405,      CONFIG_MOUSSE,     CONFIG_W7OLMG,
-		CONFIG_ELPPC,      CONFIG_MPC8260ADS, CONFIG_WALNUT405,
-		CONFIG_ERIC,       CONFIG_MUSENKI,    CONFIG_ZUMA,
-		CONFIG_ESTEEM192E, CONFIG_MVS1,       CONFIG_c2mon,
-		CONFIG_ETX094,     CONFIG_NX823,      CONFIG_cogent_mpc8260,
+		CONFIG_DU405,	   CONFIG_MOUSSE,     CONFIG_W7OLMG,
+		CONFIG_ELPPC,	   CONFIG_MPC8260ADS, CONFIG_WALNUT405,
+		CONFIG_ERIC,	   CONFIG_MUSENKI,    CONFIG_ZUMA,
+		CONFIG_ESTEEM192E, CONFIG_MVS1,	      CONFIG_c2mon,
+		CONFIG_ETX094,	   CONFIG_NX823,      CONFIG_cogent_mpc8260,
 		CONFIG_EVB64260,   CONFIG_OCRTC,      CONFIG_cogent_mpc8xx,
-		CONFIG_FADS823,    CONFIG_ORSG,       CONFIG_ep8260,
-		CONFIG_FADS850SAR, CONFIG_OXC,        CONFIG_gw8260,
+		CONFIG_FADS823,	   CONFIG_ORSG,	      CONFIG_ep8260,
+		CONFIG_FADS850SAR, CONFIG_OXC,	      CONFIG_gw8260,
 		CONFIG_FADS860T,   CONFIG_PCI405,     CONFIG_hermes,
-		CONFIG_FLAGADM,    CONFIG_PCIPPC2,    CONFIG_hymod,
-		CONFIG_FPS850L,    CONFIG_PCIPPC6,    CONFIG_lwmon,
-		CONFIG_GEN860T,    CONFIG_PIP405,     CONFIG_pcu_e,
-		CONFIG_GENIETV,    CONFIG_PM826,      CONFIG_ppmc8260,
-		CONFIG_GTH,        CONFIG_RPXClassic, CONFIG_rsdproto,
-		CONFIG_IAD210,     CONFIG_RPXlite,    CONFIG_sbc8260,
-		CONFIG_EBONY,      CONFIG_sacsng,     CONFIG_FPS860L,
-		CONFIG_V37,        CONFIG_ELPT860,    CONFIG_CMI,
-		CONFIG_NETVIA,     CONFIG_RBC823,     CONFIG_ZPC1900,
+		CONFIG_FLAGADM,	   CONFIG_PCIPPC2,    CONFIG_hymod,
+		CONFIG_FPS850L,	   CONFIG_PCIPPC6,    CONFIG_lwmon,
+		CONFIG_GEN860T,	   CONFIG_PIP405,     CONFIG_pcu_e,
+		CONFIG_GENIETV,	   CONFIG_PM826,      CONFIG_ppmc8260,
+		CONFIG_GTH,	   CONFIG_RPXClassic, CONFIG_rsdproto,
+		CONFIG_IAD210,	   CONFIG_RPXlite,    CONFIG_sbc8260,
+		CONFIG_EBONY,	   CONFIG_sacsng,     CONFIG_FPS860L,
+		CONFIG_V37,	   CONFIG_ELPT860,    CONFIG_CMI,
+		CONFIG_NETVIA,	   CONFIG_RBC823,     CONFIG_ZPC1900,
 		CONFIG_MPC8540ADS, CONFIG_MPC8560ADS, CONFIG_QS850,
-		CONFIG_QS823,      CONFIG_QS860T,     CONFIG_DB64360,
+		CONFIG_QS823,	   CONFIG_QS860T,     CONFIG_DB64360,
 		CONFIG_DB64460,	   CONFIG_DUET_ADS
 
 		ARM based boards:
 		-----------------
 
 		CONFIG_HHP_CRADLE,  CONFIG_DNP1110,    CONFIG_EP7312,
-		CONFIG_IMPA7,       CONFIG_LART,       CONFIG_LUBBOCK,
+		CONFIG_IMPA7,	    CONFIG_LART,       CONFIG_LUBBOCK,
 		CONFIG_INNOVATOROMAP1510,	CONFIG_INNOVATOROMAP1610
-		CONFIG_SHANNON,     CONFIG_SMDK2400,   CONFIG_SMDK2410,
+		CONFIG_SHANNON,	    CONFIG_SMDK2400,   CONFIG_SMDK2410,
 		CONFIG_TRAB,	    CONFIG_VCMA9,      CONFIG_AT91RM9200DK
 
 
@@ -430,12 +430,12 @@
 
 		CFG_MEASURE_CPUCLK
 
-                Define this to measure the actual CPU clock instead
-                of relying on the correctness of the configured
-                values. Mostly useful for board bringup to make sure
-                the PLL is locked at the intended frequency. Note
-                that this requires a (stable) reference clock (32 kHz
-                RTC clock),
+		Define this to measure the actual CPU clock instead
+		of relying on the correctness of the configured
+		values. Mostly useful for board bringup to make sure
+		the PLL is locked at the intended frequency. Note
+		that this requires a (stable) reference clock (32 kHz
+		RTC clock),
 
 - Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ
@@ -479,11 +479,11 @@
 						bit-blit (cf. smiLynxEM)
 			VIDEO_VISIBLE_COLS	visible pixel columns
 						(cols=pitch)
-			VIDEO_VISIBLE_ROWS      visible pixel rows
-			VIDEO_PIXEL_SIZE        bytes per pixel
+			VIDEO_VISIBLE_ROWS	visible pixel rows
+			VIDEO_PIXEL_SIZE	bytes per pixel
 			VIDEO_DATA_FORMAT	graphic data format
 						(0-5, cf. cfb_console.c)
-			VIDEO_FB_ADRS           framebuffer address
+			VIDEO_FB_ADRS		framebuffer address
 			VIDEO_KBD_INIT_FCT	keyboard int fct
 						(i.e. i8042_kbd_init())
 			VIDEO_TSTC_FCT		test char fct
@@ -619,15 +619,15 @@
 		CFG_CMD_AUTOSCRIPT Autoscript Support
 		CFG_CMD_BDI	  bdinfo
 		CFG_CMD_BEDBUG	  Include BedBug Debugger
-		CFG_CMD_BMP     * BMP support
+		CFG_CMD_BMP	* BMP support
 		CFG_CMD_BOOTD	  bootd
 		CFG_CMD_CACHE	  icache, dcache
 		CFG_CMD_CONSOLE	  coninfo
 		CFG_CMD_DATE	* support for RTC, date/time...
 		CFG_CMD_DHCP	  DHCP support
-		CFG_CMD_DIAG    * Diagnostics
-		CFG_CMD_DOC     * Disk-On-Chip Support
-		CFG_CMD_DTT       Digital Therm and Thermostat
+		CFG_CMD_DIAG	* Diagnostics
+		CFG_CMD_DOC	* Disk-On-Chip Support
+		CFG_CMD_DTT	  Digital Therm and Thermostat
 		CFG_CMD_ECHO	* echo arguments
 		CFG_CMD_EEPROM	* EEPROM read/write support
 		CFG_CMD_ELF	  bootelf, bootvx
@@ -637,37 +637,37 @@
 		CFG_CMD_FDOS	* Dos diskette Support
 		CFG_CMD_FLASH	  flinfo, erase, protect
 		CFG_CMD_FPGA	  FPGA device initialization support
-		CFG_CMD_HWFLOW  * RTS/CTS hw flow control
+		CFG_CMD_HWFLOW	* RTS/CTS hw flow control
 		CFG_CMD_I2C	* I2C serial bus support
 		CFG_CMD_IDE	* IDE harddisk support
 		CFG_CMD_IMI	  iminfo
-		CFG_CMD_IMLS      List all found images
+		CFG_CMD_IMLS	  List all found images
 		CFG_CMD_IMMAP	* IMMR dump support
 		CFG_CMD_IRQ	* irqinfo
-		CFG_CMD_JFFS2   * JFFS2 Support
+		CFG_CMD_JFFS2	* JFFS2 Support
 		CFG_CMD_KGDB	* kgdb
 		CFG_CMD_LOADB	  loadb
 		CFG_CMD_LOADS	  loads
 		CFG_CMD_MEMORY	  md, mm, nm, mw, cp, cmp, crc, base,
 				  loop, mtest
-		CFG_CMD_MISC      Misc functions like sleep etc
+		CFG_CMD_MISC	  Misc functions like sleep etc
 		CFG_CMD_MMC	  MMC memory mapped support
 		CFG_CMD_MII	  MII utility commands
-		CFG_CMD_NAND    * NAND support
+		CFG_CMD_NAND	* NAND support
 		CFG_CMD_NET	  bootp, tftpboot, rarpboot
 		CFG_CMD_PCI	* pciinfo
 		CFG_CMD_PCMCIA	* PCMCIA support
-		CFG_CMD_PING    * send ICMP ECHO_REQUEST to network host
-		CFG_CMD_PORTIO  * Port I/O
+		CFG_CMD_PING	* send ICMP ECHO_REQUEST to network host
+		CFG_CMD_PORTIO	* Port I/O
 		CFG_CMD_REGINFO * Register dump
 		CFG_CMD_RUN	  run command in env variable
-		CFG_CMD_SAVES     save S record dump
+		CFG_CMD_SAVES	  save S record dump
 		CFG_CMD_SCSI	* SCSI Support
-		CFG_CMD_SDRAM   * print SDRAM configuration information
+		CFG_CMD_SDRAM	* print SDRAM configuration information
 		CFG_CMD_SETGETDCR Support for DCR Register access (4xx only)
 		CFG_CMD_SPI	* SPI serial bus support
 		CFG_CMD_USB	* USB support
-		CFG_CMD_VFD     * VFD support (TRAB)
+		CFG_CMD_VFD	* VFD support (TRAB)
 		CFG_CMD_BSP	* Board SPecific functions
 		-----------------------------------------------
 		CFG_CMD_ALL	all
@@ -850,9 +850,9 @@
 		Following modes are supported  (* is default):
 
 			    800x600  1024x768  1280x1024
-	      256  (8bit)     303*      305       307
-	    65536 (16bit)     314       317       31a
-	16,7 Mill (24bit)     315       318       31b
+	      256  (8bit)     303*	305	  307
+	    65536 (16bit)     314	317	  31a
+	16,7 Mill (24bit)     315	318	  31b
 		(i.e. setenv videomode 317; saveenv; reset;)
 
 		CONFIG_VIDEO_SED13806
@@ -1031,7 +1031,7 @@
 		clock chips. See common/cmd_i2c.c for a description of the
 		command line interface.
 
-		CONFIG_HARD_I2C	selects the CPM hardware driver for I2C.
+		CONFIG_HARD_I2C selects the CPM hardware driver for I2C.
 
 		CONFIG_SOFT_I2C configures u-boot to use a software (aka
 		bit-banging) driver instead of CPM or similar hardware
@@ -1061,7 +1061,7 @@
 		(Optional). Any commands necessary to enable the I2C
 		controller or configure ports.
 
-		eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=  PB_SCL)
+		eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=	PB_SCL)
 
 		I2C_PORT
 
@@ -1099,7 +1099,7 @@
 
 		eg: #define I2C_SDA(bit) \
 			if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
 
 		I2C_SCL(bit)
 
@@ -1108,7 +1108,7 @@
 
 		eg: #define I2C_SCL(bit) \
 			if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
 
 		I2C_DELAY
 
@@ -1205,7 +1205,7 @@
 		Time to wait after FPGA configuration. The default is
 		200 mS.
 
-- FPGA Support:	CONFIG_FPGA_COUNT
+- FPGA Support: CONFIG_FPGA_COUNT
 
 		Specify the number of FPGA devices to support.
 
@@ -1422,11 +1422,11 @@
 
   Arg	Where			When
     1	common/cmd_bootm.c	before attempting to boot an image
-   -1	common/cmd_bootm.c	Image header has bad     magic number
+   -1	common/cmd_bootm.c	Image header has bad	 magic number
     2	common/cmd_bootm.c	Image header has correct magic number
-   -2	common/cmd_bootm.c	Image header has bad     checksum
+   -2	common/cmd_bootm.c	Image header has bad	 checksum
     3	common/cmd_bootm.c	Image header has correct checksum
-   -3	common/cmd_bootm.c	Image data   has bad     checksum
+   -3	common/cmd_bootm.c	Image data   has bad	 checksum
     4	common/cmd_bootm.c	Image data   has correct checksum
    -4	common/cmd_bootm.c	Image is for unsupported architecture
     5	common/cmd_bootm.c	Architecture check OK
@@ -1439,10 +1439,10 @@
     8	common/cmd_bootm.c	Image Type check OK
    -9	common/cmd_bootm.c	Unsupported OS (not Linux, BSD, VxWorks, QNX)
     9	common/cmd_bootm.c	Start initial ramdisk verification
-  -10	common/cmd_bootm.c	Ramdisk header has bad     magic number
-  -11	common/cmd_bootm.c	Ramdisk header has bad     checksum
+  -10	common/cmd_bootm.c	Ramdisk header has bad	   magic number
+  -11	common/cmd_bootm.c	Ramdisk header has bad	   checksum
    10	common/cmd_bootm.c	Ramdisk header is OK
-  -12	common/cmd_bootm.c	Ramdisk data   has bad     checksum
+  -12	common/cmd_bootm.c	Ramdisk data   has bad	   checksum
    11	common/cmd_bootm.c	Ramdisk data   has correct checksum
    12	common/cmd_bootm.c	Ramdisk verification complete, start loading
   -13	common/cmd_bootm.c	Wrong Image Type (not PPC Linux Ramdisk)
@@ -1470,7 +1470,7 @@
    -1	common/cmd_nand.c	Read Error on boot device
    -1	common/cmd_nand.c	Image header has bad magic number
 
-   -1	common/env_common.c     Environment has a bad CRC, using default
+   -1	common/env_common.c	Environment has a bad CRC, using default
 
 
 Modem Support:
@@ -1774,7 +1774,7 @@
 
 	- CFG_EEPROM_PAGE_WRITE_DELAY_MS:
 	  If defined, the number of milliseconds to delay between
-	  page writes.  The default is zero milliseconds.
+	  page writes.	The default is zero milliseconds.
 
 	- CFG_I2C_EEPROM_ADDR_LEN:
 	  The length in bytes of the EEPROM memory array address.  Note
@@ -1992,7 +1992,7 @@
 	CROSS_COMPILE = ppc_4xx-
 
 
-U-Boot is intended to be  simple  to  build.  After  installing  the
+U-Boot is intended to be  simple  to  build.  After  installing	 the
 sources	 you must configure U-Boot for one specific board type. This
 is done by typing:
 
@@ -2020,7 +2020,7 @@
     at91rm9200dk_config	  omap1510inn_config	MPC8260ADS_config
     omap1610inn_config	  ZPC1900_config	MPC8540ADS_config
     MPC8560ADS_config	  QS850_config		QS823_config
-    QS860T_config         DUET_ADS_config
+    QS860T_config	  DUET_ADS_config
 
 Note: for some board special configuration names may exist; check  if
       additional  information is available from the board vendor; for
@@ -2136,15 +2136,15 @@
 cp	- memory copy
 cmp	- memory compare
 crc32	- checksum calculation
-imd     - i2c memory display
-imm     - i2c memory modify (auto-incrementing)
-inm     - i2c memory modify (constant address)
-imw     - i2c memory write (fill)
-icrc32  - i2c checksum calculation
-iprobe  - probe to discover valid I2C chip addresses
-iloop   - infinite loop on address range
-isdram  - print SDRAM configuration information
-sspi    - SPI utility commands
+imd	- i2c memory display
+imm	- i2c memory modify (auto-incrementing)
+inm	- i2c memory modify (constant address)
+imw	- i2c memory write (fill)
+icrc32	- i2c checksum calculation
+iprobe	- probe to discover valid I2C chip addresses
+iloop	- infinite loop on address range
+isdram	- print SDRAM configuration information
+sspi	- SPI utility commands
 base	- print or set address offset
 printenv- print environment variables
 setenv	- set environment variables
@@ -2473,7 +2473,7 @@
 	make uImage
 
 The "uImage" build target uses a special tool (in 'tools/mkimage') to
-encapsulate a compressed Linux kernel image with header  information,
+encapsulate a compressed Linux kernel image with header	 information,
 CRC32 checksum etc. for use with U-Boot. This is what we are doing:
 
 * build a standard "vmlinux" kernel image (in ELF binary format):
@@ -2860,9 +2860,9 @@
 Nevertheless, if you absolutely want to use it try adding this
 configuration to your "File transfer protocols" section:
 
-	   Name    Program                      Name U/D FullScr IO-Red. Multi
-	X  kermit  /usr/bin/kermit -i -l %l -s   Y    U    Y       N      N
-	Y  kermit  /usr/bin/kermit -i -l %l -r   N    D    Y       N      N
+	   Name	   Program			Name U/D FullScr IO-Red. Multi
+	X  kermit  /usr/bin/kermit -i -l %l -s	 Y    U	   Y	   N	  N
+	Y  kermit  /usr/bin/kermit -i -l %l -r	 N    D	   Y	   N	  N
 
 
 NetBSD Notes:
@@ -2918,7 +2918,7 @@
 MPC826x processors), on others (parts of) the data cache can be
 locked as (mis-) used as memory, etc.
 
-	Chris Hallinan posted a good summary of  these  issues  to  the
+	Chris Hallinan posted a good summary of	 these	issues	to  the
 	u-boot-users mailing list:
 
 	Subject: RE: [U-Boot-Users] RE: More On Memory Bank x (nothingness)?
@@ -2987,7 +2987,7 @@
 	R1:	stack pointer
 	R2:	TOC pointer
 	R3-R4:	parameter passing and return values
-	R5-R10:	parameter passing
+	R5-R10: parameter passing
 	R13:	small data area pointer
 	R30:	GOT pointer
 	R31:	frame pointer
diff --git a/board/xpedite1k/Makefile b/board/xpedite1k/Makefile
new file mode 100644
index 0000000..c5c0915
--- /dev/null
+++ b/board/xpedite1k/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2002-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o
+OBJS +=flash.o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/xpedite1k/config.mk b/board/xpedite1k/config.mk
new file mode 100644
index 0000000..c0f0da8
--- /dev/null
+++ b/board/xpedite1k/config.mk
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2002-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0xFFFE0000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/xpedite1k/flash.c b/board/xpedite1k/flash.c
new file mode 100644
index 0000000..ce5d4e1
--- /dev/null
+++ b/board/xpedite1k/flash.c
@@ -0,0 +1,607 @@
+/*
+ * (C) Copyright 2002-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+/*
+ * Ported to XPedite1000, 1/2 mb boot flash only
+ * Travis B. Sawyer, <travis.sawyer@sandburst.com>
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+#define BOOT_SMALL_FLASH	32		/* 00100000 */
+#define FLASH_ONBD_N		2		/* 00000010 */
+#define FLASH_SRAM_SEL		1		/* 00000001 */
+
+#define BOOT_SMALL_FLASH_VAL	4
+#define FLASH_ONBD_N_VAL	2
+#define FLASH_SRAM_SEL_VAL	1
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+	{0xfff80000},	/* 0:000: configuraton 3 */
+	{0xfff90000},	/* 1:001: configuraton 4 */
+	{0xfffa0000},	/* 2:010: configuraton 7 */
+	{0xfffb0000},	/* 3:011: configuraton 8 */
+	{0xfffc0000},	/* 4:100: configuraton 1 */
+	{0xfffd0000},	/* 5:101: configuraton 2 */
+	{0xfffe0000},	/* 6:110: configuraton 5 */
+	{0xffff0000}	/* 7:111: configuraton 6 */
+};
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+
+#ifdef CONFIG_XPEDITE1K
+#define ADDR0		0x5555
+#define ADDR1		0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	unsigned short index = 0;
+	int i;
+
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0) {
+			continue;
+		}
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size(
+			(vu_long *)flash_addr_table[index][i], &flash_info[i]);
+		flash_info[i].size = size_b[i];
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+				i, size_b[i], size_b[i]<<20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMD016:	printf ("AM29F016D (16 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_AM040:	printf ("AM29F040 (512 Kbit, uniform sector size)\n");
+		break;
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_SST800A:	printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_SST160A:	printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+		break;
+	default:		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+			size = info->start[i+1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;	 /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		{
+			if (*flash++ != 0xffffffff)
+			{
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+			printf (" %08lX%s%s",
+				info->start[i],
+				erased ? " E" : "  ",
+				info->protect[i] ? "RO " : "   "
+				);
+			}
+		printf ("\n");
+		return;
+	}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	FLASH_WORD_SIZE value;
+	ulong base = (ulong)addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr );
+
+	/* Write auto select command: read Manufacturer ID */
+	udelay(10000);
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+	udelay(1000);
+	addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+	udelay(1000);
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
+	udelay(1000);
+
+#ifdef CONFIG_ADCIOP
+	value = addr2[2];
+#else
+	value = addr2[0];
+#endif
+
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FLASH_WORD_SIZE)FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (FLASH_WORD_SIZE)SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (FLASH_WORD_SIZE)STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+#ifdef CONFIG_ADCIOP
+	value = addr2[0];			/* device ID		*/
+	debug ("\ndev_code=%x\n", value);
+#else
+	value = addr2[1];			/* device ID		*/
+#endif
+
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000; /* => 512 kb */
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+		    (info->flash_id  == FLASH_AM040) ||
+		    (info->flash_id  == FLASH_AMD016)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type	*/
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type		*/
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+#ifdef CONFIG_ADCIOP
+		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		info->protect[i] = addr2[4] & 1;
+#else
+		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+#endif
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+#if 0 /* test-only */
+#ifdef CONFIG_ADCIOP
+		addr2 = (volatile unsigned char *)info->start[0];
+		addr2[ADDR0] = 0xAA;
+		addr2[ADDR1] = 0x55;
+		addr2[ADDR0] = 0xF0;  /* reset bank */
+#else
+		addr2 = (FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+#endif
+#else /* test-only */
+		addr2 = (FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+#endif /* test-only */
+	}
+
+	return (info->size);
+}
+
+int wait_for_DQ7(flash_info_t *info, int sect)
+{
+	ulong start, now, last;
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+
+	start = get_timer (0);
+	last  = start;
+	while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {  /* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
+			printf("Erasing sector %p\n", addr2);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE)0x00500050;	 /* block erase */
+				for (i=0; i<50; i++)
+					udelay(1000);  /* wait 1 ms */
+			} else {
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE)0x00300030;	 /* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+#if 0
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+	wait_for_DQ7(info, l_sect);
+
+DONE:
+#endif
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile FLASH_WORD_SIZE *) dest) &
+	     (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts ();
+
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/xpedite1k/init.S b/board/xpedite1k/init.S
new file mode 100644
index 0000000..6cb20e4
--- /dev/null
+++ b/board/xpedite1k/init.S
@@ -0,0 +1,96 @@
+/*
+*  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)		( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+	tlbtab_end
diff --git a/board/xpedite1k/u-boot.lds b/board/xpedite1k/u-boot.lds
new file mode 100644
index 0000000..3f964c8
--- /dev/null
+++ b/board/xpedite1k/u-boot.lds
@@ -0,0 +1,155 @@
+/*
+ * (C) Copyright 2002-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/xpedite1k/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/405gp_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/xpedite1k/u-boot.lds.debug b/board/xpedite1k/u-boot.lds.debug
new file mode 100644
index 0000000..3530c98
--- /dev/null
+++ b/board/xpedite1k/u-boot.lds.debug
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2002-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/xpedite1k/init.o (.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/405gp_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    common/environment.o(.text) */
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/xpedite1k/xpedite1k.c b/board/xpedite1k/xpedite1k.c
new file mode 100644
index 0000000..c025c85
--- /dev/null
+++ b/board/xpedite1k/xpedite1k.c
@@ -0,0 +1,358 @@
+/*
+ *  Copyright (C) 2003 Travis B. Sawyer	 <travis.sawyer@sandburst.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+
+#define BOOT_SMALL_FLASH	32	/* 00100000 */
+#define FLASH_ONBD_N		2	/* 00000010 */
+#define FLASH_SRAM_SEL		1	/* 00000001 */
+
+long int fixed_sdram (void);
+
+int board_pre_init (void)
+{
+	unsigned long sdrreg;
+	/* TBS:	 Setup the GPIO access for the user LEDs */
+	mfsdr(sdr_pfc0, sdrreg);
+	mtsdr(sdr_pfc0, (sdrreg & ~0x00000100) | 0x00000E00);
+	out32(CFG_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
+	LED0_OFF();
+	LED1_OFF();
+	LED2_OFF();
+	LED3_OFF();
+
+	/*--------------------------------------------------------------------
+	 * Setup the external bus controller/chip selects
+	 *-------------------------------------------------------------------*/
+
+	/* set the bus controller */
+	mtebc (pb0ap, 0x04055200);	/* FLASH/SRAM */
+	mtebc (pb0cr, 0xfff18000);	/* BAS=0xfff 1MB R/W 8-bit */
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+	mtdcr (uic0er, 0x00000000);	/* disable all */
+	mtdcr (uic0cr, 0x00000003);	/* SMI & UIC1 crit are critical */
+	mtdcr (uic0pr, 0xfffffe00);	/* per ref-board manual */
+	mtdcr (uic0tr, 0x01c00000);	/* per ref-board manual */
+	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+	mtdcr (uic1er, 0x00000000);	/* disable all */
+	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic1pr, 0xffffc0ff);	/* per ref-board manual */
+	mtdcr (uic1tr, 0x00ff8000);	/* per ref-board manual */
+	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+	mtdcr (uic2er, 0x00000000);	/* disable all */
+	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic2pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr (uic2tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uicb0sr, 0xfc000000); /* clear all */
+	mtdcr (uicb0er, 0x00000000); /* disable all */
+	mtdcr (uicb0cr, 0x00000000); /* all non-critical */
+	mtdcr (uicb0pr, 0xfc000000); /* */
+	mtdcr (uicb0tr, 0x00000000); /* */
+	mtdcr (uicb0vr, 0x00000001); /* */
+
+	LED0_ON();
+
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	sys_info_t sysinfo;
+	get_sys_info (&sysinfo);
+
+	printf ("Board: XES XPedite1000 440GX\n");
+	printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
+	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+	printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+	printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+	printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
+
+	return (0);
+}
+
+
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram (0);
+#else
+	dram_size = fixed_sdram ();
+#endif
+	return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) 0x00000000;
+	uint *pend = (uint *) 0x08000000;
+	uint *p;
+
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ *
+ *  Assumes:	128 MB, non-ECC, non-registered
+ *		PLB @ 133 MHz
+ *
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+	uint reg;
+
+	/*--------------------------------------------------------------------
+	 * Setup some default
+	 *------------------------------------------------------------------*/
+	mtsdram (mem_uabba, 0x00000000);	/* ubba=0 (default)		*/
+	mtsdram (mem_slio, 0x00000000);		/* rdre=0 wrre=0 rarw=0		*/
+	mtsdram (mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)		*/
+	mtsdram (mem_wddctr, 0x00000000);	/* wrcp=0 dcd=0			*/
+	mtsdram (mem_clktr, 0x40000000);	/* clkp=1 (90 deg wr) dcdt=0	*/
+
+	/*--------------------------------------------------------------------
+	 * Setup for board-specific specific mem
+	 *------------------------------------------------------------------*/
+	/*
+	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
+	 */
+	mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+	mtsdram (mem_tr0, 0x410a4012);	/* WR=2	 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+	/* RA=10 RD=3			    */
+	mtsdram (mem_tr1, 0x8080082f);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
+	mtsdram (mem_rtr, 0x08200000);	/* Rate 15.625 ns @ 133 MHz PLB	    */
+	mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM    */
+	udelay (400);			/* Delay 200 usecs (min)	    */
+
+	/*--------------------------------------------------------------------
+	 * Enable the controller, then wait for DCEN to complete
+	 *------------------------------------------------------------------*/
+	mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit	    */
+	for (;;) {
+		mfsdram (mem_mcsts, reg);
+		if (reg & 0x80000000)
+			break;
+	}
+
+	return (128 * 1024 * 1024);	/* 128 MB			    */
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
+
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller * hose )
+{
+	unsigned long strap;
+
+	/*--------------------------------------------------------------------------+
+	 * TBS:
+	 *	The xpedite1k is a PrPMC board, however for our purposes it is the host
+	 *--------------------------------------------------------------------------*/
+	strap = mfdcr(cpc0_strp1);
+	if( (strap & 0x00100000) == 0 ){
+		printf("PCI: CPC0_STRP1[PAE] not set.\n");
+		return 0;
+	}
+
+	return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller * hose )
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/*--------------------------------------------------------------------------+
+	 * Disable everything
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0SA, 0 ); /* disable */
+	out32r( PCIX0_PIM1SA, 0 ); /* disable */
+	out32r( PCIX0_PIM2SA, 0 ); /* disable */
+	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+
+	/*--------------------------------------------------------------------------+
+	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+	 * options to not support sizes such as 128/256 MB.
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAH, 0 );
+	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+
+	out32r( PCIX0_BAR0, 0 );
+
+	/*--------------------------------------------------------------------------+
+	 * Program the board's subsystem id/vendor id
+	 *--------------------------------------------------------------------------*/
+	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+
+	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	/* The ebony board is always configured as host. */
+	/* TBS:	 The xpedite1k is not necessarily the host, however for our purposes, it is. */
+	return(1);
+}
+#endif /* defined(CONFIG_PCI) */
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+
+	return (ctrlc());
+}
+
+void post_word_store (ulong a)
+{
+	volatile ulong *save_addr =
+		(volatile ulong *)(CFG_POST_WORD_ADDR);
+
+	*save_addr = a;
+}
+
+ulong post_word_load (void)
+{
+	volatile ulong *save_addr =
+		(volatile ulong *)(CFG_POST_WORD_ADDR);
+
+	return *save_addr;
+}
+#endif
+
+/*-----------------------------------------------------------------------------
+ * board_get_enetaddr -- Read the MAC Addresses in the I2C EEPROM
+ *-----------------------------------------------------------------------------
+ */
+static int enetaddr_num = 0;
+void board_get_enetaddr (uchar * enet)
+{
+	int i;
+	unsigned char buff[0x100], *cp;
+
+	/* Initialize I2C					*/
+	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+	/* Read 256 bytes in EEPROM				*/
+	i2c_read (0x50, 0, 1, buff, 0x100);
+
+	if (enetaddr_num == 0) {
+		cp = &buff[0xF4];
+		enetaddr_num = 1;
+	}
+	else
+		cp = &buff[0xFA];
+
+	for (i = 0; i < 6; i++,cp++)
+		enet[i] = *cp;
+
+	printf ("MAC address = %02x:%02x:%02x:%02x:%02x:%02x\n",
+		enet[0], enet[1], enet[2], enet[3], enet[4], enet[5]);
+
+}
diff --git a/cpu/ppc4xx/405gp_enet.c b/cpu/ppc4xx/405gp_enet.c
index 7394c21..65036d1 100644
--- a/cpu/ppc4xx/405gp_enet.c
+++ b/cpu/ppc4xx/405gp_enet.c
@@ -83,7 +83,8 @@
 #include <malloc.h>
 #include "vecnum.h"
 
-#if defined(CONFIG_405GP) || defined(CONFIG_440) || defined(CONFIG_405EP)
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
+  ( defined(CONFIG_440)   && !defined(CONFIG_NET_MULTI))
 
 #define EMAC_RESET_TIMEOUT 1000	/* 1000 ms reset timeout */
 #define PHY_AUTONEGOTIATE_TIMEOUT 4000	/* 4000 ms autonegotiate timeout */
diff --git a/cpu/ppc4xx/440gx_enet.c b/cpu/ppc4xx/440gx_enet.c
new file mode 100644
index 0000000..617a174
--- /dev/null
+++ b/cpu/ppc4xx/440gx_enet.c
@@ -0,0 +1,1144 @@
+/*-----------------------------------------------------------------------------+
+ *
+ *       This source code has been made available to you by IBM on an AS-IS
+ *       basis.  Anyone receiving this source is licensed under IBM
+ *       copyrights to use it in any way he or she deems fit, including
+ *       copying it, modifying it, compiling it, and redistributing it either
+ *       with or without modifications.  No license under IBM patents or
+ *       patent applications is to be implied by the copyright license.
+ *
+ *       Any user of this software should understand that IBM cannot provide
+ *       technical support for this software and will not be responsible for
+ *       any consequences resulting from the use of this software.
+ *
+ *       Any person who transfers this source code or any derivative work
+ *       must include the IBM copyright notice, this paragraph, and the
+ *       preceding two paragraphs in the transferred software.
+ *
+ *       COPYRIGHT   I B M   CORPORATION 1995
+ *       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *-----------------------------------------------------------------------------*/
+/*-----------------------------------------------------------------------------+
+ *
+ *  File Name:  enetemac.c
+ *
+ *  Function:   Device driver for the ethernet EMAC3 macro on the 405GP.
+ *
+ *  Author:     Mark Wisner
+ *
+ *  Change Activity-
+ *
+ *  Date        Description of Change                                       BY
+ *  ---------   ---------------------                                       ---
+ *  05-May-99   Created                                                     MKW
+ *  27-Jun-99   Clean up                                                    JWB
+ *  16-Jul-99   Added MAL error recovery and better IP packet handling      MKW
+ *  29-Jul-99   Added Full duplex support                                   MKW
+ *  06-Aug-99   Changed names for Mal CR reg                                MKW
+ *  23-Aug-99   Turned off SYE when running at 10Mbs                        MKW
+ *  24-Aug-99   Marked descriptor empty after call_xlc                      MKW
+ *  07-Sep-99   Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16     MCG
+ *              to avoid chaining maximum sized packets. Push starting
+ *              RX descriptor address up to the next cache line boundary.
+ *  16-Jan-00   Added support for booting with IP of 0x0                    MKW
+ *  15-Mar-00   Updated enetInit() to enable broadcast addresses in the
+ *	        EMAC_RXM register.                                          JWB
+ *  12-Mar-01   anne-sophie.harnois@nextream.fr
+ *               - Variables are compatible with those already defined in
+ *                include/net.h
+ *              - Receive buffer descriptor ring is used to send buffers
+ *                to the user
+ *              - Info print about send/received/handled packet number if
+ *                INFO_405_ENET is set
+ *  17-Apr-01   stefan.roese@esd-electronics.com
+ *              - MAL reset in "eth_halt" included
+ *              - Enet speed and duplex output now in one line
+ *  08-May-01   stefan.roese@esd-electronics.com
+ *              - MAL error handling added (eth_init called again)
+ *  13-Nov-01   stefan.roese@esd-electronics.com
+ *              - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
+ *  04-Jan-02   stefan.roese@esd-electronics.com
+ *              - Wait for PHY auto negotiation to complete added
+ *  06-Feb-02   stefan.roese@esd-electronics.com
+ *              - Bug fixed in waiting for auto negotiation to complete
+ *  26-Feb-02   stefan.roese@esd-electronics.com
+ *              - rx and tx buffer descriptors now allocated (no fixed address
+ *                used anymore)
+ *  17-Jun-02   stefan.roese@esd-electronics.com
+ *              - MAL error debug printf 'M' removed (rx de interrupt may
+ *                occur upon many incoming packets with only 4 rx buffers).
+ *-----------------------------------------------------------------------------*
+ *  17-Nov-03   travis.sawyer@sandburst.com
+ *              - ported from 405gp_enet.c to utilized upto 4 EMAC ports
+ *                in the 440GX.  This port should work with the 440GP
+ *                (2 EMACs) also
+ *-----------------------------------------------------------------------------*/
+
+#include <config.h>
+#if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
+
+#include <common.h>
+#include <net.h>
+#include <asm/processor.h>
+#include <ppc440.h>
+#include <commproc.h>
+#include <440gx_enet.h>
+#include <405_mal.h>
+#include <miiphy.h>
+#include <malloc.h>
+#include "vecnum.h"
+
+
+#define EMAC_RESET_TIMEOUT 1000	/* 1000 ms reset timeout */
+#define PHY_AUTONEGOTIATE_TIMEOUT 4000	/* 4000 ms autonegotiate timeout */
+
+
+/* Ethernet Transmit and Receive Buffers */
+/* AS.HARNOIS
+ * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
+ * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
+ */
+#define ENET_MAX_MTU           PKTSIZE
+#define ENET_MAX_MTU_ALIGNED   PKTSIZE_ALIGN
+
+
+/* define the number of channels implemented */
+#define EMAC_RXCHL      EMAC_NUM_DEV
+#define EMAC_TXCHL      EMAC_NUM_DEV
+
+/*-----------------------------------------------------------------------------+
+ * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
+ * Interrupt Controller).
+ *-----------------------------------------------------------------------------*/
+#define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE  | UIC_MAL_RXDE)
+#define MAL_UIC_DEF  (UIC_MAL_RXEOB | MAL_UIC_ERR)
+#define EMAC_UIC_DEF UIC_ENET
+
+#undef INFO_440_ENET
+
+/*-----------------------------------------------------------------------------+
+ * Global variables. TX and RX descriptors and buffers.
+ *-----------------------------------------------------------------------------*/
+/* IER globals */
+static uint32_t mal_ier;
+
+/*-----------------------------------------------------------------------------+
+ * Prototypes and externals.
+ *-----------------------------------------------------------------------------*/
+static void enet_rcv (struct eth_device *dev, unsigned long malisr);
+
+int enetInt (struct eth_device *dev);
+static void mal_err (struct eth_device *dev, unsigned long isr,
+		     unsigned long uic, unsigned long maldef,
+		     unsigned long mal_errr);
+static void emac_err (struct eth_device *dev, unsigned long isr);
+
+/*-----------------------------------------------------------------------------+
+| ppc_440x_eth_halt
+| Disable MAL channel, and EMACn
+|
+|
++-----------------------------------------------------------------------------*/
+static void ppc_440x_eth_halt (struct eth_device *dev)
+{
+	EMAC_440GX_HW_PST hw_p = dev->priv;
+	uint32_t failsafe = 10000;
+
+	out32 (EMAC_IER + hw_p->hw_addr, 0x00000000);	/* disable emac interrupts */
+
+	/* 1st reset MAL channel */
+	/* Note: writing a 0 to a channel has no effect */
+	mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
+	mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
+
+	/* wait for reset */
+	while (mfdcr (maltxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
+		udelay (1000);	/* Delay 1 MS so as not to hammer the register */
+		failsafe--;
+		if (failsafe == 0)
+			break;
+
+	}
+
+	/* EMAC RESET */
+	out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
+
+	hw_p->print_speed = 1;	/* print speed message again next time */
+
+	return;
+}
+
+extern int phy_setup_aneg (unsigned char addr);
+extern int miiphy_reset (unsigned char addr);
+
+static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
+{
+	int i;
+	unsigned long reg;
+	unsigned long msr;
+	unsigned long speed;
+	unsigned long duplex;
+	unsigned long failsafe;
+	unsigned mode_reg;
+	unsigned short devnum;
+	unsigned short reg_short;
+	sys_info_t sysinfo;
+
+	EMAC_440GX_HW_PST hw_p = dev->priv;
+
+	/* before doing anything, figure out if we have a MAC address */
+	/* if not, bail */
+	if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0)
+		return -1;
+
+	/* Need to get the OPB frequency so we can access the PHY */
+	get_sys_info (&sysinfo);
+
+
+	msr = mfmsr ();
+	mtmsr (msr & ~(MSR_EE));	/* disable interrupts */
+
+	devnum = hw_p->devnum;
+
+#ifdef INFO_440_ENET
+	/* AS.HARNOIS
+	 * We should have :
+	 * hw_p->stats.pkts_handled <=  hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
+	 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
+	 * is possible that new packets (without relationship with
+	 * current transfer) have got the time to arrived before
+	 * netloop calls eth_halt
+	 */
+	printf ("About preceeding transfer (eth%d):\n"
+		"- Sent packet number %d\n"
+		"- Received packet number %d\n"
+		"- Handled packet number %d\n",
+		hw_p->devnum,
+		hw_p->stats.pkts_tx,
+		hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
+
+	hw_p->stats.pkts_tx = 0;
+	hw_p->stats.pkts_rx = 0;
+	hw_p->stats.pkts_handled = 0;
+#endif
+
+	/* MAL Channel RESET */
+	/* 1st reset MAL channel */
+	/* Note: writing a 0 to a channel has no effect */
+	mtdcr (maltxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
+	mtdcr (malrxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
+
+	/* wait for reset */
+	/* TBS:  should have udelay and failsafe here */
+	failsafe = 10000;
+	/* wait for reset */
+	while (mfdcr (maltxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
+		udelay (1000);	/* Delay 1 MS so as not to hammer the register */
+		failsafe--;
+		if (failsafe == 0)
+			break;
+
+	}
+
+	hw_p->tx_err_index = 0;	/* Transmit Error Index for tx_err_log */
+	hw_p->rx_err_index = 0;	/* Receive Error Index for rx_err_log */
+
+	hw_p->rx_slot = 0;	/* MAL Receive Slot */
+	hw_p->rx_i_index = 0;	/* Receive Interrupt Queue Index */
+	hw_p->rx_u_index = 0;	/* Receive User Queue Index */
+
+	hw_p->tx_slot = 0;	/* MAL Transmit Slot */
+	hw_p->tx_i_index = 0;	/* Transmit Interrupt Queue Index */
+	hw_p->tx_u_index = 0;	/* Transmit User Queue Index */
+
+	/* set RMII mode */
+	/* NOTE: 440GX spec states that mode is mutually exclusive */
+	/* NOTE: Therefore, disable all other EMACS, since we handle */
+	/* NOTE: only one emac at a time */
+	reg = 0;
+	out32 (ZMII_FER, 0);
+	udelay (100);
+	out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
+	out32 (ZMII_SSR, 0x11110000);
+	/* reset emac so we have access to the phy */
+	__asm__ volatile ("eieio");
+
+	out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
+	__asm__ volatile ("eieio");
+
+	if ((devnum == 2) || (devnum == 3))
+		out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
+				   (RGMII_FER_RGMII << RGMII_FER_V (3))));
+	__asm__ volatile ("eieio");
+
+	failsafe = 1000;
+	while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
+		udelay (1000);
+		failsafe--;
+	}
+
+	/* Whack the M1 register */
+	mode_reg = 0x0;
+	mode_reg &= ~0x00000038;
+	if (sysinfo.freqOPB <= 50000000);
+	else if (sysinfo.freqOPB <= 66666667)
+		mode_reg |= EMAC_M1_OBCI_66;
+	else if (sysinfo.freqOPB <= 83333333)
+		mode_reg |= EMAC_M1_OBCI_83;
+	else if (sysinfo.freqOPB <= 100000000)
+		mode_reg |= EMAC_M1_OBCI_100;
+	else
+		mode_reg |= EMAC_M1_OBCI_GT100;
+
+	out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
+
+
+	/* wait for PHY to complete auto negotiation */
+	reg_short = 0;
+#ifndef CONFIG_CS8952_PHY
+	switch (devnum) {
+	case 0:
+		reg = CONFIG_PHY_ADDR;
+		break;
+	case 1:
+		reg = CONFIG_PHY1_ADDR;
+		break;
+#if defined (CONFIG_440_GX)
+	case 2:
+		reg = CONFIG_PHY2_ADDR;
+		break;
+	case 3:
+		reg = CONFIG_PHY3_ADDR;
+		break;
+#endif
+	default:
+		reg = CONFIG_PHY_ADDR;
+		break;
+	}
+
+	/* Reset the phy */
+	miiphy_reset (reg);
+
+	/* Start/Restart autonegotiation */
+/*	miiphy_write(reg, PHY_BMCR, 0x9340); */
+	phy_setup_aneg (reg);
+	udelay (1000);
+
+	miiphy_read (reg, PHY_BMSR, &reg_short);
+
+	/*
+	 * Wait if PHY is able of autonegotiation and autonegotiation is not complete
+	 */
+	if ((reg_short & PHY_BMSR_AUTN_ABLE)
+	    && !(reg_short & PHY_BMSR_AUTN_COMP)) {
+		puts ("Waiting for PHY auto negotiation to complete");
+		i = 0;
+		while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
+			/*
+			 * Timeout reached ?
+			 */
+			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
+				puts (" TIMEOUT !\n");
+				break;
+			}
+
+			if ((i++ % 1000) == 0) {
+				putc ('.');
+			}
+			udelay (1000);	/* 1 ms */
+			miiphy_read (reg, PHY_BMSR, &reg_short);
+
+		}
+		puts (" done\n");
+		udelay (500000);	/* another 500 ms (results in faster booting) */
+	}
+#endif
+	speed = miiphy_speed (reg);
+	duplex = miiphy_duplex (reg);
+
+	if (hw_p->print_speed) {
+		hw_p->print_speed = 0;
+		printf ("ENET Speed is %d Mbps - %s duplex connection\n",
+			(int) speed, (duplex == HALF) ? "HALF" : "FULL");
+	}
+
+	/* Set ZMII/RGMII speed according to the phy link speed */
+	reg = in32 (ZMII_SSR);
+	if (speed == 100)
+		out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
+	else
+		out32 (ZMII_SSR,
+		       reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
+
+	if ((devnum == 2) || (devnum == 3)) {
+		if (speed == 1000)
+			reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
+		else if (speed == 100)
+			reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
+		else
+			reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
+
+		out32 (RGMII_SSR, reg);
+	}
+
+	/* set the Mal configuration reg */
+	/* Errata 1.12: MAL_1 -- Disable MAL bursting */
+	if (get_pvr () == PVR_440GP_RB)
+		mtdcr (malmcr,
+		       MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
+	else
+		mtdcr (malmcr,
+		       MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
+		       MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
+
+	/* Free "old" buffers */
+	if (hw_p->alloc_tx_buf)
+		free (hw_p->alloc_tx_buf);
+	if (hw_p->alloc_rx_buf)
+		free (hw_p->alloc_rx_buf);
+
+	/*
+	 * Malloc MAL buffer desciptors, make sure they are
+	 * aligned on cache line boundary size
+	 * (401/403/IOP480 = 16, 405 = 32)
+	 * and doesn't cross cache block boundaries.
+	 */
+	hw_p->alloc_tx_buf =
+		(mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
+				       ((2 * CFG_CACHELINE_SIZE) - 2));
+	if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
+		hw_p->tx =
+			(mal_desc_t *) ((int) hw_p->alloc_tx_buf +
+					CFG_CACHELINE_SIZE -
+					((int) hw_p->
+					 alloc_tx_buf & CACHELINE_MASK));
+	} else {
+		hw_p->tx = hw_p->alloc_tx_buf;
+	}
+
+	hw_p->alloc_rx_buf =
+		(mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
+				       ((2 * CFG_CACHELINE_SIZE) - 2));
+	if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
+		hw_p->rx =
+			(mal_desc_t *) ((int) hw_p->alloc_rx_buf +
+					CFG_CACHELINE_SIZE -
+					((int) hw_p->
+					 alloc_rx_buf & CACHELINE_MASK));
+	} else {
+		hw_p->rx = hw_p->alloc_rx_buf;
+	}
+
+	for (i = 0; i < NUM_TX_BUFF; i++) {
+		hw_p->tx[i].ctrl = 0;
+		hw_p->tx[i].data_len = 0;
+		if (hw_p->first_init == 0)
+			hw_p->txbuf_ptr =
+				(char *) malloc (ENET_MAX_MTU_ALIGNED);
+		hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
+		if ((NUM_TX_BUFF - 1) == i)
+			hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
+		hw_p->tx_run[i] = -1;
+#if 0
+		printf ("TX_BUFF %d @ 0x%08lx\n", i,
+			(ulong) hw_p->tx[i].data_ptr);
+#endif
+	}
+
+	for (i = 0; i < NUM_RX_BUFF; i++) {
+		hw_p->rx[i].ctrl = 0;
+		hw_p->rx[i].data_len = 0;
+		/*       rx[i].data_ptr = (char *) &rx_buff[i]; */
+		hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
+		if ((NUM_RX_BUFF - 1) == i)
+			hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
+		hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
+		hw_p->rx_ready[i] = -1;
+#if 0
+		printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
+#endif
+	}
+
+	reg = 0x00000000;
+
+	reg |= dev->enetaddr[0];	/* set high address */
+	reg = reg << 8;
+	reg |= dev->enetaddr[1];
+
+	out32 (EMAC_IAH + hw_p->hw_addr, reg);
+
+	reg = 0x00000000;
+	reg |= dev->enetaddr[2];	/* set low address  */
+	reg = reg << 8;
+	reg |= dev->enetaddr[3];
+	reg = reg << 8;
+	reg |= dev->enetaddr[4];
+	reg = reg << 8;
+	reg |= dev->enetaddr[5];
+
+	out32 (EMAC_IAL + hw_p->hw_addr, reg);
+
+	switch (devnum) {
+	case 1:
+		/* setup MAL tx & rx channel pointers */
+		mtdcr (maltxbattr, 0x0);
+		mtdcr (maltxctp1r, hw_p->tx);
+		mtdcr (malrxbattr, 0x0);
+		mtdcr (malrxctp1r, hw_p->rx);
+		/* set RX buffer size */
+		mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
+		break;
+#if defined (CONFIG_440_GX)
+	case 2:
+		/* setup MAL tx & rx channel pointers */
+		mtdcr (maltxbattr, 0x0);
+		mtdcr (maltxctp2r, hw_p->tx);
+		mtdcr (malrxbattr, 0x0);
+		mtdcr (malrxctp2r, hw_p->rx);
+		/* set RX buffer size */
+		mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
+		break;
+	case 3:
+		/* setup MAL tx & rx channel pointers */
+		mtdcr (maltxbattr, 0x0);
+		mtdcr (maltxctp3r, hw_p->tx);
+		mtdcr (malrxbattr, 0x0);
+		mtdcr (malrxctp3r, hw_p->rx);
+		/* set RX buffer size */
+		mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
+		break;
+#endif /*CONFIG_440_GX */
+	case 0:
+	default:
+		/* setup MAL tx & rx channel pointers */
+		mtdcr (maltxbattr, 0x0);
+		mtdcr (maltxctp0r, hw_p->tx);
+		mtdcr (malrxbattr, 0x0);
+		mtdcr (malrxctp0r, hw_p->rx);
+		/* set RX buffer size */
+		mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
+		break;
+	}
+
+	/* Enable MAL transmit and receive channels */
+	mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
+	mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
+
+	/* set transmit enable & receive enable */
+	out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
+
+	/* set receive fifo to 4k and tx fifo to 2k */
+	mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
+	mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
+
+	/* set speed */
+	/* TBS: do 1GbE */
+	if (speed == _100BASET)
+		mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
+	else
+		mode_reg = mode_reg & ~0x00C00000;	/* 10 MBPS */
+	if (duplex == FULL)
+		mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
+
+	out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
+
+	/* Enable broadcast and indvidual address */
+	/* TBS: enabling runts as some misbehaved nics will send runts */
+	out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
+
+	/* we probably need to set the tx mode1 reg? maybe at tx time */
+
+	/* set transmit request threshold register */
+	out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000);	/* 256 byte threshold */
+
+	/* set receive  low/high water mark register */
+	/* 440GP has a 64 byte burst length */
+	out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
+	out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
+
+	/* Set fifo limit entry in tx mode 0 */
+	out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
+	/* Frame gap set */
+	out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
+
+	/* Set EMAC IER */
+	hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
+		EMAC_ISR_PTLE | EMAC_ISR_ORE | EMAC_ISR_IRE;
+	if (speed == _100BASET)
+		hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
+
+	out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff);	/* clear pending interrupts */
+	out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
+
+	if (hw_p->first_init == 0) {
+		/*
+		 * Connect interrupt service routines
+		 */
+		irq_install_handler (VECNUM_EWU0 + (hw_p->devnum * 2),
+				     (interrupt_handler_t *) enetInt, dev);
+		irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
+				     (interrupt_handler_t *) enetInt, dev);
+	}
+#if 0				/* done by irq_install_handler */
+	/* set up interrupt handler */
+	/* setup interrupt controller to take interrupts from the MAL &
+	   EMAC */
+	mtdcr (uicsr, 0xffffffff);	/* clear pending interrupts */
+	mtdcr (uicer, mfdcr (uicer) | MAL_UIC_DEF | EMAC_UIC_DEF);
+#endif
+
+	mtmsr (msr);		/* enable interrupts again */
+
+	hw_p->bis = bis;
+	hw_p->first_init = 1;
+
+	return (1);
+}
+
+
+static int ppc_440x_eth_send (struct eth_device *dev, volatile void *ptr,
+			      int len)
+{
+	struct enet_frame *ef_ptr;
+	ulong time_start, time_now;
+	unsigned long temp_txm0;
+	EMAC_440GX_HW_PST hw_p = dev->priv;
+
+	ef_ptr = (struct enet_frame *) ptr;
+
+	/*-----------------------------------------------------------------------+
+	 *  Copy in our address into the frame.
+	 *-----------------------------------------------------------------------*/
+	(void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
+
+	/*-----------------------------------------------------------------------+
+	 * If frame is too long or too short, modify length.
+	 *-----------------------------------------------------------------------*/
+	/* TBS: where does the fragment go???? */
+	if (len > ENET_MAX_MTU)
+		len = ENET_MAX_MTU;
+
+	/*   memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
+	memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
+
+	/*-----------------------------------------------------------------------+
+	 * set TX Buffer busy, and send it
+	 *-----------------------------------------------------------------------*/
+	hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
+					EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
+		~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
+	if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
+		hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
+
+	hw_p->tx[hw_p->tx_slot].data_len = (short) len;
+	hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
+
+	__asm__ volatile ("eieio");
+
+	out32 (EMAC_TXM0 + hw_p->hw_addr,
+	       in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
+#ifdef INFO_440_ENET
+	hw_p->stats.pkts_tx++;
+#endif
+
+	/*-----------------------------------------------------------------------+
+	 * poll unitl the packet is sent and then make sure it is OK
+	 *-----------------------------------------------------------------------*/
+	time_start = get_timer (0);
+	while (1) {
+		temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
+		/* loop until either TINT turns on or 3 seconds elapse */
+		if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
+			/* transmit is done, so now check for errors
+			 * If there is an error, an interrupt should
+			 * happen when we return
+			 */
+			time_now = get_timer (0);
+			if ((time_now - time_start) > 3000) {
+				return (-1);
+			}
+		} else {
+			return (len);
+		}
+	}
+}
+
+
+int enetInt (struct eth_device *dev)
+{
+	int serviced;
+	int rc = -1;		/* default to not us */
+	unsigned long mal_isr;
+	unsigned long emac_isr = 0;
+	unsigned long mal_rx_eob;
+	unsigned long my_uic0msr, my_uic1msr;
+
+#if defined(CONFIG_440_GX)
+	unsigned long my_uic2msr;
+#endif
+	EMAC_440GX_HW_PST hw_p;
+
+	/*
+	 * Because the mal is generic, we need to get the current
+	 * eth device
+	 */
+	dev = eth_get_dev ();
+
+	hw_p = dev->priv;
+
+
+	/* enter loop that stays in interrupt code until nothing to service */
+	do {
+		serviced = 0;
+
+		my_uic0msr = mfdcr (uic0msr);
+		my_uic1msr = mfdcr (uic1msr);
+#if defined(CONFIG_440_GX)
+		my_uic2msr = mfdcr (uic2msr);
+#endif
+		if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
+		    && !(my_uic1msr &
+			 (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE |
+			  UIC_MRDE))) {
+			/* not for us */
+			return (rc);
+		}
+#if defined (CONFIG_440_GX)
+		if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
+		    && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
+			/* not for us */
+			return (rc);
+		}
+#endif
+		/* get and clear controller status interrupts */
+		/* look at Mal and EMAC interrupts */
+		if ((my_uic0msr & (UIC_MRE | UIC_MTE))
+		    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
+			/* we have a MAL interrupt */
+			mal_isr = mfdcr (malesr);
+			/* look for mal error */
+			if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
+				mal_err (dev, mal_isr, my_uic0msr,
+					 MAL_UIC_DEF, MAL_UIC_ERR);
+				serviced = 1;
+				rc = 0;
+			}
+		}
+
+		/* port by port dispatch of emac interrupts */
+		if (hw_p->devnum == 0) {
+			if (UIC_ETH0 & my_uic1msr) {	/* look for EMAC errors */
+				emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
+				if ((hw_p->emac_ier & emac_isr) != 0) {
+					emac_err (dev, emac_isr);
+					serviced = 1;
+					rc = 0;
+				}
+			}
+			if ((hw_p->emac_ier & emac_isr)
+			    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
+				mtdcr (uic0sr, UIC_MRE | UIC_MTE);	/* Clear */
+				mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
+				return (rc);	/* we had errors so get out */
+			}
+		}
+
+		if (hw_p->devnum == 1) {
+			if (UIC_ETH1 & my_uic1msr) {	/* look for EMAC errors */
+				emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
+				if ((hw_p->emac_ier & emac_isr) != 0) {
+					emac_err (dev, emac_isr);
+					serviced = 1;
+					rc = 0;
+				}
+			}
+			if ((hw_p->emac_ier & emac_isr)
+			    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
+				mtdcr (uic0sr, UIC_MRE | UIC_MTE);	/* Clear */
+				mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
+				return (rc);	/* we had errors so get out */
+			}
+		}
+#if defined (CONFIG_440_GX)
+		if (hw_p->devnum == 2) {
+			if (UIC_ETH2 & my_uic2msr) {	/* look for EMAC errors */
+				emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
+				if ((hw_p->emac_ier & emac_isr) != 0) {
+					emac_err (dev, emac_isr);
+					serviced = 1;
+					rc = 0;
+				}
+			}
+			if ((hw_p->emac_ier & emac_isr)
+			    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
+				mtdcr (uic0sr, UIC_MRE | UIC_MTE);	/* Clear */
+				mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
+				mtdcr (uic2sr, UIC_ETH2);
+				return (rc);	/* we had errors so get out */
+			}
+		}
+
+		if (hw_p->devnum == 3) {
+			if (UIC_ETH3 & my_uic2msr) {	/* look for EMAC errors */
+				emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
+				if ((hw_p->emac_ier & emac_isr) != 0) {
+					emac_err (dev, emac_isr);
+					serviced = 1;
+					rc = 0;
+				}
+			}
+			if ((hw_p->emac_ier & emac_isr)
+			    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
+				mtdcr (uic0sr, UIC_MRE | UIC_MTE);	/* Clear */
+				mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
+				mtdcr (uic2sr, UIC_ETH3);
+				return (rc);	/* we had errors so get out */
+			}
+		}
+#endif /* CONFIG_440_GX */
+		/* handle MAX TX EOB interrupt from a tx */
+		if (my_uic0msr & UIC_MTE) {
+			mal_rx_eob = mfdcr (maltxeobisr);
+			mtdcr (maltxeobisr, mal_rx_eob);
+			mtdcr (uic0sr, UIC_MTE);
+		}
+		/* handle MAL RX EOB  interupt from a receive */
+		/* check for EOB on valid channels            */
+		if (my_uic0msr & UIC_MRE) {
+			mal_rx_eob = mfdcr (malrxeobisr);
+			if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) {	/* call emac routine for channel x */
+				/* clear EOB
+				   mtdcr(malrxeobisr, mal_rx_eob); */
+				enet_rcv (dev, emac_isr);
+				/* indicate that we serviced an interrupt */
+				serviced = 1;
+				rc = 0;
+			}
+		}
+		mtdcr (uic0sr, UIC_MRE);	/* Clear */
+		mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
+		switch (hw_p->devnum) {
+		case 0:
+			mtdcr (uic1sr, UIC_ETH0);
+			break;
+		case 1:
+			mtdcr (uic1sr, UIC_ETH1);
+			break;
+#if defined (CONFIG_440_GX)
+		case 2:
+			mtdcr (uic2sr, UIC_ETH2);
+			break;
+		case 3:
+			mtdcr (uic2sr, UIC_ETH3);
+			break;
+#endif /* CONFIG_440_GX */
+		default:
+			break;
+		}
+	} while (serviced);
+
+	return (rc);
+}
+
+/*-----------------------------------------------------------------------------+
+ *  MAL Error Routine
+ *-----------------------------------------------------------------------------*/
+static void mal_err (struct eth_device *dev, unsigned long isr,
+		     unsigned long uic, unsigned long maldef,
+		     unsigned long mal_errr)
+{
+	EMAC_440GX_HW_PST hw_p = dev->priv;
+
+	mtdcr (malesr, isr);	/* clear interrupt */
+
+	/* clear DE interrupt */
+	mtdcr (maltxdeir, 0xC0000000);
+	mtdcr (malrxdeir, 0x80000000);
+
+#ifdef INFO_440_ENET
+	printf ("\nMAL error occured.... ISR = %lx UIC = = %lx  MAL_DEF = %lx  MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
+#endif
+
+	eth_init (hw_p->bis);	/* start again... */
+}
+
+/*-----------------------------------------------------------------------------+
+ *  EMAC Error Routine
+ *-----------------------------------------------------------------------------*/
+static void emac_err (struct eth_device *dev, unsigned long isr)
+{
+	EMAC_440GX_HW_PST hw_p = dev->priv;
+
+	printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
+	out32 (EMAC_ISR + hw_p->hw_addr, isr);
+}
+
+/*-----------------------------------------------------------------------------+
+ *  enet_rcv() handles the ethernet receive data
+ *-----------------------------------------------------------------------------*/
+static void enet_rcv (struct eth_device *dev, unsigned long malisr)
+{
+	struct enet_frame *ef_ptr;
+	unsigned long data_len;
+	unsigned long rx_eob_isr;
+	EMAC_440GX_HW_PST hw_p = dev->priv;
+
+	int handled = 0;
+	int i;
+	int loop_count = 0;
+
+	rx_eob_isr = mfdcr (malrxeobisr);
+	if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
+		/* clear EOB */
+		mtdcr (malrxeobisr, rx_eob_isr);
+
+		/* EMAC RX done */
+		while (1) {	/* do all */
+			i = hw_p->rx_slot;
+
+			if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
+			    || (loop_count >= NUM_RX_BUFF))
+				break;
+			loop_count++;
+			hw_p->rx_slot++;
+			if (NUM_RX_BUFF == hw_p->rx_slot)
+				hw_p->rx_slot = 0;
+			handled++;
+			data_len = (unsigned long) hw_p->rx[i].data_len;	/* Get len */
+			if (data_len) {
+				if (data_len > ENET_MAX_MTU)	/* Check len */
+					data_len = 0;
+				else {
+					if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) {	/* Check Errors */
+						data_len = 0;
+						hw_p->stats.rx_err_log[hw_p->
+								       rx_err_index]
+							= hw_p->rx[i].ctrl;
+						hw_p->rx_err_index++;
+						if (hw_p->rx_err_index ==
+						    MAX_ERR_LOG)
+							hw_p->rx_err_index =
+								0;
+					}	/* emac_erros         */
+				}	/* data_len < max mtu */
+			}	/* if data_len        */
+			if (!data_len) {	/* no data */
+				hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY;	/* Free Recv Buffer */
+
+				hw_p->stats.data_len_err++;	/* Error at Rx */
+			}
+
+			/* !data_len */
+			/* AS.HARNOIS */
+			/* Check if user has already eaten buffer */
+			/* if not => ERROR */
+			else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
+				if (hw_p->is_receiving)
+					printf ("ERROR : Receive buffers are full!\n");
+				break;
+			} else {
+				hw_p->stats.rx_frames++;
+				hw_p->stats.rx += data_len;
+				ef_ptr = (struct enet_frame *) hw_p->rx[i].
+					data_ptr;
+#ifdef INFO_440_ENET
+				hw_p->stats.pkts_rx++;
+#endif
+				/* AS.HARNOIS
+				 * use ring buffer
+				 */
+				hw_p->rx_ready[hw_p->rx_i_index] = i;
+				hw_p->rx_i_index++;
+				if (NUM_RX_BUFF == hw_p->rx_i_index)
+					hw_p->rx_i_index = 0;
+
+				/* printf("X");  /|* test-only *|/ */
+
+				/*  AS.HARNOIS
+				 * free receive buffer only when
+				 * buffer has been handled (eth_rx)
+				 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
+				 */
+			}	/* if data_len */
+		}		/* while */
+	}			/* if EMACK_RXCHL */
+}
+
+
+static int ppc_440x_eth_rx (struct eth_device *dev)
+{
+	int length;
+	int user_index;
+	unsigned long msr;
+	EMAC_440GX_HW_PST hw_p = dev->priv;
+
+	hw_p->is_receiving = 1;	/* tell driver */
+
+	for (;;) {
+		/* AS.HARNOIS
+		 * use ring buffer and
+		 * get index from rx buffer desciptor queue
+		 */
+		user_index = hw_p->rx_ready[hw_p->rx_u_index];
+		if (user_index == -1) {
+			length = -1;
+			break;	/* nothing received - leave for() loop */
+		}
+
+		msr = mfmsr ();
+		mtmsr (msr & ~(MSR_EE));
+
+		length = hw_p->rx[user_index].data_len;
+
+		/* Pass the packet up to the protocol layers. */
+		/*       NetReceive(NetRxPackets[rxIdx], length - 4); */
+		/*       NetReceive(NetRxPackets[i], length); */
+		NetReceive (NetRxPackets[user_index], length - 4);
+		/* Free Recv Buffer */
+		hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
+		/* Free rx buffer descriptor queue */
+		hw_p->rx_ready[hw_p->rx_u_index] = -1;
+		hw_p->rx_u_index++;
+		if (NUM_RX_BUFF == hw_p->rx_u_index)
+			hw_p->rx_u_index = 0;
+
+#ifdef INFO_440_ENET
+		hw_p->stats.pkts_handled++;
+#endif
+
+		mtmsr (msr);	/* Enable IRQ's */
+	}
+
+	hw_p->is_receiving = 0;	/* tell driver */
+
+	return length;
+}
+
+int ppc_440x_eth_initialize (bd_t * bis)
+{
+	static int virgin = 0;
+	unsigned long pfc1;
+	struct eth_device *dev;
+	int eth_num = 0;
+
+	EMAC_440GX_HW_PST hw = NULL;
+
+	mfsdr (sdr_pfc1, pfc1);
+	pfc1 &= ~(0x01e00000);
+	pfc1 |= 0x01200000;
+	mtsdr (sdr_pfc1, pfc1);
+
+	for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
+
+		/* See if we can actually bring up the interface, otherwise, skip it */
+		switch (eth_num) {
+		case 0:
+			if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0)
+				continue;
+			break;
+		case 1:
+			if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) ==
+			    0)
+				continue;
+			break;
+		case 2:
+			if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) ==
+			    0)
+				continue;
+			break;
+		case 3:
+			if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) ==
+			    0)
+				continue;
+			break;
+		default:
+			if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0)
+				continue;
+			break;
+		}
+
+		/* Allocate device structure */
+		dev = (struct eth_device *) malloc (sizeof (*dev));
+		if (dev == NULL) {
+			printf (__FUNCTION__
+				": Cannot allocate eth_device %d\n", eth_num);
+			return (-1);
+		}
+
+		/* Allocate our private use data */
+		hw = (EMAC_440GX_HW_PST) malloc (sizeof (*hw));
+		if (hw == NULL) {
+			printf (__FUNCTION__
+				": Cannot allocate private hw data for eth_device %d",
+				eth_num);
+			free (dev);
+			return (-1);
+		}
+
+		switch (eth_num) {
+		case 0:
+			hw->hw_addr = 0;
+			memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
+			break;
+		case 1:
+			hw->hw_addr = 0x100;
+			memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
+			break;
+		case 2:
+			hw->hw_addr = 0x400;
+			memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
+			break;
+		case 3:
+			hw->hw_addr = 0x600;
+			memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
+			break;
+		default:
+			hw->hw_addr = 0;
+			memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
+			break;
+		}
+
+		hw->devnum = eth_num;
+
+		sprintf (dev->name, "ppc_440x_eth%d", eth_num);
+		dev->priv = (void *) hw;
+		dev->init = ppc_440x_eth_init;
+		dev->halt = ppc_440x_eth_halt;
+		dev->send = ppc_440x_eth_send;
+		dev->recv = ppc_440x_eth_rx;
+
+		if (0 == virgin) {
+			/* set the MAL IER ??? names may change with new spec ??? */
+			mal_ier =
+				MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
+				MAL_IER_OPBE | MAL_IER_PLBE;
+			mtdcr (malesr, 0xffffffff);	/* clear pending interrupts */
+			mtdcr (maltxdeir, 0xffffffff);	/* clear pending interrupts */
+			mtdcr (malrxdeir, 0xffffffff);	/* clear pending interrupts */
+			mtdcr (malier, mal_ier);
+
+			/* install MAL interrupt handler */
+			irq_install_handler (VECNUM_MS,
+					     (interrupt_handler_t *) enetInt,
+					     dev);
+			irq_install_handler (VECNUM_MTE,
+					     (interrupt_handler_t *) enetInt,
+					     dev);
+			irq_install_handler (VECNUM_MRE,
+					     (interrupt_handler_t *) enetInt,
+					     dev);
+			irq_install_handler (VECNUM_TXDE,
+					     (interrupt_handler_t *) enetInt,
+					     dev);
+			irq_install_handler (VECNUM_RXDE,
+					     (interrupt_handler_t *) enetInt,
+					     dev);
+			virgin = 1;
+		}
+
+		eth_register (dev);
+
+	}			/* end for each supported device */
+	return (1);
+}
+#endif /* CONFIG_440 && CONFIG_NET_MULTI */
diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile
index 12f1fdf..9b54d32 100644
--- a/cpu/ppc4xx/Makefile
+++ b/cpu/ppc4xx/Makefile
@@ -27,9 +27,12 @@
 
 START	= start.o resetvec.o kgdb.o
 AOBJS	= dcr.o
-COBJS	= traps.o serial.o cpu.o cpu_init.o speed.o interrupts.o \
-	  405gp_pci.o 405gp_enet.o miiphy.o i2c.o bedbug_405.o \
-	  spd_sdram.o sdram.o
+COBJS	= 405gp_enet.o 405gp_pci.o 440gx_enet.o \
+	  bedbug_405.o \
+	  cpu.o cpu_init.o i2c.o interrupts.o \
+	  miiphy.o miiphy_440.o sdram.o serial.o \
+	  spd_sdram.o speed.o traps.o
+
 OBJS	= $(AOBJS) $(COBJS)
 
 all:	.depend $(START) $(LIB)
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 0ad99b8..df19605 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -152,10 +152,10 @@
 #endif
 
 #if defined(CONFIG_440)
-	puts ("IBM PowerPC 440 Rev. ");
+	puts ("IBM PowerPC 440 G");
 	switch(pvr) {
 	case PVR_440GP_RB:
-		putc('B');
+		puts("P Rev. B");
 		/* See errata 1.12: CHIP_4 */
 		if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
 		    (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
@@ -167,7 +167,13 @@
 		}
 		break;
 	case PVR_440GP_RC:
-		putc('C');
+		puts("P Rev. C");
+		break;
+	case PVR_440GX_RA:
+		puts("X Rev. A");
+		break;
+	case PVR_440GX_RB:
+		puts("X Rev. B");
 		break;
 	default:
 		printf ("UNKNOWN (PVR=%08x)", pvr);
diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c
index 974797f..71052b4 100644
--- a/cpu/ppc4xx/interrupts.c
+++ b/cpu/ppc4xx/interrupts.c
@@ -5,6 +5,9 @@
  * (C) Copyright 2002 (440 port)
  * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
  *
+ * (C) Copyright 2003 (440GX port)
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -50,7 +53,15 @@
 static struct irq_action irq_vecs1[32]; /* For UIC1 */
 
 void uic1_interrupt( void * parms); /* UIC1 handler */
-#endif
+
+#if defined(CONFIG_440_GX)
+static struct irq_action irq_vecs2[32]; /* For UIC2 */
+
+void uic0_interrupt( void * parms); /* UIC0 handler */
+void uic2_interrupt( void * parms); /* UIC2 handler */
+#endif /* CONFIG_440_GX */
+
+#endif /* CONFIG_440 */
 
 /****************************************************************************/
 #if defined(CONFIG_440)
@@ -104,6 +115,11 @@
 		irq_vecs1[vec].handler = NULL;
 		irq_vecs1[vec].arg = NULL;
 		irq_vecs1[vec].count = 0;
+#if defined(CONFIG_440_GX)
+		irq_vecs2[vec].handler = NULL;
+		irq_vecs2[vec].arg = NULL;
+		irq_vecs2[vec].count = 0;
+#endif /* CONFIG_440_GX */
 #endif
 	}
 
@@ -146,10 +162,18 @@
 	set_evpr(0x00000000);
 
 #if defined(CONFIG_440)
+#if !defined(CONFIG_440_GX)
 	/* Install the UIC1 handlers */
 	irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0);
 	irq_install_handler(VECNUM_UIC1C, uic1_interrupt, 0);
 #endif
+#endif
+
+#if defined(CONFIG_440_GX)
+	/* Enable UIC interrupts via UIC Base Enable Register */
+	mtdcr(uicb0er, UICB0_ALL);
+	mtdcr(uicb0cr, UICB0_ALL);
+#endif
 
 	return (0);
 }
@@ -159,9 +183,32 @@
 /*
  * Handle external interrupts
  */
+#if defined(CONFIG_440_GX)
 void external_interrupt(struct pt_regs *regs)
 {
 	ulong uic_msr;
+
+	/*
+	 * Read masked interrupt status register to determine interrupt source
+	 */
+	/* 440 GX uses base uic register */
+	uic_msr = mfdcr(uicb0msr);
+
+	uic0_interrupt(0);
+	uic1_interrupt(0);
+	uic2_interrupt(0);
+
+	mtdcr(uicb0sr, UICB0_ALL);
+
+	return;
+
+} /* external_interrupt CONFIG_440_GX */
+
+#else
+
+void external_interrupt(struct pt_regs *regs)
+{
+	ulong uic_msr;
 	ulong msr_shift;
 	int vec;
 
@@ -200,6 +247,53 @@
 		vec++;
 	}
 }
+#endif
+
+#if defined(CONFIG_440_GX)
+/* Handler for UIC0 interrupt */
+void uic0_interrupt( void * parms)
+{
+	ulong uic_msr;
+	ulong msr_shift;
+	int vec;
+
+	/*
+	 * Read masked interrupt status register to determine interrupt source
+	 */
+	uic_msr = mfdcr(uicmsr);
+	msr_shift = uic_msr;
+	vec = 0;
+
+	while (msr_shift != 0) {
+		if (msr_shift & 0x80000000) {
+			/*
+			 * Increment irq counter (for debug purpose only)
+			 */
+			irq_vecs[vec].count++;
+
+			if (irq_vecs[vec].handler != NULL) {
+				/* call isr */
+				(*irq_vecs[vec].handler)(irq_vecs[vec].arg);
+			} else {
+				mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec));
+				printf ("Masking bogus interrupt vector (uic0) 0x%x\n", vec);
+			}
+
+			/*
+			 * After servicing the interrupt, we have to remove the status indicator.
+			 */
+			mtdcr(uicsr, (0x80000000 >> vec));
+		}
+
+		/*
+		 * Shift msr to next position and increment vector
+		 */
+		msr_shift <<= 1;
+		vec++;
+	}
+}
+
+#endif /* CONFIG_440_GX */
 
 #if defined(CONFIG_440)
 /* Handler for UIC1 interrupt */
@@ -246,50 +340,119 @@
 }
 #endif /* defined(CONFIG_440) */
 
+#if defined(CONFIG_440_GX)
+/* Handler for UIC1 interrupt */
+void uic2_interrupt( void * parms)
+{
+	ulong uic2_msr;
+	ulong msr_shift;
+	int vec;
+
+	/*
+	 * Read masked interrupt status register to determine interrupt source
+	 */
+	uic2_msr = mfdcr(uic2msr);
+	msr_shift = uic2_msr;
+	vec = 0;
+
+	while (msr_shift != 0) {
+		if (msr_shift & 0x80000000) {
+			/*
+			 * Increment irq counter (for debug purpose only)
+			 */
+			irq_vecs2[vec].count++;
+
+			if (irq_vecs2[vec].handler != NULL) {
+				/* call isr */
+				(*irq_vecs2[vec].handler)(irq_vecs2[vec].arg);
+			} else {
+				mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> vec));
+				printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec);
+			}
+
+			/*
+			 * After servicing the interrupt, we have to remove the status indicator.
+			 */
+			mtdcr(uic2sr, (0x80000000 >> vec));
+		}
+
+		/*
+		 * Shift msr to next position and increment vector
+		 */
+		msr_shift <<= 1;
+		vec++;
+	}
+}
+#endif /* defined(CONFIG_440_GX) */
+
 /****************************************************************************/
 
 /*
  * Install and free a interrupt handler.
  */
 
-void
-irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
+void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
 {
 	struct irq_action *irqa = irq_vecs;
-	int   i = vec;
+	int i = vec;
 
 #if defined(CONFIG_440)
+#if defined(CONFIG_440_GX)
+	if ((vec > 31) && (vec < 64)) {
+		i = vec - 32;
+		irqa = irq_vecs1;
+	} else if (vec > 63) {
+		i = vec - 64;
+		irqa = irq_vecs2;
+	}
+#else  /* CONFIG_440_GX */
 	if (vec > 31) {
 		i = vec - 32;
 		irqa = irq_vecs1;
 	}
-#endif
+#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440 */
 
 	if (irqa[i].handler != NULL) {
 		printf ("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
-			vec, (uint)handler, (uint)irqa[i].handler);
+			vec, (uint) handler, (uint) irqa[i].handler);
 	}
 	irqa[i].handler = handler;
-	irqa[i].arg     = arg;
+	irqa[i].arg = arg;
 
 #if defined(CONFIG_440)
-	if( vec > 31 )
-		mtdcr(uic1er, mfdcr(uic1er) | (0x80000000 >> i));
+#if defined(CONFIG_440_GX)
+	if ((vec > 31) && (vec < 64))
+		mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
+	else if (vec > 63)
+		mtdcr (uic2er, mfdcr (uic2er) | (0x80000000 >> i));
+	else
+#endif /* CONFIG_440_GX */
+	if (vec > 31)
+		mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
 	else
 #endif
-		mtdcr(uicer, mfdcr(uicer) | (0x80000000 >> i));
+		mtdcr (uicer, mfdcr (uicer) | (0x80000000 >> i));
 #if 0
 	printf ("Install interrupt for vector %d ==> %p\n", vec, handler);
 #endif
 }
 
-void
-irq_free_handler(int vec)
+void irq_free_handler (int vec)
 {
 	struct irq_action *irqa = irq_vecs;
-	int   i = vec;
+	int i = vec;
 
 #if defined(CONFIG_440)
+#if defined(CONFIG_440_GX)
+	if ((vec > 31) && (vec < 64)) {
+		irqa = irq_vecs1;
+		i = vec - 32;
+	} else if (vec > 63) {
+		irqa = irq_vecs2;
+		i = vec - 64;
+	}
+#endif /* CONFIG_440_GX */
 	if (vec > 31) {
 		irqa = irq_vecs1;
 		i = vec - 32;
@@ -302,14 +465,21 @@
 #endif
 
 #if defined(CONFIG_440)
+#if defined(CONFIG_440_GX)
+	if ((vec > 31) && (vec < 64))
+		mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
+	else if (vec > 63)
+		mtdcr (uic2er, mfdcr (uic2er) & ~(0x80000000 >> i));
+	else
+#endif /* CONFIG_440_GX */
 	if (vec > 31)
-		mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> i));
+		mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
 	else
 #endif
-		mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> i));
+		mtdcr (uicer, mfdcr (uicer) & ~(0x80000000 >> i));
 
 	irqa[i].handler = NULL;
-	irqa[i].arg     = NULL;
+	irqa[i].arg = NULL;
 }
 
 /****************************************************************************/
@@ -354,8 +524,7 @@
 	printf ("\nUIC 1\n");
 	printf ("Nr  Routine   Arg       Count\n");
 
-	for (vec=0; vec<32; vec++)
-	{
+	for (vec=0; vec<32; vec++) {
 		if (irq_vecs1[vec].handler != NULL)
 			printf ("%02d  %08lx  %08lx  %d\n",
 				vec+31, (ulong)irq_vecs1[vec].handler,
@@ -363,8 +532,20 @@
 	}
 	printf("\n");
 #endif
-	return 0;
-}
 
+#if defined(CONFIG_440_GX)
+	printf ("\nUIC 2\n");
+	printf ("Nr  Routine   Arg       Count\n");
 
+	for (vec=0; vec<32; vec++) {
+		if (irq_vecs2[vec].handler != NULL)
+			printf ("%02d  %08lx  %08lx  %d\n",
+				vec+63, (ulong)irq_vecs2[vec].handler,
+				(ulong)irq_vecs2[vec].arg, irq_vecs2[vec].count);
+	}
+	printf("\n");
+#endif
+
+	return 0;
+}
 #endif  /* CONFIG_COMMANDS & CFG_CMD_IRQ */
diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c
index fce5f4b..5ca6681 100644
--- a/cpu/ppc4xx/miiphy.c
+++ b/cpu/ppc4xx/miiphy.c
@@ -48,8 +48,8 @@
 #include <405_mal.h>
 #include <miiphy.h>
 
-#if defined(CONFIG_405GP) || defined(CONFIG_440) || defined(CONFIG_405EP)
-
+#if (defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_440)) \
+   && !defined (CONFIG_NET_MULTI)
 
 /***********************************************************/
 /* Dump out to the screen PHY regs                         */
diff --git a/cpu/ppc4xx/miiphy_440.c b/cpu/ppc4xx/miiphy_440.c
new file mode 100644
index 0000000..bbe535a
--- /dev/null
+++ b/cpu/ppc4xx/miiphy_440.c
@@ -0,0 +1,259 @@
+/*-----------------------------------------------------------------------------+
+  |
+  |	  This source code has been made available to you by IBM on an AS-IS
+  |	  basis.  Anyone receiving this source is licensed under IBM
+  |	  copyrights to use it in any way he or she deems fit, including
+  |	  copying it, modifying it, compiling it, and redistributing it either
+  |	  with or without modifications.  No license under IBM patents or
+  |	  patent applications is to be implied by the copyright license.
+  |
+  |	  Any user of this software should understand that IBM cannot provide
+  |	  technical support for this software and will not be responsible for
+  |	  any consequences resulting from the use of this software.
+  |
+  |	  Any person who transfers this source code or any derivative work
+  |	  must include the IBM copyright notice, this paragraph, and the
+  |	  preceding two paragraphs in the transferred software.
+  |
+  |	  COPYRIGHT   I B M   CORPORATION 1995
+  |	  LICENSED MATERIAL  -	PROGRAM PROPERTY OF I B M
+  +-----------------------------------------------------------------------------*/
+/*-----------------------------------------------------------------------------+
+  |
+  |  File Name:	 miiphy.c
+  |
+  |  Function:	 This module has utilities for accessing the MII PHY through
+  |	       the EMAC3 macro.
+  |
+  |  Author:	 Mark Wisner
+  |
+  |  Change Activity-
+  |
+  |  Date	 Description of Change					     BY
+  |  ---------	 ---------------------					     ---
+  |  05-May-99	 Created						     MKW
+  |  01-Jul-99	 Changed clock setting of sta_reg from 66Mhz to 50Mhz to
+  |		 better match OPB speed. Also modified delay times.	     JWB
+  |  29-Jul-99	 Added Full duplex support				     MKW
+  |  24-Aug-99	 Removed printf from dp83843_duplex()			     JWB
+  |  19-Jul-00	 Ported to esd cpci405					     sr
+  |  23-Dec-03	 Ported from miiphy.c to 440GX Travis Sawyer		     TBS
+  |		 <travis.sawyer@sandburst.com>
+  |
+  +-----------------------------------------------------------------------------*/
+
+#include <common.h>
+#include <asm/processor.h>
+#include <ppc_asm.tmpl>
+#include <commproc.h>
+#include <440gx_enet.h>
+#include <405_mal.h>
+#include <miiphy.h>
+
+#if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
+
+
+/***********************************************************/
+/* Dump out to the screen PHY regs			   */
+/***********************************************************/
+
+void miiphy_dump (unsigned char addr)
+{
+	unsigned long i;
+	unsigned short data;
+
+
+	for (i = 0; i < 0x1A; i++) {
+		if (miiphy_read (addr, i, &data)) {
+			printf ("read error for reg %lx\n", i);
+			return;
+		}
+		printf ("Phy reg %lx ==> %4x\n", i, data);
+
+		/* jump to the next set of regs */
+		if (i == 0x07)
+			i = 0x0f;
+
+	}			/* end for loop */
+}				/* end dump */
+
+
+/***********************************************************/
+/* (Re)start autonegotiation				   */
+/***********************************************************/
+int phy_setup_aneg (unsigned char addr)
+{
+	unsigned short ctl, adv;
+
+	/* Setup standard advertise */
+	miiphy_read (addr, PHY_ANAR, &adv);
+	adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
+		PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
+		PHY_ANLPAR_10);
+	miiphy_write (addr, PHY_ANAR, adv);
+
+	/* Start/Restart aneg */
+	miiphy_read (addr, PHY_BMCR, &ctl);
+	ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+	miiphy_write (addr, PHY_BMCR, ctl);
+
+	return 0;
+}
+
+
+/***********************************************************/
+/* read a phy reg and return the value with a rc	   */
+/***********************************************************/
+unsigned int miiphy_getemac_offset (void)
+{
+	unsigned long zmii;
+	unsigned long eoffset;
+
+	/* Need to find out which mdi port we're using */
+	zmii = in32 (ZMII_FER);
+
+	if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) {
+		/* using port 0 */
+		eoffset = 0;
+	} else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) {
+		/* using port 1 */
+		eoffset = 0x100;
+	} else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) {
+		/* using port 2 */
+		eoffset = 0x400;
+	} else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) {
+		/* using port 3 */
+		eoffset = 0x600;
+	} else {
+		/* None of the mdi ports are enabled! */
+		/* enable port 0 */
+		zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
+		out32 (ZMII_FER, zmii);
+		eoffset = 0;
+		/* need to soft reset port 0 */
+		zmii = in32 (EMAC_M0);
+		zmii |= EMAC_M0_SRST;
+		out32 (EMAC_M0, zmii);
+	}
+
+	return (eoffset);
+
+}
+
+
+int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
+{
+	unsigned long sta_reg;	/* STA scratch area */
+	unsigned long i;
+	unsigned long emac_reg;
+
+
+	emac_reg = miiphy_getemac_offset ();
+	/* see if it is ready for 1000 nsec */
+	i = 0;
+
+	/* see if it is ready for  sec */
+	while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
+		udelay (7);
+		if (i > 5) {
+#if 0
+			printf ("read err 1\n");
+#endif
+			return -1;
+		}
+		i++;
+	}
+	sta_reg = reg;		/* reg address */
+	/* set clock (50Mhz) and read flags */
+#if defined(CONFIG_440_GX)
+	sta_reg |= EMAC_STACR_READ;
+#else
+	sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
+#endif
+
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440_GX)
+	sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
+#endif
+	sta_reg = sta_reg | (addr << 5);	/* Phy address */
+
+	out32 (EMAC_STACR + emac_reg, sta_reg);
+#if 0				/* test-only */
+	printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg);	/* test-only */
+#endif
+
+	sta_reg = in32 (EMAC_STACR + emac_reg);
+	i = 0;
+	while ((sta_reg & EMAC_STACR_OC) == 0) {
+		udelay (7);
+		if (i > 5) {
+			return -1;
+		}
+		i++;
+		sta_reg = in32 (EMAC_STACR + emac_reg);
+	}
+	if ((sta_reg & EMAC_STACR_PHYE) != 0) {
+		return -1;
+	}
+
+	*value = *(short *) (&sta_reg);
+	return 0;
+
+
+}				/* phy_read */
+
+
+/***********************************************************/
+/* write a phy reg and return the value with a rc	    */
+/***********************************************************/
+
+int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
+{
+	unsigned long sta_reg;	/* STA scratch area */
+	unsigned long i;
+	unsigned long emac_reg;
+
+	emac_reg = miiphy_getemac_offset ();
+	/* see if it is ready for 1000 nsec */
+	i = 0;
+
+	while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
+		if (i > 5)
+			return -1;
+		udelay (7);
+		i++;
+	}
+	sta_reg = 0;
+	sta_reg = reg;		/* reg address */
+	/* set clock (50Mhz) and read flags */
+#if defined(CONFIG_440_GX)
+	sta_reg |= EMAC_STACR_WRITE;
+#else
+	sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
+#endif
+
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440_GX)
+	sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;	/* Set clock frequency (PLB freq. dependend) */
+#endif
+	sta_reg = sta_reg | ((unsigned long) addr << 5);	/* Phy address */
+	memcpy (&sta_reg, &value, 2);	/* put in data */
+
+	out32 (EMAC_STACR + emac_reg, sta_reg);
+
+	/* wait for completion */
+	i = 0;
+	sta_reg = in32 (EMAC_STACR + emac_reg);
+	while ((sta_reg & EMAC_STACR_OC) == 0) {
+		udelay (7);
+		if (i > 5)
+			return -1;
+		i++;
+		sta_reg = in32 (EMAC_STACR + emac_reg);
+	}
+
+	if ((sta_reg & EMAC_STACR_PHYE) != 0)
+		return -1;
+	return 0;
+
+}				/* phy_write */
+
+#endif /* CONFIG_405GP */
diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c
index 6b0e39a..2c77338 100644
--- a/cpu/ppc4xx/serial.c
+++ b/cpu/ppc4xx/serial.c
@@ -271,9 +271,15 @@
 #if defined(CONFIG_440)
 #define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000200
 #define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000300
+#if defined(CONFIG_440_GX)
+#define CR0_MASK        0xdfffffff
+#define CR0_EXTCLK_ENA  0x00800000
+#define CR0_UDIV_POS    0
+#else
 #define CR0_MASK        0x3fff0000
 #define CR0_EXTCLK_ENA  0x00600000
 #define CR0_UDIV_POS    16
+#endif /* CONFIG_440_GX */
 #elif defined(CONFIG_405EP)
 #define UART0_BASE      0xef600300
 #define UART1_BASE      0xef600400
@@ -295,9 +301,17 @@
 #if defined(CONFIG_UART1_CONSOLE)
 #define ACTING_UART0_BASE	UART1_BASE
 #define ACTING_UART1_BASE	UART0_BASE
+#if defined(CONFIG_440_GX)
+#define UART0_SDR           sdr_uart1
+#define UART1_SDR           sdr_uart0
+#endif /* CONFIG_440_GX */
 #else
 #define ACTING_UART0_BASE	UART0_BASE
 #define ACTING_UART1_BASE	UART1_BASE
+#if defined(CONFIG_440_GX)
+#define UART0_SDR           sdr_uart0
+#define UART1_SDR           sdr_uart1
+#endif /* CONFIG_440_GX */
 #endif
 
 #if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
@@ -416,7 +430,12 @@
 	unsigned long tmp;
 #endif
 
+#if defined(CONFIG_440_GX)
+	mfsdr(UART0_SDR,reg);
+	reg &= ~CR0_MASK;
+#else
 	reg = mfdcr(cntrl0) & ~CR0_MASK;
+#endif /* CONFIG_440_GX */
 #ifdef CFG_EXT_SERIAL_CLOCK
 	reg |= CR0_EXTCLK_ENA;
 	udiv = 1;
@@ -430,9 +449,13 @@
 	serial_divs (gd->baudrate, &udiv, &bdiv);
 #endif
 
+#if defined(CONFIG_440_GX)
+	reg |= udiv << CR0_UDIV_POS;	/* set the UART divisor */
+	mtsdr (UART0_SDR,reg);
+#else
 	reg |= (udiv - 1) << CR0_UDIV_POS;	/* set the UART divisor */
 	mtdcr (cntrl0, reg);
-
+#endif
 	out8 (ACTING_UART0_BASE + UART_LCR, 0x80);	/* set DLAB bit */
 	out8 (ACTING_UART0_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
 	out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index 7263227..dfd2a04 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -206,6 +206,7 @@
 
 
 #elif defined(CONFIG_440)
+#if !defined(CONFIG_440_GX)
 void get_sys_info (sys_info_t * sysInfo)
 {
 	unsigned long strp0;
@@ -237,6 +238,58 @@
 	sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
 
 }
+#else
+void get_sys_info (sys_info_t * sysInfo)
+{
+	unsigned long strp0;
+	unsigned long strp1;
+	unsigned long temp;
+	unsigned long temp1;
+	unsigned long lfdiv;
+	unsigned long m;
+
+
+	/* Extract configured divisors */
+	mfsdr( sdr_sdstp0,strp0 );
+	mfsdr( sdr_sdstp1,strp1 );
+
+	temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8);
+	sysInfo->pllFwdDivA = temp ? temp : 16 ;
+	temp = ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 5);
+	sysInfo->pllFwdDivB = temp ? temp: 8 ;
+	temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 12;
+	sysInfo->pllFbkDiv = temp ? temp : 32;
+	temp = (strp0 & PLLSYS0_OPB_DIV_MASK);
+	sysInfo->pllOpbDiv = temp ? temp : 4;
+	temp = (strp1 & PLLSYS1_PERCLK_DIV_MASK) >> 24;
+	sysInfo->pllExtBusDiv = temp ? temp : 4;
+
+	/* Calculate 'M' based on feedback source */
+	temp = (strp0 & PLLSYS0_SEL_MASK) >> 27;
+	temp1 = (strp1 & PLLSYS1_LF_DIV_MASK) >> 26;
+	lfdiv = temp1 ? temp1 : 64;
+	if (temp == 0) { /* PLL output */
+		/* Figure which pll to use */
+		temp = (strp0 & PLLSYS0_SRC_MASK) >> 30;
+		if (!temp)
+			m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
+		else
+			m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB;
+	}
+	else if (temp == 1) /* CPU output */
+		m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
+	else /* PerClk */
+		m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
+
+	/* Now calculate the individual clocks */
+	sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
+	sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
+	sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB;
+	sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
+	sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
+
+}
+#endif
 
 ulong get_OPB_freq (void)
 {
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index e25101a..3473baa 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -166,7 +166,12 @@
 	mtspr	srr1,r0
 	mtspr	csrr0,r0
 	mtspr	csrr1,r0
-
+#if defined (CONFIG_440_GX) /* NOTE: 440GX adds machine check status regs */
+	mtspr   mcsrr0,r0
+	mtspr   mcsrr1,r0
+	mfspr   r1, mcsr
+	mtspr   mcsr,r1
+#endif
 	/*----------------------------------------------------------------*/
 	/* Initialize debug */
 	/*----------------------------------------------------------------*/
@@ -335,9 +340,23 @@
 	mtspr	tcr,r0			/* disable all */
 	mtspr	esr,r0			/* clear exception syndrome register */
 	mtxer	r0			/* clear integer exception register */
+#if !defined(CONFIG_440_GX)
 	lis	r1,0x0002		/* set CE bit (Critical Exceptions) */
 	ori	r1,r1,0x1000		/* set ME bit (Machine Exceptions) */
 	mtmsr	r1			/* change MSR */
+#else
+	bl	__440gx_msr_set
+	b	__440gx_msr_continue
+
+__440gx_msr_set:
+	lis 	r1, 0x0002		/* set CE bit (Critical Exceptions) */
+	ori 	r1,r1,0x1000	/* set ME bit (Machine Exceptions) */
+	mtspr	srr1,r1
+	mflr	r1
+	mtspr	srr0,r1
+	rfi
+__440gx_msr_continue:
+#endif
 
 	/*----------------------------------------------------------------*/
 	/* Debug setup -- some (not very good) ice's need an event*/
@@ -358,6 +377,9 @@
 	/* Setup the internal SRAM */
 	/*----------------------------------------------------------------*/
 	li	r0,0
+#if defined (CONFIG_440_GX)
+	mtdcr   l2_cache_cfg,r0		/* Ensure L2 Cache is off */
+#endif
 	mtdcr	isram0_sb1cr,r0		/* Disable bank 1 */
 
 	li	r2,0x7fff
@@ -370,8 +392,22 @@
 	mtdcr	isram0_pmeg,r1
 
 	lis	r1,0x8000		/* BAS = 8000_0000 */
+#if defined(CONFIG_440_GX)
+	ori	r1,r1,0x0980		/* first 64k */
+	mtdcr   isram0_sb0cr,r1
+	lis	r1,0x8001
+	ori	r1,r1,0x0980		/* second 64k */
+	mtdcr   isram0_sb1cr,r1
+	lis	r1, 0x8002
+	ori	r1,r1, 0x0980		/* third 64k */
+	mtdcr   isram0_sb2cr,r1
+	lis	r1, 0x8003
+	ori	r1,r1, 0x0980		/* fourth 64k */
+	mtdcr   isram0_sb3cr,r1
+#else
 	ori	r1,r1,0x0380		/* 8k rw */
 	mtdcr	isram0_sb0cr,r1
+#endif
 
 	/*----------------------------------------------------------------*/
 	/* Setup the stack in internal SRAM */
@@ -921,7 +957,12 @@
 invalidate_dcache:
 	addi	r6,0,0x0000		/* clear GPR 6 */
 	/* Do loop for # of dcache congruence classes. */
+#if defined(CONFIG_440_GX)
+	lis     r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha	/* TBS for large sized cache */
+	ori     r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
+#else
 	addi	r7,r0, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
+#endif
 					/* NOTE: dccci invalidates both */
 	mtctr	r7			/* ways in the D cache */
 ..dcloop:
@@ -942,8 +983,15 @@
 	mtdccr	r10
 
 	/* do loop for # of congruence classes. */
+#if defined(CONFIG_440_GX)
+	lis     r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha	/* TBS: for large cache sizes */
+	ori     r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
+	lis     r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
+	ori     r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
+#else
 	addi	r10,r0,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
 	addi	r11,r0,(CFG_DCACHE_SIZE / 2) /* D cache set size - 2 way sets */
+#endif
 	mtctr	r10
 	addi	r10,r0,(0xE000-0x10000)	/* start at 0xFFFFE000 */
 	add	r11,r10,r11		/* add to get to other side of cache line */
diff --git a/doc/README.xpedite1k b/doc/README.xpedite1k
new file mode 100644
index 0000000..34bba13
--- /dev/null
+++ b/doc/README.xpedite1k
@@ -0,0 +1,82 @@
+			   XES XPedite1000 Board
+
+		    Last Update: December 29, 2003
+=======================================================================
+
+This file contains some handy info regarding U-Boot and the XES
+XPedite1000 PPC440GX PrPMC board. See the README.ppc440 for additional
+information.
+
+
+SWITCH SETTINGS & JUMPERS
+==========================
+
+Jumpers selected for AMD29LV040B flash part as the boot flash.
+
+
+I2C Strap EEPROM & Environment Settings
+=======================================
+
+The XPedite1000 uses a single I2C eeprom for the 440 strappings and for
+the environment variables.  The first page (256 bytes) contains the
+strappings and the 2 EMAC HW Ethernet addresses.  Be careful not to
+change the 1st page of the EEPROM!  Unpopulated jumper J560 can get you
+out of trouble as it disables the strapping read from EEPROM.
+
+I2C iprobe
+=====================
+
+The i2c utilities work and have been tested on Rev B. of the 440GX. See
+README.ebony for more information about i2c probing with the 440.
+
+
+GETTING OUT OF I2C TROUBLE
+===========================
+
+(Direct quote from README.ebony)
+If you're like me ... you may have screwed up your bootstrap serial
+eeprom ... or worse, your SPD eeprom when experimenting with the
+i2c commands. If so, here are some ideas on how to get out of
+trouble:
+
+Serial bootstrap eeprom corruption:
+-----------------------------------
+Power down the board and set the following straps:
+
+J560 - closed
+
+This will select the default sys0 and sys1 settings (the serial
+eeproms are not used). Then power up the board and fix the serial
+eeprom using the imm command. Here are the values I currently
+use:
+
+=> imd 50 0 10
+
+0000: 85 7d 42 06 07 80 11 00 00 00 00 00 00 00 00 00    .}B.............
+
+Once you have the eeproms set correctly change the
+J560 straps as you desire.
+
+
+PPC440GX Ethernet EMACs
+=======================
+
+The XES XPedite1000 uses emac 2 & 3 and ignores emac 0 & 1.  PHYs are connected
+only to emac 2 & 3.  The HW Ethernet addresses are read from the i2c eeprom and
+placed in the bd info structure for enet2addr and enet3addr.  The ethernet driver
+senses that enetaddr and enet1addr are 0's and does not use them.
+
+As of this writing gigabit ethernet and the TCPIP acceleration hardware is not
+supported.
+
+
+Flash Support
+=============
+
+As of this writing, there is support for the 1/2mb boot flash only.  User flash
+is not yet supported.
+
+
+Regards,
+--Travis
+<travis.sawyer@sandburst.com>
diff --git a/include/405_mal.h b/include/405_mal.h
index 020874f..69d20c9 100644
--- a/include/405_mal.h
+++ b/include/405_mal.h
@@ -1,39 +1,43 @@
 /* include/mal.h, openbios_walnut, walnut_bios 8/6/99 08:48:40 */
 /*----------------------------------------------------------------------------+
 |
-|       This source code has been made available to you by IBM on an AS-IS
-|       basis.  Anyone receiving this source is licensed under IBM
-|       copyrights to use it in any way he or she deems fit, including
-|       copying it, modifying it, compiling it, and redistributing it either
-|       with or without modifications.  No license under IBM patents or
-|       patent applications is to be implied by the copyright license.
+|	This source code has been made available to you by IBM on an AS-IS
+|	basis.	Anyone receiving this source is licensed under IBM
+|	copyrights to use it in any way he or she deems fit, including
+|	copying it, modifying it, compiling it, and redistributing it either
+|	with or without modifications.	No license under IBM patents or
+|	patent applications is to be implied by the copyright license.
 |
-|       Any user of this software should understand that IBM cannot provide
-|       technical support for this software and will not be responsible for
-|       any consequences resulting from the use of this software.
+|	Any user of this software should understand that IBM cannot provide
+|	technical support for this software and will not be responsible for
+|	any consequences resulting from the use of this software.
 |
-|       Any person who transfers this source code or any derivative work
-|       must include the IBM copyright notice, this paragraph, and the
-|       preceding two paragraphs in the transferred software.
+|	Any person who transfers this source code or any derivative work
+|	must include the IBM copyright notice, this paragraph, and the
+|	preceding two paragraphs in the transferred software.
 |
-|       COPYRIGHT   I B M   CORPORATION 1999
-|       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+|	COPYRIGHT   I B M   CORPORATION 1999
+|	LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
 +----------------------------------------------------------------------------*/
 /*----------------------------------------------------------------------------+
 |
-|  File Name:   mal.h
+|  File Name:	mal.h
 |
-|  Function:    Header file for the MAL (MADMAL) macro on the 405GP.
+|  Function:	Header file for the MAL (MADMAL) macro on the 405GP.
 |
-|  Author:      Mark Wisner
+|  Author:	Mark Wisner
 |
 |  Change Activity-
 |
-|  Date        Description of Change                                       BY
-|  ---------   ---------------------                                       ---
-|  29-Apr-99   Created                                                     MKW
+|  Date	       Description of Change					   BY
+|  ---------   ---------------------					   ---
+|  29-Apr-99   Created							   MKW
 |
 +----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+|  17-Nov-03  Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+|	      Added register bit definitions to support multiple channels
++----------------------------------------------------------------------------*/
 #ifndef _mal_h_
 #define _mal_h_
 /* MADMAL transmit and receive status/control bits  */
@@ -41,7 +45,7 @@
 
 #define MAL_TX_CTRL_READY 0x8000
 #define MAL_TX_CTRL_WRAP  0x4000
-#define MAL_TX_CTRL_CM    0x2000
+#define MAL_TX_CTRL_CM	  0x2000
 #define MAL_TX_CTRL_LAST  0x1000
 #define MAL_TX_CTRL_INTR  0x0400
 
@@ -56,14 +60,14 @@
 #define MAL_CR_MMSR	  0x80000000
 #define MAL_CR_PLBP_1	  0x00400000   /* lowsest is 00 */
 #define MAL_CR_PLBP_2	  0x00800000
-#define MAL_CR_PLBP_3	  0x00C00000   /* highest       */
+#define MAL_CR_PLBP_3	  0x00C00000   /* highest	*/
 #define MAL_CR_GA	  0x00200000
 #define MAL_CR_OA	  0x00100000
 #define MAL_CR_PLBLE	  0x00080000
-#define MAL_CR_PLBLT_1  0x00040000
-#define MAL_CR_PLBLT_2  0x00020000
-#define MAL_CR_PLBLT_3  0x00010000
-#define MAL_CR_PLBLT_4  0x00008000
+#define MAL_CR_PLBLT_1	0x00040000
+#define MAL_CR_PLBLT_2	0x00020000
+#define MAL_CR_PLBLT_3	0x00010000
+#define MAL_CR_PLBLT_4	0x00008000
 #define MAL_CR_PLBLT_DEFAULT 0x00078000 /* ????? */
 #define MAL_CR_PLBB	  0x00004000
 #define MAL_CR_OPBBL	  0x00000080
@@ -71,7 +75,7 @@
 #define MAL_CR_LEA	  0x00000002
 #define MAL_CR_MSD	  0x00000001
 
-    /* Error Status Reg    */
+    /* Error Status Reg	   */
 #define MAL_ESR_EVB	  0x80000000
 #define MAL_ESR_CID	  0x40000000
 #define MAL_ESR_DE	  0x00100000
@@ -80,26 +84,31 @@
 #define MAL_ESR_OSE	  0x00020000
 #define MAL_ESR_PEIN	  0x00010000
       /* same bit position as the IER */
-      /* VV                      VV   */
+      /* VV			 VV   */
 #define MAL_ESR_DEI	  0x00000010
 #define MAL_ESR_ONEI	  0x00000008
 #define MAL_ESR_OTEI	  0x00000004
 #define MAL_ESR_OSEI	  0x00000002
 #define MAL_ESR_PBEI	  0x00000001
-      /* ^^                      ^^   */
-      /* Mal IER                      */
+      /* ^^			 ^^   */
+      /* Mal IER		      */
 #define MAL_IER_DE	  0x00000010
 #define MAL_IER_NE	  0x00000008
 #define MAL_IER_TE	  0x00000004
 #define MAL_IER_OPBE	  0x00000002
 #define MAL_IER_PLBE	  0x00000001
 
+/* MAL Channel Active Set and Reset Registers */
+#define MAL_TXRX_CASR	(0x80000000)
+
+#define MAL_TXRX_CASR_V(__x)  (__x)  /* Channel 0 shifts 0, channel 1 shifts 1, etc */
+
 
 /* MAL Buffer Descriptor structure */
 typedef struct {
-  short  ctrl;              /* MAL / Commac status control bits */
-  short  data_len;          /* Max length is 4K-1 (12 bits)     */
-  char  *data_ptr;          /* pointer to actual data buffer    */
+  short	 ctrl;		    /* MAL / Commac status control bits */
+  short	 data_len;	    /* Max length is 4K-1 (12 bits)	*/
+  char	*data_ptr;	    /* pointer to actual data buffer	*/
 } mal_desc_t;
 
 #endif
diff --git a/include/440gx_enet.h b/include/440gx_enet.h
new file mode 100644
index 0000000..8caf969
--- /dev/null
+++ b/include/440gx_enet.h
@@ -0,0 +1,440 @@
+/*----------------------------------------------------------------------------+
+|
+|	This source code has been made available to you by IBM on an AS-IS
+|	basis.	Anyone receiving this source is licensed under IBM
+|	copyrights to use it in any way he or she deems fit, including
+|	copying it, modifying it, compiling it, and redistributing it either
+|	with or without modifications.	No license under IBM patents or
+|	patent applications is to be implied by the copyright license.
+|
+|	Any user of this software should understand that IBM cannot provide
+|	technical support for this software and will not be responsible for
+|	any consequences resulting from the use of this software.
+|
+|	Any person who transfers this source code or any derivative work
+|	must include the IBM copyright notice, this paragraph, and the
+|	preceding two paragraphs in the transferred software.
+|
+|	COPYRIGHT   I B M   CORPORATION 1999
+|	LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
++----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+|
+|  File Name:	enetemac.h
+|
+|  Function:	Header file for the EMAC3 macro on the 405GP.
+|
+|  Author:	Mark Wisner
+|
+|  Change Activity-
+|
+|  Date	       Description of Change					   BY
+|  ---------   ---------------------					   ---
+|  29-Apr-99   Created							   MKW
+|
++----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+|  19-Nov-03   Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+|	       ported to handle 440GP and 440GX multiple EMACs
++----------------------------------------------------------------------------*/
+
+#ifndef _emacgx_enet_h_
+#define _emacgx_enet_h_
+
+#if defined(CONFIG_440)
+#include <net.h>
+#include "405_mal.h"
+
+
+/*-----------------------------------------------------------------------------+
+| General enternet defines.  802 frames are not supported.
++-----------------------------------------------------------------------------*/
+#define ENET_ADDR_LENGTH		6
+#define ENET_ARPTYPE			0x806
+#define ARP_REQUEST			1
+#define ARP_REPLY			2
+#define ENET_IPTYPE			0x800
+#define ARP_CACHE_SIZE			5
+
+#define NUM_TX_BUFF 1
+#define NUM_RX_BUFF PKTBUFSRX
+
+struct enet_frame {
+   unsigned char	dest_addr[ENET_ADDR_LENGTH];
+   unsigned char	source_addr[ENET_ADDR_LENGTH];
+   unsigned short	type;
+   unsigned char	enet_data[1];
+};
+
+struct arp_entry {
+   unsigned long	inet_address;
+   unsigned char	mac_address[ENET_ADDR_LENGTH];
+   unsigned long	valid;
+   unsigned long	sec;
+   unsigned long	nsec;
+};
+
+
+/* Statistic Areas */
+#define MAX_ERR_LOG 10
+
+typedef struct emac_stats_st{	/* Statistic Block */
+	int data_len_err;
+	int rx_frames;
+	int rx;
+	int rx_prot_err;
+	int int_err;
+    int pkts_tx;
+    int pkts_rx;
+    int pkts_handled;
+	short tx_err_log[MAX_ERR_LOG];
+	short rx_err_log[MAX_ERR_LOG];
+} EMAC_STATS_ST, *EMAC_STATS_PST;
+
+/* Structure containing variables used by the shared code (440gx_enet.c) */
+typedef struct emac_440gx_hw_st {
+    uint32_t		hw_addr;		/* EMAC offset */
+    uint32_t		tah_addr;		/* TAH offset */
+    uint32_t		phy_id;
+    uint32_t		phy_addr;
+    uint32_t		original_fc;
+    uint32_t		txcw;
+    uint32_t		autoneg_failed;
+    uint32_t		emac_ier;
+    volatile mal_desc_t *tx;
+    volatile mal_desc_t *rx;
+    bd_t		*bis;	/* for eth_init upon mal error */
+    mal_desc_t		*alloc_tx_buf;
+    mal_desc_t		*alloc_rx_buf;
+    char		*txbuf_ptr;
+    uint16_t		devnum;
+    int			get_link_status;
+    int			tbi_compatibility_en;
+    int			tbi_compatibility_on;
+    int			fc_send_xon;
+    int			report_tx_early;
+    int			first_init;
+    int			tx_err_index;
+    int			rx_err_index;
+    int			rx_slot;			/* MAL Receive Slot */
+    int			rx_i_index;		/* Receive Interrupt Queue Index */
+    int			rx_u_index;		/* Receive User Queue Index */
+    int			tx_slot;			/* MAL Transmit Slot */
+    int			tx_i_index;		/* Transmit Interrupt Queue Index */
+    int			tx_u_index;		/* Transmit User Queue Index */
+    int			rx_ready[NUM_RX_BUFF];	/* Receive Ready Queue */
+    int			tx_run[NUM_TX_BUFF];	/* Transmit Running Queue */
+    int			is_receiving;	/* sync with eth interrupt */
+    int			print_speed;	/* print speed message upon start */
+    EMAC_STATS_ST	stats;
+} EMAC_440GX_HW_ST, *EMAC_440GX_HW_PST;
+
+
+#if defined(CONFIG_440_GX)
+#define EMAC_NUM_DEV	    4
+#elif defined(CONFIG_440) && !defined(CONFIG_440_GX)
+#define EMAC_NUM_DEV	    2
+#else
+#warning Bad configuration
+#endif
+
+
+/*ZMII Bridge Register addresses */
+#define ZMII_BASE			(CFG_PERIPHERAL_BASE + 0x0780)
+#define ZMII_FER			(ZMII_BASE)
+#define ZMII_SSR			(ZMII_BASE + 4)
+#define ZMII_SMIISR			(ZMII_BASE + 8)
+
+#define ZMII_RMII			0x22000000
+#define ZMII_MDI0			0x80000000
+
+/* ZMII FER Register Bit Definitions */
+#define ZMII_FER_MDI		(0x8)
+#define ZMII_FER_SMII		(0x4)
+#define ZMII_FER_RMII		(0x2)
+#define ZMII_FER_MII		(0x1)
+
+#define ZMII_FER_RSVD11		(0x00200000)
+#define ZMII_FER_RSVD10		(0x00100000)
+#define ZMII_FER_RSVD14_31	(0x0003FFFF)
+
+#define ZMII_FER_V(__x)		(((3 - __x) * 4) + 16)
+
+
+/* ZMII Speed Selection Register Bit Definitions */
+#define ZMII_SSR_SCI		(0x4)
+#define ZMII_SSR_FSS		(0x2)
+#define ZMII_SSR_SP		(0x1)
+#define ZMII_SSR_RSVD16_31	(0x0000FFFF)
+
+#define ZMII_SSR_V(__x)		(((3 - __x) * 4) + 16)
+
+
+/* ZMII SMII Status Register Bit Definitions */
+#define ZMII_SMIISR_E1		(0x80)
+#define ZMII_SMIISR_EC		(0x40)
+#define ZMII_SMIISR_EN		(0x20)
+#define ZMII_SMIISR_EJ		(0x10)
+#define ZMII_SMIISR_EL		(0x08)
+#define ZMII_SMIISR_ED		(0x04)
+#define ZMII_SMIISR_ES		(0x02)
+#define ZMII_SMIISR_EF		(0x01)
+
+#define ZMII_SMIISR_V(__x)	((3 - __x) * 8)
+
+/* RGMII Register Addresses */
+#define RGMII_BASE		(CFG_PERIPHERAL_BASE + 0x0790)
+#define RGMII_FER		(RGMII_BASE + 0x00)
+#define RGMII_SSR		(RGMII_BASE + 0x04)
+
+/* RGMII Function Enable (FER) Register Bit Definitions */
+/* Note: for EMAC 2 and 3 only, 440GX only */
+#define RGMII_FER_DIS		(0x00)
+#define RGMII_FER_RTBI		(0x04)
+#define RGMII_FER_RGMII		(0x05)
+#define RGMII_FER_TBI		(0x06)
+#define RGMII_FER_GMII		(0x07)
+
+#define RGMII_FER_V(__x)	((__x - 2) * 4)
+
+/* RGMII Speed Selection Register Bit Definitions */
+#define RGMII_SSR_SP_10MBPS	(0x00)
+#define RGMII_SSR_SP_100MBPS	(0x02)
+#define RGMII_SSR_SP_1000MBPS	(0x04)
+
+#define RGMII_SSR_V(__x)	((__x -2) * 8)
+
+
+/*---------------------------------------------------------------------------+
+|  TCP/IP Acceleration Hardware (TAH) 440GX Only
++---------------------------------------------------------------------------*/
+#if defined(CONFIG_440_GX)
+#define TAH_BASE		(CFG_PERIPHERAL_BASE + 0x0B50)
+#define TAH_REVID		(TAH_BASE + 0x0)    /* Revision ID (RO)*/
+#define TAH_MR			(TAH_BASE + 0x10)   /* Mode Register (R/W) */
+#define TAH_SSR0		(TAH_BASE + 0x14)   /* Segment Size Reg 0 (R/W) */
+#define TAH_SSR1		(TAH_BASE + 0x18)   /* Segment Size Reg 1 (R/W) */
+#define TAH_SSR2		(TAH_BASE + 0x1C)   /* Segment Size Reg 2 (R/W) */
+#define TAH_SSR3		(TAH_BASE + 0x20)   /* Segment Size Reg 3 (R/W) */
+#define TAH_SSR4		(TAH_BASE + 0x24)   /* Segment Size Reg 4 (R/W) */
+#define TAH_SSR5		(TAH_BASE + 0x28)   /* Segment Size Reg 5 (R/W) */
+#define TAH_TSR			(TAH_BASE + 0x2C)   /* Transmit Status Register (RO) */
+
+
+/* TAH Revision */
+#define TAH_REV_RN_M		(0x000FFF00)	    /* Revision Number */
+#define TAH_REV_BN_M		(0x000000FF)	    /* Branch Revision Number */
+
+#define TAH_REV_RN_V		(8)
+#define TAH_REV_BN_V		(0)
+
+/* TAH Mode Register */
+#define TAH_MR_CVR		(0x80000000)	    /* Checksum verification on RX */
+#define TAH_MR_SR		(0x40000000)	    /* Software reset */
+#define TAH_MR_ST		(0x3F000000)	    /* Send Threshold */
+#define TAH_MR_TFS		(0x00E00000)	    /* Transmit FIFO size */
+#define TAH_MR_DTFP		(0x00100000)	    /* Disable TX FIFO parity */
+#define TAH_MR_DIG		(0x00080000)	    /* Disable interrupt generation */
+#define TAH_MR_RSVD		(0x0007FFFF)	    /* Reserved */
+
+#define TAH_MR_ST_V		(20)
+#define TAH_MR_TFS_V		(17)
+
+#define TAH_MR_TFS_2K		(0x1)		    /* Transmit FIFO size 2Kbyte */
+#define TAH_MR_TFS_4K		(0x2)		    /* Transmit FIFO size 4Kbyte */
+#define TAH_MR_TFS_6K		(0x3)		    /* Transmit FIFO size 6Kbyte */
+#define TAH_MR_TFS_8K		(0x4)		    /* Transmit FIFO size 8Kbyte */
+#define TAH_MR_TFS_10K		(0x5)		    /* Transmit FIFO size 10Kbyte (max)*/
+
+
+/* TAH Segment Size Registers 0:5 */
+#define TAH_SSR_RSVD0		(0xC0000000)	    /* Reserved */
+#define TAH_SSR_SS		(0x3FFE0000)	    /* Segment size in multiples of 2 */
+#define TAH_SSR_RSVD1		(0x0001FFFF)	    /* Reserved */
+
+/* TAH Transmit Status Register */
+#define TAH_TSR_TFTS		(0x80000000)	    /* Transmit FIFO too small */
+#define TAH_TSR_UH		(0x40000000)	    /* Unrecognized header */
+#define TAH_TSR_NIPF		(0x20000000)	    /* Not IPv4 */
+#define TAH_TSR_IPOP		(0x10000000)	    /* IP option present */
+#define TAH_TSR_NISF		(0x08000000)	    /* No IEEE SNAP format */
+#define TAH_TSR_ILTS		(0x04000000)	    /* IP length too short */
+#define TAH_TSR_IPFP		(0x02000000)	    /* IP fragment present */
+#define TAH_TSR_UP		(0x01000000)	    /* Unsupported protocol */
+#define TAH_TSR_TFP		(0x00800000)	    /* TCP flags present */
+#define TAH_TSR_SUDP		(0x00400000)	    /* Segmentation for UDP */
+#define TAH_TSR_DLM		(0x00200000)	    /* Data length mismatch */
+#define TAH_TSR_SIEEE		(0x00100000)	    /* Segmentation for IEEE */
+#define TAH_TSR_TFPE		(0x00080000)	    /* Transmit FIFO parity error */
+#define TAH_TSR_SSTS		(0x00040000)	    /* Segment size too small */
+#define TAH_TSR_RSVD		(0x0003FFFF)	    /* Reserved */
+#endif /* CONFIG_440_GX */
+
+
+/* Ethernet MAC Regsiter Addresses */
+#define EMAC_BASE			    (CFG_PERIPHERAL_BASE + 0x0800)
+
+#define EMAC_M0				    (EMAC_BASE)
+#define EMAC_M1				    (EMAC_BASE + 4)
+#define EMAC_TXM0				(EMAC_BASE + 8)
+#define EMAC_TXM1				(EMAC_BASE + 12)
+#define EMAC_RXM				(EMAC_BASE + 16)
+#define EMAC_ISR				(EMAC_BASE + 20)
+#define EMAC_IER				(EMAC_BASE + 24)
+#define EMAC_IAH				(EMAC_BASE + 28)
+#define EMAC_IAL				(EMAC_BASE + 32)
+#define EMAC_VLAN_TPID_REG		(EMAC_BASE + 36)
+#define EMAC_VLAN_TCI_REG		(EMAC_BASE + 40)
+#define EMAC_PAUSE_TIME_REG	(EMAC_BASE + 44)
+#define EMAC_IND_HASH_1			(EMAC_BASE + 48)
+#define EMAC_IND_HASH_2			(EMAC_BASE + 52)
+#define EMAC_IND_HASH_3			(EMAC_BASE + 56)
+#define EMAC_IND_HASH_4			(EMAC_BASE + 60)
+#define EMAC_GRP_HASH_1			(EMAC_BASE + 64)
+#define EMAC_GRP_HASH_2			(EMAC_BASE + 68)
+#define EMAC_GRP_HASH_3			(EMAC_BASE + 72)
+#define EMAC_GRP_HASH_4			(EMAC_BASE + 76)
+#define EMAC_LST_SRC_LOW		(EMAC_BASE + 80)
+#define EMAC_LST_SRC_HI			(EMAC_BASE + 84)
+#define EMAC_I_FRAME_GAP_REG	(EMAC_BASE + 88)
+#define EMAC_STACR			    (EMAC_BASE + 92)
+#define EMAC_TRTR				(EMAC_BASE + 96)
+#define EMAC_RX_HI_LO_WMARK		(EMAC_BASE + 100)
+
+/* bit definitions */
+/* MODE REG 0 */
+#define EMAC_M0_RXI			    (0x80000000)
+#define EMAC_M0_TXI			    (0x40000000)
+#define EMAC_M0_SRST			(0x20000000)
+#define EMAC_M0_TXE			    (0x10000000)
+#define EMAC_M0_RXE			    (0x08000000)
+#define EMAC_M0_WKE			    (0x04000000)
+
+/* MODE Reg 1 */
+#define EMAC_M1_FDE		(0x80000000)
+#define EMAC_M1_ILE		(0x40000000)
+#define EMAC_M1_VLE		(0x20000000)
+#define EMAC_M1_EIFC			(0x10000000)
+#define EMAC_M1_APP			    (0x08000000)
+#define EMAC_M1_RSVD			(0x06000000)
+#define EMAC_M1_IST			    (0x01000000)
+#define EMAC_M1_MF_1000MBPS		(0x00800000)	/* 0's for 10MBPS */
+#define EMAC_M1_MF_100MBPS		(0x00400000)
+#define EMAC_M1_RFS_16K			(0x00280000)	/* ~4k for 512 byte */
+#define EMAC_M1_RFS_8K			(0x00200000)	/* ~4k for 512 byte */
+#define EMAC_M1_RFS_4K			(0x00180000)	/* ~4k for 512 byte */
+#define EMAC_M1_RFS_2K			(0x00100000)
+#define EMAC_M1_RFS_1K			(0x00080000)
+#define EMAC_M1_TX_FIFO_16K		(0x00050000)	/* 0's for 512 byte */
+#define EMAC_M1_TX_FIFO_8K		(0x00040000)
+#define EMAC_M1_TX_FIFO_4K		(0x00030000)
+#define EMAC_M1_TX_FIFO_2K	(0x00020000)
+#define EMAC_M1_TX_FIFO_1K		(0x00010000)
+#define EMAC_M1_TR_MULTI		(0x00008000)	/* 0'x for single packet */
+#define EMAC_M1_MWSW		(0x00007000)
+#define EMAC_M1_JUMBO_ENABLE	(0x00000800)
+#define EMAC_M1_IPPA		(0x000007c0)
+#define EMAC_M1_OBCI_GT100	(0x00000020)
+#define EMAC_M1_OBCI_100	(0x00000018)
+#define EMAC_M1_OBCI_83		(0x00000010)
+#define EMAC_M1_OBCI_66		(0x00000008)
+#define EMAC_M1_RSVD1		(0x00000007)
+/* Transmit Mode Register 0 */
+#define EMAC_TXM0_GNP0			(0x80000000)
+#define EMAC_TXM0_GNP1			(0x40000000)
+#define EMAC_TXM0_GNPD			(0x20000000)
+#define EMAC_TXM0_FC			(0x10000000)
+
+/* Receive Mode Register */
+#define EMAC_RMR_SP		(0x80000000)
+#define EMAC_RMR_SFCS		(0x40000000)
+#define EMAC_RMR_ARRP		(0x20000000)
+#define EMAC_RMR_ARP		(0x10000000)
+#define EMAC_RMR_AROP		(0x08000000)
+#define EMAC_RMR_ARPI		(0x04000000)
+#define EMAC_RMR_PPP		(0x02000000)
+#define EMAC_RMR_PME		(0x01000000)
+#define EMAC_RMR_PMME		(0x00800000)
+#define EMAC_RMR_IAE		(0x00400000)
+#define EMAC_RMR_MIAE		(0x00200000)
+#define EMAC_RMR_BAE		(0x00100000)
+#define EMAC_RMR_MAE		(0x00080000)
+
+/* Interrupt Status & enable Regs */
+#define EMAC_ISR_OVR		(0x02000000)
+#define EMAC_ISR_PP		(0x01000000)
+#define EMAC_ISR_BP		(0x00800000)
+#define EMAC_ISR_RP		(0x00400000)
+#define EMAC_ISR_SE			(0x00200000)
+#define EMAC_ISR_SYE			(0x00100000)
+#define EMAC_ISR_BFCS			(0x00080000)
+#define EMAC_ISR_PTLE			(0x00040000)
+#define EMAC_ISR_ORE			(0x00020000)
+#define EMAC_ISR_IRE			(0x00010000)
+#define EMAC_ISR_DBDM			(0x00000200)
+#define EMAC_ISR_DB0			(0x00000100)
+#define EMAC_ISR_SE0			(0x00000080)
+#define EMAC_ISR_TE0			(0x00000040)
+#define EMAC_ISR_DB1			(0x00000020)
+#define EMAC_ISR_SE1			(0x00000010)
+#define EMAC_ISR_TE1			(0x00000008)
+#define EMAC_ISR_MOS			(0x00000002)
+#define EMAC_ISR_MOF			(0x00000001)
+
+
+/* STA CONTROL REG */
+#define EMAC_STACR_OC			(0x00008000)
+#define EMAC_STACR_PHYE			(0x00004000)
+#define EMAC_STACR_WRITE		(0x00002000)
+#define EMAC_STACR_READ			(0x00001000)
+#define EMAC_STACR_CLK_83MHZ	(0x00000800)  /* 0's for 50Mhz */
+#define EMAC_STACR_CLK_66MHZ	(0x00000400)
+#define EMAC_STACR_CLK_100MHZ	(0x00000C00)
+
+/* Transmit Request Threshold Register */
+#define EMAC_TRTR_256			(0x18000000)   /* 0's for 64 Bytes */
+#define EMAC_TRTR_192			(0x10000000)
+#define EMAC_TRTR_128			(0x01000000)
+
+/* the follwing defines are for the MadMAL status and control registers. */
+/* For bits 0..5 look at the mal.h file					 */
+#define EMAC_TX_CTRL_GFCS	(0x0200)
+#define EMAC_TX_CTRL_GP		(0x0100)
+#define EMAC_TX_CTRL_ISA	(0x0080)
+#define EMAC_TX_CTRL_RSA	(0x0040)
+#define EMAC_TX_CTRL_IVT	(0x0020)
+#define EMAC_TX_CTRL_RVT	(0x0010)
+
+#define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
+
+#define EMAC_TX_ST_BFCS		(0x0200)
+#define EMAC_TX_ST_BPP		(0x0100)
+#define EMAC_TX_ST_LCS		(0x0080)
+#define EMAC_TX_ST_ED		(0x0040)
+#define EMAC_TX_ST_EC		(0x0020)
+#define EMAC_TX_ST_LC		(0x0010)
+#define EMAC_TX_ST_MC		(0x0008)
+#define EMAC_TX_ST_SC		(0x0004)
+#define EMAC_TX_ST_UR		(0x0002)
+#define EMAC_TX_ST_SQE		(0x0001)
+
+#define EMAC_TX_ST_DEFAULT	(0x03F3)
+
+
+/* madmal receive status / Control bits */
+
+#define EMAC_RX_ST_OE		(0x0200)
+#define EMAC_RX_ST_PP		(0x0100)
+#define EMAC_RX_ST_BP		(0x0080)
+#define EMAC_RX_ST_RP		(0x0040)
+#define EMAC_RX_ST_SE		(0x0020)
+#define EMAC_RX_ST_AE		(0x0010)
+#define EMAC_RX_ST_BFCS		(0x0008)
+#define EMAC_RX_ST_PTL		(0x0004)
+#define EMAC_RX_ST_ORE		(0x0002)
+#define EMAC_RX_ST_IRE		(0x0001)
+/* all the errors we care about */
+#define EMAC_RX_ERRORS		(0x03FF)
+
+#endif /* CONFIG_440 */
+#endif /* _enetLib_h_ */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 9ca11d9..ac4ab47 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -690,6 +690,8 @@
 #define	PVR_405GPR_RB	0x50910951
 #define	PVR_440GP_RB	0x40120440
 #define	PVR_440GP_RC	0x40120481
+#define	PVR_440GX_RA	0x51B21850
+#define	PVR_440GX_RB	0x51B21851
 #define	PVR_405EP_RB	0x51210950
 #define	PVR_601		0x00010000
 #define	PVR_602		0x00050000
diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
index a442003..a53efe5 100644
--- a/include/asm-ppc/u-boot.h
+++ b/include/asm-ppc/u-boot.h
@@ -83,15 +83,20 @@
     defined(CONFIG_SXNI855T)		|| \
     defined(CONFIG_SVM_SC8xx)		|| \
     defined(CONFIG_MPC8540ADS)          || \
-    defined(CONFIG_MPC8560ADS)
+    defined(CONFIG_MPC8560ADS)      || \
+    defined(CONFIG_440_GX)
 	/* second onboard ethernet port */
 	unsigned char   bi_enet1addr[6];
 #endif
 #if defined(CFG_GT_6426x) || defined(CONFIG_SVM_SC8xx) || \
-    defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS)
+    defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS) || \
+    defined(CONFIG_440_GX)
 	/* third onboard ethernet port */
 	unsigned char	bi_enet2addr[6];
 #endif
+#if defined(CONFIG_440_GX)
+	unsigned char   bi_enet3addr[6];
+#endif
 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
 	unsigned int	bi_opbfreq;		/* OPB clock in Hz */
 	int		bi_iic_fast[2];		/* Use fast i2c mode */
diff --git a/include/bmp_logo.h b/include/bmp_logo.h
index 265f744..9c924b8 100644
--- a/include/bmp_logo.h
+++ b/include/bmp_logo.h
@@ -18,7 +18,7 @@
 	0x0343,  0x0454,  0x0565,  0x0565,  0x0676,  0x0787,  0x0898,  0x0999,
 	0x0AAA,  0x0ABA,  0x0BCB,  0x0CCC,  0x0DDD,  0x0EEE,  0x0FFF,  0x0FB3,
 	0x0FB4,  0x0FC4,  0x0FC5,  0x0FC6,  0x0FD7,  0x0FD8,  0x0FD9,  0x0FDA,
-	0x0FEA,  0x0FEB,  0x0FEC,  0x0FFD,  0x0FFE,  0x0FFF,  0x0FFF,  
+	0x0FEA,  0x0FEB,  0x0FEC,  0x0FFD,  0x0FFE,  0x0FFF,  0x0FFF,
 };
 
 unsigned char bmp_logo_bitmap[] = {
diff --git a/include/common.h b/include/common.h
index c04a9d3..fed04a9 100644
--- a/include/common.h
+++ b/include/common.h
@@ -266,7 +266,8 @@
 void	board_ether_init (void);
 #endif
 
-#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_MBX) || defined(CONFIG_IAD210)
+#if defined(CONFIG_RPXCLASSIC)	|| defined(CONFIG_MBX) || \
+    defined(CONFIG_IAD210)	|| defined(CONFIG_XPEDITE1K)
 void	board_get_enetaddr (uchar *addr);
 #endif
 
diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h
new file mode 100644
index 0000000..845449c
--- /dev/null
+++ b/include/configs/XPEDITE1K.h
@@ -0,0 +1,266 @@
+/*
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * config for XPedite1000 from XES Inc.
+ * Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
+ * (C) Copyright 2003 Sandburst Corporation
+ * board/config_EBONY.h - configuration for IBM 440GP Ref (Ebony)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_XPEDITE1K	1		/* Board is XPedite 1000 */
+#define CONFIG_4xx		1		/* ... PPC4xx family	*/
+#define CONFIG_440		1
+#define CONFIG_440_GX		1		/* 440 GX */
+#define CONFIG_BOARD_PRE_INIT	1		/* Call board_pre_init	*/
+#undef	CFG_DRAM_TEST				/* Disable-takes long time! */
+#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll */
+
+
+/* POST support */
+#define CONFIG_POST		(CFG_POST_RTC	   | \
+				 CFG_POST_I2C)
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE	    0x00000000		/* _must_ be 0		*/
+#define CFG_FLASH_BASE	    0xfff80000		/* start of FLASH	*/
+
+#define CFG_MONITOR_BASE    CFG_FLASH_BASE	/* start of monitor	*/
+#define CFG_PCI_MEMBASE	    0x80000000		/* mapped pci memory	*/
+#define CFG_PERIPHERAL_BASE 0xe0000000		/* internal peripherals */
+#define CFG_ISRAM_BASE	    0xc0000000		/* internal SRAM	*/
+#define CFG_PCI_BASE	    0xd0000000		/* internal PCI regs	*/
+
+#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
+#define CFG_GPIO_BASE	    (CFG_PERIPHERAL_BASE + 0x00000700)
+
+#define USR_LED0	    0x00000080
+#define USR_LED1	    0x00000100
+#define USR_LED2	    0x00000200
+#define USR_LED3	    0x00000400
+
+#ifndef __ASSEMBLY__
+extern unsigned long in32(unsigned int);
+extern void out32(unsigned int, unsigned long);
+
+#define LED0_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED0))
+#define LED1_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED1))
+#define LED2_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED2))
+#define LED3_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED3))
+
+#define LED0_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED0))
+#define LED1_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED1))
+#define LED2_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED2))
+#define LED3_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED3))
+#endif
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
+#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE   128		    /* num bytes initial data	*/
+
+
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR  (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET  CFG_POST_WORD_ADDR
+
+#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
+#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_BAUDRATE		9600
+
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+/* TBS:	 Xpedite 1000 has STMicro M41T00 via IIC */
+#define CONFIG_RTC_M41T11 1
+#define CFG_I2C_RTC_ADDR 0x68
+#define CFG_M41T11_BASE_YEAR 2000
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS	1		    /* number of banks	    */
+#define CFG_MAX_FLASH_SECT	8		    /* sectors per device   */
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	    /* Timeout for Flash Write (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup	*/
+#define SPD_EEPROM_ADDRESS {0x54}	/* SPD i2c spd addresses	*/
+#define CONFIG_VERY_BIG_RAM 1
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7f
+#define CFG_I2C_NOPROBES	{0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69}	/* Don't probe these addrs */
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_EEPROM 1
+#define CFG_ENV_SIZE		0x100	    /* Size of Environment vars */
+#define CFG_ENV_OFFSET		0x100
+#define CFG_I2C_EEPROM_ADDR	0x50		/* this is actually the second page of the eeprom */
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#define CONFIG_BOOTARGS		"root=/dev/hda1 "
+#define CONFIG_BOOTCOMMAND	"bootm ffc00000"    /* autoboot command */
+#define CONFIG_BOOTDELAY	-1		    /* disable autoboot */
+#define CONFIG_BAUDRATE		9600
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII			1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address phy0 not populated */
+#define CONFIG_PHY1_ADDR	1	/* PHY address phy1 not populated */
+#define CONFIG_PHY2_ADDR	4	/* PHY address phy2 */
+#define CONFIG_PHY3_ADDR	8	/* PHY address phy3 */
+#define CONFIG_NET_MULTI	1
+#define CFG_RX_ETH_BUFFER   32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_BEDBUG	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_PING | \
+				CFG_CMD_ELF | \
+			    CFG_CMD_MII | \
+				CFG_CMD_DIAG | \
+				CFG_CMD_FAT )
+
+/*				CFG_CMD_DHCP	| \ */
+/*				CFG_CMD_KGDB	| \ */
+
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI				    /* include pci support		*/
+#define CONFIG_PCI_PNP				/* do pci plug-and-play		*/
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
+#define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
+#define CFG_PCI_TARGET_INIT		    /* let board init pci target    */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		8192 /* For IBM 440GX CPUs */
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+#endif	/* __CONFIG_H */
diff --git a/include/ppc440.h b/include/ppc440.h
index 76930a5..6eb33f1 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1,148 +1,210 @@
 /*----------------------------------------------------------------------------+
 |
-|       This source code has been made available to you by IBM on an AS-IS
-|       basis.  Anyone receiving this source is licensed under IBM
-|       copyrights to use it in any way he or she deems fit, including
-|       copying it, modifying it, compiling it, and redistributing it either
-|       with or without modifications.  No license under IBM patents or
-|       patent applications is to be implied by the copyright license.
+|	This source code has been made available to you by IBM on an AS-IS
+|	basis.	Anyone receiving this source is licensed under IBM
+|	copyrights to use it in any way he or she deems fit, including
+|	copying it, modifying it, compiling it, and redistributing it either
+|	with or without modifications.	No license under IBM patents or
+|	patent applications is to be implied by the copyright license.
 |
-|       Any user of this software should understand that IBM cannot provide
-|       technical support for this software and will not be responsible for
-|       any consequences resulting from the use of this software.
+|	Any user of this software should understand that IBM cannot provide
+|	technical support for this software and will not be responsible for
+|	any consequences resulting from the use of this software.
 |
-|       Any person who transfers this source code or any derivative work
-|       must include the IBM copyright notice, this paragraph, and the
-|       preceding two paragraphs in the transferred software.
+|	Any person who transfers this source code or any derivative work
+|	must include the IBM copyright notice, this paragraph, and the
+|	preceding two paragraphs in the transferred software.
 |
-|       COPYRIGHT   I B M   CORPORATION 1999
-|       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+|	COPYRIGHT   I B M   CORPORATION 1999
+|	LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
 +----------------------------------------------------------------------------*/
 
-#ifndef	__PPC440_H__
+#ifndef __PPC440_H__
 #define __PPC440_H__
 
 /*--------------------------------------------------------------------- */
 /* Special Purpose Registers						*/
 /*--------------------------------------------------------------------- */
-	#define  dec	0x016	/* decrementer */
-	#define  srr0	0x01a	/* save/restore register 0 */
-	#define  srr1	0x01b	/* save/restore register 1 */
-	#define  pid	0x030	/* process id */
-	#define  decar	0x036	/* decrementer auto-reload */
-	#define  csrr0	0x03a	/* critical save/restore register 0 */
-	#define  csrr1	0x03b	/* critical save/restore register 1 */
-	#define  dear	0x03d	/* data exception address register */
-	#define  esr	0x03e	/* exception syndrome register */
-	#define  ivpr	0x03f	/* interrupt prefix register */
-	#define  usprg0	0x100	/* user special purpose register general 0 */
-	#define  usprg1	0x110	/* user special purpose register general 1 */
-	#define  sprg1	0x111	/* special purpose register general 1 */
-	#define  sprg2	0x112	/* special purpose register general 2 */
-	#define  sprg3	0x113	/* special purpose register general 3 */
-	#define  sprg4	0x114	/* special purpose register general 4 */
-	#define  sprg5	0x115	/* special purpose register general 5 */
-	#define  sprg6	0x116	/* special purpose register general 6 */
-	#define  sprg7	0x117	/* special purpose register general 7 */
-	#define  tbl	0x11c	/* time base lower (supervisor)*/
-	#define  tbu	0x11d	/* time base upper (supervisor)*/
-	#define  pir	0x11e	/* processor id register */
-	/*#define  pvr	0x11f	 processor version register */
-	#define  dbsr	0x130	/* debug status register */
-	#define  dbcr0	0x134	/* debug control register 0 */
-	#define  dbcr1	0x135	/* debug control register 1 */
-	#define  dbcr2	0x136	/* debug control register 2 */
-	#define  iac1	0x138	/* instruction address compare 1 */
-	#define  iac2	0x139	/* instruction address compare 2 */
-	#define  iac3	0x13a	/* instruction address compare 3 */
-	#define  iac4	0x13b	/* instruction address compare 4 */
-	#define  dac1	0x13c	/* data address compare 1 */
-	#define  dac2	0x13d	/* data address compare 2 */
-	#define  dvc1	0x13e	/* data value compare 1 */
-	#define  dvc2	0x13f	/* data value compare 2 */
-	#define  tsr	0x150	/* timer status register */
-	#define  tcr	0x154	/* timer control register */
-	#define  ivor0	0x190	/* interrupt vector offset register 0 */
-	#define  ivor1	0x191	/* interrupt vector offset register 1 */
-	#define  ivor2	0x192	/* interrupt vector offset register 2 */
-	#define  ivor3	0x193	/* interrupt vector offset register 3 */
-	#define  ivor4	0x194	/* interrupt vector offset register 4 */
-	#define  ivor5	0x195	/* interrupt vector offset register 5 */
-	#define  ivor6	0x196	/* interrupt vector offset register 6 */
-	#define  ivor7	0x197	/* interrupt vector offset register 7 */
-	#define  ivor8	0x198	/* interrupt vector offset register 8 */
-	#define  ivor9	0x199	/* interrupt vector offset register 9 */
-	#define  ivor10	0x19a	/* interrupt vector offset register 10 */
-	#define  ivor11	0x19b	/* interrupt vector offset register 11 */
-	#define  ivor12	0x19c	/* interrupt vector offset register 12 */
-	#define  ivor13	0x19d	/* interrupt vector offset register 13 */
-	#define  ivor14	0x19e	/* interrupt vector offset register 14 */
-	#define  ivor15	0x19f	/* interrupt vector offset register 15 */
-	#define  inv0	0x370	/* instruction cache normal victim 0 */
-	#define  inv1	0x371	/* instruction cache normal victim 1 */
-	#define  inv2	0x372	/* instruction cache normal victim 2 */
-	#define  inv3	0x373	/* instruction cache normal victim 3 */
-	#define  itv0	0x374	/* instruction cache transient victim 0 */
-	#define  itv1	0x375	/* instruction cache transient victim 1 */
-	#define  itv2	0x376	/* instruction cache transient victim 2 */
-	#define  itv3	0x377	/* instruction cache transient victim 3 */
-	#define  dnv0	0x390	/* data cache normal victim 0 */
-	#define  dnv1	0x391	/* data cache normal victim 1 */
-	#define  dnv2	0x392	/* data cache normal victim 2 */
-	#define  dnv3	0x393	/* data cache normal victim 3 */
-	#define  dtv0	0x394	/* data cache transient victim 0 */
-	#define  dtv1	0x395	/* data cache transient victim 1 */
-	#define  dtv2	0x396	/* data cache transient victim 2 */
-	#define  dtv3	0x397	/* data cache transient victim 3 */
-	#define  dvlim	0x398	/* data cache victim limit */
-	#define  ivlim	0x399	/* instruction cache victim limit */
-	#define  rstcfg	0x39b	/* reset configuration */
-	#define  dcdbtrl 0x39c	/* data cache debug tag register low */
-	#define  dcdbtrh 0x39d	/* data cache debug tag register high */
-	#define  icdbtrl 0x39e	/* instruction cache debug tag register low */
-	#define  icdbtrh 0x39f	/* instruction cache debug tag register high */
-	#define  mmucr	0x3b2	/* mmu control register */
-	#define  ccr0	0x3b3	/* core configuration register 0 */
-	#define  icdbdr 0x3d3	/* instruction cache debug data register */
-	#define  dbdr	0x3f3	/* debug data register */
+#define	 dec	0x016	/* decrementer */
+#define	 srr0	0x01a	/* save/restore register 0 */
+#define	 srr1	0x01b	/* save/restore register 1 */
+#define	 pid	0x030	/* process id */
+#define	 decar	0x036	/* decrementer auto-reload */
+#define	 csrr0	0x03a	/* critical save/restore register 0 */
+#define	 csrr1	0x03b	/* critical save/restore register 1 */
+#define	 dear	0x03d	/* data exception address register */
+#define	 esr	0x03e	/* exception syndrome register */
+#define	 ivpr	0x03f	/* interrupt prefix register */
+#define	 usprg0 0x100	/* user special purpose register general 0 */
+#define	 usprg1 0x110	/* user special purpose register general 1 */
+#define	 sprg1	0x111	/* special purpose register general 1 */
+#define	 sprg2	0x112	/* special purpose register general 2 */
+#define	 sprg3	0x113	/* special purpose register general 3 */
+#define	 sprg4	0x114	/* special purpose register general 4 */
+#define	 sprg5	0x115	/* special purpose register general 5 */
+#define	 sprg6	0x116	/* special purpose register general 6 */
+#define	 sprg7	0x117	/* special purpose register general 7 */
+#define	 tbl	0x11c	/* time base lower (supervisor)*/
+#define	 tbu	0x11d	/* time base upper (supervisor)*/
+#define	 pir	0x11e	/* processor id register */
+/*#define  pvr	0x11f	 processor version register */
+#define	 dbsr	0x130	/* debug status register */
+#define	 dbcr0	0x134	/* debug control register 0 */
+#define	 dbcr1	0x135	/* debug control register 1 */
+#define	 dbcr2	0x136	/* debug control register 2 */
+#define	 iac1	0x138	/* instruction address compare 1 */
+#define	 iac2	0x139	/* instruction address compare 2 */
+#define	 iac3	0x13a	/* instruction address compare 3 */
+#define	 iac4	0x13b	/* instruction address compare 4 */
+#define	 dac1	0x13c	/* data address compare 1 */
+#define	 dac2	0x13d	/* data address compare 2 */
+#define	 dvc1	0x13e	/* data value compare 1 */
+#define	 dvc2	0x13f	/* data value compare 2 */
+#define	 tsr	0x150	/* timer status register */
+#define	 tcr	0x154	/* timer control register */
+#define	 ivor0	0x190	/* interrupt vector offset register 0 */
+#define	 ivor1	0x191	/* interrupt vector offset register 1 */
+#define	 ivor2	0x192	/* interrupt vector offset register 2 */
+#define	 ivor3	0x193	/* interrupt vector offset register 3 */
+#define	 ivor4	0x194	/* interrupt vector offset register 4 */
+#define	 ivor5	0x195	/* interrupt vector offset register 5 */
+#define	 ivor6	0x196	/* interrupt vector offset register 6 */
+#define	 ivor7	0x197	/* interrupt vector offset register 7 */
+#define	 ivor8	0x198	/* interrupt vector offset register 8 */
+#define	 ivor9	0x199	/* interrupt vector offset register 9 */
+#define	 ivor10 0x19a	/* interrupt vector offset register 10 */
+#define	 ivor11 0x19b	/* interrupt vector offset register 11 */
+#define	 ivor12 0x19c	/* interrupt vector offset register 12 */
+#define	 ivor13 0x19d	/* interrupt vector offset register 13 */
+#define	 ivor14 0x19e	/* interrupt vector offset register 14 */
+#define	 ivor15 0x19f	/* interrupt vector offset register 15 */
+#if defined(CONFIG_440_GX)
+#define	 mcsrr0 0x23a	/* machine check save/restore register 0 */
+#define	 mcsrr1 0x23b	/* mahcine check save/restore register 1 */
+#define	 mcsr	0x23c	/* machine check status register */
+#endif
+#define	 inv0	0x370	/* instruction cache normal victim 0 */
+#define	 inv1	0x371	/* instruction cache normal victim 1 */
+#define	 inv2	0x372	/* instruction cache normal victim 2 */
+#define	 inv3	0x373	/* instruction cache normal victim 3 */
+#define	 itv0	0x374	/* instruction cache transient victim 0 */
+#define	 itv1	0x375	/* instruction cache transient victim 1 */
+#define	 itv2	0x376	/* instruction cache transient victim 2 */
+#define	 itv3	0x377	/* instruction cache transient victim 3 */
+#define	 dnv0	0x390	/* data cache normal victim 0 */
+#define	 dnv1	0x391	/* data cache normal victim 1 */
+#define	 dnv2	0x392	/* data cache normal victim 2 */
+#define	 dnv3	0x393	/* data cache normal victim 3 */
+#define	 dtv0	0x394	/* data cache transient victim 0 */
+#define	 dtv1	0x395	/* data cache transient victim 1 */
+#define	 dtv2	0x396	/* data cache transient victim 2 */
+#define	 dtv3	0x397	/* data cache transient victim 3 */
+#define	 dvlim	0x398	/* data cache victim limit */
+#define	 ivlim	0x399	/* instruction cache victim limit */
+#define	 rstcfg 0x39b	/* reset configuration */
+#define	 dcdbtrl 0x39c	/* data cache debug tag register low */
+#define	 dcdbtrh 0x39d	/* data cache debug tag register high */
+#define	 icdbtrl 0x39e	/* instruction cache debug tag register low */
+#define	 icdbtrh 0x39f	/* instruction cache debug tag register high */
+#define	 mmucr	0x3b2	/* mmu control register */
+#define	 ccr0	0x3b3	/* core configuration register 0 */
+#define	 icdbdr 0x3d3	/* instruction cache debug data register */
+#define	 dbdr	0x3f3	/* debug data register */
 
 /******************************************************************************
  * DCRs & Related
  ******************************************************************************/
 
 /*-----------------------------------------------------------------------------
+ | Clocking Controller
+ +----------------------------------------------------------------------------*/
+#define CLOCKING_DCR_BASE 0x0c
+#define clkcfga	 (CLOCKING_DCR_BASE+0x0)
+#define clkcfgd	 (CLOCKING_DCR_BASE+0x1)
+
+/* values for clkcfga register - indirect addressing of these regs */
+#define clk_clkukpd	0x0020
+#define clk_pllc	0x0040
+#define clk_plld	0x0060
+#define clk_primad	0x0080
+#define clk_primbd	0x00a0
+#define clk_opbd	0x00c0
+#define clk_perd	0x00e0
+#define clk_mald	0x0100
+#define clk_icfg	0x0140
+
+/* 440gx sdr register definations */
+#define SDR_DCR_BASE	0x0e
+#define sdrcfga		(SDR_DCR_BASE+0x0)
+#define sdrcfgd		(SDR_DCR_BASE+0x1)
+#define sdr_sdstp0	0x0020	    /* */
+#define sdr_sdstp1	0x0021	    /* */
+#define sdr_pinstp	0x0040
+#define sdr_sdcs	0x0060
+#define sdr_ecid0	0x0080
+#define sdr_ecid1	0x0081
+#define sdr_ecid2	0x0082
+#define sdr_jtag	0x00c0
+#define sdr_ddrdl	0x00e0
+#define sdr_ebc		0x0100
+#define sdr_uart0	0x0120	/* UART0 Config */
+#define sdr_uart1	0x0121	/* UART1 Config */
+#define sdr_cp440	0x0180
+#define sdr_xcr		0x01c0
+#define sdr_xpllc	0x01c1
+#define sdr_xplld	0x01c2
+#define sdr_srst	0x0200
+#define sdr_slpipe	0x0220
+#define sdr_amp		0x0240
+#define sdr_mirq0	0x0260
+#define sdr_mirq1	0x0261
+#define sdr_maltbl	0x0280
+#define sdr_malrbl	0x02a0
+#define sdr_maltbs	0x02c0
+#define sdr_malrbs	0x02e0
+#define sdr_cust0	0x4000
+#define sdr_sdstp2	0x4001
+#define sdr_cust1	0x4002
+#define sdr_sdstp3	0x4003
+#define sdr_pfc0	0x4100	/* Pin Function 0 */
+#define sdr_pfc1	0x4101	/* Pin Function 1 */
+#define sdr_plbtr	0x4200
+#define sdr_mfr		0x4300	/* SDR0_MFR reg */
+
+
+/*-----------------------------------------------------------------------------
  | SDRAM Controller
  +----------------------------------------------------------------------------*/
 #define SDRAM_DCR_BASE 0x10
-#define memcfga  (SDRAM_DCR_BASE+0x0)   /* Memory configuration address reg */
-#define memcfgd  (SDRAM_DCR_BASE+0x1)   /* Memory configuration data reg    */
+#define memcfga	 (SDRAM_DCR_BASE+0x0)	/* Memory configuration address reg */
+#define memcfgd	 (SDRAM_DCR_BASE+0x1)	/* Memory configuration data reg    */
 
-  /* values for memcfga register - indirect addressing of these regs        */
-  #define mem_besr0_clr     0x0000  /* bus error status reg 0 (clr)         */
-  #define mem_besr0_set     0x0004  /* bus error status reg 0 (set)         */
-  #define mem_besr1_clr     0x0008  /* bus error status reg 1 (clr)         */
-  #define mem_besr1_set     0x000c  /* bus error status reg 1 (set)         */
-  #define mem_bear          0x0010  /* bus error address reg                */
-  #define mem_mirq_clr      0x0011  /* bus master interrupt (clr)           */
-  #define mem_mirq_set      0x0012  /* bus master interrupt (set)           */
-  #define mem_slio          0x0018  /* ddr sdram slave interface options    */
-  #define mem_cfg0          0x0020  /* ddr sdram options 0                  */
-  #define mem_cfg1          0x0021  /* ddr sdram options 1                  */
-  #define mem_devopt        0x0022  /* ddr sdram device options             */
-  #define mem_mcsts         0x0024  /* memory controller status             */
-  #define mem_rtr           0x0030  /* refresh timer register               */
-  #define mem_pmit          0x0034  /* power management idle timer          */
-  #define mem_uabba         0x0038  /* plb UABus base address               */
-  #define mem_b0cr          0x0040  /* ddr sdram bank 0 configuration       */
-  #define mem_b1cr          0x0044  /* ddr sdram bank 1 configuration       */
-  #define mem_b2cr          0x0048  /* ddr sdram bank 2 configuration       */
-  #define mem_b3cr          0x004c  /* ddr sdram bank 3 configuration       */
-  #define mem_tr0           0x0080  /* sdram timing register 0              */
-  #define mem_tr1           0x0081  /* sdram timing register 1              */
-  #define mem_clktr         0x0082  /* ddr clock timing register            */
-  #define mem_wddctr        0x0083  /* write data/dm/dqs clock timing reg   */
-  #define mem_dlycal        0x0084  /* delay line calibration register      */
-  #define mem_eccesr        0x0098  /* ECC error status                     */
+/* values for memcfga register - indirect addressing of these regs	    */
+#define mem_besr0_clr	0x0000	/* bus error status reg 0 (clr)		    */
+#define mem_besr0_set	0x0004	/* bus error status reg 0 (set)		    */
+#define mem_besr1_clr	0x0008	/* bus error status reg 1 (clr)		    */
+#define mem_besr1_set	0x000c	/* bus error status reg 1 (set)		    */
+#define mem_bear	0x0010	/* bus error address reg		    */
+#define mem_mirq_clr	0x0011	/* bus master interrupt (clr)		    */
+#define mem_mirq_set	0x0012	/* bus master interrupt (set)		    */
+#define mem_slio	0x0018	/* ddr sdram slave interface options	    */
+#define mem_cfg0	0x0020	/* ddr sdram options 0			    */
+#define mem_cfg1	0x0021	/* ddr sdram options 1			    */
+#define mem_devopt	0x0022	/* ddr sdram device options		    */
+#define mem_mcsts	0x0024	/* memory controller status		    */
+#define mem_rtr		0x0030	/* refresh timer register		    */
+#define mem_pmit	0x0034	/* power management idle timer		    */
+#define mem_uabba	0x0038	/* plb UABus base address		    */
+#define mem_b0cr	0x0040	/* ddr sdram bank 0 configuration	    */
+#define mem_b1cr	0x0044	/* ddr sdram bank 1 configuration	    */
+#define mem_b2cr	0x0048	/* ddr sdram bank 2 configuration	    */
+#define mem_b3cr	0x004c	/* ddr sdram bank 3 configuration	    */
+#define mem_tr0		0x0080	/* sdram timing register 0		    */
+#define mem_tr1		0x0081	/* sdram timing register 1		    */
+#define mem_clktr	0x0082	/* ddr clock timing register		    */
+#define mem_wddctr	0x0083	/* write data/dm/dqs clock timing reg	    */
+#define mem_dlycal	0x0084	/* delay line calibration register	    */
+#define mem_eccesr	0x0098	/* ECC error status			    */
 
 /*-----------------------------------------------------------------------------
  | Extrnal Bus Controller
@@ -150,45 +212,61 @@
 #define EBC_DCR_BASE 0x12
 #define ebccfga (EBC_DCR_BASE+0x0)   /* External bus controller addr reg     */
 #define ebccfgd (EBC_DCR_BASE+0x1)   /* External bus controller data reg     */
-  /* values for ebccfga register - indirect addressing of these regs */
-  #define pb0cr       0x00    /* periph bank 0 config reg            */
-  #define pb1cr       0x01    /* periph bank 1 config reg            */
-  #define pb2cr       0x02    /* periph bank 2 config reg            */
-  #define pb3cr       0x03    /* periph bank 3 config reg            */
-  #define pb4cr       0x04    /* periph bank 4 config reg            */
-  #define pb5cr       0x05    /* periph bank 5 config reg            */
-  #define pb6cr       0x06    /* periph bank 6 config reg            */
-  #define pb7cr       0x07    /* periph bank 7 config reg            */
-  #define pb0ap       0x10    /* periph bank 0 access parameters     */
-  #define pb1ap       0x11    /* periph bank 1 access parameters     */
-  #define pb2ap       0x12    /* periph bank 2 access parameters     */
-  #define pb3ap       0x13    /* periph bank 3 access parameters     */
-  #define pb4ap       0x14    /* periph bank 4 access parameters     */
-  #define pb5ap       0x15    /* periph bank 5 access parameters     */
-  #define pb6ap       0x16    /* periph bank 6 access parameters     */
-  #define pb7ap       0x17    /* periph bank 7 access parameters     */
-  #define pbear       0x20    /* periph bus error addr reg           */
-  #define pbesr       0x21    /* periph bus error status reg         */
-  #define xbcfg       0x23    /* external bus configuration reg      */
-  #define xbcid       0x23    /* external bus core id reg            */
+/* values for ebccfga register - indirect addressing of these regs */
+#define pb0cr		0x00	/* periph bank 0 config reg		*/
+#define pb1cr		0x01	/* periph bank 1 config reg		*/
+#define pb2cr		0x02	/* periph bank 2 config reg		*/
+#define pb3cr		0x03	/* periph bank 3 config reg		*/
+#define pb4cr		0x04	/* periph bank 4 config reg		*/
+#define pb5cr		0x05	/* periph bank 5 config reg		*/
+#define pb6cr		0x06	/* periph bank 6 config reg		*/
+#define pb7cr		0x07	/* periph bank 7 config reg		*/
+#define pb0ap		0x10	/* periph bank 0 access parameters	*/
+#define pb1ap		0x11	/* periph bank 1 access parameters	*/
+#define pb2ap		0x12	/* periph bank 2 access parameters	*/
+#define pb3ap		0x13	/* periph bank 3 access parameters	*/
+#define pb4ap		0x14	/* periph bank 4 access parameters	*/
+#define pb5ap		0x15	/* periph bank 5 access parameters	*/
+#define pb6ap		0x16	/* periph bank 6 access parameters	*/
+#define pb7ap		0x17	/* periph bank 7 access parameters	*/
+#define pbear		0x20	/* periph bus error addr reg		*/
+#define pbesr		0x21	/* periph bus error status reg		*/
+#define xbcfg		0x23	/* external bus configuration reg	*/
+#define xbcid		0x23	/* external bus core id reg		*/
 
 /*-----------------------------------------------------------------------------
  | Internal SRAM
  +----------------------------------------------------------------------------*/
 #define ISRAM0_DCR_BASE 0x020
-#define isram0_sb0cr    (ISRAM0_DCR_BASE+0x00)  /* SRAM bank config 0*/
-#define isram0_sb1cr    (ISRAM0_DCR_BASE+0x01)  /* SRAM bank config 1*/
-#define isram0_sb2cr    (ISRAM0_DCR_BASE+0x02)  /* SRAM bank config 2*/
-#define isram0_sb3cr    (ISRAM0_DCR_BASE+0x03)  /* SRAM bank config 3*/
-#define isram0_bear     (ISRAM0_DCR_BASE+0x04)  /* SRAM bus error addr reg */
-#define isram0_besr0    (ISRAM0_DCR_BASE+0x05)  /* SRAM bus error status reg 0 */
-#define isram0_besr1    (ISRAM0_DCR_BASE+0x06)  /* SRAM bus error status reg 1 */
-#define isram0_pmeg     (ISRAM0_DCR_BASE+0x07)  /* SRAM power management */
-#define isram0_cid      (ISRAM0_DCR_BASE+0x08)  /* SRAM bus core id reg */
-#define isram0_revid    (ISRAM0_DCR_BASE+0x09)  /* SRAM bus revision id reg */
-#define isram0_dpc      (ISRAM0_DCR_BASE+0x0a)  /* SRAM data parity check reg */
+#define isram0_sb0cr	(ISRAM0_DCR_BASE+0x00)	/* SRAM bank config 0*/
+#define isram0_sb1cr	(ISRAM0_DCR_BASE+0x01)	/* SRAM bank config 1*/
+#define isram0_sb2cr	(ISRAM0_DCR_BASE+0x02)	/* SRAM bank config 2*/
+#define isram0_sb3cr	(ISRAM0_DCR_BASE+0x03)	/* SRAM bank config 3*/
+#define isram0_bear	(ISRAM0_DCR_BASE+0x04)	/* SRAM bus error addr reg */
+#define isram0_besr0	(ISRAM0_DCR_BASE+0x05)	/* SRAM bus error status reg 0 */
+#define isram0_besr1	(ISRAM0_DCR_BASE+0x06)	/* SRAM bus error status reg 1 */
+#define isram0_pmeg	(ISRAM0_DCR_BASE+0x07)	/* SRAM power management */
+#define isram0_cid	(ISRAM0_DCR_BASE+0x08)	/* SRAM bus core id reg */
+#define isram0_revid	(ISRAM0_DCR_BASE+0x09)	/* SRAM bus revision id reg */
+#define isram0_dpc	(ISRAM0_DCR_BASE+0x0a)	/* SRAM data parity check reg */
 
 /*-----------------------------------------------------------------------------
+ | L2 Cache
+ +----------------------------------------------------------------------------*/
+#if defined (CONFIG_440_GX)
+#define L2_CACHE_BASE	0x030
+#define l2_cache_cfg	(L2_CACHE_BASE+0x00)	/* L2 Cache Config	*/
+#define l2_cache_cmd	(L2_CACHE_BASE+0x01)	/* L2 Cache Command	*/
+#define l2_cache_addr	(L2_CACHE_BASE+0x02)	/* L2 Cache Address	*/
+#define l2_cache_data	(L2_CACHE_BASE+0x03)	/* L2 Cache Data	*/
+#define l2_cache_stat	(L2_CACHE_BASE+0x04)	/* L2 Cache Status	*/
+#define l2_cache_cver	(L2_CACHE_BASE+0x05)	/* L2 Cache Revision ID */
+#define l2_cache_snp0	(L2_CACHE_BASE+0x06)	/* L2 Cache Snoop reg 0 */
+#define l2_cache_snp1	(L2_CACHE_BASE+0x07)	/* L2 Cache Snoop reg 1 */
+
+#endif /* CONFIG_440_GX */
+
+/*-----------------------------------------------------------------------------
  | On-Chip Buses
  +----------------------------------------------------------------------------*/
 /* TODO: as needed */
@@ -197,10 +275,15 @@
  | Clocking, Power Management and Chip Control
  +----------------------------------------------------------------------------*/
 #define CNTRL_DCR_BASE 0x0b0
-
-#define cpc0_sr     (CNTRL_DCR_BASE+0x00)   /* CPM status register          */
-#define cpc0_er     (CNTRL_DCR_BASE+0x01)   /* CPM enable register          */
-#define cpc0_fr     (CNTRL_DCR_BASE+0x02)   /* CPM force register           */
+#if defined (CONFIG_440_GX)
+#define cpc0_er	    (CNTRL_DCR_BASE+0x00)   /* CPM enable register	    */
+#define cpc0_fr	    (CNTRL_DCR_BASE+0x01)   /* CPM force register	    */
+#define cpc0_sr	    (CNTRL_DCR_BASE+0x02)   /* CPM status register	    */
+#else
+#define cpc0_sr	    (CNTRL_DCR_BASE+0x00)   /* CPM status register	    */
+#define cpc0_er	    (CNTRL_DCR_BASE+0x01)   /* CPM enable register	    */
+#define cpc0_fr	    (CNTRL_DCR_BASE+0x02)   /* CPM force register	    */
+#endif
 
 #define cpc0_sys0   (CNTRL_DCR_BASE+0x30)   /* System configuration reg 0   */
 #define cpc0_sys1   (CNTRL_DCR_BASE+0x31)   /* System configuration reg 1   */
@@ -212,31 +295,54 @@
 #define cpc0_strp2	(CNTRL_DCR_BASE+0x36)	/* Power-on config reg 2 (RO)	*/
 #define cpc0_strp3	(CNTRL_DCR_BASE+0x37)	/* Power-on config reg 3 (RO)	*/
 
-#define cntrl0      (CNTRL_DCR_BASE+0x3b)   /* Control 0 register           */
-#define cntrl1      (CNTRL_DCR_BASE+0x3a)   /* Control 1 register           */
+#define cntrl0	    (CNTRL_DCR_BASE+0x3b)   /* Control 0 register	    */
+#define cntrl1	    (CNTRL_DCR_BASE+0x3a)   /* Control 1 register	    */
 
 /*-----------------------------------------------------------------------------
  | Universal interrupt controller
  +----------------------------------------------------------------------------*/
 #define UIC0_DCR_BASE 0xc0
-#define uic0sr  (UIC0_DCR_BASE+0x0)   /* UIC0 status                       */
-#define uic0er  (UIC0_DCR_BASE+0x2)   /* UIC0 enable                       */
-#define uic0cr  (UIC0_DCR_BASE+0x3)   /* UIC0 critical                     */
-#define uic0pr  (UIC0_DCR_BASE+0x4)   /* UIC0 polarity                     */
-#define uic0tr  (UIC0_DCR_BASE+0x5)   /* UIC0 triggering                   */
-#define uic0msr (UIC0_DCR_BASE+0x6)   /* UIC0 masked status                */
-#define uic0vr  (UIC0_DCR_BASE+0x7)   /* UIC0 vector                       */
-#define uic0vcr (UIC0_DCR_BASE+0x8)   /* UIC0 vector configuration         */
+#define uic0sr	(UIC0_DCR_BASE+0x0)   /* UIC0 status			   */
+#define uic0er	(UIC0_DCR_BASE+0x2)   /* UIC0 enable			   */
+#define uic0cr	(UIC0_DCR_BASE+0x3)   /* UIC0 critical			   */
+#define uic0pr	(UIC0_DCR_BASE+0x4)   /* UIC0 polarity			   */
+#define uic0tr	(UIC0_DCR_BASE+0x5)   /* UIC0 triggering		   */
+#define uic0msr (UIC0_DCR_BASE+0x6)   /* UIC0 masked status		   */
+#define uic0vr	(UIC0_DCR_BASE+0x7)   /* UIC0 vector			   */
+#define uic0vcr (UIC0_DCR_BASE+0x8)   /* UIC0 vector configuration	   */
 
 #define UIC1_DCR_BASE 0xd0
-#define uic1sr  (UIC1_DCR_BASE+0x0)   /* UIC1 status                       */
-#define uic1er  (UIC1_DCR_BASE+0x2)   /* UIC1 enable                       */
-#define uic1cr  (UIC1_DCR_BASE+0x3)   /* UIC1 critical                     */
-#define uic1pr  (UIC1_DCR_BASE+0x4)   /* UIC1 polarity                     */
-#define uic1tr  (UIC1_DCR_BASE+0x5)   /* UIC1 triggering                   */
-#define uic1msr (UIC1_DCR_BASE+0x6)   /* UIC1 masked status                */
-#define uic1vr  (UIC1_DCR_BASE+0x7)   /* UIC1 vector                       */
-#define uic1vcr (UIC1_DCR_BASE+0x8)   /* UIC1 vector configuration         */
+#define uic1sr	(UIC1_DCR_BASE+0x0)   /* UIC1 status			   */
+#define uic1er	(UIC1_DCR_BASE+0x2)   /* UIC1 enable			   */
+#define uic1cr	(UIC1_DCR_BASE+0x3)   /* UIC1 critical			   */
+#define uic1pr	(UIC1_DCR_BASE+0x4)   /* UIC1 polarity			   */
+#define uic1tr	(UIC1_DCR_BASE+0x5)   /* UIC1 triggering		   */
+#define uic1msr (UIC1_DCR_BASE+0x6)   /* UIC1 masked status		   */
+#define uic1vr	(UIC1_DCR_BASE+0x7)   /* UIC1 vector			   */
+#define uic1vcr (UIC1_DCR_BASE+0x8)   /* UIC1 vector configuration	   */
+
+#if defined(CONFIG_440_GX)
+#define UIC2_DCR_BASE 0x210
+#define uic2sr	(UIC2_DCR_BASE+0x0)   /* UIC2 status			   */
+#define uic2er	(UIC2_DCR_BASE+0x2)   /* UIC2 enable			   */
+#define uic2cr	(UIC2_DCR_BASE+0x3)   /* UIC2 critical			   */
+#define uic2pr	(UIC2_DCR_BASE+0x4)   /* UIC2 polarity			   */
+#define uic2tr	(UIC2_DCR_BASE+0x5)   /* UIC2 triggering		   */
+#define uic2msr (UIC2_DCR_BASE+0x6)   /* UIC2 masked status		   */
+#define uic2vr	(UIC2_DCR_BASE+0x7)   /* UIC2 vector			   */
+#define uic2vcr (UIC2_DCR_BASE+0x8)   /* UIC2 vector configuration	   */
+
+
+#define UIC_DCR_BASE 0x200
+#define uicb0sr	 (UIC_DCR_BASE+0x0)   /* UIC Base Status Register	   */
+#define uicb0er	 (UIC_DCR_BASE+0x2)   /* UIC Base enable		   */
+#define uicb0cr	 (UIC_DCR_BASE+0x3)   /* UIC Base critical		   */
+#define uicb0pr	 (UIC_DCR_BASE+0x4)   /* UIC Base polarity		   */
+#define uicb0tr	 (UIC_DCR_BASE+0x5)   /* UIC Base triggering		   */
+#define uicb0msr (UIC_DCR_BASE+0x6)   /* UIC Base masked status		   */
+#define uicb0vr	 (UIC_DCR_BASE+0x7)   /* UIC Base vector		   */
+#define uicb0vcr (UIC_DCR_BASE+0x8)   /* UIC Base vector configuration	   */
+#endif /* CONFIG_440_GX */
 
 /* The following is for compatibility with 405 code */
 #define uicsr  uic0sr
@@ -252,204 +358,308 @@
  | DMA
  +----------------------------------------------------------------------------*/
 #define DMA_DCR_BASE 0x100
-#define dmacr0  (DMA_DCR_BASE+0x00)  /* DMA channel control register 0       */
-#define dmact0  (DMA_DCR_BASE+0x01)  /* DMA count register 0                 */
-#define dmasah0 (DMA_DCR_BASE+0x02)  /* DMA source address high 0            */
-#define dmasal0 (DMA_DCR_BASE+0x03)  /* DMA source address low 0             */
-#define dmadah0 (DMA_DCR_BASE+0x04)  /* DMA destination address high 0       */
-#define dmadal0 (DMA_DCR_BASE+0x05)  /* DMA destination address low 0        */
+#define dmacr0	(DMA_DCR_BASE+0x00)  /* DMA channel control register 0	     */
+#define dmact0	(DMA_DCR_BASE+0x01)  /* DMA count register 0		     */
+#define dmasah0 (DMA_DCR_BASE+0x02)  /* DMA source address high 0	     */
+#define dmasal0 (DMA_DCR_BASE+0x03)  /* DMA source address low 0	     */
+#define dmadah0 (DMA_DCR_BASE+0x04)  /* DMA destination address high 0	     */
+#define dmadal0 (DMA_DCR_BASE+0x05)  /* DMA destination address low 0	     */
 #define dmasgh0 (DMA_DCR_BASE+0x06)  /* DMA scatter/gather desc addr high 0  */
 #define dmasgl0 (DMA_DCR_BASE+0x07)  /* DMA scatter/gather desc addr low 0   */
-#define dmacr1  (DMA_DCR_BASE+0x08)  /* DMA channel control register 1       */
-#define dmact1  (DMA_DCR_BASE+0x09)  /* DMA count register 1                 */
-#define dmasah1 (DMA_DCR_BASE+0x0a)  /* DMA source address high 1            */
-#define dmasal1 (DMA_DCR_BASE+0x0b)  /* DMA source address low 1             */
-#define dmadah1 (DMA_DCR_BASE+0x0c)  /* DMA destination address high 1       */
-#define dmadal1 (DMA_DCR_BASE+0x0d)  /* DMA destination address low 1        */
+#define dmacr1	(DMA_DCR_BASE+0x08)  /* DMA channel control register 1	     */
+#define dmact1	(DMA_DCR_BASE+0x09)  /* DMA count register 1		     */
+#define dmasah1 (DMA_DCR_BASE+0x0a)  /* DMA source address high 1	     */
+#define dmasal1 (DMA_DCR_BASE+0x0b)  /* DMA source address low 1	     */
+#define dmadah1 (DMA_DCR_BASE+0x0c)  /* DMA destination address high 1	     */
+#define dmadal1 (DMA_DCR_BASE+0x0d)  /* DMA destination address low 1	     */
 #define dmasgh1 (DMA_DCR_BASE+0x0e)  /* DMA scatter/gather desc addr high 1  */
 #define dmasgl1 (DMA_DCR_BASE+0x0f)  /* DMA scatter/gather desc addr low 1   */
-#define dmacr2  (DMA_DCR_BASE+0x10)  /* DMA channel control register 2       */
-#define dmact2  (DMA_DCR_BASE+0x11)  /* DMA count register 2                 */
-#define dmasah2 (DMA_DCR_BASE+0x12)  /* DMA source address high 2            */
-#define dmasal2 (DMA_DCR_BASE+0x13)  /* DMA source address low 2             */
-#define dmadah2 (DMA_DCR_BASE+0x14)  /* DMA destination address high 2       */
-#define dmadal2 (DMA_DCR_BASE+0x15)  /* DMA destination address low 2        */
+#define dmacr2	(DMA_DCR_BASE+0x10)  /* DMA channel control register 2	     */
+#define dmact2	(DMA_DCR_BASE+0x11)  /* DMA count register 2		     */
+#define dmasah2 (DMA_DCR_BASE+0x12)  /* DMA source address high 2	     */
+#define dmasal2 (DMA_DCR_BASE+0x13)  /* DMA source address low 2	     */
+#define dmadah2 (DMA_DCR_BASE+0x14)  /* DMA destination address high 2	     */
+#define dmadal2 (DMA_DCR_BASE+0x15)  /* DMA destination address low 2	     */
 #define dmasgh2 (DMA_DCR_BASE+0x16)  /* DMA scatter/gather desc addr high 2  */
 #define dmasgl2 (DMA_DCR_BASE+0x17)  /* DMA scatter/gather desc addr low 2   */
-#define dmacr3  (DMA_DCR_BASE+0x18)  /* DMA channel control register 2       */
-#define dmact3  (DMA_DCR_BASE+0x19)  /* DMA count register 2                 */
-#define dmasah3 (DMA_DCR_BASE+0x1a)  /* DMA source address high 2            */
-#define dmasal3 (DMA_DCR_BASE+0x1b)  /* DMA source address low 2             */
-#define dmadah3 (DMA_DCR_BASE+0x1c)  /* DMA destination address high 2       */
-#define dmadal3 (DMA_DCR_BASE+0x1d)  /* DMA destination address low 2        */
+#define dmacr3	(DMA_DCR_BASE+0x18)  /* DMA channel control register 2	     */
+#define dmact3	(DMA_DCR_BASE+0x19)  /* DMA count register 2		     */
+#define dmasah3 (DMA_DCR_BASE+0x1a)  /* DMA source address high 2	     */
+#define dmasal3 (DMA_DCR_BASE+0x1b)  /* DMA source address low 2	     */
+#define dmadah3 (DMA_DCR_BASE+0x1c)  /* DMA destination address high 2	     */
+#define dmadal3 (DMA_DCR_BASE+0x1d)  /* DMA destination address low 2	     */
 #define dmasgh3 (DMA_DCR_BASE+0x1e)  /* DMA scatter/gather desc addr high 2  */
 #define dmasgl3 (DMA_DCR_BASE+0x1f)  /* DMA scatter/gather desc addr low 2   */
-#define dmasr   (DMA_DCR_BASE+0x20)  /* DMA status register                  */
-#define dmasgc  (DMA_DCR_BASE+0x23)  /* DMA scatter/gather command register  */
-#define dmaslp  (DMA_DCR_BASE+0x25)  /* DMA sleep mode register              */
-#define dmapol  (DMA_DCR_BASE+0x26)  /* DMA polarity configuration register  */
+#define dmasr	(DMA_DCR_BASE+0x20)  /* DMA status register		     */
+#define dmasgc	(DMA_DCR_BASE+0x23)  /* DMA scatter/gather command register  */
+#define dmaslp	(DMA_DCR_BASE+0x25)  /* DMA sleep mode register		     */
+#define dmapol	(DMA_DCR_BASE+0x26)  /* DMA polarity configuration register  */
 
 /*-----------------------------------------------------------------------------
  | Memory Access Layer
  +----------------------------------------------------------------------------*/
 #define MAL_DCR_BASE 0x180
-#define malmcr      (MAL_DCR_BASE+0x00) /* MAL Config reg                   */
-#define malesr      (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear)    */
-#define malier      (MAL_DCR_BASE+0x02) /* Interrupt enable reg             */
-#define maldbr      (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only)        */
-#define maltxcasr   (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)      */
+#define malmcr	    (MAL_DCR_BASE+0x00) /* MAL Config reg		    */
+#define malesr	    (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear)    */
+#define malier	    (MAL_DCR_BASE+0x02) /* Interrupt enable reg		    */
+#define maldbr	    (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only)	    */
+#define maltxcasr   (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)	    */
 #define maltxcarr   (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset)    */
 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg  */
-#define maltxdeir   (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg          */
-#define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg             */
-#define maltxbattr  (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg      */
-#define malrxcasr   (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)      */
+#define maltxdeir   (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg	    */
+#define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg		    */
+#define maltxbattr  (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg	    */
+#define malrxcasr   (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)	    */
 #define malrxcarr   (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset)    */
 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg  */
-#define malrxdeir   (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg          */
-#define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg             */
-#define malrxbattr  (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg      */
+#define malrxdeir   (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg	    */
+#define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg		    */
+#define malrxbattr  (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg	    */
 #define maltxctp0r  (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg   */
 #define maltxctp1r  (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg   */
+#if defined(CONFIG_440_GX)
+#define maltxctp2r  (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg   */
+#define maltxctp3r  (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg   */
+#endif /* CONFIG_440_GX */
 #define malrxctp0r  (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg   */
 #define malrxctp1r  (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg   */
-#define malrcbs0    (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg     */
+#if defined(CONFIG_440_GX)
+#define malrxctp2r  (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg   */
+#define malrxctp3r  (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg   */
+#endif /* CONFIG_440_GX */
+#define malrcbs0    (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg	    */
+#define malrcbs1    (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg	    */
+#if defined(CONFIG_440_GX)
+#define malrcbs2    (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg	    */
+#define malrcbs3    (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg	    */
+#endif /* CONFIG_440_GX */
+
 
 /*---------------------------------------------------------------------------+
 |  Universal interrupt controller 0 interrupts (UIC0)
 +---------------------------------------------------------------------------*/
-#define UIC_U0          0x80000000      /* UART 0                           */
-#define UIC_U1          0x40000000      /* UART 1                           */
-#define UIC_IIC0        0x20000000      /* IIC                              */
-#define UIC_IIC1        0x10000000      /* IIC                              */
-#define UIC_PIM         0x08000000      /* PCI inbound message              */
-#define UIC_PCRW        0x04000000      /* PCI command register write       */
-#define UIC_PPM         0x02000000      /* PCI power management             */
-#define UIC_MSI0        0x01000000      /* PCI MSI level 0                  */
-#define UIC_MSI1        0x00800000      /* PCI MSI level 1                  */
-#define UIC_MSI2        0x00400000      /* PCI MSI level 2                  */
-#define UIC_MTE         0x00200000      /* MAL TXEOB                        */
-#define UIC_MRE         0x00100000      /* MAL RXEOB                        */
-#define UIC_D0          0x00080000      /* DMA channel 0                    */
-#define UIC_D1          0x00040000      /* DMA channel 1                    */
-#define UIC_D2          0x00020000      /* DMA channel 2                    */
-#define UIC_D3          0x00010000      /* DMA channel 3                    */
-#define UIC_RSVD0       0x00008000      /* Reserved                         */
-#define UIC_RSVD1       0x00004000      /* Reserved                         */
-#define UIC_CT0         0x00002000      /* GPT compare timer 0              */
-#define UIC_CT1         0x00001000      /* GPT compare timer 1              */
-#define UIC_CT2         0x00000800      /* GPT compare timer 2              */
-#define UIC_CT3         0x00000400      /* GPT compare timer 3              */
-#define UIC_CT4         0x00000200      /* GPT compare timer 4              */
-#define UIC_EIR0        0x00000100      /* External interrupt 0             */
-#define UIC_EIR1        0x00000080      /* External interrupt 1             */
-#define UIC_EIR2        0x00000040      /* External interrupt 2             */
-#define UIC_EIR3        0x00000020      /* External interrupt 3             */
-#define UIC_EIR4        0x00000010      /* External interrupt 4             */
-#define UIC_EIR5        0x00000008      /* External interrupt 5             */
-#define UIC_EIR6        0x00000004      /* External interrupt 6             */
-#define UIC_UIC1NC      0x00000002      /* UIC1 non-critical interrupt      */
-#define UIC_UIC1C       0x00000001      /* UIC1 critical interrupt          */
+#define UIC_U0		0x80000000	/* UART 0			    */
+#define UIC_U1		0x40000000	/* UART 1			    */
+#define UIC_IIC0	0x20000000	/* IIC				    */
+#define UIC_IIC1	0x10000000	/* IIC				    */
+#define UIC_PIM		0x08000000	/* PCI inbound message		    */
+#define UIC_PCRW	0x04000000	/* PCI command register write	    */
+#define UIC_PPM		0x02000000	/* PCI power management		    */
+#define UIC_MSI0	0x01000000	/* PCI MSI level 0		    */
+#define UIC_MSI1	0x00800000	/* PCI MSI level 1		    */
+#define UIC_MSI2	0x00400000	/* PCI MSI level 2		    */
+#define UIC_MTE		0x00200000	/* MAL TXEOB			    */
+#define UIC_MRE		0x00100000	/* MAL RXEOB			    */
+#define UIC_D0		0x00080000	/* DMA channel 0		    */
+#define UIC_D1		0x00040000	/* DMA channel 1		    */
+#define UIC_D2		0x00020000	/* DMA channel 2		    */
+#define UIC_D3		0x00010000	/* DMA channel 3		    */
+#define UIC_RSVD0	0x00008000	/* Reserved			    */
+#define UIC_RSVD1	0x00004000	/* Reserved			    */
+#define UIC_CT0		0x00002000	/* GPT compare timer 0		    */
+#define UIC_CT1		0x00001000	/* GPT compare timer 1		    */
+#define UIC_CT2		0x00000800	/* GPT compare timer 2		    */
+#define UIC_CT3		0x00000400	/* GPT compare timer 3		    */
+#define UIC_CT4		0x00000200	/* GPT compare timer 4		    */
+#define UIC_EIR0	0x00000100	/* External interrupt 0		    */
+#define UIC_EIR1	0x00000080	/* External interrupt 1		    */
+#define UIC_EIR2	0x00000040	/* External interrupt 2		    */
+#define UIC_EIR3	0x00000020	/* External interrupt 3		    */
+#define UIC_EIR4	0x00000010	/* External interrupt 4		    */
+#define UIC_EIR5	0x00000008	/* External interrupt 5		    */
+#define UIC_EIR6	0x00000004	/* External interrupt 6		    */
+#define UIC_UIC1NC	0x00000002	/* UIC1 non-critical interrupt	    */
+#define UIC_UIC1C	0x00000001	/* UIC1 critical interrupt	    */
 
 /* For compatibility with 405 code */
-#define UIC_MAL_TXEOB   UIC_MTE
-#define UIC_MAL_RXEOB   UIC_MRE
+#define UIC_MAL_TXEOB	UIC_MTE
+#define UIC_MAL_RXEOB	UIC_MRE
 
 /*---------------------------------------------------------------------------+
 |  Universal interrupt controller 1 interrupts (UIC1)
 +---------------------------------------------------------------------------*/
-#define UIC_MS          0x80000000      /* MAL SERR                         */
-#define UIC_MTDE        0x40000000      /* MAL TXDE                         */
-#define UIC_MRDE        0x20000000      /* MAL RXDE                         */
-#define UIC_DEUE        0x10000000      /* DDR SDRAM ECC uncorrectible error*/
-#define UIC_DECE        0x08000000      /* DDR SDRAM correctible error      */
-#define UIC_EBCO        0x04000000      /* EBCO interrupt status            */
-#define UIC_EBMI        0x02000000      /* EBMI interrupt status            */
-#define UIC_OPB         0x01000000      /* OPB to PLB bridge interrupt stat */
-#define UIC_MSI3        0x00800000      /* PCI MSI level 3                  */
-#define UIC_MSI4        0x00400000      /* PCI MSI level 4                  */
-#define UIC_MSI5        0x00200000      /* PCI MSI level 5                  */
-#define UIC_MSI6        0x00100000      /* PCI MSI level 6                  */
-#define UIC_MSI7        0x00080000      /* PCI MSI level 7                  */
-#define UIC_MSI8        0x00040000      /* PCI MSI level 8                  */
-#define UIC_MSI9        0x00020000      /* PCI MSI level 9                  */
-#define UIC_MSI10       0x00010000      /* PCI MSI level 10                 */
-#define UIC_MSI11       0x00008000      /* PCI MSI level 11                 */
-#define UIC_PPMI        0x00004000      /* PPM interrupt status             */
-#define UIC_EIR7        0x00002000      /* External interrupt 7             */
-#define UIC_EIR8        0x00001000      /* External interrupt 8             */
-#define UIC_EIR9        0x00000800      /* External interrupt 9             */
-#define UIC_EIR10       0x00000400      /* External interrupt 10            */
-#define UIC_EIR11       0x00000200      /* External interrupt 11            */
-#define UIC_EIR12       0x00000100      /* External interrupt 12            */
-#define UIC_SRE         0x00000080      /* Serial ROM error                 */
-#define UIC_RSVD2       0x00000040      /* Reserved                         */
-#define UIC_RSVD3       0x00000020      /* Reserved                         */
-#define UIC_PAE         0x00000010      /* PCI asynchronous error           */
-#define UIC_ETH0        0x00000008      /* Ethernet 0                       */
-#define UIC_EWU0        0x00000004      /* Ethernet 0 wakeup                */
-#define UIC_ETH1        0x00000002      /* Ethernet 1                       */
-#define UIC_EWU1        0x00000001      /* Ethernet 1 wakeup                */
+#define UIC_MS		0x80000000	/* MAL SERR			    */
+#define UIC_MTDE	0x40000000	/* MAL TXDE			    */
+#define UIC_MRDE	0x20000000	/* MAL RXDE			    */
+#define UIC_DEUE	0x10000000	/* DDR SDRAM ECC uncorrectible error*/
+#define UIC_DECE	0x08000000	/* DDR SDRAM correctible error	    */
+#define UIC_EBCO	0x04000000	/* EBCO interrupt status	    */
+#define UIC_EBMI	0x02000000	/* EBMI interrupt status	    */
+#define UIC_OPB		0x01000000	/* OPB to PLB bridge interrupt stat */
+#define UIC_MSI3	0x00800000	/* PCI MSI level 3		    */
+#define UIC_MSI4	0x00400000	/* PCI MSI level 4		    */
+#define UIC_MSI5	0x00200000	/* PCI MSI level 5		    */
+#define UIC_MSI6	0x00100000	/* PCI MSI level 6		    */
+#define UIC_MSI7	0x00080000	/* PCI MSI level 7		    */
+#define UIC_MSI8	0x00040000	/* PCI MSI level 8		    */
+#define UIC_MSI9	0x00020000	/* PCI MSI level 9		    */
+#define UIC_MSI10	0x00010000	/* PCI MSI level 10		    */
+#define UIC_MSI11	0x00008000	/* PCI MSI level 11		    */
+#define UIC_PPMI	0x00004000	/* PPM interrupt status		    */
+#define UIC_EIR7	0x00002000	/* External interrupt 7		    */
+#define UIC_EIR8	0x00001000	/* External interrupt 8		    */
+#define UIC_EIR9	0x00000800	/* External interrupt 9		    */
+#define UIC_EIR10	0x00000400	/* External interrupt 10	    */
+#define UIC_EIR11	0x00000200	/* External interrupt 11	    */
+#define UIC_EIR12	0x00000100	/* External interrupt 12	    */
+#define UIC_SRE		0x00000080	/* Serial ROM error		    */
+#define UIC_RSVD2	0x00000040	/* Reserved			    */
+#define UIC_RSVD3	0x00000020	/* Reserved			    */
+#define UIC_PAE		0x00000010	/* PCI asynchronous error	    */
+#define UIC_ETH0	0x00000008	/* Ethernet 0			    */
+#define UIC_EWU0	0x00000004	/* Ethernet 0 wakeup		    */
+#define UIC_ETH1	0x00000002	/* Ethernet 1			    */
+#define UIC_EWU1	0x00000001	/* Ethernet 1 wakeup		    */
 
 /* For compatibility with 405 code */
-#define UIC_MAL_SERR    UIC_MS
-#define UIC_MAL_TXDE    UIC_MTDE
-#define UIC_MAL_RXDE    UIC_MRDE
-#define UIC_ENET        UIC_ETH0
+#define UIC_MAL_SERR	UIC_MS
+#define UIC_MAL_TXDE	UIC_MTDE
+#define UIC_MAL_RXDE	UIC_MRDE
+#define UIC_ENET	UIC_ETH0
+
+/*---------------------------------------------------------------------------+
+|  Universal interrupt controller 2 interrupts (UIC2)
++---------------------------------------------------------------------------*/
+#if defined(CONFIG_440_GX)
+#define UIC_ETH2	0x80000000	/* Ethernet 2			    */
+#define UIC_EWU2	0x40000000	/* Ethernet 2 wakeup		    */
+#define UIC_ETH3	0x20000000	/* Ethernet 3			    */
+#define UIC_EWU3	0x10000000	/* Ethernet 3 wakeup		    */
+#define UIC_TAH0	0x08000000	/* TAH 0			    */
+#define UIC_TAH1	0x04000000	/* TAH 1			    */
+#define UIC_IMUOBFQ	0x02000000	/* IMU outbound free queue	    */
+#define UIC_IMUIBPQ	0x01000000	/* IMU inbound post queue	    */
+#define UIC_IMUIRQDB	0x00800000	/* IMU irq doorbell		    */
+#define UIC_IMUIBDB	0x00400000	/* IMU inbound doorbell		    */
+#define UIC_IMUMSG0	0x00200000	/* IMU inbound message 0	    */
+#define UIC_IMUMSG1	0x00100000	/* IMU inbound message 1	    */
+#define UIC_IMUTO	0x00080000	/* IMU timeout			    */
+#define UIC_MSI12	0x00040000	/* PCI MSI level 12		    */
+#define UIC_MSI13	0x00020000	/* PCI MSI level 13		    */
+#define UIC_MSI14	0x00010000	/* PCI MSI level 14		    */
+#define UIC_MSI15	0x00008000	/* PCI MSI level 15		    */
+#define UIC_EIR13	0x00004000	/* External interrupt 13	    */
+#define UIC_EIR14	0x00002000	/* External interrupt 14	    */
+#define UIC_EIR15	0x00001000	/* External interrupt 15	    */
+#define UIC_EIR16	0x00000800	/* External interrupt 16	    */
+#define UIC_EIR17	0x00000400	/* External interrupt 17	    */
+#define UIC_PCIVPD	0x00000200	/* PCI VPD			    */
+#define UIC_L2C		0x00000100	/* L2 Cache			    */
+#define UIC_ETH2PCS	0x00000080	/* Ethernet 2 PCS		    */
+#define UIC_ETH3PCS	0x00000040	/* Ethernet 3 PCS		    */
+#define UIC_RSVD26	0x00000020	/* Reserved			    */
+#define UIC_RSVD27	0x00000010	/* Reserved			    */
+#define UIC_RSVD28	0x00000008	/* Reserved			    */
+#define UIC_RSVD29	0x00000004	/* Reserved			    */
+#define UIC_RSVD30	0x00000002	/* Reserved			    */
+#define UIC_RSVD31	0x00000001	/* Reserved			    */
+#endif	/* CONFIG_440_GX */
+
+/*---------------------------------------------------------------------------+
+|  Universal interrupt controller Base 0 interrupts (UICB0)
++---------------------------------------------------------------------------*/
+#if defined(CONFIG_440_GX)
+#define UICB0_UIC0CI	0x80000000	/* UIC0 Critical Interrupt	    */
+#define UICB0_UIC0NCI	0x40000000	/* UIC0 Noncritical Interrupt	    */
+#define UICB0_UIC1CI	0x20000000	/* UIC1 Critical Interrupt	    */
+#define UICB0_UIC1NCI	0x10000000	/* UIC1 Noncritical Interrupt	    */
+#define UICB0_UIC2CI	0x08000000	/* UIC2 Critical Interrupt	    */
+#define UICB0_UIC2NCI	0x04000000	/* UIC2 Noncritical Interrupt	    */
+
+#define UICB0_ALL		(UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
+						 UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
+#endif /* CONFIG_440_GX */
 
 /*-----------------------------------------------------------------------------+
 |  Clocking
 +-----------------------------------------------------------------------------*/
-#define PLLSYS0_TUNE_MASK       0xffc00000      /* PLL TUNE bits            */
-#define PLLSYS0_FB_DIV_MASK     0x003c0000      /* Feedback divisor         */
-#define PLLSYS0_FWD_DIV_A_MASK  0x00038000      /* Forward divisor A        */
-#define PLLSYS0_FWD_DIV_B_MASK  0x00007000      /* Forward divisor B        */
-#define PLLSYS0_OPB_DIV_MASK    0x00000c00      /* OPB divisor              */
-#define PLLSYS0_EPB_DIV_MASK    0x00000300      /* EPB divisor              */
-#define PLLSYS0_EXTSL_MASK      0x00000080      /* PerClk feedback path     */
-#define PLLSYS0_RW_MASK         0x00000060      /* ROM width                */
-#define PLLSYS0_RL_MASK         0x00000010      /* ROM location             */
-#define PLLSYS0_ZMII_SEL_MASK   0x0000000c      /* ZMII selection           */
-#define PLLSYS0_BYPASS_MASK     0x00000002      /* Bypass PLL               */
-#define PLLSYS0_NTO1_MASK       0x00000001      /* CPU:PLB N-to-1 ratio     */
+#if !defined (CONFIG_440_GX)
+#define PLLSYS0_TUNE_MASK	0xffc00000	/* PLL TUNE bits	    */
+#define PLLSYS0_FB_DIV_MASK	0x003c0000	/* Feedback divisor	    */
+#define PLLSYS0_FWD_DIV_A_MASK	0x00038000	/* Forward divisor A	    */
+#define PLLSYS0_FWD_DIV_B_MASK	0x00007000	/* Forward divisor B	    */
+#define PLLSYS0_OPB_DIV_MASK	0x00000c00	/* OPB divisor		    */
+#define PLLSYS0_EPB_DIV_MASK	0x00000300	/* EPB divisor		    */
+#define PLLSYS0_EXTSL_MASK	0x00000080	/* PerClk feedback path	    */
+#define PLLSYS0_RW_MASK		0x00000060	/* ROM width		    */
+#define PLLSYS0_RL_MASK		0x00000010	/* ROM location		    */
+#define PLLSYS0_ZMII_SEL_MASK	0x0000000c	/* ZMII selection	    */
+#define PLLSYS0_BYPASS_MASK	0x00000002	/* Bypass PLL		    */
+#define PLLSYS0_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio	    */
 
-#define PLL_VCO_FREQ_MIN        500             /* Min VCO freq (MHz)       */
-#define PLL_VCO_FREQ_MAX        1000            /* Max VCO freq (MHz)       */
-#define PLL_CPU_FREQ_MAX        400             /* Max CPU freq (MHz)       */
-#define PLL_PLB_FREQ_MAX        133             /* Max PLB freq (MHz)       */
+#define PLL_VCO_FREQ_MIN	500		/* Min VCO freq (MHz)	    */
+#define PLL_VCO_FREQ_MAX	1000		/* Max VCO freq (MHz)	    */
+#define PLL_CPU_FREQ_MAX	400		/* Max CPU freq (MHz)	    */
+#define PLL_PLB_FREQ_MAX	133		/* Max PLB freq (MHz)	    */
+#else /* !CONFIG_440_GX */
+#define PLLSYS0_ENG_MASK	0x80000000	/* 0 = SysClk, 1 = PLL VCO */
+#define PLLSYS0_SRC_MASK	0x40000000	/* 0 = PLL A, 1 = PLL B */
+#define PLLSYS0_SEL_MASK	0x38000000	/* 0 = PLL, 1 = CPU, 5 = PerClk */
+#define PLLSYS0_TUNE_MASK	0x07fe0000	/* PLL Tune bits */
+#define PLLSYS0_FB_DIV_MASK	0x0001f000	/* Feedback divisor */
+#define PLLSYS0_FWD_DIV_A_MASK	0x00000f00	/* Fwd Div A */
+#define PLLSYS0_FWD_DIV_B_MASK	0x000000e0	/* Fwd Div B */
+#define PLLSYS0_PRI_DIV_B_MASK	0x0000001c	/* PLL Primary Divisor B */
+#define PLLSYS0_OPB_DIV_MASK	0x00000003	/* OPB Divisor */
+
+#define PLL_VCO_FREQ_MIN	500		/* Min VCO freq (MHz)	    */
+#define PLL_VCO_FREQ_MAX	1000		/* Max VCO freq (MHz)	    */
+#define PLL_CPU_FREQ_MAX	400		/* Max CPU freq (MHz)	    */
+#define PLL_PLB_FREQ_MAX	133		/* Max PLB freq (MHz)	    */
+
+/* Strap 1 Register */
+#define PLLSYS1_LF_DIV_MASK	0xfc000000	/* PLL Local Feedback Divisor */
+#define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
+#define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
+#define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
+#define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
+#define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
+#define PLLSYS1_PCWE_MASK	0x00008000	/* PCI local cpu wait enable */
+#define PLLSYS1_PPIM_MASK	0x00007800	/* PCI inbound map */
+#define PLLSYS1_PR64E_MASK	0x00000400	/* PCI init Req64 enable */
+#define PLLSYS1_PXFS_MASK	0x00000300	/* PCI-X Freq Sel */
+#define PLLSYS1_RSVD_MASK	0x00000080	/* RSVD */
+#define PLLSYS1_PDM_MASK	0x00000040	/* PCI-X Driver Mode */
+#define PLLSYS1_EPS_MASK	0x00000038	/* Ethernet Pin Select */
+#define PLLSYS1_RMII_MASK	0x00000004	/* RMII Mode */
+#define PLLSYS1_TRE_MASK	0x00000002	/* GPIO Trace Enable */
+#define PLLSYS1_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio */
+#endif /* CONFIG_440_GX */
 
 /*-----------------------------------------------------------------------------
 | IIC Register Offsets
 '----------------------------------------------------------------------------*/
-#define    IICMDBUF         0x00
-#define    IICSDBUF         0x02
-#define    IICLMADR         0x04
-#define    IICHMADR         0x05
-#define    IICCNTL          0x06
-#define    IICMDCNTL        0x07
-#define    IICSTS           0x08
-#define    IICEXTSTS        0x09
-#define    IICLSADR         0x0A
-#define    IICHSADR         0x0B
-#define    IICCLKDIV        0x0C
-#define    IICINTRMSK       0x0D
-#define    IICXFRCNT        0x0E
-#define    IICXTCNTLSS      0x0F
-#define    IICDIRECTCNTL    0x10
+#define	   IICMDBUF	    0x00
+#define	   IICSDBUF	    0x02
+#define	   IICLMADR	    0x04
+#define	   IICHMADR	    0x05
+#define	   IICCNTL	    0x06
+#define	   IICMDCNTL	    0x07
+#define	   IICSTS	    0x08
+#define	   IICEXTSTS	    0x09
+#define	   IICLSADR	    0x0A
+#define	   IICHSADR	    0x0B
+#define	   IICCLKDIV	    0x0C
+#define	   IICINTRMSK	    0x0D
+#define	   IICXFRCNT	    0x0E
+#define	   IICXTCNTLSS	    0x0F
+#define	   IICDIRECTCNTL    0x10
 
 /*-----------------------------------------------------------------------------
 | UART Register Offsets
 '----------------------------------------------------------------------------*/
 #define		DATA_REG	0x00
-#define		DL_LSB    	0x00
-#define		DL_MSB  	0x01
-#define		INT_ENABLE      0x01
-#define		FIFO_CONTROL    0x02
-#define		LINE_CONTROL    0x03
-#define		MODEM_CONTROL   0x04
-#define		LINE_STATUS  	0x05
-#define		MODEM_STATUS    0x06
-#define		SCRATCH         0x07
+#define		DL_LSB		0x00
+#define		DL_MSB		0x01
+#define		INT_ENABLE	0x01
+#define		FIFO_CONTROL	0x02
+#define		LINE_CONTROL	0x03
+#define		MODEM_CONTROL	0x04
+#define		LINE_STATUS	0x05
+#define		MODEM_STATUS	0x06
+#define		SCRATCH		0x07
 
 /*-----------------------------------------------------------------------------
 | PCI Internal Registers et. al. (accessed via plb)
@@ -488,8 +698,8 @@
 #define		PCIX0_MINGNT		(PCIX0_CFGBASE + PCI_MIN_GNT )
 #define		PCIX0_MAXLTNCY		(PCIX0_CFGBASE + PCI_MAX_LAT )
 
-#define     PCIX0_BRDGOPT1      (PCIX0_CFGBASE + 0x0040)
-#define     PCIX0_BRDGOPT2      (PCIX0_CFGBASE + 0x0044)
+#define	    PCIX0_BRDGOPT1	(PCIX0_CFGBASE + 0x0040)
+#define	    PCIX0_BRDGOPT2	(PCIX0_CFGBASE + 0x0044)
 
 #define		PCIX0_POM0LAL		(PCIX0_CFGBASE + 0x0068)
 #define		PCIX0_POM0LAH		(PCIX0_CFGBASE + 0x006c)
@@ -513,7 +723,7 @@
 #define		PCIX0_PIM2LAL		(PCIX0_CFGBASE + 0x00b4)
 #define		PCIX0_PIM2LAH		(PCIX0_CFGBASE + 0x00b8)
 
-#define     PCIX0_STS           (PCIX0_CFGBASE + 0x00e0)
+#define	    PCIX0_STS		(PCIX0_CFGBASE + 0x00e0)
 
 /*
  * Macros for accessing the indirect EBC registers
@@ -527,6 +737,18 @@
 #define mtsdram(reg, data)  mtdcr(memcfga,reg);mtdcr(memcfgd,data)
 #define mfsdram(reg, data)  mtdcr(memcfga,reg);data = mfdcr(memcfgd)
 
+/*
+ * Macros for accessing the indirect clocking controller registers
+ */
+#define mtclk(reg, data)  mtdcr(clkcfga,reg);mtdcr(clkcfgd,data)
+#define mfclk(reg, data)  mtdcr(clkcfga,reg);data = mfdcr(clkcfgd)
+
+/*
+ * Macros for accessing the sdr controller registers
+ */
+#define mtsdr(reg, data)  mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data)
+#define mfsdr(reg, data)  mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd)
+
 
 #ifndef __ASSEMBLY__
 
@@ -537,14 +759,14 @@
   unsigned long pllFbkDiv;
   unsigned long pllOpbDiv;
   unsigned long pllExtBusDiv;
-  unsigned long freqVCOMhz;             /* in MHz                          */
+  unsigned long freqVCOMhz;		/* in MHz			   */
   unsigned long freqProcessor;
   unsigned long freqPLB;
   unsigned long freqOPB;
   unsigned long freqEPB;
 } PPC440_SYS_INFO;
 
-#endif  /* _ASMLANGUAGE */
+#endif	/* _ASMLANGUAGE */
 
 #define RESET_VECTOR	0xfffffffc
 #define CACHELINE_MASK	(CFG_CACHELINE_SIZE - 1) /* Address mask for cache
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index 5b0dd4d..d7cee2b 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -749,7 +749,7 @@
 #endif
 
 #if defined(CFG_GT_6426x) || defined(CONFIG_PN62) || defined(CONFIG_PPCHAMELEONEVB) || \
-    defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS)
+    defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS) || defined(CONFIG_440_GX)
 	/* handle the 2nd ethernet address */
 
 	s = getenv ("eth1addr");
@@ -760,11 +760,16 @@
 			s = (*e) ? e + 1 : e;
 	}
 #endif
-#if defined(CFG_GT_6426x) || defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS)
+#if defined(CFG_GT_6426x) || defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS) || \
+	defined(CONFIG_440_GX)
 	/* handle the 3rd ethernet address */
 
 	s = getenv ("eth2addr");
-
+#if defined(CONFIG_XPEDITE1K)
+	if (s == NULL)
+		board_get_enetaddr(bd->bi_enet2addr);
+	else
+#endif
 	for (i = 0; i < 6; ++i) {
 		bd->bi_enet2addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
 		if (s)
@@ -772,6 +777,20 @@
 	}
 #endif
 
+#if defined(CONFIG_440_GX)
+	/* handle 4th ethernet address */
+	s = getenv("eth3addr");
+#if defined(CONFIG_XPEDITE1K)
+	if (s == NULL)
+		board_get_enetaddr(bd->bi_enet3addr);
+	else
+#endif
+	for (i = 0; i < 6; ++i) {
+		bd->bi_enet3addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
+		if (s)
+			s = (*e) ? e + 1 : e;
+	}
+#endif
 
 #if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \
     defined(CONFIG_CCM)
diff --git a/net/eth.c b/net/eth.c
index 32051a1..177fab8 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -46,6 +46,7 @@
 extern int pcnet_initialize(bd_t*);
 extern int plb2800_eth_initialize(bd_t*);
 extern int ppc_4xx_eth_initialize(bd_t *);
+extern int ppc_440x_eth_initialize(bd_t *);
 extern int rtl8139_initialize(bd_t*);
 extern int scc_initialize(bd_t*);
 extern int skge_initialize(bd_t*);
@@ -112,9 +113,12 @@
 #ifdef CONFIG_DB64460
 	mv6446x_eth_initialize(bis);
 #endif
-#if defined(CONFIG_405GP) || defined(CONFIG_440) || defined(CONFIG_405EP)
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || ( defined(CONFIG_440) && !defined(CONFIG_NET_MULTI) )
 	ppc_4xx_eth_initialize(bis);
 #endif
+#if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
+	ppc_440x_eth_initialize(bis);
+#endif
 #ifdef CONFIG_INCA_IP_SWITCH
 	inca_switch_initialize(bis);
 #endif