diff --git a/cpu/ppc4xx/405gp_enet.c b/cpu/ppc4xx/405gp_enet.c
index 7394c21..65036d1 100644
--- a/cpu/ppc4xx/405gp_enet.c
+++ b/cpu/ppc4xx/405gp_enet.c
@@ -83,7 +83,8 @@
 #include <malloc.h>
 #include "vecnum.h"
 
-#if defined(CONFIG_405GP) || defined(CONFIG_440) || defined(CONFIG_405EP)
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
+  ( defined(CONFIG_440)   && !defined(CONFIG_NET_MULTI))
 
 #define EMAC_RESET_TIMEOUT 1000	/* 1000 ms reset timeout */
 #define PHY_AUTONEGOTIATE_TIMEOUT 4000	/* 4000 ms autonegotiate timeout */
diff --git a/cpu/ppc4xx/440gx_enet.c b/cpu/ppc4xx/440gx_enet.c
new file mode 100644
index 0000000..617a174
--- /dev/null
+++ b/cpu/ppc4xx/440gx_enet.c
@@ -0,0 +1,1144 @@
+/*-----------------------------------------------------------------------------+
+ *
+ *       This source code has been made available to you by IBM on an AS-IS
+ *       basis.  Anyone receiving this source is licensed under IBM
+ *       copyrights to use it in any way he or she deems fit, including
+ *       copying it, modifying it, compiling it, and redistributing it either
+ *       with or without modifications.  No license under IBM patents or
+ *       patent applications is to be implied by the copyright license.
+ *
+ *       Any user of this software should understand that IBM cannot provide
+ *       technical support for this software and will not be responsible for
+ *       any consequences resulting from the use of this software.
+ *
+ *       Any person who transfers this source code or any derivative work
+ *       must include the IBM copyright notice, this paragraph, and the
+ *       preceding two paragraphs in the transferred software.
+ *
+ *       COPYRIGHT   I B M   CORPORATION 1995
+ *       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *-----------------------------------------------------------------------------*/
+/*-----------------------------------------------------------------------------+
+ *
+ *  File Name:  enetemac.c
+ *
+ *  Function:   Device driver for the ethernet EMAC3 macro on the 405GP.
+ *
+ *  Author:     Mark Wisner
+ *
+ *  Change Activity-
+ *
+ *  Date        Description of Change                                       BY
+ *  ---------   ---------------------                                       ---
+ *  05-May-99   Created                                                     MKW
+ *  27-Jun-99   Clean up                                                    JWB
+ *  16-Jul-99   Added MAL error recovery and better IP packet handling      MKW
+ *  29-Jul-99   Added Full duplex support                                   MKW
+ *  06-Aug-99   Changed names for Mal CR reg                                MKW
+ *  23-Aug-99   Turned off SYE when running at 10Mbs                        MKW
+ *  24-Aug-99   Marked descriptor empty after call_xlc                      MKW
+ *  07-Sep-99   Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16     MCG
+ *              to avoid chaining maximum sized packets. Push starting
+ *              RX descriptor address up to the next cache line boundary.
+ *  16-Jan-00   Added support for booting with IP of 0x0                    MKW
+ *  15-Mar-00   Updated enetInit() to enable broadcast addresses in the
+ *	        EMAC_RXM register.                                          JWB
+ *  12-Mar-01   anne-sophie.harnois@nextream.fr
+ *               - Variables are compatible with those already defined in
+ *                include/net.h
+ *              - Receive buffer descriptor ring is used to send buffers
+ *                to the user
+ *              - Info print about send/received/handled packet number if
+ *                INFO_405_ENET is set
+ *  17-Apr-01   stefan.roese@esd-electronics.com
+ *              - MAL reset in "eth_halt" included
+ *              - Enet speed and duplex output now in one line
+ *  08-May-01   stefan.roese@esd-electronics.com
+ *              - MAL error handling added (eth_init called again)
+ *  13-Nov-01   stefan.roese@esd-electronics.com
+ *              - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
+ *  04-Jan-02   stefan.roese@esd-electronics.com
+ *              - Wait for PHY auto negotiation to complete added
+ *  06-Feb-02   stefan.roese@esd-electronics.com
+ *              - Bug fixed in waiting for auto negotiation to complete
+ *  26-Feb-02   stefan.roese@esd-electronics.com
+ *              - rx and tx buffer descriptors now allocated (no fixed address
+ *                used anymore)
+ *  17-Jun-02   stefan.roese@esd-electronics.com
+ *              - MAL error debug printf 'M' removed (rx de interrupt may
+ *                occur upon many incoming packets with only 4 rx buffers).
+ *-----------------------------------------------------------------------------*
+ *  17-Nov-03   travis.sawyer@sandburst.com
+ *              - ported from 405gp_enet.c to utilized upto 4 EMAC ports
+ *                in the 440GX.  This port should work with the 440GP
+ *                (2 EMACs) also
+ *-----------------------------------------------------------------------------*/
+
+#include <config.h>
+#if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
+
+#include <common.h>
+#include <net.h>
+#include <asm/processor.h>
+#include <ppc440.h>
+#include <commproc.h>
+#include <440gx_enet.h>
+#include <405_mal.h>
+#include <miiphy.h>
+#include <malloc.h>
+#include "vecnum.h"
+
+
+#define EMAC_RESET_TIMEOUT 1000	/* 1000 ms reset timeout */
+#define PHY_AUTONEGOTIATE_TIMEOUT 4000	/* 4000 ms autonegotiate timeout */
+
+
+/* Ethernet Transmit and Receive Buffers */
+/* AS.HARNOIS
+ * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
+ * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
+ */
+#define ENET_MAX_MTU           PKTSIZE
+#define ENET_MAX_MTU_ALIGNED   PKTSIZE_ALIGN
+
+
+/* define the number of channels implemented */
+#define EMAC_RXCHL      EMAC_NUM_DEV
+#define EMAC_TXCHL      EMAC_NUM_DEV
+
+/*-----------------------------------------------------------------------------+
+ * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
+ * Interrupt Controller).
+ *-----------------------------------------------------------------------------*/
+#define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE  | UIC_MAL_RXDE)
+#define MAL_UIC_DEF  (UIC_MAL_RXEOB | MAL_UIC_ERR)
+#define EMAC_UIC_DEF UIC_ENET
+
+#undef INFO_440_ENET
+
+/*-----------------------------------------------------------------------------+
+ * Global variables. TX and RX descriptors and buffers.
+ *-----------------------------------------------------------------------------*/
+/* IER globals */
+static uint32_t mal_ier;
+
+/*-----------------------------------------------------------------------------+
+ * Prototypes and externals.
+ *-----------------------------------------------------------------------------*/
+static void enet_rcv (struct eth_device *dev, unsigned long malisr);
+
+int enetInt (struct eth_device *dev);
+static void mal_err (struct eth_device *dev, unsigned long isr,
+		     unsigned long uic, unsigned long maldef,
+		     unsigned long mal_errr);
+static void emac_err (struct eth_device *dev, unsigned long isr);
+
+/*-----------------------------------------------------------------------------+
+| ppc_440x_eth_halt
+| Disable MAL channel, and EMACn
+|
+|
++-----------------------------------------------------------------------------*/
+static void ppc_440x_eth_halt (struct eth_device *dev)
+{
+	EMAC_440GX_HW_PST hw_p = dev->priv;
+	uint32_t failsafe = 10000;
+
+	out32 (EMAC_IER + hw_p->hw_addr, 0x00000000);	/* disable emac interrupts */
+
+	/* 1st reset MAL channel */
+	/* Note: writing a 0 to a channel has no effect */
+	mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
+	mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
+
+	/* wait for reset */
+	while (mfdcr (maltxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
+		udelay (1000);	/* Delay 1 MS so as not to hammer the register */
+		failsafe--;
+		if (failsafe == 0)
+			break;
+
+	}
+
+	/* EMAC RESET */
+	out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
+
+	hw_p->print_speed = 1;	/* print speed message again next time */
+
+	return;
+}
+
+extern int phy_setup_aneg (unsigned char addr);
+extern int miiphy_reset (unsigned char addr);
+
+static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
+{
+	int i;
+	unsigned long reg;
+	unsigned long msr;
+	unsigned long speed;
+	unsigned long duplex;
+	unsigned long failsafe;
+	unsigned mode_reg;
+	unsigned short devnum;
+	unsigned short reg_short;
+	sys_info_t sysinfo;
+
+	EMAC_440GX_HW_PST hw_p = dev->priv;
+
+	/* before doing anything, figure out if we have a MAC address */
+	/* if not, bail */
+	if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0)
+		return -1;
+
+	/* Need to get the OPB frequency so we can access the PHY */
+	get_sys_info (&sysinfo);
+
+
+	msr = mfmsr ();
+	mtmsr (msr & ~(MSR_EE));	/* disable interrupts */
+
+	devnum = hw_p->devnum;
+
+#ifdef INFO_440_ENET
+	/* AS.HARNOIS
+	 * We should have :
+	 * hw_p->stats.pkts_handled <=  hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
+	 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
+	 * is possible that new packets (without relationship with
+	 * current transfer) have got the time to arrived before
+	 * netloop calls eth_halt
+	 */
+	printf ("About preceeding transfer (eth%d):\n"
+		"- Sent packet number %d\n"
+		"- Received packet number %d\n"
+		"- Handled packet number %d\n",
+		hw_p->devnum,
+		hw_p->stats.pkts_tx,
+		hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
+
+	hw_p->stats.pkts_tx = 0;
+	hw_p->stats.pkts_rx = 0;
+	hw_p->stats.pkts_handled = 0;
+#endif
+
+	/* MAL Channel RESET */
+	/* 1st reset MAL channel */
+	/* Note: writing a 0 to a channel has no effect */
+	mtdcr (maltxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
+	mtdcr (malrxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
+
+	/* wait for reset */
+	/* TBS:  should have udelay and failsafe here */
+	failsafe = 10000;
+	/* wait for reset */
+	while (mfdcr (maltxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
+		udelay (1000);	/* Delay 1 MS so as not to hammer the register */
+		failsafe--;
+		if (failsafe == 0)
+			break;
+
+	}
+
+	hw_p->tx_err_index = 0;	/* Transmit Error Index for tx_err_log */
+	hw_p->rx_err_index = 0;	/* Receive Error Index for rx_err_log */
+
+	hw_p->rx_slot = 0;	/* MAL Receive Slot */
+	hw_p->rx_i_index = 0;	/* Receive Interrupt Queue Index */
+	hw_p->rx_u_index = 0;	/* Receive User Queue Index */
+
+	hw_p->tx_slot = 0;	/* MAL Transmit Slot */
+	hw_p->tx_i_index = 0;	/* Transmit Interrupt Queue Index */
+	hw_p->tx_u_index = 0;	/* Transmit User Queue Index */
+
+	/* set RMII mode */
+	/* NOTE: 440GX spec states that mode is mutually exclusive */
+	/* NOTE: Therefore, disable all other EMACS, since we handle */
+	/* NOTE: only one emac at a time */
+	reg = 0;
+	out32 (ZMII_FER, 0);
+	udelay (100);
+	out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
+	out32 (ZMII_SSR, 0x11110000);
+	/* reset emac so we have access to the phy */
+	__asm__ volatile ("eieio");
+
+	out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
+	__asm__ volatile ("eieio");
+
+	if ((devnum == 2) || (devnum == 3))
+		out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
+				   (RGMII_FER_RGMII << RGMII_FER_V (3))));
+	__asm__ volatile ("eieio");
+
+	failsafe = 1000;
+	while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
+		udelay (1000);
+		failsafe--;
+	}
+
+	/* Whack the M1 register */
+	mode_reg = 0x0;
+	mode_reg &= ~0x00000038;
+	if (sysinfo.freqOPB <= 50000000);
+	else if (sysinfo.freqOPB <= 66666667)
+		mode_reg |= EMAC_M1_OBCI_66;
+	else if (sysinfo.freqOPB <= 83333333)
+		mode_reg |= EMAC_M1_OBCI_83;
+	else if (sysinfo.freqOPB <= 100000000)
+		mode_reg |= EMAC_M1_OBCI_100;
+	else
+		mode_reg |= EMAC_M1_OBCI_GT100;
+
+	out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
+
+
+	/* wait for PHY to complete auto negotiation */
+	reg_short = 0;
+#ifndef CONFIG_CS8952_PHY
+	switch (devnum) {
+	case 0:
+		reg = CONFIG_PHY_ADDR;
+		break;
+	case 1:
+		reg = CONFIG_PHY1_ADDR;
+		break;
+#if defined (CONFIG_440_GX)
+	case 2:
+		reg = CONFIG_PHY2_ADDR;
+		break;
+	case 3:
+		reg = CONFIG_PHY3_ADDR;
+		break;
+#endif
+	default:
+		reg = CONFIG_PHY_ADDR;
+		break;
+	}
+
+	/* Reset the phy */
+	miiphy_reset (reg);
+
+	/* Start/Restart autonegotiation */
+/*	miiphy_write(reg, PHY_BMCR, 0x9340); */
+	phy_setup_aneg (reg);
+	udelay (1000);
+
+	miiphy_read (reg, PHY_BMSR, &reg_short);
+
+	/*
+	 * Wait if PHY is able of autonegotiation and autonegotiation is not complete
+	 */
+	if ((reg_short & PHY_BMSR_AUTN_ABLE)
+	    && !(reg_short & PHY_BMSR_AUTN_COMP)) {
+		puts ("Waiting for PHY auto negotiation to complete");
+		i = 0;
+		while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
+			/*
+			 * Timeout reached ?
+			 */
+			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
+				puts (" TIMEOUT !\n");
+				break;
+			}
+
+			if ((i++ % 1000) == 0) {
+				putc ('.');
+			}
+			udelay (1000);	/* 1 ms */
+			miiphy_read (reg, PHY_BMSR, &reg_short);
+
+		}
+		puts (" done\n");
+		udelay (500000);	/* another 500 ms (results in faster booting) */
+	}
+#endif
+	speed = miiphy_speed (reg);
+	duplex = miiphy_duplex (reg);
+
+	if (hw_p->print_speed) {
+		hw_p->print_speed = 0;
+		printf ("ENET Speed is %d Mbps - %s duplex connection\n",
+			(int) speed, (duplex == HALF) ? "HALF" : "FULL");
+	}
+
+	/* Set ZMII/RGMII speed according to the phy link speed */
+	reg = in32 (ZMII_SSR);
+	if (speed == 100)
+		out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
+	else
+		out32 (ZMII_SSR,
+		       reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
+
+	if ((devnum == 2) || (devnum == 3)) {
+		if (speed == 1000)
+			reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
+		else if (speed == 100)
+			reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
+		else
+			reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
+
+		out32 (RGMII_SSR, reg);
+	}
+
+	/* set the Mal configuration reg */
+	/* Errata 1.12: MAL_1 -- Disable MAL bursting */
+	if (get_pvr () == PVR_440GP_RB)
+		mtdcr (malmcr,
+		       MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
+	else
+		mtdcr (malmcr,
+		       MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
+		       MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
+
+	/* Free "old" buffers */
+	if (hw_p->alloc_tx_buf)
+		free (hw_p->alloc_tx_buf);
+	if (hw_p->alloc_rx_buf)
+		free (hw_p->alloc_rx_buf);
+
+	/*
+	 * Malloc MAL buffer desciptors, make sure they are
+	 * aligned on cache line boundary size
+	 * (401/403/IOP480 = 16, 405 = 32)
+	 * and doesn't cross cache block boundaries.
+	 */
+	hw_p->alloc_tx_buf =
+		(mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
+				       ((2 * CFG_CACHELINE_SIZE) - 2));
+	if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
+		hw_p->tx =
+			(mal_desc_t *) ((int) hw_p->alloc_tx_buf +
+					CFG_CACHELINE_SIZE -
+					((int) hw_p->
+					 alloc_tx_buf & CACHELINE_MASK));
+	} else {
+		hw_p->tx = hw_p->alloc_tx_buf;
+	}
+
+	hw_p->alloc_rx_buf =
+		(mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
+				       ((2 * CFG_CACHELINE_SIZE) - 2));
+	if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
+		hw_p->rx =
+			(mal_desc_t *) ((int) hw_p->alloc_rx_buf +
+					CFG_CACHELINE_SIZE -
+					((int) hw_p->
+					 alloc_rx_buf & CACHELINE_MASK));
+	} else {
+		hw_p->rx = hw_p->alloc_rx_buf;
+	}
+
+	for (i = 0; i < NUM_TX_BUFF; i++) {
+		hw_p->tx[i].ctrl = 0;
+		hw_p->tx[i].data_len = 0;
+		if (hw_p->first_init == 0)
+			hw_p->txbuf_ptr =
+				(char *) malloc (ENET_MAX_MTU_ALIGNED);
+		hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
+		if ((NUM_TX_BUFF - 1) == i)
+			hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
+		hw_p->tx_run[i] = -1;
+#if 0
+		printf ("TX_BUFF %d @ 0x%08lx\n", i,
+			(ulong) hw_p->tx[i].data_ptr);
+#endif
+	}
+
+	for (i = 0; i < NUM_RX_BUFF; i++) {
+		hw_p->rx[i].ctrl = 0;
+		hw_p->rx[i].data_len = 0;
+		/*       rx[i].data_ptr = (char *) &rx_buff[i]; */
+		hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
+		if ((NUM_RX_BUFF - 1) == i)
+			hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
+		hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
+		hw_p->rx_ready[i] = -1;
+#if 0
+		printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
+#endif
+	}
+
+	reg = 0x00000000;
+
+	reg |= dev->enetaddr[0];	/* set high address */
+	reg = reg << 8;
+	reg |= dev->enetaddr[1];
+
+	out32 (EMAC_IAH + hw_p->hw_addr, reg);
+
+	reg = 0x00000000;
+	reg |= dev->enetaddr[2];	/* set low address  */
+	reg = reg << 8;
+	reg |= dev->enetaddr[3];
+	reg = reg << 8;
+	reg |= dev->enetaddr[4];
+	reg = reg << 8;
+	reg |= dev->enetaddr[5];
+
+	out32 (EMAC_IAL + hw_p->hw_addr, reg);
+
+	switch (devnum) {
+	case 1:
+		/* setup MAL tx & rx channel pointers */
+		mtdcr (maltxbattr, 0x0);
+		mtdcr (maltxctp1r, hw_p->tx);
+		mtdcr (malrxbattr, 0x0);
+		mtdcr (malrxctp1r, hw_p->rx);
+		/* set RX buffer size */
+		mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
+		break;
+#if defined (CONFIG_440_GX)
+	case 2:
+		/* setup MAL tx & rx channel pointers */
+		mtdcr (maltxbattr, 0x0);
+		mtdcr (maltxctp2r, hw_p->tx);
+		mtdcr (malrxbattr, 0x0);
+		mtdcr (malrxctp2r, hw_p->rx);
+		/* set RX buffer size */
+		mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
+		break;
+	case 3:
+		/* setup MAL tx & rx channel pointers */
+		mtdcr (maltxbattr, 0x0);
+		mtdcr (maltxctp3r, hw_p->tx);
+		mtdcr (malrxbattr, 0x0);
+		mtdcr (malrxctp3r, hw_p->rx);
+		/* set RX buffer size */
+		mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
+		break;
+#endif /*CONFIG_440_GX */
+	case 0:
+	default:
+		/* setup MAL tx & rx channel pointers */
+		mtdcr (maltxbattr, 0x0);
+		mtdcr (maltxctp0r, hw_p->tx);
+		mtdcr (malrxbattr, 0x0);
+		mtdcr (malrxctp0r, hw_p->rx);
+		/* set RX buffer size */
+		mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
+		break;
+	}
+
+	/* Enable MAL transmit and receive channels */
+	mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
+	mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
+
+	/* set transmit enable & receive enable */
+	out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
+
+	/* set receive fifo to 4k and tx fifo to 2k */
+	mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
+	mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
+
+	/* set speed */
+	/* TBS: do 1GbE */
+	if (speed == _100BASET)
+		mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
+	else
+		mode_reg = mode_reg & ~0x00C00000;	/* 10 MBPS */
+	if (duplex == FULL)
+		mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
+
+	out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
+
+	/* Enable broadcast and indvidual address */
+	/* TBS: enabling runts as some misbehaved nics will send runts */
+	out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
+
+	/* we probably need to set the tx mode1 reg? maybe at tx time */
+
+	/* set transmit request threshold register */
+	out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000);	/* 256 byte threshold */
+
+	/* set receive  low/high water mark register */
+	/* 440GP has a 64 byte burst length */
+	out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
+	out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
+
+	/* Set fifo limit entry in tx mode 0 */
+	out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
+	/* Frame gap set */
+	out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
+
+	/* Set EMAC IER */
+	hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
+		EMAC_ISR_PTLE | EMAC_ISR_ORE | EMAC_ISR_IRE;
+	if (speed == _100BASET)
+		hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
+
+	out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff);	/* clear pending interrupts */
+	out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
+
+	if (hw_p->first_init == 0) {
+		/*
+		 * Connect interrupt service routines
+		 */
+		irq_install_handler (VECNUM_EWU0 + (hw_p->devnum * 2),
+				     (interrupt_handler_t *) enetInt, dev);
+		irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
+				     (interrupt_handler_t *) enetInt, dev);
+	}
+#if 0				/* done by irq_install_handler */
+	/* set up interrupt handler */
+	/* setup interrupt controller to take interrupts from the MAL &
+	   EMAC */
+	mtdcr (uicsr, 0xffffffff);	/* clear pending interrupts */
+	mtdcr (uicer, mfdcr (uicer) | MAL_UIC_DEF | EMAC_UIC_DEF);
+#endif
+
+	mtmsr (msr);		/* enable interrupts again */
+
+	hw_p->bis = bis;
+	hw_p->first_init = 1;
+
+	return (1);
+}
+
+
+static int ppc_440x_eth_send (struct eth_device *dev, volatile void *ptr,
+			      int len)
+{
+	struct enet_frame *ef_ptr;
+	ulong time_start, time_now;
+	unsigned long temp_txm0;
+	EMAC_440GX_HW_PST hw_p = dev->priv;
+
+	ef_ptr = (struct enet_frame *) ptr;
+
+	/*-----------------------------------------------------------------------+
+	 *  Copy in our address into the frame.
+	 *-----------------------------------------------------------------------*/
+	(void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
+
+	/*-----------------------------------------------------------------------+
+	 * If frame is too long or too short, modify length.
+	 *-----------------------------------------------------------------------*/
+	/* TBS: where does the fragment go???? */
+	if (len > ENET_MAX_MTU)
+		len = ENET_MAX_MTU;
+
+	/*   memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
+	memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
+
+	/*-----------------------------------------------------------------------+
+	 * set TX Buffer busy, and send it
+	 *-----------------------------------------------------------------------*/
+	hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
+					EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
+		~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
+	if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
+		hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
+
+	hw_p->tx[hw_p->tx_slot].data_len = (short) len;
+	hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
+
+	__asm__ volatile ("eieio");
+
+	out32 (EMAC_TXM0 + hw_p->hw_addr,
+	       in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
+#ifdef INFO_440_ENET
+	hw_p->stats.pkts_tx++;
+#endif
+
+	/*-----------------------------------------------------------------------+
+	 * poll unitl the packet is sent and then make sure it is OK
+	 *-----------------------------------------------------------------------*/
+	time_start = get_timer (0);
+	while (1) {
+		temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
+		/* loop until either TINT turns on or 3 seconds elapse */
+		if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
+			/* transmit is done, so now check for errors
+			 * If there is an error, an interrupt should
+			 * happen when we return
+			 */
+			time_now = get_timer (0);
+			if ((time_now - time_start) > 3000) {
+				return (-1);
+			}
+		} else {
+			return (len);
+		}
+	}
+}
+
+
+int enetInt (struct eth_device *dev)
+{
+	int serviced;
+	int rc = -1;		/* default to not us */
+	unsigned long mal_isr;
+	unsigned long emac_isr = 0;
+	unsigned long mal_rx_eob;
+	unsigned long my_uic0msr, my_uic1msr;
+
+#if defined(CONFIG_440_GX)
+	unsigned long my_uic2msr;
+#endif
+	EMAC_440GX_HW_PST hw_p;
+
+	/*
+	 * Because the mal is generic, we need to get the current
+	 * eth device
+	 */
+	dev = eth_get_dev ();
+
+	hw_p = dev->priv;
+
+
+	/* enter loop that stays in interrupt code until nothing to service */
+	do {
+		serviced = 0;
+
+		my_uic0msr = mfdcr (uic0msr);
+		my_uic1msr = mfdcr (uic1msr);
+#if defined(CONFIG_440_GX)
+		my_uic2msr = mfdcr (uic2msr);
+#endif
+		if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
+		    && !(my_uic1msr &
+			 (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE |
+			  UIC_MRDE))) {
+			/* not for us */
+			return (rc);
+		}
+#if defined (CONFIG_440_GX)
+		if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
+		    && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
+			/* not for us */
+			return (rc);
+		}
+#endif
+		/* get and clear controller status interrupts */
+		/* look at Mal and EMAC interrupts */
+		if ((my_uic0msr & (UIC_MRE | UIC_MTE))
+		    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
+			/* we have a MAL interrupt */
+			mal_isr = mfdcr (malesr);
+			/* look for mal error */
+			if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
+				mal_err (dev, mal_isr, my_uic0msr,
+					 MAL_UIC_DEF, MAL_UIC_ERR);
+				serviced = 1;
+				rc = 0;
+			}
+		}
+
+		/* port by port dispatch of emac interrupts */
+		if (hw_p->devnum == 0) {
+			if (UIC_ETH0 & my_uic1msr) {	/* look for EMAC errors */
+				emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
+				if ((hw_p->emac_ier & emac_isr) != 0) {
+					emac_err (dev, emac_isr);
+					serviced = 1;
+					rc = 0;
+				}
+			}
+			if ((hw_p->emac_ier & emac_isr)
+			    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
+				mtdcr (uic0sr, UIC_MRE | UIC_MTE);	/* Clear */
+				mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
+				return (rc);	/* we had errors so get out */
+			}
+		}
+
+		if (hw_p->devnum == 1) {
+			if (UIC_ETH1 & my_uic1msr) {	/* look for EMAC errors */
+				emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
+				if ((hw_p->emac_ier & emac_isr) != 0) {
+					emac_err (dev, emac_isr);
+					serviced = 1;
+					rc = 0;
+				}
+			}
+			if ((hw_p->emac_ier & emac_isr)
+			    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
+				mtdcr (uic0sr, UIC_MRE | UIC_MTE);	/* Clear */
+				mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
+				return (rc);	/* we had errors so get out */
+			}
+		}
+#if defined (CONFIG_440_GX)
+		if (hw_p->devnum == 2) {
+			if (UIC_ETH2 & my_uic2msr) {	/* look for EMAC errors */
+				emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
+				if ((hw_p->emac_ier & emac_isr) != 0) {
+					emac_err (dev, emac_isr);
+					serviced = 1;
+					rc = 0;
+				}
+			}
+			if ((hw_p->emac_ier & emac_isr)
+			    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
+				mtdcr (uic0sr, UIC_MRE | UIC_MTE);	/* Clear */
+				mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
+				mtdcr (uic2sr, UIC_ETH2);
+				return (rc);	/* we had errors so get out */
+			}
+		}
+
+		if (hw_p->devnum == 3) {
+			if (UIC_ETH3 & my_uic2msr) {	/* look for EMAC errors */
+				emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
+				if ((hw_p->emac_ier & emac_isr) != 0) {
+					emac_err (dev, emac_isr);
+					serviced = 1;
+					rc = 0;
+				}
+			}
+			if ((hw_p->emac_ier & emac_isr)
+			    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
+				mtdcr (uic0sr, UIC_MRE | UIC_MTE);	/* Clear */
+				mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
+				mtdcr (uic2sr, UIC_ETH3);
+				return (rc);	/* we had errors so get out */
+			}
+		}
+#endif /* CONFIG_440_GX */
+		/* handle MAX TX EOB interrupt from a tx */
+		if (my_uic0msr & UIC_MTE) {
+			mal_rx_eob = mfdcr (maltxeobisr);
+			mtdcr (maltxeobisr, mal_rx_eob);
+			mtdcr (uic0sr, UIC_MTE);
+		}
+		/* handle MAL RX EOB  interupt from a receive */
+		/* check for EOB on valid channels            */
+		if (my_uic0msr & UIC_MRE) {
+			mal_rx_eob = mfdcr (malrxeobisr);
+			if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) {	/* call emac routine for channel x */
+				/* clear EOB
+				   mtdcr(malrxeobisr, mal_rx_eob); */
+				enet_rcv (dev, emac_isr);
+				/* indicate that we serviced an interrupt */
+				serviced = 1;
+				rc = 0;
+			}
+		}
+		mtdcr (uic0sr, UIC_MRE);	/* Clear */
+		mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
+		switch (hw_p->devnum) {
+		case 0:
+			mtdcr (uic1sr, UIC_ETH0);
+			break;
+		case 1:
+			mtdcr (uic1sr, UIC_ETH1);
+			break;
+#if defined (CONFIG_440_GX)
+		case 2:
+			mtdcr (uic2sr, UIC_ETH2);
+			break;
+		case 3:
+			mtdcr (uic2sr, UIC_ETH3);
+			break;
+#endif /* CONFIG_440_GX */
+		default:
+			break;
+		}
+	} while (serviced);
+
+	return (rc);
+}
+
+/*-----------------------------------------------------------------------------+
+ *  MAL Error Routine
+ *-----------------------------------------------------------------------------*/
+static void mal_err (struct eth_device *dev, unsigned long isr,
+		     unsigned long uic, unsigned long maldef,
+		     unsigned long mal_errr)
+{
+	EMAC_440GX_HW_PST hw_p = dev->priv;
+
+	mtdcr (malesr, isr);	/* clear interrupt */
+
+	/* clear DE interrupt */
+	mtdcr (maltxdeir, 0xC0000000);
+	mtdcr (malrxdeir, 0x80000000);
+
+#ifdef INFO_440_ENET
+	printf ("\nMAL error occured.... ISR = %lx UIC = = %lx  MAL_DEF = %lx  MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
+#endif
+
+	eth_init (hw_p->bis);	/* start again... */
+}
+
+/*-----------------------------------------------------------------------------+
+ *  EMAC Error Routine
+ *-----------------------------------------------------------------------------*/
+static void emac_err (struct eth_device *dev, unsigned long isr)
+{
+	EMAC_440GX_HW_PST hw_p = dev->priv;
+
+	printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
+	out32 (EMAC_ISR + hw_p->hw_addr, isr);
+}
+
+/*-----------------------------------------------------------------------------+
+ *  enet_rcv() handles the ethernet receive data
+ *-----------------------------------------------------------------------------*/
+static void enet_rcv (struct eth_device *dev, unsigned long malisr)
+{
+	struct enet_frame *ef_ptr;
+	unsigned long data_len;
+	unsigned long rx_eob_isr;
+	EMAC_440GX_HW_PST hw_p = dev->priv;
+
+	int handled = 0;
+	int i;
+	int loop_count = 0;
+
+	rx_eob_isr = mfdcr (malrxeobisr);
+	if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
+		/* clear EOB */
+		mtdcr (malrxeobisr, rx_eob_isr);
+
+		/* EMAC RX done */
+		while (1) {	/* do all */
+			i = hw_p->rx_slot;
+
+			if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
+			    || (loop_count >= NUM_RX_BUFF))
+				break;
+			loop_count++;
+			hw_p->rx_slot++;
+			if (NUM_RX_BUFF == hw_p->rx_slot)
+				hw_p->rx_slot = 0;
+			handled++;
+			data_len = (unsigned long) hw_p->rx[i].data_len;	/* Get len */
+			if (data_len) {
+				if (data_len > ENET_MAX_MTU)	/* Check len */
+					data_len = 0;
+				else {
+					if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) {	/* Check Errors */
+						data_len = 0;
+						hw_p->stats.rx_err_log[hw_p->
+								       rx_err_index]
+							= hw_p->rx[i].ctrl;
+						hw_p->rx_err_index++;
+						if (hw_p->rx_err_index ==
+						    MAX_ERR_LOG)
+							hw_p->rx_err_index =
+								0;
+					}	/* emac_erros         */
+				}	/* data_len < max mtu */
+			}	/* if data_len        */
+			if (!data_len) {	/* no data */
+				hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY;	/* Free Recv Buffer */
+
+				hw_p->stats.data_len_err++;	/* Error at Rx */
+			}
+
+			/* !data_len */
+			/* AS.HARNOIS */
+			/* Check if user has already eaten buffer */
+			/* if not => ERROR */
+			else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
+				if (hw_p->is_receiving)
+					printf ("ERROR : Receive buffers are full!\n");
+				break;
+			} else {
+				hw_p->stats.rx_frames++;
+				hw_p->stats.rx += data_len;
+				ef_ptr = (struct enet_frame *) hw_p->rx[i].
+					data_ptr;
+#ifdef INFO_440_ENET
+				hw_p->stats.pkts_rx++;
+#endif
+				/* AS.HARNOIS
+				 * use ring buffer
+				 */
+				hw_p->rx_ready[hw_p->rx_i_index] = i;
+				hw_p->rx_i_index++;
+				if (NUM_RX_BUFF == hw_p->rx_i_index)
+					hw_p->rx_i_index = 0;
+
+				/* printf("X");  /|* test-only *|/ */
+
+				/*  AS.HARNOIS
+				 * free receive buffer only when
+				 * buffer has been handled (eth_rx)
+				 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
+				 */
+			}	/* if data_len */
+		}		/* while */
+	}			/* if EMACK_RXCHL */
+}
+
+
+static int ppc_440x_eth_rx (struct eth_device *dev)
+{
+	int length;
+	int user_index;
+	unsigned long msr;
+	EMAC_440GX_HW_PST hw_p = dev->priv;
+
+	hw_p->is_receiving = 1;	/* tell driver */
+
+	for (;;) {
+		/* AS.HARNOIS
+		 * use ring buffer and
+		 * get index from rx buffer desciptor queue
+		 */
+		user_index = hw_p->rx_ready[hw_p->rx_u_index];
+		if (user_index == -1) {
+			length = -1;
+			break;	/* nothing received - leave for() loop */
+		}
+
+		msr = mfmsr ();
+		mtmsr (msr & ~(MSR_EE));
+
+		length = hw_p->rx[user_index].data_len;
+
+		/* Pass the packet up to the protocol layers. */
+		/*       NetReceive(NetRxPackets[rxIdx], length - 4); */
+		/*       NetReceive(NetRxPackets[i], length); */
+		NetReceive (NetRxPackets[user_index], length - 4);
+		/* Free Recv Buffer */
+		hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
+		/* Free rx buffer descriptor queue */
+		hw_p->rx_ready[hw_p->rx_u_index] = -1;
+		hw_p->rx_u_index++;
+		if (NUM_RX_BUFF == hw_p->rx_u_index)
+			hw_p->rx_u_index = 0;
+
+#ifdef INFO_440_ENET
+		hw_p->stats.pkts_handled++;
+#endif
+
+		mtmsr (msr);	/* Enable IRQ's */
+	}
+
+	hw_p->is_receiving = 0;	/* tell driver */
+
+	return length;
+}
+
+int ppc_440x_eth_initialize (bd_t * bis)
+{
+	static int virgin = 0;
+	unsigned long pfc1;
+	struct eth_device *dev;
+	int eth_num = 0;
+
+	EMAC_440GX_HW_PST hw = NULL;
+
+	mfsdr (sdr_pfc1, pfc1);
+	pfc1 &= ~(0x01e00000);
+	pfc1 |= 0x01200000;
+	mtsdr (sdr_pfc1, pfc1);
+
+	for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
+
+		/* See if we can actually bring up the interface, otherwise, skip it */
+		switch (eth_num) {
+		case 0:
+			if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0)
+				continue;
+			break;
+		case 1:
+			if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) ==
+			    0)
+				continue;
+			break;
+		case 2:
+			if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) ==
+			    0)
+				continue;
+			break;
+		case 3:
+			if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) ==
+			    0)
+				continue;
+			break;
+		default:
+			if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0)
+				continue;
+			break;
+		}
+
+		/* Allocate device structure */
+		dev = (struct eth_device *) malloc (sizeof (*dev));
+		if (dev == NULL) {
+			printf (__FUNCTION__
+				": Cannot allocate eth_device %d\n", eth_num);
+			return (-1);
+		}
+
+		/* Allocate our private use data */
+		hw = (EMAC_440GX_HW_PST) malloc (sizeof (*hw));
+		if (hw == NULL) {
+			printf (__FUNCTION__
+				": Cannot allocate private hw data for eth_device %d",
+				eth_num);
+			free (dev);
+			return (-1);
+		}
+
+		switch (eth_num) {
+		case 0:
+			hw->hw_addr = 0;
+			memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
+			break;
+		case 1:
+			hw->hw_addr = 0x100;
+			memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
+			break;
+		case 2:
+			hw->hw_addr = 0x400;
+			memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
+			break;
+		case 3:
+			hw->hw_addr = 0x600;
+			memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
+			break;
+		default:
+			hw->hw_addr = 0;
+			memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
+			break;
+		}
+
+		hw->devnum = eth_num;
+
+		sprintf (dev->name, "ppc_440x_eth%d", eth_num);
+		dev->priv = (void *) hw;
+		dev->init = ppc_440x_eth_init;
+		dev->halt = ppc_440x_eth_halt;
+		dev->send = ppc_440x_eth_send;
+		dev->recv = ppc_440x_eth_rx;
+
+		if (0 == virgin) {
+			/* set the MAL IER ??? names may change with new spec ??? */
+			mal_ier =
+				MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
+				MAL_IER_OPBE | MAL_IER_PLBE;
+			mtdcr (malesr, 0xffffffff);	/* clear pending interrupts */
+			mtdcr (maltxdeir, 0xffffffff);	/* clear pending interrupts */
+			mtdcr (malrxdeir, 0xffffffff);	/* clear pending interrupts */
+			mtdcr (malier, mal_ier);
+
+			/* install MAL interrupt handler */
+			irq_install_handler (VECNUM_MS,
+					     (interrupt_handler_t *) enetInt,
+					     dev);
+			irq_install_handler (VECNUM_MTE,
+					     (interrupt_handler_t *) enetInt,
+					     dev);
+			irq_install_handler (VECNUM_MRE,
+					     (interrupt_handler_t *) enetInt,
+					     dev);
+			irq_install_handler (VECNUM_TXDE,
+					     (interrupt_handler_t *) enetInt,
+					     dev);
+			irq_install_handler (VECNUM_RXDE,
+					     (interrupt_handler_t *) enetInt,
+					     dev);
+			virgin = 1;
+		}
+
+		eth_register (dev);
+
+	}			/* end for each supported device */
+	return (1);
+}
+#endif /* CONFIG_440 && CONFIG_NET_MULTI */
diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile
index 12f1fdf..9b54d32 100644
--- a/cpu/ppc4xx/Makefile
+++ b/cpu/ppc4xx/Makefile
@@ -27,9 +27,12 @@
 
 START	= start.o resetvec.o kgdb.o
 AOBJS	= dcr.o
-COBJS	= traps.o serial.o cpu.o cpu_init.o speed.o interrupts.o \
-	  405gp_pci.o 405gp_enet.o miiphy.o i2c.o bedbug_405.o \
-	  spd_sdram.o sdram.o
+COBJS	= 405gp_enet.o 405gp_pci.o 440gx_enet.o \
+	  bedbug_405.o \
+	  cpu.o cpu_init.o i2c.o interrupts.o \
+	  miiphy.o miiphy_440.o sdram.o serial.o \
+	  spd_sdram.o speed.o traps.o
+
 OBJS	= $(AOBJS) $(COBJS)
 
 all:	.depend $(START) $(LIB)
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 0ad99b8..df19605 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -152,10 +152,10 @@
 #endif
 
 #if defined(CONFIG_440)
-	puts ("IBM PowerPC 440 Rev. ");
+	puts ("IBM PowerPC 440 G");
 	switch(pvr) {
 	case PVR_440GP_RB:
-		putc('B');
+		puts("P Rev. B");
 		/* See errata 1.12: CHIP_4 */
 		if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
 		    (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
@@ -167,7 +167,13 @@
 		}
 		break;
 	case PVR_440GP_RC:
-		putc('C');
+		puts("P Rev. C");
+		break;
+	case PVR_440GX_RA:
+		puts("X Rev. A");
+		break;
+	case PVR_440GX_RB:
+		puts("X Rev. B");
 		break;
 	default:
 		printf ("UNKNOWN (PVR=%08x)", pvr);
diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c
index 974797f..71052b4 100644
--- a/cpu/ppc4xx/interrupts.c
+++ b/cpu/ppc4xx/interrupts.c
@@ -5,6 +5,9 @@
  * (C) Copyright 2002 (440 port)
  * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
  *
+ * (C) Copyright 2003 (440GX port)
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -50,7 +53,15 @@
 static struct irq_action irq_vecs1[32]; /* For UIC1 */
 
 void uic1_interrupt( void * parms); /* UIC1 handler */
-#endif
+
+#if defined(CONFIG_440_GX)
+static struct irq_action irq_vecs2[32]; /* For UIC2 */
+
+void uic0_interrupt( void * parms); /* UIC0 handler */
+void uic2_interrupt( void * parms); /* UIC2 handler */
+#endif /* CONFIG_440_GX */
+
+#endif /* CONFIG_440 */
 
 /****************************************************************************/
 #if defined(CONFIG_440)
@@ -104,6 +115,11 @@
 		irq_vecs1[vec].handler = NULL;
 		irq_vecs1[vec].arg = NULL;
 		irq_vecs1[vec].count = 0;
+#if defined(CONFIG_440_GX)
+		irq_vecs2[vec].handler = NULL;
+		irq_vecs2[vec].arg = NULL;
+		irq_vecs2[vec].count = 0;
+#endif /* CONFIG_440_GX */
 #endif
 	}
 
@@ -146,10 +162,18 @@
 	set_evpr(0x00000000);
 
 #if defined(CONFIG_440)
+#if !defined(CONFIG_440_GX)
 	/* Install the UIC1 handlers */
 	irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0);
 	irq_install_handler(VECNUM_UIC1C, uic1_interrupt, 0);
 #endif
+#endif
+
+#if defined(CONFIG_440_GX)
+	/* Enable UIC interrupts via UIC Base Enable Register */
+	mtdcr(uicb0er, UICB0_ALL);
+	mtdcr(uicb0cr, UICB0_ALL);
+#endif
 
 	return (0);
 }
@@ -159,9 +183,32 @@
 /*
  * Handle external interrupts
  */
+#if defined(CONFIG_440_GX)
 void external_interrupt(struct pt_regs *regs)
 {
 	ulong uic_msr;
+
+	/*
+	 * Read masked interrupt status register to determine interrupt source
+	 */
+	/* 440 GX uses base uic register */
+	uic_msr = mfdcr(uicb0msr);
+
+	uic0_interrupt(0);
+	uic1_interrupt(0);
+	uic2_interrupt(0);
+
+	mtdcr(uicb0sr, UICB0_ALL);
+
+	return;
+
+} /* external_interrupt CONFIG_440_GX */
+
+#else
+
+void external_interrupt(struct pt_regs *regs)
+{
+	ulong uic_msr;
 	ulong msr_shift;
 	int vec;
 
@@ -200,6 +247,53 @@
 		vec++;
 	}
 }
+#endif
+
+#if defined(CONFIG_440_GX)
+/* Handler for UIC0 interrupt */
+void uic0_interrupt( void * parms)
+{
+	ulong uic_msr;
+	ulong msr_shift;
+	int vec;
+
+	/*
+	 * Read masked interrupt status register to determine interrupt source
+	 */
+	uic_msr = mfdcr(uicmsr);
+	msr_shift = uic_msr;
+	vec = 0;
+
+	while (msr_shift != 0) {
+		if (msr_shift & 0x80000000) {
+			/*
+			 * Increment irq counter (for debug purpose only)
+			 */
+			irq_vecs[vec].count++;
+
+			if (irq_vecs[vec].handler != NULL) {
+				/* call isr */
+				(*irq_vecs[vec].handler)(irq_vecs[vec].arg);
+			} else {
+				mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec));
+				printf ("Masking bogus interrupt vector (uic0) 0x%x\n", vec);
+			}
+
+			/*
+			 * After servicing the interrupt, we have to remove the status indicator.
+			 */
+			mtdcr(uicsr, (0x80000000 >> vec));
+		}
+
+		/*
+		 * Shift msr to next position and increment vector
+		 */
+		msr_shift <<= 1;
+		vec++;
+	}
+}
+
+#endif /* CONFIG_440_GX */
 
 #if defined(CONFIG_440)
 /* Handler for UIC1 interrupt */
@@ -246,50 +340,119 @@
 }
 #endif /* defined(CONFIG_440) */
 
+#if defined(CONFIG_440_GX)
+/* Handler for UIC1 interrupt */
+void uic2_interrupt( void * parms)
+{
+	ulong uic2_msr;
+	ulong msr_shift;
+	int vec;
+
+	/*
+	 * Read masked interrupt status register to determine interrupt source
+	 */
+	uic2_msr = mfdcr(uic2msr);
+	msr_shift = uic2_msr;
+	vec = 0;
+
+	while (msr_shift != 0) {
+		if (msr_shift & 0x80000000) {
+			/*
+			 * Increment irq counter (for debug purpose only)
+			 */
+			irq_vecs2[vec].count++;
+
+			if (irq_vecs2[vec].handler != NULL) {
+				/* call isr */
+				(*irq_vecs2[vec].handler)(irq_vecs2[vec].arg);
+			} else {
+				mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> vec));
+				printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec);
+			}
+
+			/*
+			 * After servicing the interrupt, we have to remove the status indicator.
+			 */
+			mtdcr(uic2sr, (0x80000000 >> vec));
+		}
+
+		/*
+		 * Shift msr to next position and increment vector
+		 */
+		msr_shift <<= 1;
+		vec++;
+	}
+}
+#endif /* defined(CONFIG_440_GX) */
+
 /****************************************************************************/
 
 /*
  * Install and free a interrupt handler.
  */
 
-void
-irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
+void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
 {
 	struct irq_action *irqa = irq_vecs;
-	int   i = vec;
+	int i = vec;
 
 #if defined(CONFIG_440)
+#if defined(CONFIG_440_GX)
+	if ((vec > 31) && (vec < 64)) {
+		i = vec - 32;
+		irqa = irq_vecs1;
+	} else if (vec > 63) {
+		i = vec - 64;
+		irqa = irq_vecs2;
+	}
+#else  /* CONFIG_440_GX */
 	if (vec > 31) {
 		i = vec - 32;
 		irqa = irq_vecs1;
 	}
-#endif
+#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440 */
 
 	if (irqa[i].handler != NULL) {
 		printf ("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
-			vec, (uint)handler, (uint)irqa[i].handler);
+			vec, (uint) handler, (uint) irqa[i].handler);
 	}
 	irqa[i].handler = handler;
-	irqa[i].arg     = arg;
+	irqa[i].arg = arg;
 
 #if defined(CONFIG_440)
-	if( vec > 31 )
-		mtdcr(uic1er, mfdcr(uic1er) | (0x80000000 >> i));
+#if defined(CONFIG_440_GX)
+	if ((vec > 31) && (vec < 64))
+		mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
+	else if (vec > 63)
+		mtdcr (uic2er, mfdcr (uic2er) | (0x80000000 >> i));
+	else
+#endif /* CONFIG_440_GX */
+	if (vec > 31)
+		mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
 	else
 #endif
-		mtdcr(uicer, mfdcr(uicer) | (0x80000000 >> i));
+		mtdcr (uicer, mfdcr (uicer) | (0x80000000 >> i));
 #if 0
 	printf ("Install interrupt for vector %d ==> %p\n", vec, handler);
 #endif
 }
 
-void
-irq_free_handler(int vec)
+void irq_free_handler (int vec)
 {
 	struct irq_action *irqa = irq_vecs;
-	int   i = vec;
+	int i = vec;
 
 #if defined(CONFIG_440)
+#if defined(CONFIG_440_GX)
+	if ((vec > 31) && (vec < 64)) {
+		irqa = irq_vecs1;
+		i = vec - 32;
+	} else if (vec > 63) {
+		irqa = irq_vecs2;
+		i = vec - 64;
+	}
+#endif /* CONFIG_440_GX */
 	if (vec > 31) {
 		irqa = irq_vecs1;
 		i = vec - 32;
@@ -302,14 +465,21 @@
 #endif
 
 #if defined(CONFIG_440)
+#if defined(CONFIG_440_GX)
+	if ((vec > 31) && (vec < 64))
+		mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
+	else if (vec > 63)
+		mtdcr (uic2er, mfdcr (uic2er) & ~(0x80000000 >> i));
+	else
+#endif /* CONFIG_440_GX */
 	if (vec > 31)
-		mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> i));
+		mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
 	else
 #endif
-		mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> i));
+		mtdcr (uicer, mfdcr (uicer) & ~(0x80000000 >> i));
 
 	irqa[i].handler = NULL;
-	irqa[i].arg     = NULL;
+	irqa[i].arg = NULL;
 }
 
 /****************************************************************************/
@@ -354,8 +524,7 @@
 	printf ("\nUIC 1\n");
 	printf ("Nr  Routine   Arg       Count\n");
 
-	for (vec=0; vec<32; vec++)
-	{
+	for (vec=0; vec<32; vec++) {
 		if (irq_vecs1[vec].handler != NULL)
 			printf ("%02d  %08lx  %08lx  %d\n",
 				vec+31, (ulong)irq_vecs1[vec].handler,
@@ -363,8 +532,20 @@
 	}
 	printf("\n");
 #endif
-	return 0;
-}
 
+#if defined(CONFIG_440_GX)
+	printf ("\nUIC 2\n");
+	printf ("Nr  Routine   Arg       Count\n");
 
+	for (vec=0; vec<32; vec++) {
+		if (irq_vecs2[vec].handler != NULL)
+			printf ("%02d  %08lx  %08lx  %d\n",
+				vec+63, (ulong)irq_vecs2[vec].handler,
+				(ulong)irq_vecs2[vec].arg, irq_vecs2[vec].count);
+	}
+	printf("\n");
+#endif
+
+	return 0;
+}
 #endif  /* CONFIG_COMMANDS & CFG_CMD_IRQ */
diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c
index fce5f4b..5ca6681 100644
--- a/cpu/ppc4xx/miiphy.c
+++ b/cpu/ppc4xx/miiphy.c
@@ -48,8 +48,8 @@
 #include <405_mal.h>
 #include <miiphy.h>
 
-#if defined(CONFIG_405GP) || defined(CONFIG_440) || defined(CONFIG_405EP)
-
+#if (defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_440)) \
+   && !defined (CONFIG_NET_MULTI)
 
 /***********************************************************/
 /* Dump out to the screen PHY regs                         */
diff --git a/cpu/ppc4xx/miiphy_440.c b/cpu/ppc4xx/miiphy_440.c
new file mode 100644
index 0000000..bbe535a
--- /dev/null
+++ b/cpu/ppc4xx/miiphy_440.c
@@ -0,0 +1,259 @@
+/*-----------------------------------------------------------------------------+
+  |
+  |	  This source code has been made available to you by IBM on an AS-IS
+  |	  basis.  Anyone receiving this source is licensed under IBM
+  |	  copyrights to use it in any way he or she deems fit, including
+  |	  copying it, modifying it, compiling it, and redistributing it either
+  |	  with or without modifications.  No license under IBM patents or
+  |	  patent applications is to be implied by the copyright license.
+  |
+  |	  Any user of this software should understand that IBM cannot provide
+  |	  technical support for this software and will not be responsible for
+  |	  any consequences resulting from the use of this software.
+  |
+  |	  Any person who transfers this source code or any derivative work
+  |	  must include the IBM copyright notice, this paragraph, and the
+  |	  preceding two paragraphs in the transferred software.
+  |
+  |	  COPYRIGHT   I B M   CORPORATION 1995
+  |	  LICENSED MATERIAL  -	PROGRAM PROPERTY OF I B M
+  +-----------------------------------------------------------------------------*/
+/*-----------------------------------------------------------------------------+
+  |
+  |  File Name:	 miiphy.c
+  |
+  |  Function:	 This module has utilities for accessing the MII PHY through
+  |	       the EMAC3 macro.
+  |
+  |  Author:	 Mark Wisner
+  |
+  |  Change Activity-
+  |
+  |  Date	 Description of Change					     BY
+  |  ---------	 ---------------------					     ---
+  |  05-May-99	 Created						     MKW
+  |  01-Jul-99	 Changed clock setting of sta_reg from 66Mhz to 50Mhz to
+  |		 better match OPB speed. Also modified delay times.	     JWB
+  |  29-Jul-99	 Added Full duplex support				     MKW
+  |  24-Aug-99	 Removed printf from dp83843_duplex()			     JWB
+  |  19-Jul-00	 Ported to esd cpci405					     sr
+  |  23-Dec-03	 Ported from miiphy.c to 440GX Travis Sawyer		     TBS
+  |		 <travis.sawyer@sandburst.com>
+  |
+  +-----------------------------------------------------------------------------*/
+
+#include <common.h>
+#include <asm/processor.h>
+#include <ppc_asm.tmpl>
+#include <commproc.h>
+#include <440gx_enet.h>
+#include <405_mal.h>
+#include <miiphy.h>
+
+#if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
+
+
+/***********************************************************/
+/* Dump out to the screen PHY regs			   */
+/***********************************************************/
+
+void miiphy_dump (unsigned char addr)
+{
+	unsigned long i;
+	unsigned short data;
+
+
+	for (i = 0; i < 0x1A; i++) {
+		if (miiphy_read (addr, i, &data)) {
+			printf ("read error for reg %lx\n", i);
+			return;
+		}
+		printf ("Phy reg %lx ==> %4x\n", i, data);
+
+		/* jump to the next set of regs */
+		if (i == 0x07)
+			i = 0x0f;
+
+	}			/* end for loop */
+}				/* end dump */
+
+
+/***********************************************************/
+/* (Re)start autonegotiation				   */
+/***********************************************************/
+int phy_setup_aneg (unsigned char addr)
+{
+	unsigned short ctl, adv;
+
+	/* Setup standard advertise */
+	miiphy_read (addr, PHY_ANAR, &adv);
+	adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
+		PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
+		PHY_ANLPAR_10);
+	miiphy_write (addr, PHY_ANAR, adv);
+
+	/* Start/Restart aneg */
+	miiphy_read (addr, PHY_BMCR, &ctl);
+	ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+	miiphy_write (addr, PHY_BMCR, ctl);
+
+	return 0;
+}
+
+
+/***********************************************************/
+/* read a phy reg and return the value with a rc	   */
+/***********************************************************/
+unsigned int miiphy_getemac_offset (void)
+{
+	unsigned long zmii;
+	unsigned long eoffset;
+
+	/* Need to find out which mdi port we're using */
+	zmii = in32 (ZMII_FER);
+
+	if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) {
+		/* using port 0 */
+		eoffset = 0;
+	} else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) {
+		/* using port 1 */
+		eoffset = 0x100;
+	} else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) {
+		/* using port 2 */
+		eoffset = 0x400;
+	} else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) {
+		/* using port 3 */
+		eoffset = 0x600;
+	} else {
+		/* None of the mdi ports are enabled! */
+		/* enable port 0 */
+		zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
+		out32 (ZMII_FER, zmii);
+		eoffset = 0;
+		/* need to soft reset port 0 */
+		zmii = in32 (EMAC_M0);
+		zmii |= EMAC_M0_SRST;
+		out32 (EMAC_M0, zmii);
+	}
+
+	return (eoffset);
+
+}
+
+
+int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
+{
+	unsigned long sta_reg;	/* STA scratch area */
+	unsigned long i;
+	unsigned long emac_reg;
+
+
+	emac_reg = miiphy_getemac_offset ();
+	/* see if it is ready for 1000 nsec */
+	i = 0;
+
+	/* see if it is ready for  sec */
+	while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
+		udelay (7);
+		if (i > 5) {
+#if 0
+			printf ("read err 1\n");
+#endif
+			return -1;
+		}
+		i++;
+	}
+	sta_reg = reg;		/* reg address */
+	/* set clock (50Mhz) and read flags */
+#if defined(CONFIG_440_GX)
+	sta_reg |= EMAC_STACR_READ;
+#else
+	sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
+#endif
+
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440_GX)
+	sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
+#endif
+	sta_reg = sta_reg | (addr << 5);	/* Phy address */
+
+	out32 (EMAC_STACR + emac_reg, sta_reg);
+#if 0				/* test-only */
+	printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg);	/* test-only */
+#endif
+
+	sta_reg = in32 (EMAC_STACR + emac_reg);
+	i = 0;
+	while ((sta_reg & EMAC_STACR_OC) == 0) {
+		udelay (7);
+		if (i > 5) {
+			return -1;
+		}
+		i++;
+		sta_reg = in32 (EMAC_STACR + emac_reg);
+	}
+	if ((sta_reg & EMAC_STACR_PHYE) != 0) {
+		return -1;
+	}
+
+	*value = *(short *) (&sta_reg);
+	return 0;
+
+
+}				/* phy_read */
+
+
+/***********************************************************/
+/* write a phy reg and return the value with a rc	    */
+/***********************************************************/
+
+int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
+{
+	unsigned long sta_reg;	/* STA scratch area */
+	unsigned long i;
+	unsigned long emac_reg;
+
+	emac_reg = miiphy_getemac_offset ();
+	/* see if it is ready for 1000 nsec */
+	i = 0;
+
+	while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
+		if (i > 5)
+			return -1;
+		udelay (7);
+		i++;
+	}
+	sta_reg = 0;
+	sta_reg = reg;		/* reg address */
+	/* set clock (50Mhz) and read flags */
+#if defined(CONFIG_440_GX)
+	sta_reg |= EMAC_STACR_WRITE;
+#else
+	sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
+#endif
+
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440_GX)
+	sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;	/* Set clock frequency (PLB freq. dependend) */
+#endif
+	sta_reg = sta_reg | ((unsigned long) addr << 5);	/* Phy address */
+	memcpy (&sta_reg, &value, 2);	/* put in data */
+
+	out32 (EMAC_STACR + emac_reg, sta_reg);
+
+	/* wait for completion */
+	i = 0;
+	sta_reg = in32 (EMAC_STACR + emac_reg);
+	while ((sta_reg & EMAC_STACR_OC) == 0) {
+		udelay (7);
+		if (i > 5)
+			return -1;
+		i++;
+		sta_reg = in32 (EMAC_STACR + emac_reg);
+	}
+
+	if ((sta_reg & EMAC_STACR_PHYE) != 0)
+		return -1;
+	return 0;
+
+}				/* phy_write */
+
+#endif /* CONFIG_405GP */
diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c
index 6b0e39a..2c77338 100644
--- a/cpu/ppc4xx/serial.c
+++ b/cpu/ppc4xx/serial.c
@@ -271,9 +271,15 @@
 #if defined(CONFIG_440)
 #define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000200
 #define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000300
+#if defined(CONFIG_440_GX)
+#define CR0_MASK        0xdfffffff
+#define CR0_EXTCLK_ENA  0x00800000
+#define CR0_UDIV_POS    0
+#else
 #define CR0_MASK        0x3fff0000
 #define CR0_EXTCLK_ENA  0x00600000
 #define CR0_UDIV_POS    16
+#endif /* CONFIG_440_GX */
 #elif defined(CONFIG_405EP)
 #define UART0_BASE      0xef600300
 #define UART1_BASE      0xef600400
@@ -295,9 +301,17 @@
 #if defined(CONFIG_UART1_CONSOLE)
 #define ACTING_UART0_BASE	UART1_BASE
 #define ACTING_UART1_BASE	UART0_BASE
+#if defined(CONFIG_440_GX)
+#define UART0_SDR           sdr_uart1
+#define UART1_SDR           sdr_uart0
+#endif /* CONFIG_440_GX */
 #else
 #define ACTING_UART0_BASE	UART0_BASE
 #define ACTING_UART1_BASE	UART1_BASE
+#if defined(CONFIG_440_GX)
+#define UART0_SDR           sdr_uart0
+#define UART1_SDR           sdr_uart1
+#endif /* CONFIG_440_GX */
 #endif
 
 #if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
@@ -416,7 +430,12 @@
 	unsigned long tmp;
 #endif
 
+#if defined(CONFIG_440_GX)
+	mfsdr(UART0_SDR,reg);
+	reg &= ~CR0_MASK;
+#else
 	reg = mfdcr(cntrl0) & ~CR0_MASK;
+#endif /* CONFIG_440_GX */
 #ifdef CFG_EXT_SERIAL_CLOCK
 	reg |= CR0_EXTCLK_ENA;
 	udiv = 1;
@@ -430,9 +449,13 @@
 	serial_divs (gd->baudrate, &udiv, &bdiv);
 #endif
 
+#if defined(CONFIG_440_GX)
+	reg |= udiv << CR0_UDIV_POS;	/* set the UART divisor */
+	mtsdr (UART0_SDR,reg);
+#else
 	reg |= (udiv - 1) << CR0_UDIV_POS;	/* set the UART divisor */
 	mtdcr (cntrl0, reg);
-
+#endif
 	out8 (ACTING_UART0_BASE + UART_LCR, 0x80);	/* set DLAB bit */
 	out8 (ACTING_UART0_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
 	out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index 7263227..dfd2a04 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -206,6 +206,7 @@
 
 
 #elif defined(CONFIG_440)
+#if !defined(CONFIG_440_GX)
 void get_sys_info (sys_info_t * sysInfo)
 {
 	unsigned long strp0;
@@ -237,6 +238,58 @@
 	sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
 
 }
+#else
+void get_sys_info (sys_info_t * sysInfo)
+{
+	unsigned long strp0;
+	unsigned long strp1;
+	unsigned long temp;
+	unsigned long temp1;
+	unsigned long lfdiv;
+	unsigned long m;
+
+
+	/* Extract configured divisors */
+	mfsdr( sdr_sdstp0,strp0 );
+	mfsdr( sdr_sdstp1,strp1 );
+
+	temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8);
+	sysInfo->pllFwdDivA = temp ? temp : 16 ;
+	temp = ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 5);
+	sysInfo->pllFwdDivB = temp ? temp: 8 ;
+	temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 12;
+	sysInfo->pllFbkDiv = temp ? temp : 32;
+	temp = (strp0 & PLLSYS0_OPB_DIV_MASK);
+	sysInfo->pllOpbDiv = temp ? temp : 4;
+	temp = (strp1 & PLLSYS1_PERCLK_DIV_MASK) >> 24;
+	sysInfo->pllExtBusDiv = temp ? temp : 4;
+
+	/* Calculate 'M' based on feedback source */
+	temp = (strp0 & PLLSYS0_SEL_MASK) >> 27;
+	temp1 = (strp1 & PLLSYS1_LF_DIV_MASK) >> 26;
+	lfdiv = temp1 ? temp1 : 64;
+	if (temp == 0) { /* PLL output */
+		/* Figure which pll to use */
+		temp = (strp0 & PLLSYS0_SRC_MASK) >> 30;
+		if (!temp)
+			m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
+		else
+			m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB;
+	}
+	else if (temp == 1) /* CPU output */
+		m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
+	else /* PerClk */
+		m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
+
+	/* Now calculate the individual clocks */
+	sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
+	sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
+	sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB;
+	sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
+	sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
+
+}
+#endif
 
 ulong get_OPB_freq (void)
 {
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index e25101a..3473baa 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -166,7 +166,12 @@
 	mtspr	srr1,r0
 	mtspr	csrr0,r0
 	mtspr	csrr1,r0
-
+#if defined (CONFIG_440_GX) /* NOTE: 440GX adds machine check status regs */
+	mtspr   mcsrr0,r0
+	mtspr   mcsrr1,r0
+	mfspr   r1, mcsr
+	mtspr   mcsr,r1
+#endif
 	/*----------------------------------------------------------------*/
 	/* Initialize debug */
 	/*----------------------------------------------------------------*/
@@ -335,9 +340,23 @@
 	mtspr	tcr,r0			/* disable all */
 	mtspr	esr,r0			/* clear exception syndrome register */
 	mtxer	r0			/* clear integer exception register */
+#if !defined(CONFIG_440_GX)
 	lis	r1,0x0002		/* set CE bit (Critical Exceptions) */
 	ori	r1,r1,0x1000		/* set ME bit (Machine Exceptions) */
 	mtmsr	r1			/* change MSR */
+#else
+	bl	__440gx_msr_set
+	b	__440gx_msr_continue
+
+__440gx_msr_set:
+	lis 	r1, 0x0002		/* set CE bit (Critical Exceptions) */
+	ori 	r1,r1,0x1000	/* set ME bit (Machine Exceptions) */
+	mtspr	srr1,r1
+	mflr	r1
+	mtspr	srr0,r1
+	rfi
+__440gx_msr_continue:
+#endif
 
 	/*----------------------------------------------------------------*/
 	/* Debug setup -- some (not very good) ice's need an event*/
@@ -358,6 +377,9 @@
 	/* Setup the internal SRAM */
 	/*----------------------------------------------------------------*/
 	li	r0,0
+#if defined (CONFIG_440_GX)
+	mtdcr   l2_cache_cfg,r0		/* Ensure L2 Cache is off */
+#endif
 	mtdcr	isram0_sb1cr,r0		/* Disable bank 1 */
 
 	li	r2,0x7fff
@@ -370,8 +392,22 @@
 	mtdcr	isram0_pmeg,r1
 
 	lis	r1,0x8000		/* BAS = 8000_0000 */
+#if defined(CONFIG_440_GX)
+	ori	r1,r1,0x0980		/* first 64k */
+	mtdcr   isram0_sb0cr,r1
+	lis	r1,0x8001
+	ori	r1,r1,0x0980		/* second 64k */
+	mtdcr   isram0_sb1cr,r1
+	lis	r1, 0x8002
+	ori	r1,r1, 0x0980		/* third 64k */
+	mtdcr   isram0_sb2cr,r1
+	lis	r1, 0x8003
+	ori	r1,r1, 0x0980		/* fourth 64k */
+	mtdcr   isram0_sb3cr,r1
+#else
 	ori	r1,r1,0x0380		/* 8k rw */
 	mtdcr	isram0_sb0cr,r1
+#endif
 
 	/*----------------------------------------------------------------*/
 	/* Setup the stack in internal SRAM */
@@ -921,7 +957,12 @@
 invalidate_dcache:
 	addi	r6,0,0x0000		/* clear GPR 6 */
 	/* Do loop for # of dcache congruence classes. */
+#if defined(CONFIG_440_GX)
+	lis     r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha	/* TBS for large sized cache */
+	ori     r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
+#else
 	addi	r7,r0, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
+#endif
 					/* NOTE: dccci invalidates both */
 	mtctr	r7			/* ways in the D cache */
 ..dcloop:
@@ -942,8 +983,15 @@
 	mtdccr	r10
 
 	/* do loop for # of congruence classes. */
+#if defined(CONFIG_440_GX)
+	lis     r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha	/* TBS: for large cache sizes */
+	ori     r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
+	lis     r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
+	ori     r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
+#else
 	addi	r10,r0,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
 	addi	r11,r0,(CFG_DCACHE_SIZE / 2) /* D cache set size - 2 way sets */
+#endif
 	mtctr	r10
 	addi	r10,r0,(0xE000-0x10000)	/* start at 0xFFFFE000 */
 	add	r11,r10,r11		/* add to get to other side of cache line */