* Add support for Promess ATC board
* Patch by Keith Outwater, 28 Apr 2003:
- Miscellaneous corrections and additions to GEN860T board specific code.
- Added GEN860_SC variant to GEN860T.
- Miscellaneous corrections to GEN860T documentation.
- Correct duplicate entry in U-Boot CREDITS file.
- Add GEN860T_SC entry in MAINTAINERS file.
- Update CREDITS file with GEN860T_SC info.
* Update Smiths Aerospace addresses in MAINTAINERS file
* Fix error handling in hush's version of "run" command
diff --git a/include/asm-ppc/cpm_8260.h b/include/asm-ppc/cpm_8260.h
index bf2e2a2..5c70603 100644
--- a/include/asm-ppc/cpm_8260.h
+++ b/include/asm-ppc/cpm_8260.h
@@ -170,7 +170,7 @@
*/
#define PROFF_SMC1 (0)
#define PROFF_SMC2 (64)
-
+#define PROFF_SPI ((16*1024) - 128)
/* Define enough so I can at least use the serial port as a UART.
*/
@@ -737,6 +737,17 @@
#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
#define SPMODE_PM(x) ((x) &0xF)
+/* SPI Event/Mask register.
+*/
+#define SPI_EMASK 0x37 /* Event Mask */
+#define SPI_MME 0x20 /* Multi-Master Error */
+#define SPI_TXE 0x10 /* Transmit Error */
+#define SPI_BSY 0x04 /* Busy */
+#define SPI_TXB 0x02 /* Tx Buffer Empty */
+#define SPI_RXB 0x01 /* RX Buffer full/closed */
+
+#define SPI_STR 0x80 /* SPCOM: Start transmit */
+
#define SPI_EB ((u_char)0x10) /* big endian byte order */
#define BD_IIC_START ((ushort)0x0400)
diff --git a/include/common.h b/include/common.h
index 5096754..2ff1c8c 100644
--- a/include/common.h
+++ b/include/common.h
@@ -198,7 +198,7 @@
# define CFG_DEF_EEPROM_ADDR CFG_I2C_EEPROM_ADDR
#endif /* CONFIG_SPI || !defined(CFG_I2C_EEPROM_ADDR) */
-#if defined(CONFIG_PCU_E) || defined(CONFIG_CCM)
+#if defined(CONFIG_PCU_E) || defined(CONFIG_CCM) || defined(CONFIG_ATC)
extern void spi_init_f (void);
extern void spi_init_r (void);
extern ssize_t spi_read (uchar *, int, uchar *, int);
diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h
index 29e4807..47a8786 100644
--- a/include/configs/GEN860T.h
+++ b/include/configs/GEN860T.h
@@ -38,14 +38,22 @@
/*
* Identify the board
*/
-#define CONFIG_IDENT_STRING " GEN860T"
+#if !defined(CONFIG_SC)
+#define CONFIG_IDENT_STRING " B2"
+#else
+#define CONFIG_IDENT_STRING " SC"
+#endif
/*
* Don't depend on the RTC clock to determine clock frequency -
* the 860's internal rtc uses a 32.768 KHz clock which is
* generated by the DS1337 - and the DS1337 clock can be turned off.
*/
-#define CONFIG_8xx_GCLK_FREQ 66600000
+#if !defined(CONFIG_SC)
+#define CONFIG_8xx_GCLK_FREQ 66600000
+#else
+#define CONFIG_8xx_GCLK_FREQ 48000000
+#endif
/*
* The RS-232 console port is on SMC1
@@ -143,7 +151,7 @@
* environment so that we can autoscript the full default environment.
*/
#define CONFIG_ETHADDR 9a:52:63:15:85:25
-#define CONFIG_SERVERIP 10.0.4.200
+#define CONFIG_SERVERIP 10.0.4.201
#define CONFIG_IPADDR 10.0.4.111
/*
@@ -156,17 +164,20 @@
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */
#define CFG_ENV_EEPROM_SIZE (32 * 1024)
-#undef CONFIG_HARD_I2C
-#define CONFIG_SOFT_I2C
-
/*
- * Configure software I2C support (taken from IP860 BSP).
- * The I2C bus is connected to the GEN860T's 'dedicated' I2C
- * pins, i.e. PB26 and PB27
+ * Enable I2C and select the hardware/software driver
*/
+#define CONFIG_HARD_I2C 1 /* CPM based I2C */
+#undef CONFIG_SOFT_I2C /* Bit-banged I2C */
+
+#ifdef CONFIG_HARD_I2C
+#define CFG_I2C_SPEED 100000 /* clock speed in Hz */
+#define CFG_I2C_SLAVE 0xFE /* I2C slave address */
+#endif
+
+#ifdef CONFIG_SOFT_I2C
#define PB_SCL 0x00000020 /* PB 26 */
#define PB_SDA 0x00000010 /* PB 27 */
-
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
@@ -176,15 +187,14 @@
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-#define CFG_I2C_SPEED 100000 /* clock speed in Hz */
-#define CFG_I2C_SLAVE 0xFE /* I2C slave address */
+#endif
/*
* Allow environment overwrites by anyone
*/
#define CONFIG_ENV_OVERWRITE
+#if !defined(CONFIG_SC)
/*
* The MPC860's internal RTC is horribly broken in rev D masks. Three
* internal MPC860T circuit nodes were inadvertently left floating; this
@@ -193,35 +203,55 @@
* reasonable battery can keep that kind RTC running during powerdown for any
* length of time, so we use an external RTC on the I2C bus instead.
*/
-#undef CONFIG_RTC_MPC8xx
#define CONFIG_RTC_DS1337
-#define CFG_I2C_RTC_ADDR 0x68
+#define CFG_I2C_RTC_ADDR 0x68
+#else
/*
- * Allow partial commands to be matched to uniqueness.
+ * No external RTC on SC variant, so we're stuck with the internal one.
*/
-#define CFG_MATCH_PARTIAL_CMD
+#define CONFIG_RTC_MPC8xx
+#endif
+
+/*
+ * Power On Self Test support
+ */
+#define CONFIG_POST ( CFG_POST_CACHE | \
+ CFG_POST_MEMORY | \
+ CFG_POST_CPU | \
+ CFG_POST_UART | \
+ CFG_POST_SPR )
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+#else
+#define CFG_CMD_POST_DIAG 0
+#endif
/*
* List of available monitor commands. Use the system default list
* plus add some of the "non-standard" commands back in.
* See ./cmd_confdefs.h
*/
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+#define BASE_CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_DHCP | \
CFG_CMD_I2C | \
- CFG_CMD_DOC | \
CFG_CMD_EEPROM | \
CFG_CMD_REGINFO | \
CFG_CMD_IMMAP | \
CFG_CMD_ELF | \
CFG_CMD_DATE | \
- CFG_CMD_DATE | \
CFG_CMD_FPGA | \
CFG_CMD_MII | \
- CFG_CMD_BEDBUG \
- )
+ CFG_CMD_BEDBUG | \
+ CFG_CMD_POST_DIAG )
+
+#if !defined(CONFIG_SC)
+#define CONFIG_COMMANDS ( BASE_CONFIG_COMMANDS | CFG_CMD_DOC )
+#else
+#define CONFIG_COMMANDS BASE_CONFIG_COMMANDS
+#endif
/*
* There is no IDE/PCMCIA hardware support on the board.
@@ -258,7 +288,12 @@
* Verbose help from command monitor.
*/
#define CFG_LONGHELP
-#define CFG_PROMPT "gen860t> "
+#if !defined(CONFIG_SC)
+#define CFG_PROMPT "B2> "
+#else
+#define CFG_PROMPT "SC> "
+#endif
+
/*
* Use the "hush" command parser
@@ -393,15 +428,9 @@
/*
* Reserve memory for U-Boot.
*/
-#define CFG_MAX_U_BOOT_SECT 3
-
-#if defined(DEBUG)
-#define CFG_MONITOR_LEN (512 * 1024)
-#else
-#define CFG_MONITOR_LEN (256 * 1024)
-#endif
-
-#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MAX_UBOOT_SECTS 4
+#define CFG_MONITOR_LEN (CFG_MAX_UBOOT_SECTS * CFG_FLASH_SECT_SIZE)
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
/*
* Select environment placement. NOTE that u-boot.lds must
@@ -414,8 +443,14 @@
#define CFG_ENV_SIZE (2 * 1024)
#define CFG_ENV_OFFSET (CFG_ENV_EEPROM_SIZE - (8 * 1024))
#else
-#define CFG_ENV_SIZE (4 * 1024)
-#define CFG_ENV_OFFSET (CFG_MAX_U_BOOT_SECT * CFG_FLASH_SECT_SIZE)
+#define CFG_ENV_SIZE 0x1000
+#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SIZE
+
+/*
+ * This ultimately gets passed right into the linker script, so we have to
+ * use a number :(
+ */
+#define CFG_ENV_OFFSET 0x060000
#endif
/*
@@ -439,7 +474,7 @@
#endif
/*------------------------------------------------------------------------
- * SYPCR - System Protection Control UM 11-9
+ * SYPCR - System Protection Control UM 11-9
* -----------------------------------------------------------------------
* SYPCR can only be written once after reset!
*
@@ -523,6 +558,7 @@
*/
#define SCCR_MASK SCCR_EBDF11
+#if !defined(CONFIG_SC)
#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
SCCR_COM00 | /* full strength CLKOUT */ \
SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
@@ -530,6 +566,17 @@
SCCR_DFNL000 | \
SCCR_DFNH000 \
)
+#else
+#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
+ SCCR_COM00 | /* full strength CLKOUT */ \
+ SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
+ SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
+ SCCR_DFNL000 | \
+ SCCR_DFNH000 | \
+ SCCR_RTDIV | \
+ SCCR_RTSEL \
+ )
+#endif
/*-----------------------------------------------------------------------
* DER - Debug Enable Register UM 37-46
@@ -695,10 +742,12 @@
/*
* Disk On Chip (millenium) configuration
*/
+#if !defined(CONFIG_SC)
#define CFG_MAX_DOC_DEVICE 1
#undef CFG_DOC_SUPPORT_2000
#define CFG_DOC_SUPPORT_MILLENNIUM
#undef CFG_DOC_PASSIVE_PROBE
+#endif
/*
* FEC interrupt assignment
diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h
index 86281dd..1ea9a5e 100644
--- a/include/configs/TQM8260.h
+++ b/include/configs/TQM8260.h
@@ -203,11 +203,15 @@
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#ifndef CONFIG_300MHz
-#define CONFIG_8260_CLKIN 66666666 /* in Hz */
-#else
-#define CONFIG_8260_CLKIN 83333000 /* in Hz */
-#endif
+#ifdef CONFIG_MPC8255
+# define CONFIG_8260_CLKIN 66666666 /* in Hz */
+#else /* !CONFIG_MPC8255 */
+# ifndef CONFIG_300MHz
+# define CONFIG_8260_CLKIN 66666666 /* in Hz */
+# else
+# define CONFIG_8260_CLKIN 83333000 /* in Hz */
+# endif
+#endif /* CONFIG_MPC8255 */
#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
#define CONFIG_BAUDRATE 230400
@@ -311,15 +315,19 @@
* defines for the various registers affected by the HRCW e.g. changing
* HRCW_DPPCxx requires you to also change CFG_SIUMCR.
*/
-#if defined(CONFIG_266MHz)
-#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
- HRCW_MODCK_H0111)
-#elif defined(CONFIG_300MHz)
-#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
- HRCW_MODCK_H0110)
-#else
-#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
-#endif
+#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
+
+#ifdef CONFIG_MPC8255
+# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111)
+#else /* ! MPC8255 */
+# if defined(CONFIG_266MHz)
+# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111)
+# elif defined(CONFIG_300MHz)
+# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0110)
+# else
+# define CFG_HRCW_MASTER (__HRCW__ALL__)
+# endif
+#endif /* CONFIG_MPC8255 */
/* no slaves so just fill with zeros */
#define CFG_HRCW_SLAVE1 0
diff --git a/include/configs/atc.h b/include/configs/atc.h
new file mode 100644
index 0000000..ca6b740
--- /dev/null
+++ b/include/configs/atc.h
@@ -0,0 +1,442 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
+#define CONFIG_ATC 1 /* ...on a ATC board */
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#define CONFIG_CONS_ON_SMC /* define if console on SMC */
+#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
+#undef CONFIG_CONS_NONE /* define if console on something else*/
+#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
+
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ *
+ */
+#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
+#undef CONFIG_ETHER_NONE /* define if ether on something else */
+#define CONFIG_ETHER_ON_FCC
+
+#define CONFIG_NET_MULTI
+#define CONFIG_ETHER_ON_FCC2
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CFG_CPMFCR_RAMTYPE 0
+# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#define CONFIG_ETHER_ON_FCC3
+
+/*
+ * - Rx-CLK is CLK15
+ * - Tx-CLK is CLK16
+ * - RAM for BD/Buffers is on the local Bus (see 28-13)
+ * - Enable Half Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN 64000000 /* in Hz */
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */
+
+#define CONFIG_PREBOOT \
+ "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;"\
+ "echo"
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+ "bootp;" \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"\
+ "bootm"
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configuration options
+ */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_EEPROM)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */
+
+#define CFG_ALLOC_DPRAM
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_SPI
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Flash configuration
+ */
+
+#define CFG_BOOTROM_BASE 0xFF800000
+#define CFG_BOOTROM_SIZE 0x00080000
+#define CFG_FLASH_BASE 0xFF000000
+#define CFG_FLASH_SIZE 0x00800000
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
+
+#define CONFIG_FLASH_16BIT
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CFG_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ */
+#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
+ HRCW_BPS10 | HRCW_DPPC10 |\
+ HRCW_APPC10)
+
+/* no slaves so just fill with zeros */
+#define CFG_HRCW_SLAVE1 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ *
+ * 60x SDRAM is mapped at CFG_SDRAM_BASE.
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+# define CFG_RAMBOOT
+#endif
+
+#if 1
+/* environment is in Flash */
+#define CFG_ENV_IS_IN_FLASH 1
+# define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000)
+# define CFG_ENV_SIZE 0x10000
+# define CFG_ENV_SECT_SIZE 0x10000
+#else
+#define CFG_ENV_IS_IN_EEPROM 1
+#define CFG_ENV_OFFSET 0
+#define CFG_ENV_SIZE 2048
+#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
+#endif
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers 2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
+ HID0_DCI|HID0_IFEM|HID0_ABE)
+#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
+#define CFG_HID2 0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register 5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CFG_RMR RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration 4-25
+ *-----------------------------------------------------------------------
+ */
+#define BCR_APD01 0x10000000
+#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 4-31
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC10|SIUMCR_APPC10|\
+ SIUMCR_CS10PC00|SIUMCR_BCTLC10)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+ SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+ SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control 4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control 9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CFG_SCCR SCCR_DFBRG01
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration 13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR 0
+
+#define CFG_MIN_AM_MASK 0xC0000000
+/*-----------------------------------------------------------------------
+ * MPTPR - Memory Refresh Timer Prescaler Register 10-18
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MPTPR 0x1F00
+
+/*-----------------------------------------------------------------------
+ * PSRT - Refresh Timer Register 10-16
+ *-----------------------------------------------------------------------
+ */
+#define CFG_PSRT 0x0f
+
+/*-----------------------------------------------------------------------
+ * PSRT - SDRAM Mode Register 10-10
+ *-----------------------------------------------------------------------
+ */
+
+ /* SDRAM initialization values for 8-column chips
+ */
+#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
+ ORxS_BPD_4 |\
+ ORxS_ROWST_PBI0_A10 |\
+ ORxS_NUMR_11)
+
+#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
+ PSDMR_BSMA_A16_A18 |\
+ PSDMR_SDA10_PBI0_A10 |\
+ PSDMR_RFRC_7_CLK |\
+ PSDMR_PRETOACT_2W |\
+ PSDMR_ACTTORW_1W |\
+ PSDMR_LDOTOPRE_1C |\
+ PSDMR_WRC_1C |\
+ PSDMR_CL_2)
+
+ /* SDRAM initialization values for 9-column chips
+ */
+#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
+ ORxS_BPD_4 |\
+ ORxS_ROWST_PBI0_A7 |\
+ ORxS_NUMR_13)
+
+#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
+ PSDMR_BSMA_A13_A15 |\
+ PSDMR_SDA10_PBI0_A9 |\
+ PSDMR_RFRC_7_CLK |\
+ PSDMR_PRETOACT_2W |\
+ PSDMR_ACTTORW_1W |\
+ PSDMR_LDOTOPRE_1C |\
+ PSDMR_WRC_1C |\
+ PSDMR_CL_2)
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus Machine PortSz Device
+ * ---- --- ------- ------ ------
+ * 0 60x GPCM 8 bit Boot ROM
+ * 1 60x GPCM 64 bit FLASH
+ * 2 60x SDRAM 64 bit SDRAM
+ *
+ */
+
+#define CFG_MRS_OFFS 0x00000000
+
+/* Bank 0 - FLASH
+ */
+#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
+ BRx_PS_16 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
+
+#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
+ ORxG_CSNT |\
+ ORxG_ACS_DIV1 |\
+ ORxG_SCY_3_CLK |\
+ ORxU_EHTR_8IDLE)
+
+
+/* Bank 2 - 60x bus SDRAM
+ */
+#ifndef CFG_RAMBOOT
+#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
+ BRx_PS_64 |\
+ BRx_MS_SDRAM_P |\
+ BRx_V)
+
+#define CFG_OR2_PRELIM CFG_OR2_8COL
+
+#define CFG_PSDMR CFG_PSDMR_8COL
+#endif /* CFG_RAMBOOT */
+
+#endif /* __CONFIG_H */
diff --git a/include/status_led.h b/include/status_led.h
index 773573d..0d5a56e 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -97,20 +97,20 @@
# define STATUS_LED_DAT im_ioport.iop_padat
# define STATUS_LED_BIT 0x0800 /* Red LED 0 is on PA.4 */
-# define STATUS_LED_PERIOD (CFG_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
+# define STATUS_LED_PERIOD (CFG_HZ / 4)
+# define STATUS_LED_STATE STATUS_LED_OFF
# define STATUS_LED_BIT1 0x0400 /* Grn LED 1 is on PA.5 */
-# define STATUS_LED_PERIOD1 (CFG_HZ / 2)
+# define STATUS_LED_PERIOD1 (CFG_HZ / 8)
# define STATUS_LED_STATE1 STATUS_LED_BLINKING
# define STATUS_LED_BIT2 0x0080 /* Red LED 2 is on PA.8 */
-# define STATUS_LED_PERIOD2 (CFG_HZ / 2)
-# define STATUS_LED_STATE2 STATUS_LED_BLINKING
+# define STATUS_LED_PERIOD2 (CFG_HZ / 4)
+# define STATUS_LED_STATE2 STATUS_LED_OFF
# define STATUS_LED_BIT3 0x0040 /* Grn LED 3 is on PA.9 */
-# define STATUS_LED_PERIOD3 (CFG_HZ / 2)
-# define STATUS_LED_STATE3 STATUS_LED_BLINKING
+# define STATUS_LED_PERIOD3 (CFG_HZ / 4)
+# define STATUS_LED_STATE3 STATUS_LED_OFF
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-# define STATUS_LED_BOOT 0 /* Boot status on LED 1 */
+# define STATUS_LED_BOOT 1 /* Boot status on LED 1 */
/***** IVMS8 **********************************************************/
#elif defined(CONFIG_IVMS8)