74xx_7xx: CPCI750: Add CPCI adapter/target support
The CPCI750 can be built as CPCI host or adapter/target board. This patch
adds support for runtime detection of those variants.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
index 4ac1ff4..2ae4cbd 100644
--- a/board/esd/cpci750/cpci750.c
+++ b/board/esd/cpci750/cpci750.c
@@ -140,6 +140,15 @@
unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
int display_mem_map (void);
+/*
+ * Skip video initialization on slave variant.
+ * This function will overwrite the weak default in cfb_console.c
+ */
+int board_video_skip(void)
+{
+ return CPCI750_SLAVE_TEST;
+}
+
/* ------------------------------------------------------------------------- */
/*
diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c
index 9bdc523..638219f 100644
--- a/board/esd/cpci750/ide.c
+++ b/board/esd/cpci750/ide.c
@@ -39,6 +39,8 @@
int l;
status = 1;
+ if (CPCI750_SLAVE_TEST != 0)
+ return status;
for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
ide_bus_offset[l] = -ATA_STATUS;
}
@@ -57,7 +59,7 @@
ide_bus_offset[1] &= 0xfffffffe;
ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE;
}
- return (status);
+ return status;
}
void ide_set_reset (int flag) {
diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c
index 3b59b16..a2c1c50 100644
--- a/board/esd/cpci750/pci.c
+++ b/board/esd/cpci750/pci.c
@@ -795,7 +795,6 @@
PCI_DEV (dev), bus,
value);
}
-
return 0;
}
@@ -807,6 +806,9 @@
u32 bar_response, bar_value;
int bar;
+ if (CPCI750_SLAVE_TEST != 0)
+ return;
+
for (bar = 0; bar < 6; bar++) {
/*ronen different function for 3rd bank. */
unsigned int offset =
@@ -833,6 +835,9 @@
{
u32 bar_value, pci_response;
+ if (CPCI750_SLAVE_TEST != 0)
+ return;
+
pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response);
@@ -911,6 +916,7 @@
void pci_init_board (void)
{
unsigned int command;
+ unsigned int slave;
#ifdef CONFIG_PCI_PNP
unsigned int bar;
#endif
@@ -922,6 +928,8 @@
gt_cpcidvi_rom.base = 0;
#endif
+ slave = CPCI750_SLAVE_TEST;
+
pci0_hose.config_table = gt_config_table;
pci1_hose.config_table = gt_config_table;
@@ -957,27 +965,40 @@
pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
pci_register_hose (&pci0_hose);
- pciArbiterEnable (PCI_HOST0);
- pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
- command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MASTER;
- pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
- command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MEMORY;
- pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+ if (slave == 0) {
+ pciArbiterEnable (PCI_HOST0);
+ pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+ command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+ command |= PCI_COMMAND_MASTER;
+ pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+ command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+ command |= PCI_COMMAND_MEMORY;
+ pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
#ifdef CONFIG_PCI_PNP
- pciauto_config_init(&pci0_hose);
- pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
+ pciauto_config_init(&pci0_hose);
+ pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
#endif
#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
+ printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
- pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, pci0_hose.first_busno);
+ pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose,
+ pci0_hose.first_busno);
#ifdef DEBUG
- gt_pci_bus_mode_display (PCI_HOST1);
+ gt_pci_bus_mode_display (PCI_HOST1);
#endif
+ } else {
+ pciArbiterDisable (PCI_HOST0);
+ pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+ command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+ command |= PCI_COMMAND_MASTER;
+ pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+ command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+ command |= PCI_COMMAND_MEMORY;
+ pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+ pci0_hose.last_busno = pci0_hose.first_busno;
+ }
pci1_hose.first_busno = pci0_hose.last_busno + 1;
pci1_hose.last_busno = 0xff;
pci1_hose.current_busno = pci1_hose.first_busno;