// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 NXP
 * Copyright (C) 2023 Pengutronix, Marco Felsch <kernel@pengutronix.de>
 */

#include "imx8mp.dtsi"

/ {
	model = "Polyhex i.MX8MPlus Debix SOM A";
	compatible = "polyhex,imx8mp-debix-som-a", "fsl,imx8mp";

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};
};

&A53_0 {
	cpu-supply = <&buck2>;
};

&A53_1 {
	cpu-supply = <&buck2>;
};

&A53_2 {
	cpu-supply = <&buck2>;
};

&A53_3 {
	cpu-supply = <&buck2>;
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic@25 {
		compatible = "nxp,pca9450c";
		reg = <0x25>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio1>;
		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;

		regulators {
			buck1: BUCK1 {
				regulator-name = "BUCK1";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
			};

			buck2: BUCK2 {
				regulator-name = "BUCK2";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
				nxp,dvs-run-voltage = <950000>;
				nxp,dvs-standby-voltage = <850000>;
			};

			buck4: BUCK4 {
				regulator-name = "BUCK4";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck5: BUCK5 {
				regulator-name = "BUCK5";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck6: BUCK6 {
				regulator-name = "BUCK6";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1: LDO1 {
				regulator-name = "LDO1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo2: LDO2 {
				regulator-name = "LDO2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1150000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo3: LDO3 {
				regulator-name = "LDO3";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo4: LDO4 {
				regulator-name = "LDO4";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo5: LDO5 {
				regulator-name = "LDO5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};
};

&i2c4 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	status = "okay";

	adc@48 {
		 compatible = "ti,ads1115";
		 reg = <0x48>;
		 #address-cells = <1>;
		 #size-cells = <0>;

		 channel@4 {
			 reg = <4>;
			 ti,gain = <1>;
			 ti,datarate = <7>;
		 };

		 channel@5 {
			 reg = <5>;
			 ti,gain = <1>;
			 ti,datarate = <7>;
		 };

		 channel@6 {
			 reg = <6>;
			 ti,gain = <1>;
			 ti,datarate = <7>;
		 };

		 channel@7 {
			 reg = <7>;
			 ti,gain = <1>;
			 ti,datarate = <7>;
		 };
	 };
};

&snvs_pwrkey {
	status = "okay";
};

/* eMMC */
&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
	assigned-clock-rates = <400000000>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL			0x400001c2
			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA			0x400001c2
		>;
	};

	pinctrl_i2c4: i2c4grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL			0x400001c3
			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA			0x400001c3
		>;
	};

	pinctrl_pmic: pmicgrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x41
		>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x41
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6
		>;
	};
};