Squashed 'dts/upstream/' content from commit aaba2d45dc2a
git-subtree-dir: dts/upstream
git-subtree-split: aaba2d45dc2a1b3bbb710f2a3808ee1c9f340abe
diff --git a/src/riscv/allwinner/sun20i-d1s.dtsi b/src/riscv/allwinner/sun20i-d1s.dtsi
new file mode 100644
index 0000000..64c3c2e
--- /dev/null
+++ b/src/riscv/allwinner/sun20i-d1s.dtsi
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
+
+#define SOC_PERIPHERAL_IRQ(nr) (nr + 16)
+
+#include "sunxi-d1s-t113.dtsi"
+
+/ {
+ cpus {
+ timebase-frequency = <24000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "thead,c906", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&ccu CLK_RISCV>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <32768>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ operating-points-v2 = <&opp_table_cpu>;
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+ #cooling-cells = <2>;
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ opp_table_cpu: opp-table-cpu {
+ compatible = "operating-points-v2";
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <900000 900000 1100000>;
+ };
+
+ opp-1080000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <900000 900000 1100000>;
+ };
+ };
+
+ soc {
+ interrupt-parent = <&plic>;
+
+ riscv_wdt: watchdog@6011000 {
+ compatible = "allwinner,sun20i-d1-wdt";
+ reg = <0x6011000 0x20>;
+ interrupts = <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dcxo>, <&rtc CLK_OSC32K>;
+ clock-names = "hosc", "losc";
+ };
+
+ plic: interrupt-controller@10000000 {
+ compatible = "allwinner,sun20i-d1-plic",
+ "thead,c900-plic";
+ reg = <0x10000000 0x4000000>;
+ interrupts-extended = <&cpu0_intc 11>,
+ <&cpu0_intc 9>;
+ interrupt-controller;
+ riscv,ndev = <175>;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmu {
+ compatible = "riscv,pmu";
+ riscv,event-to-mhpmcounters =
+ <0x00003 0x00003 0x00000008>,
+ <0x00004 0x00004 0x00000010>,
+ <0x00005 0x00005 0x00000200>,
+ <0x00006 0x00006 0x00000100>,
+ <0x10000 0x10000 0x00004000>,
+ <0x10001 0x10001 0x00008000>,
+ <0x10002 0x10002 0x00010000>,
+ <0x10003 0x10003 0x00020000>,
+ <0x10019 0x10019 0x00000040>,
+ <0x10021 0x10021 0x00000020>;
+ riscv,event-to-mhpmevent =
+ <0x00003 0x00000000 0x00000001>,
+ <0x00004 0x00000000 0x00000002>,
+ <0x00005 0x00000000 0x00000007>,
+ <0x00006 0x00000000 0x00000006>,
+ <0x10000 0x00000000 0x0000000c>,
+ <0x10001 0x00000000 0x0000000d>,
+ <0x10002 0x00000000 0x0000000e>,
+ <0x10003 0x00000000 0x0000000f>,
+ <0x10019 0x00000000 0x00000004>,
+ <0x10021 0x00000000 0x00000003>;
+ riscv,raw-event-to-mhpmcounters =
+ <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
+ <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
+ <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
+ <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
+ <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
+ <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
+ <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
+ <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
+ <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
+ <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
+ <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
+ <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
+ };
+};