Squashed 'dts/upstream/' content from commit aaba2d45dc2a
git-subtree-dir: dts/upstream
git-subtree-split: aaba2d45dc2a1b3bbb710f2a3808ee1c9f340abe
diff --git a/Bindings/timer/sifive,clint.yaml b/Bindings/timer/sifive,clint.yaml
new file mode 100644
index 0000000..e8be6c4
--- /dev/null
+++ b/Bindings/timer/sifive,clint.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive Core Local Interruptor
+
+maintainers:
+ - Palmer Dabbelt <palmer@dabbelt.com>
+ - Anup Patel <anup.patel@wdc.com>
+
+description:
+ SiFive (and other RISC-V) SOCs include an implementation of the SiFive
+ Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
+ interrupts. It directly connects to the timer and inter-processor interrupt
+ lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
+ interrupt controller is the parent interrupt controller for CLINT device.
+ The clock frequency of CLINT is specified via "timebase-frequency" DT
+ property of "/cpus" DT node. The "timebase-frequency" DT property is
+ described in Documentation/devicetree/bindings/riscv/cpus.yaml
+
+ T-Head C906/C910 CPU cores include an implementation of CLINT too, however
+ their implementation lacks a memory-mapped MTIME register, thus not
+ compatible with SiFive ones.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - canaan,k210-clint # Canaan Kendryte K210
+ - sifive,fu540-c000-clint # SiFive FU540
+ - starfive,jh7100-clint # StarFive JH7100
+ - starfive,jh7110-clint # StarFive JH7110
+ - const: sifive,clint0 # SiFive CLINT v0 IP block
+ - items:
+ - enum:
+ - allwinner,sun20i-d1-clint
+ - sophgo,cv1800b-clint
+ - thead,th1520-clint
+ - const: thead,c900-clint
+ - items:
+ - const: sifive,clint0
+ - const: riscv,clint0
+ deprecated: true
+ description: For the QEMU virt machine only
+
+ description:
+ Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>"
+ when compatible with a SiFive CLINT. Please refer to
+ sifive-blocks-ip-versioning.txt for details regarding the latter.
+
+ reg:
+ maxItems: 1
+
+ interrupts-extended:
+ minItems: 1
+ maxItems: 4095
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts-extended
+
+examples:
+ - |
+ timer@2000000 {
+ compatible = "sifive,fu540-c000-clint", "sifive,clint0";
+ interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
+ <&cpu2intc 3>, <&cpu2intc 7>,
+ <&cpu3intc 3>, <&cpu3intc 7>,
+ <&cpu4intc 3>, <&cpu4intc 7>;
+ reg = <0x2000000 0x10000>;
+ };
+...