Squashed 'dts/upstream/' content from commit aaba2d45dc2a
git-subtree-dir: dts/upstream
git-subtree-split: aaba2d45dc2a1b3bbb710f2a3808ee1c9f340abe
diff --git a/Bindings/soc/socionext/socionext,uniphier-adamv.yaml b/Bindings/soc/socionext/socionext,uniphier-adamv.yaml
new file mode 100644
index 0000000..32d9cc2
--- /dev/null
+++ b/Bindings/soc/socionext/socionext,uniphier-adamv.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-adamv.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier ADAMV block
+
+maintainers:
+ - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+description: |+
+ ADAMV block implemented on Socionext UniPhier SoCs is an analog signal
+ amplifier that is a part of the external video and audio I/O system.
+
+ This block is defined for controlling audio I/O reset only.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - socionext,uniphier-ld11-adamv
+ - socionext,uniphier-ld20-adamv
+ - const: simple-mfd
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ reset-controller:
+ $ref: /schemas/reset/socionext,uniphier-reset.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@57920000 {
+ compatible = "socionext,uniphier-ld20-adamv",
+ "simple-mfd", "syscon";
+ reg = <0x57920000 0x1000>;
+
+ reset-controller {
+ compatible = "socionext,uniphier-ld20-adamv-reset";
+ #reset-cells = <1>;
+ };
+ };
diff --git a/Bindings/soc/socionext/socionext,uniphier-ahci-glue.yaml b/Bindings/soc/socionext/socionext,uniphier-ahci-glue.yaml
new file mode 100644
index 0000000..09f861c
--- /dev/null
+++ b/Bindings/soc/socionext/socionext,uniphier-ahci-glue.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-ahci-glue.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier SoC AHCI glue layer
+
+maintainers:
+ - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+description: |+
+ AHCI glue layer implemented on Socionext UniPhier SoCs is a sideband
+ logic handling signals to AHCI host controller inside AHCI component.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - socionext,uniphier-pro4-ahci-glue
+ - socionext,uniphier-pxs2-ahci-glue
+ - socionext,uniphier-pxs3-ahci-glue
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+patternProperties:
+ "^reset-controller@[0-9a-f]+$":
+ $ref: /schemas/reset/socionext,uniphier-glue-reset.yaml#
+
+ "phy@[0-9a-f]+$":
+ $ref: /schemas/phy/socionext,uniphier-ahci-phy.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ sata-controller@65700000 {
+ compatible = "socionext,uniphier-pxs3-ahci-glue", "simple-mfd";
+ reg = <0x65b00000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65700000 0x100>;
+
+ reset-controller@0 {
+ compatible = "socionext,uniphier-pxs3-ahci-reset";
+ reg = <0x0 0x4>;
+ clock-names = "link";
+ clocks = <&sys_clk 28>;
+ reset-names = "link";
+ resets = <&sys_rst 28>;
+ #reset-cells = <1>;
+ };
+
+ phy@10 {
+ compatible = "socionext,uniphier-pxs3-ahci-phy";
+ reg = <0x10 0x10>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 28>, <&sys_clk 30>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 28>, <&sys_rst 30>;
+ #phy-cells = <0>;
+ };
+ };
diff --git a/Bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml b/Bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
new file mode 100644
index 0000000..bd0def7
--- /dev/null
+++ b/Bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
+
+maintainers:
+ - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+description: |+
+ DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
+ a sideband logic handling signals to DWC3 host controller inside
+ USB3.0 component.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - socionext,uniphier-pro4-dwc3-glue
+ - socionext,uniphier-pro5-dwc3-glue
+ - socionext,uniphier-pxs2-dwc3-glue
+ - socionext,uniphier-ld20-dwc3-glue
+ - socionext,uniphier-pxs3-dwc3-glue
+ - socionext,uniphier-nx1-dwc3-glue
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+patternProperties:
+ "^reset-controller@[0-9a-f]+$":
+ $ref: /schemas/reset/socionext,uniphier-glue-reset.yaml#
+
+ "^regulator@[0-9a-f]+$":
+ $ref: /schemas/regulator/socionext,uniphier-regulator.yaml#
+
+ "^phy@[0-9a-f]+$":
+ oneOf:
+ - $ref: /schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
+ - $ref: /schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ usb@65b00000 {
+ compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
+ reg = <0x65b00000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65b00000 0x400>;
+
+ reset-controller@0 {
+ compatible = "socionext,uniphier-ld20-usb3-reset";
+ reg = <0x0 0x4>;
+ #reset-cells = <1>;
+ clock-names = "link";
+ clocks = <&sys_clk 14>;
+ reset-names = "link";
+ resets = <&sys_rst 14>;
+ };
+
+ regulator@100 {
+ compatible = "socionext,uniphier-ld20-usb3-regulator";
+ reg = <0x100 0x10>;
+ clock-names = "link";
+ clocks = <&sys_clk 14>;
+ reset-names = "link";
+ resets = <&sys_rst 14>;
+ };
+
+ phy@200 {
+ compatible = "socionext,uniphier-ld20-usb3-hsphy";
+ reg = <0x200 0x10>;
+ #phy-cells = <0>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 14>, <&sys_clk 16>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 14>, <&sys_rst 16>;
+ };
+
+ phy@300 {
+ compatible = "socionext,uniphier-ld20-usb3-ssphy";
+ reg = <0x300 0x10>;
+ #phy-cells = <0>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 14>, <&sys_clk 18>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 14>, <&sys_rst 18>;
+ };
+ };
+
diff --git a/Bindings/soc/socionext/socionext,uniphier-mioctrl.yaml b/Bindings/soc/socionext/socionext,uniphier-mioctrl.yaml
new file mode 100644
index 0000000..2cc38bb
--- /dev/null
+++ b/Bindings/soc/socionext/socionext,uniphier-mioctrl.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-mioctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier media I/O block (MIO) controller
+
+maintainers:
+ - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+description: |+
+ Media I/O block implemented on Socionext UniPhier SoCs is a legacy
+ integrated component of the stream type peripherals including USB2.0,
+ SD/eMMC, and MIO-DMAC.
+ Media I/O block has a common logic to control the component.
+
+ Recent SoCs have SD interface logic specialized only for SD functions
+ as a subset of media I/O block. See socionext,uniphier-sdctrl.yaml.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - socionext,uniphier-ld4-mioctrl
+ - socionext,uniphier-pro4-mioctrl
+ - socionext,uniphier-sld8-mioctrl
+ - socionext,uniphier-ld11-mioctrl
+ - const: simple-mfd
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ clock-controller:
+ $ref: /schemas/clock/socionext,uniphier-clock.yaml#
+
+ reset-controller:
+ $ref: /schemas/reset/socionext,uniphier-reset.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@5b3e0000 {
+ compatible = "socionext,uniphier-ld11-mioctrl",
+ "simple-mfd", "syscon";
+ reg = <0x5b3e0000 0x800>;
+
+ clock-controller {
+ compatible = "socionext,uniphier-ld11-mio-clock";
+ #clock-cells = <1>;
+ };
+
+ reset-controller {
+ compatible = "socionext,uniphier-ld11-mio-reset";
+ #reset-cells = <1>;
+ resets = <&sys_rst 7>;
+ };
+ };
+
diff --git a/Bindings/soc/socionext/socionext,uniphier-perictrl.yaml b/Bindings/soc/socionext/socionext,uniphier-perictrl.yaml
new file mode 100644
index 0000000..0adcffe
--- /dev/null
+++ b/Bindings/soc/socionext/socionext,uniphier-perictrl.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-perictrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier peripheral block controller
+
+maintainers:
+ - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+description: |+
+ Peripheral block implemented on Socionext UniPhier SoCs is an integrated
+ component of the peripherals including UART, I2C/FI2C, and SCSSI.
+ Peripheral block controller is a logic to control the component.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - socionext,uniphier-ld4-perictrl
+ - socionext,uniphier-pro4-perictrl
+ - socionext,uniphier-pro5-perictrl
+ - socionext,uniphier-pxs2-perictrl
+ - socionext,uniphier-sld8-perictrl
+ - socionext,uniphier-ld11-perictrl
+ - socionext,uniphier-ld20-perictrl
+ - socionext,uniphier-pxs3-perictrl
+ - socionext,uniphier-nx1-perictrl
+ - const: simple-mfd
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ clock-controller:
+ $ref: /schemas/clock/socionext,uniphier-clock.yaml#
+
+ reset-controller:
+ $ref: /schemas/reset/socionext,uniphier-reset.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@59820000 {
+ compatible = "socionext,uniphier-ld20-perictrl",
+ "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ clock-controller {
+ compatible = "socionext,uniphier-ld20-peri-clock";
+ #clock-cells = <1>;
+ };
+
+ reset-controller {
+ compatible = "socionext,uniphier-ld20-peri-reset";
+ #reset-cells = <1>;
+ };
+ };
diff --git a/Bindings/soc/socionext/socionext,uniphier-sdctrl.yaml b/Bindings/soc/socionext/socionext,uniphier-sdctrl.yaml
new file mode 100644
index 0000000..cb3b0d4
--- /dev/null
+++ b/Bindings/soc/socionext/socionext,uniphier-sdctrl.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-sdctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier SD interface logic
+
+maintainers:
+ - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+description: |+
+ SD interface logic implemented on Socionext UniPhier SoCs is
+ attached outside SDHC, and has some SD related functions such as
+ clock control, reset control, mode switch, and so on.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - socionext,uniphier-pro5-sdctrl
+ - socionext,uniphier-pxs2-sdctrl
+ - socionext,uniphier-ld11-sdctrl
+ - socionext,uniphier-ld20-sdctrl
+ - socionext,uniphier-pxs3-sdctrl
+ - socionext,uniphier-nx1-sdctrl
+ - const: simple-mfd
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ clock-controller:
+ $ref: /schemas/clock/socionext,uniphier-clock.yaml#
+
+ reset-controller:
+ $ref: /schemas/reset/socionext,uniphier-reset.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@59810000 {
+ compatible = "socionext,uniphier-ld20-sdctrl",
+ "simple-mfd", "syscon";
+ reg = <0x59810000 0x400>;
+
+ clock-controller {
+ compatible = "socionext,uniphier-ld20-sd-clock";
+ #clock-cells = <1>;
+ };
+
+ reset-controller {
+ compatible = "socionext,uniphier-ld20-sd-reset";
+ #reset-cells = <1>;
+ };
+ };
diff --git a/Bindings/soc/socionext/socionext,uniphier-soc-glue-debug.yaml b/Bindings/soc/socionext/socionext,uniphier-soc-glue-debug.yaml
new file mode 100644
index 0000000..1341544
--- /dev/null
+++ b/Bindings/soc/socionext/socionext,uniphier-soc-glue-debug.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue-debug.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier SoC-glue logic debug part
+
+maintainers:
+ - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+description: |+
+ SoC-glue logic debug part implemented on Socionext UniPhier SoCs is
+ a collection of miscellaneous function registers handling signals outside
+ system components for debug and monitor use.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - socionext,uniphier-ld4-soc-glue-debug
+ - socionext,uniphier-pro4-soc-glue-debug
+ - socionext,uniphier-pro5-soc-glue-debug
+ - socionext,uniphier-pxs2-soc-glue-debug
+ - socionext,uniphier-sld8-soc-glue-debug
+ - socionext,uniphier-ld11-soc-glue-debug
+ - socionext,uniphier-ld20-soc-glue-debug
+ - socionext,uniphier-pxs3-soc-glue-debug
+ - socionext,uniphier-nx1-soc-glue-debug
+ - const: simple-mfd
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+patternProperties:
+ "^efuse@[0-9a-f]+$":
+ $ref: /schemas/nvmem/socionext,uniphier-efuse.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@5f900000 {
+ compatible = "socionext,uniphier-pxs2-soc-glue-debug",
+ "simple-mfd", "syscon";
+ reg = <0x5f900000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5f900000 0x2000>;
+
+ efuse@100 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x100 0x28>;
+ };
+ };
diff --git a/Bindings/soc/socionext/socionext,uniphier-soc-glue.yaml b/Bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
new file mode 100644
index 0000000..7845dcf
--- /dev/null
+++ b/Bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier SoC-glue logic
+
+maintainers:
+ - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+description: |+
+ SoC-glue logic implemented on Socionext UniPhier SoCs is a collection of
+ miscellaneous function registers handling signals outside system components.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - socionext,uniphier-ld4-soc-glue
+ - socionext,uniphier-pro4-soc-glue
+ - socionext,uniphier-pro5-soc-glue
+ - socionext,uniphier-pxs2-soc-glue
+ - socionext,uniphier-sld8-soc-glue
+ - socionext,uniphier-ld11-soc-glue
+ - socionext,uniphier-ld20-soc-glue
+ - socionext,uniphier-pxs3-soc-glue
+ - socionext,uniphier-nx1-soc-glue
+ - const: simple-mfd
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ pinctrl:
+ $ref: /schemas/pinctrl/socionext,uniphier-pinctrl.yaml#
+
+ usb-hub:
+ $ref: /schemas/phy/socionext,uniphier-usb2-phy.yaml#
+
+ clock-controller:
+ $ref: /schemas/clock/socionext,uniphier-clock.yaml#
+
+allOf:
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - socionext,uniphier-pro4-soc-glue
+ - socionext,uniphier-ld11-soc-glue
+ then:
+ properties:
+ usb-hub: false
+
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: socionext,uniphier-pro4-soc-glue
+ then:
+ properties:
+ clock-controller: false
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@5f800000 {
+ compatible = "socionext,uniphier-pro4-soc-glue",
+ "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+
+ pinctrl {
+ compatible = "socionext,uniphier-pro4-pinctrl";
+ };
+
+ usb-hub {
+ compatible = "socionext,uniphier-pro4-usb2-phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+ };
+
+ clock-controller {
+ compatible = "socionext,uniphier-pro4-sg-clock";
+ #clock-cells = <1>;
+ };
+ };
diff --git a/Bindings/soc/socionext/socionext,uniphier-sysctrl.yaml b/Bindings/soc/socionext/socionext,uniphier-sysctrl.yaml
new file mode 100644
index 0000000..3acb142
--- /dev/null
+++ b/Bindings/soc/socionext/socionext,uniphier-sysctrl.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-sysctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier system controller
+
+maintainers:
+ - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+description: |+
+ System controller implemented on Socionext UniPhier SoCs has multiple
+ functions such as clock control, reset control, internal watchdog timer,
+ thermal management, and so on.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - socionext,uniphier-ld4-sysctrl
+ - socionext,uniphier-pro4-sysctrl
+ - socionext,uniphier-pro5-sysctrl
+ - socionext,uniphier-pxs2-sysctrl
+ - socionext,uniphier-sld8-sysctrl
+ - socionext,uniphier-ld11-sysctrl
+ - socionext,uniphier-ld20-sysctrl
+ - socionext,uniphier-pxs3-sysctrl
+ - socionext,uniphier-nx1-sysctrl
+ - const: simple-mfd
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ clock-controller:
+ $ref: /schemas/clock/socionext,uniphier-clock.yaml#
+
+ reset-controller:
+ $ref: /schemas/reset/socionext,uniphier-reset.yaml#
+
+ watchdog:
+ $ref: /schemas/watchdog/socionext,uniphier-wdt.yaml#
+
+ thermal-sensor:
+ $ref: /schemas/thermal/socionext,uniphier-thermal.yaml#
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: socionext,uniphier-ld4-sysctrl
+ then:
+ properties:
+ watchdog: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - socionext,uniphier-ld4-sysctrl
+ - socionext,uniphier-pro4-sysctrl
+ - socionext,uniphier-sld8-sysctrl
+ - socionext,uniphier-ld11-sysctrl
+ then:
+ properties:
+ thermal-sensor: false
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ syscon@61840000 {
+ compatible = "socionext,uniphier-ld20-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x4000>;
+
+ clock-controller {
+ compatible = "socionext,uniphier-ld20-clock";
+ #clock-cells = <1>;
+ };
+
+ reset-controller {
+ compatible = "socionext,uniphier-ld20-reset";
+ #reset-cells = <1>;
+ };
+
+ watchdog {
+ compatible = "socionext,uniphier-wdt";
+ };
+
+ thermal-sensor {
+ compatible = "socionext,uniphier-ld20-thermal";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ #thermal-sensor-cells = <0>;
+ };
+ };