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diff --git a/Bindings/soc/qcom/qcom,aoss-qmp.yaml b/Bindings/soc/qcom/qcom,aoss-qmp.yaml
new file mode 100644
index 0000000..d1c7c2b
--- /dev/null
+++ b/Bindings/soc/qcom/qcom,aoss-qmp.yaml
@@ -0,0 +1,111 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,aoss-qmp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Always-On Subsystem side channel
+
+maintainers:
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description:
+ This binding describes the hardware component responsible for side channel
+ requests to the always-on subsystem (AOSS), used for certain power management
+ requests that is not handled by the standard RPMh interface. Each client in the
+ SoC has its own block of message RAM and IRQ for communication with the AOSS.
+ The protocol used to communicate in the message RAM is known as Qualcomm
+ Messaging Protocol (QMP)
+
+ The AOSS side channel exposes control over a set of resources, used to control
+ a set of debug related clocks and to affect the low power state of resources
+ related to the secondary subsystems.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,qdu1000-aoss-qmp
+ - qcom,sa8775p-aoss-qmp
+ - qcom,sc7180-aoss-qmp
+ - qcom,sc7280-aoss-qmp
+ - qcom,sc8180x-aoss-qmp
+ - qcom,sc8280xp-aoss-qmp
+ - qcom,sdm845-aoss-qmp
+ - qcom,sm6350-aoss-qmp
+ - qcom,sm8150-aoss-qmp
+ - qcom,sm8250-aoss-qmp
+ - qcom,sm8350-aoss-qmp
+ - qcom,sm8450-aoss-qmp
+ - qcom,sm8550-aoss-qmp
+ - const: qcom,aoss-qmp
+
+ reg:
+ maxItems: 1
+ description:
+ The base address and size of the message RAM for this client's
+ communication with the AOSS
+
+ interrupts:
+ maxItems: 1
+ description:
+ Should specify the AOSS message IRQ for this client
+
+ mboxes:
+ maxItems: 1
+ description:
+ Reference to the mailbox representing the outgoing doorbell in APCS for
+ this client, as described in mailbox/mailbox.txt
+
+ "#clock-cells":
+ const: 0
+ description:
+ The single clock represents the QDSS clock.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - mboxes
+ - "#clock-cells"
+
+additionalProperties: false
+
+patternProperties:
+ "^(cx|mx|ebi)$":
+ type: object
+ description:
+ The AOSS side channel also provides the controls for three cooling devices,
+ these are expressed as subnodes of the QMP node. The name of the node is
+ used to identify the resource and must therefore be "cx", "mx" or "ebi".
+
+ properties:
+ "#cooling-cells":
+ const: 2
+
+ required:
+ - "#cooling-cells"
+
+ additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ aoss_qmp: qmp@c300000 {
+ compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
+ reg = <0x0c300000 0x100000>;
+ interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apss_shared 0>;
+
+ #clock-cells = <0>;
+
+ cx_cdev: cx {
+ #cooling-cells = <2>;
+ };
+
+ mx_cdev: mx {
+ #cooling-cells = <2>;
+ };
+ };
+...
diff --git a/Bindings/soc/qcom/qcom,apr-services.yaml b/Bindings/soc/qcom/qcom,apr-services.yaml
new file mode 100644
index 0000000..bdf482d
--- /dev/null
+++ b/Bindings/soc/qcom/qcom,apr-services.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,apr-services.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm APR/GPR services shared parts
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description:
+ Common parts of a static service in Qualcomm APR/GPR (Asynchronous/Generic
+ Packet Router).
+
+properties:
+ reg:
+ minimum: 1
+ maximum: 13
+ description: |
+ APR Service ID
+ 3 = DSP Core Service
+ 4 = Audio Front End Service.
+ 5 = Voice Stream Manager Service.
+ 6 = Voice processing manager.
+ 7 = Audio Stream Manager Service.
+ 8 = Audio Device Manager Service.
+ 9 = Multimode voice manager.
+ 10 = Core voice stream.
+ 11 = Core voice processor.
+ 12 = Ultrasound stream manager.
+ 13 = Listen stream manager.
+ GPR Service ID
+ 1 = Audio Process Manager Service
+ 2 = Proxy Resource Manager Service.
+ 3 = AMDB Service.
+ 4 = Voice processing manager.
+
+ qcom,protection-domain:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description: |
+ Protection domain service name and path for APR service (if supported).
+ Possible values are::
+ "avs/audio", "msm/adsp/audio_pd".
+ "kernel/elf_loader", "msm/modem/wlan_pd".
+ "tms/servreg", "msm/adsp/audio_pd".
+ "tms/servreg", "msm/modem/wlan_pd".
+ "tms/servreg", "msm/slpi/sensor_pd".
+
+required:
+ - reg
+
+additionalProperties: true
diff --git a/Bindings/soc/qcom/qcom,apr.yaml b/Bindings/soc/qcom/qcom,apr.yaml
new file mode 100644
index 0000000..e51acdc
--- /dev/null
+++ b/Bindings/soc/qcom/qcom,apr.yaml
@@ -0,0 +1,211 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,apr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm APR/GPR (Asynchronous/Generic Packet Router)
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+ This binding describes the Qualcomm APR/GPR, APR/GPR is a IPC protocol for
+ communication between Application processor and QDSP. APR/GPR is mainly
+ used for audio/voice services on the QDSP.
+
+properties:
+ compatible:
+ enum:
+ - qcom,apr
+ - qcom,apr-v2
+ - qcom,gpr
+
+ power-domains:
+ maxItems: 1
+
+ qcom,apr-domain:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 3, 4, 5, 6, 7]
+ description:
+ Selects the processor domain for apr
+ 1 = APR simulator
+ 2 = PC Domain
+ 3 = Modem Domain
+ 4 = ADSP Domain
+ 5 = Application processor Domain
+ 6 = Modem2 Domain
+ 7 = Application Processor2 Domain
+ deprecated: true
+
+ qcom,domain:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 7
+ description:
+ Selects the processor domain for apr
+ 1 = APR simulator
+ 2 = PC Domain
+ 3 = Modem Domain
+ 4 = ADSP Domain
+ 5 = Application processor Domain
+ 6 = Modem2 Domain
+ 7 = Application Processor2 Domain
+ Selects the processor domain for gpr
+ 1 = Modem Domain
+ 2 = Audio DSP Domain
+ 3 = Application Processor Domain
+
+ qcom,glink-channels:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description: Channel name used for the communication
+ maxItems: 1
+
+ qcom,intents:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ minItems: 1
+ maxItems: 32
+ items:
+ items:
+ - description: size of each intent to preallocate
+ - description: amount of intents to preallocate
+ minimum: 1
+ description:
+ List of (size, amount) pairs describing what intents should be
+ preallocated for this virtual channel. This can be used to tweak the
+ default intents available for the channel to meet expectations of the
+ remote.
+
+ qcom,smd-channels:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description: Channel name used for the communication
+ items:
+ - const: apr_audio_svc
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+patternProperties:
+ "^service@[1-9a-d]$":
+ type: object
+ $ref: /schemas/soc/qcom/qcom,apr-services.yaml
+ additionalProperties: true
+ description:
+ APR/GPR static port services.
+
+ properties:
+ compatible:
+ enum:
+ - qcom,q6core
+ - qcom,q6asm
+ - qcom,q6afe
+ - qcom,q6adm
+ - qcom,q6apm
+ - qcom,q6prm
+
+required:
+ - compatible
+ - qcom,domain
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,gpr
+ then:
+ properties:
+ qcom,glink-channels:
+ items:
+ - const: adsp_apps
+ power-domains: false
+ else:
+ properties:
+ qcom,glink-channels:
+ items:
+ - const: apr_audio_svc
+
+ - if:
+ required:
+ - qcom,glink-channels
+ then:
+ properties:
+ qcom,smd-channels: false
+
+ - if:
+ required:
+ - qcom,smd-channels
+ then:
+ properties:
+ qcom,glink-channels: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/soc/qcom,apr.h>
+ apr {
+ compatible = "qcom,apr-v2";
+ qcom,domain = <APR_DOMAIN_ADSP>;
+ qcom,glink-channels = "apr_audio_svc";
+ qcom,intents = <512 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ q6core: service@3 {
+ compatible = "qcom,q6core";
+ reg = <APR_SVC_ADSP_CORE>;
+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+ };
+
+ service@4 {
+ compatible = "qcom,q6afe";
+ reg = <APR_SVC_AFE>;
+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+
+ clock-controller {
+ compatible = "qcom,q6afe-clocks";
+ #clock-cells = <2>;
+ };
+
+ dais {
+ compatible = "qcom,q6afe-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ /* ... */
+ };
+ /* ... */
+ };
+ };
+
+ - |
+ #include <dt-bindings/soc/qcom,gpr.h>
+ gpr {
+ compatible = "qcom,gpr";
+ qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+ qcom,glink-channels = "adsp_apps";
+ qcom,intents = <512 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ service@1 {
+ compatible = "qcom,q6apm";
+ reg = <GPR_APM_MODULE_IID>;
+ #sound-dai-cells = <0>;
+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+
+ dais {
+ compatible = "qcom,q6apm-dais";
+ iommus = <&apps_smmu 0x1801 0x0>;
+ };
+
+ bedais {
+ compatible = "qcom,q6apm-lpass-dais";
+ #sound-dai-cells = <1>;
+ };
+ };
+ };
diff --git a/Bindings/soc/qcom/qcom,dcc.yaml b/Bindings/soc/qcom/qcom,dcc.yaml
new file mode 100644
index 0000000..ce7e20d
--- /dev/null
+++ b/Bindings/soc/qcom/qcom,dcc.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,dcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Data Capture and Compare
+
+maintainers:
+ - Souradeep Chowdhury <quic_schowdhu@quicinc.com>
+
+description: |
+ DCC (Data Capture and Compare) is a DMA engine which is used to save
+ configuration data or system memory contents during catastrophic failure
+ or SW trigger. DCC is used to capture and store data for debugging purpose
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,sm8150-dcc
+ - qcom,sc7280-dcc
+ - qcom,sc7180-dcc
+ - qcom,sdm845-dcc
+ - const: qcom,dcc
+
+ reg:
+ items:
+ - description: DCC base
+ - description: DCC RAM base
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ dma@10a2000{
+ compatible = "qcom,sm8150-dcc", "qcom,dcc";
+ reg = <0x010a2000 0x1000>,
+ <0x010ad000 0x2000>;
+ };
diff --git a/Bindings/soc/qcom/qcom,eud.yaml b/Bindings/soc/qcom/qcom,eud.yaml
new file mode 100644
index 0000000..f2c5ec7
--- /dev/null
+++ b/Bindings/soc/qcom/qcom,eud.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,eud.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Embedded USB Debugger
+
+maintainers:
+ - Souradeep Chowdhury <quic_schowdhu@quicinc.com>
+
+description:
+ This binding is used to describe the Qualcomm Embedded USB Debugger, which is
+ mini USB-hub implemented on chip to support USB-based debug capabilities.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,sc7280-eud
+ - const: qcom,eud
+
+ reg:
+ items:
+ - description: EUD Base Register Region
+ - description: EUD Mode Manager Register
+
+ interrupts:
+ description: EUD interrupt
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ description:
+ These ports is to be attached to the endpoint of the DWC3 controller node
+ and type C connector node. The controller has the "usb-role-switch"
+ property.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: This port is to be attached to the DWC3 controller.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: This port is to be attached to the type C connector.
+
+required:
+ - compatible
+ - reg
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ eud@88e0000 {
+ compatible = "qcom,sc7280-eud", "qcom,eud";
+ reg = <0x88e0000 0x2000>,
+ <0x88e2000 0x1000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ eud_ep: endpoint {
+ remote-endpoint = <&usb2_role_switch>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ eud_con: endpoint {
+ remote-endpoint = <&con_eud>;
+ };
+ };
+ };
+ };
diff --git a/Bindings/soc/qcom/qcom,geni-se.yaml b/Bindings/soc/qcom/qcom,geni-se.yaml
new file mode 100644
index 0000000..7b031ef
--- /dev/null
+++ b/Bindings/soc/qcom/qcom,geni-se.yaml
@@ -0,0 +1,165 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: GENI Serial Engine QUP Wrapper Controller
+
+maintainers:
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description: |
+ Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
+ is a programmable module for supporting a wide range of serial interfaces
+ like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
+ Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
+ Wrapper controller is modeled as a node with zero or more child nodes each
+ representing a serial engine.
+
+properties:
+ compatible:
+ enum:
+ - qcom,geni-se-qup
+ - qcom,geni-se-i2c-master-hub
+
+ reg:
+ description: QUP wrapper common register address and length.
+ maxItems: 1
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ ranges: true
+
+ interconnects:
+ maxItems: 1
+
+ interconnect-names:
+ const: qup-core
+
+ iommus:
+ maxItems: 1
+
+ dma-coherent: true
+
+required:
+ - compatible
+ - reg
+ - clock-names
+ - clocks
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+patternProperties:
+ "spi@[0-9a-f]+$":
+ type: object
+ description: GENI serial engine based SPI controller. SPI in master mode
+ supports up to 50MHz, up to four chip selects, programmable
+ data path from 4 bits to 32 bits and numerous protocol
+ variants.
+ $ref: /schemas/spi/qcom,spi-geni-qcom.yaml#
+
+ "i2c@[0-9a-f]+$":
+ type: object
+ description: GENI serial engine based I2C controller.
+ $ref: /schemas/i2c/qcom,i2c-geni-qcom.yaml#
+
+ "serial@[0-9a-f]+$":
+ type: object
+ description: GENI Serial Engine based UART Controller.
+ $ref: /schemas/serial/qcom,serial-geni-qcom.yaml#
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,geni-se-i2c-master-hub
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: s-ahb
+
+ clocks:
+ items:
+ - description: Slave AHB Clock
+
+ iommus: false
+
+ patternProperties:
+ "spi@[0-9a-f]+$": false
+ "serial@[0-9a-f]+$": false
+ else:
+ properties:
+ clock-names:
+ items:
+ - const: m-ahb
+ - const: s-ahb
+
+ clocks:
+ items:
+ - description: Master AHB Clock
+ - description: Slave AHB Clock
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ geniqup@8c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0 0x008c0000 0 0x6000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ i2c0: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0xa94000 0 0x4000>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_1_i2c_5_active>;
+ pinctrl-1 = <&qup_1_i2c_5_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ uart0: serial@a88000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0xa88000 0 0x7000>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_1_uart_3_active>;
+ pinctrl-1 = <&qup_1_uart_3_sleep>;
+ };
+ };
+ };
+
+...
diff --git a/Bindings/soc/qcom/qcom,gsbi.yaml b/Bindings/soc/qcom/qcom,gsbi.yaml
new file mode 100644
index 0000000..c337043
--- /dev/null
+++ b/Bindings/soc/qcom/qcom,gsbi.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,gsbi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm General Serial Bus Interface (GSBI)
+
+maintainers:
+ - Andy Gross <agross@kernel.org>
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+description:
+ The GSBI controller is modeled as a node with zero or more child nodes, each
+ representing a serial sub-node device that is mux'd as part of the GSBI
+ configuration settings. The mode setting will govern the input/output mode
+ of the 4 GSBI IOs.
+
+ A GSBI controller node can contain 0 or more child nodes representing serial
+ devices. These serial devices can be a QCOM UART, I2C controller, spi
+ controller, or some combination of aforementioned devices.
+
+properties:
+ compatible:
+ const: qcom,gsbi-v1.0.0
+
+ '#address-cells':
+ const: 1
+
+ cell-index:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The GSBI index.
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: iface
+
+ qcom,crci:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ CRCI MUX value for QUP CRCI ports. Please reference
+ include/dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
+
+ qcom,mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ MUX value for configuration of the serial interface. Please reference
+ include/dt-bindings/soc/qcom,gsbi.h for valid mux values.
+
+ '#size-cells':
+ const: 1
+
+ syscon-tcsr:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle of TCSR syscon node.Required if child uses dma.
+
+ ranges: true
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ "spi@[0-9a-f]+$":
+ type: object
+ $ref: /schemas/spi/qcom,spi-qup.yaml#
+
+ "i2c@[0-9a-f]+$":
+ type: object
+ $ref: /schemas/i2c/qcom,i2c-qup.yaml#
+
+ "serial@[0-9a-f]+$":
+ type: object
+ $ref: /schemas/serial/qcom,msm-uartdm.yaml#
+
+required:
+ - compatible
+ - cell-index
+ - clocks
+ - clock-names
+ - qcom,mode
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-msm8960.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/soc/qcom,gsbi.h>
+
+ gsbi@12440000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ reg = <0x12440000 0x100>;
+ cell-index = <1>;
+ clocks = <&gcc GSBI1_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ syscon-tcsr = <&tcsr>;
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+
+ serial@12450000 {
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+ reg = <0x12450000 0x100>,
+ <0x12400000 0x03>;
+ interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
+ clock-names = "core", "iface";
+ };
+
+ i2c@12460000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x12460000 0x1000>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-1 = <&i2c1_pins_sleep>;
+ pinctrl-names = "default", "sleep";
+ interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled"; /* UART chosen */
+ };
+ };
diff --git a/Bindings/soc/qcom/qcom,msm8976-ramp-controller.yaml b/Bindings/soc/qcom/qcom,msm8976-ramp-controller.yaml
new file mode 100644
index 0000000..aae9cf7
--- /dev/null
+++ b/Bindings/soc/qcom/qcom,msm8976-ramp-controller.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,msm8976-ramp-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Ramp Controller
+
+maintainers:
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+
+description:
+ The Ramp Controller is used to program the sequence ID for pulse
+ swallowing, enable sequences and link Sequence IDs (SIDs) for the
+ CPU cores on some Qualcomm SoCs.
+
+properties:
+ compatible:
+ enum:
+ - qcom,msm8976-ramp-controller
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ cpu-power-controller@b014000 {
+ compatible = "qcom,msm8976-ramp-controller";
+ reg = <0x0b014000 0x68>;
+ };
diff --git a/Bindings/soc/qcom/qcom,pmic-glink.yaml b/Bindings/soc/qcom/qcom,pmic-glink.yaml
new file mode 100644
index 0000000..422921c
--- /dev/null
+++ b/Bindings/soc/qcom/qcom,pmic-glink.yaml
@@ -0,0 +1,110 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,pmic-glink.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm PMIC GLINK firmware interface for battery management, USB
+ Type-C and other things.
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+
+description:
+ The PMIC GLINK service, running on a coprocessor on some modern Qualcomm
+ platforms and implement USB Type-C handling and battery management. This
+ binding describes the component in the OS used to communicate with the
+ firmware and connect it's resources to those described in the Devicetree,
+ particularly the USB Type-C controllers relationship with USB and DisplayPort
+ components.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,sc8180x-pmic-glink
+ - qcom,sc8280xp-pmic-glink
+ - qcom,sm8350-pmic-glink
+ - qcom,sm8450-pmic-glink
+ - qcom,sm8550-pmic-glink
+ - const: qcom,pmic-glink
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ orientation-gpios:
+ description: Array of input gpios for the Type-C connector orientation indication.
+ The GPIO indication is used to detect the orientation of the Type-C connector.
+ The array should contain a gpio entry for each PMIC Glink connector, in reg order.
+ It is defined that GPIO active level means "CC2" or Reversed/Flipped orientation.
+
+patternProperties:
+ '^connector@\d$':
+ $ref: /schemas/connector/usb-connector.yaml#
+ required:
+ - reg
+
+required:
+ - compatible
+
+allOf:
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8450-pmic-glink
+ - qcom,sm8550-pmic-glink
+ then:
+ properties:
+ orientation-gpios: false
+
+additionalProperties: false
+
+examples:
+ - |+
+ pmic-glink {
+ compatible = "qcom,sc8280xp-pmic-glink", "qcom,pmic-glink";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ endpoint {
+ remote-endpoint = <&usb_role>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ endpoint {
+ remote-endpoint = <&ss_phy_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ endpoint {
+ remote-endpoint = <&sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+...
+
diff --git a/Bindings/soc/qcom/qcom,rpm-master-stats.yaml b/Bindings/soc/qcom/qcom,rpm-master-stats.yaml
new file mode 100644
index 0000000..0318009
--- /dev/null
+++ b/Bindings/soc/qcom/qcom,rpm-master-stats.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,rpm-master-stats.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. (QTI) RPM Master Stats
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@linaro.org>
+
+description: |
+ The Qualcomm RPM (Resource Power Manager) architecture includes a concept
+ of "RPM Masters". They can be thought of as "the local gang leaders", usually
+ spanning a single subsystem (e.g. APSS, ADSP, CDSP). All of the RPM decisions
+ (particularly around entering hardware-driven low power modes: XO shutdown
+ and total system-wide power collapse) are first made at Master-level, and
+ only then aggregated for the entire system.
+
+ The Master Stats provide a few useful bits that can be used to assess whether
+ our device has entered the desired low-power mode, how long it took to do so,
+ the duration of that residence, how long it took to come back online,
+ how many times a given sleep state was entered and which cores are actively
+ voting for staying awake.
+
+ This scheme has been used on various SoCs in the 2013-2023 era, with some
+ newer or higher-end designs providing this information through an SMEM query.
+
+properties:
+ compatible:
+ const: qcom,rpm-master-stats
+
+ qcom,rpm-msg-ram:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: Phandle to an RPM MSG RAM slice containing the master stats
+ minItems: 1
+ maxItems: 5
+
+ qcom,master-names:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description:
+ The name of the RPM Master which owns the MSG RAM slice where this
+ instance of Master Stats resides
+ minItems: 1
+ maxItems: 5
+
+required:
+ - compatible
+ - qcom,rpm-msg-ram
+ - qcom,master-names
+
+additionalProperties: false
+
+examples:
+ - |
+ stats {
+ compatible = "qcom,rpm-master-stats";
+ qcom,rpm-msg-ram = <&apss_master_stats>,
+ <&mpss_master_stats>,
+ <&adsp_master_stats>,
+ <&cdsp_master_stats>,
+ <&tz_master_stats>;
+ qcom,master-names = "APSS",
+ "MPSS",
+ "ADSP",
+ "CDSP",
+ "TZ";
+ };
+...
diff --git a/Bindings/soc/qcom/qcom,rpm.yaml b/Bindings/soc/qcom/qcom,rpm.yaml
new file mode 100644
index 0000000..b00be9e
--- /dev/null
+++ b/Bindings/soc/qcom/qcom,rpm.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,rpm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Resource Power Manager (RPM)
+
+description:
+ This driver is used to interface with the Resource Power Manager (RPM) found
+ in various Qualcomm platforms. The RPM allows each component in the system
+ to vote for state of the system resources, such as clocks, regulators and bus
+ frequencies.
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - qcom,rpm-apq8064
+ - qcom,rpm-msm8660
+ - qcom,rpm-msm8960
+ - qcom,rpm-ipq8064
+ - qcom,rpm-mdm9615
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 3
+
+ interrupt-names:
+ items:
+ - const: ack
+ - const: err
+ - const: wakeup
+
+ qcom,ipc:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to a syscon node representing the APCS registers
+ - description: u32 representing offset to the register within the syscon
+ - description: u32 representing the ipc bit within the register
+ description:
+ Three entries specifying the outgoing ipc bit used for signaling the RPM.
+
+patternProperties:
+ "^regulators(-[01])?$":
+ type: object
+ $ref: /schemas/regulator/qcom,rpm-regulator.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - qcom,ipc
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/mfd/qcom-rpm.h>
+
+ rpm@108000 {
+ compatible = "qcom,rpm-msm8960";
+ reg = <0x108000 0x1000>;
+ qcom,ipc = <&apcs 0x8 2>;
+
+ interrupts = <GIC_SPI 19 IRQ_TYPE_NONE>, <GIC_SPI 21 IRQ_TYPE_NONE>, <GIC_SPI 22 IRQ_TYPE_NONE>;
+ interrupt-names = "ack", "err", "wakeup";
+
+ regulators {
+ compatible = "qcom,rpm-pm8921-regulators";
+ vdd_l1_l2_l12_l18-supply = <&pm8921_s4>;
+
+ s1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+
+ bias-pull-down;
+
+ qcom,switch-mode-frequency = <3200000>;
+ };
+
+ pm8921_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+
+ qcom,force-mode = <QCOM_RPM_FORCE_MODE_AUTO>;
+ };
+ };
+ };
diff --git a/Bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Bindings/soc/qcom/qcom,rpmh-rsc.yaml
new file mode 100644
index 0000000..af632d0
--- /dev/null
+++ b/Bindings/soc/qcom/qcom,rpmh-rsc.yaml
@@ -0,0 +1,269 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm RPMH RSC
+
+maintainers:
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description: |
+ Resource Power Manager Hardened (RPMH) is the mechanism for communicating
+ with the hardened resource accelerators on Qualcomm SoCs. Requests to the
+ resources can be written to the Trigger Command Set (TCS) registers and
+ using a (addr, val) pair and triggered. Messages in the TCS are then sent in
+ sequence over an internal bus.
+
+ The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
+ (Resource State Coordinator a.k.a RSC) that can handle multiple sleep and
+ active/wake resource requests. Multiple such DRVs can exist in a SoC and can
+ be written to from Linux. The structure of each DRV follows the same template
+ with a few variations that are captured by the properties here.
+
+ A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
+ have powered off to facilitate idle power saving. TCS could be classified as::
+ ACTIVE - Triggered by Linux
+ SLEEP - Triggered by F/W
+ WAKE - Triggered by F/W
+ CONTROL - Triggered by F/W
+ See also:: <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+ The order in which they are described in the DT, should match the hardware
+ configuration.
+
+ Requests can be made for the state of a resource, when the subsystem is
+ active or idle. When all subsystems like Modem, GPU, CPU are idle, the
+ resource state will be an aggregate of the sleep votes from each of those
+ subsystems. Clients may request a sleep value for their shared resources in
+ addition to the active mode requests.
+
+ Drivers that want to use the RSC to communicate with RPMH must specify their
+ bindings as child nodes of the RSC controllers they wish to communicate with.
+
+properties:
+ compatible:
+ const: qcom,rpmh-rsc
+
+ interrupts:
+ minItems: 1
+ maxItems: 4
+ description:
+ The interrupt that trips when a message complete/response is received for
+ this DRV from the accelerators.
+ Number of interrupts must match number of DRV blocks.
+
+ label:
+ description:
+ Name for the RSC. The name would be used in trace logs.
+
+ qcom,drv-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The ID of the DRV in the RSC block that will be used by this controller.
+
+ qcom,tcs-config:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ minItems: 4
+ maxItems: 4
+ items:
+ items:
+ - description: |
+ TCS type::
+ - ACTIVE_TCS
+ - SLEEP_TCS
+ - WAKE_TCS
+ - CONTROL_TCS
+ enum: [ 0, 1, 2, 3 ]
+ - description: Number of TCS
+ description: |
+ The tuple defining the configuration of TCS. Must have two cells which
+ describe each TCS type. The order of the TCS must match the hardware
+ configuration.
+
+ qcom,tcs-offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The offset of the TCS blocks.
+
+ reg:
+ minItems: 1
+ maxItems: 4
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: drv-0
+ - const: drv-1
+ - const: drv-2
+ - const: drv-3
+
+ power-domains:
+ maxItems: 1
+
+ bcm-voter:
+ $ref: /schemas/interconnect/qcom,bcm-voter.yaml#
+
+ clock-controller:
+ $ref: /schemas/clock/qcom,rpmhcc.yaml#
+
+ power-controller:
+ $ref: /schemas/power/qcom,rpmpd.yaml#
+
+patternProperties:
+ '^regulators(-[0-9])?$':
+ $ref: /schemas/regulator/qcom,rpmh-regulator.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - interrupts
+ - qcom,drv-id
+ - qcom,tcs-config
+ - qcom,tcs-offset
+ - reg
+ - reg-names
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
+ // 2, the register offsets for DRV2 start at 0D00, the register
+ // calculations are like this::
+ // DRV0: 0x179C0000
+ // DRV2: 0x179C0000 + 0x10000 = 0x179D0000
+ // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
+ // TCS-OFFSET: 0xD00
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+ rsc@179c0000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x179c0000 0x10000>,
+ <0x179d0000 0x10000>,
+ <0x179e0000 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ label = "apps_rsc";
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>,
+ <SLEEP_TCS 3>,
+ <WAKE_TCS 3>,
+ <CONTROL_TCS 1>;
+ power-domains = <&CLUSTER_PD>;
+ };
+
+ - |
+ // For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the
+ // register offsets for DRV0 start at 01C00, the register calculations are
+ // like this::
+ // DRV0: 0xAF20000
+ // TCS-OFFSET: 0x1C00
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+ rsc@af20000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0xaf20000 0x10000>;
+ reg-names = "drv-0";
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ label = "disp_rsc";
+ qcom,tcs-offset = <0x1c00>;
+ qcom,drv-id = <0>;
+ qcom,tcs-config = <ACTIVE_TCS 0>,
+ <SLEEP_TCS 1>,
+ <WAKE_TCS 1>,
+ <CONTROL_TCS 0>;
+ power-domains = <&CLUSTER_PD>;
+ };
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/soc/qcom,rpmh-rsc.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ rsc@18200000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x18200000 0x10000>,
+ <0x18210000 0x10000>,
+ <0x18220000 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ label = "apps_rsc";
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>,
+ <SLEEP_TCS 3>,
+ <WAKE_TCS 3>,
+ <CONTROL_TCS 0>;
+ power-domains = <&CLUSTER_PD>;
+
+ clock-controller {
+ compatible = "qcom,sm8350-rpmh-clk";
+ #clock-cells = <1>;
+ clock-names = "xo";
+ clocks = <&xo_board>;
+ };
+
+ power-controller {
+ compatible = "qcom,sm8350-rpmhpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp1 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_min_svs: opp2 {
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+
+ rpmhpd_opp_low_svs: opp3 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_svs: opp4 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l1: opp5 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_nom: opp6 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp7 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_nom_l2: opp8 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
+
+ rpmhpd_opp_turbo: opp9 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp10 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+ };
+ };
+
+ bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+ };
diff --git a/Bindings/soc/qcom/qcom,smd-rpm.yaml b/Bindings/soc/qcom/qcom,smd-rpm.yaml
new file mode 100644
index 0000000..2fa725b
--- /dev/null
+++ b/Bindings/soc/qcom/qcom,smd-rpm.yaml
@@ -0,0 +1,160 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,smd-rpm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Resource Power Manager (RPM) over SMD/GLINK
+
+description: |
+ This driver is used to interface with the Resource Power Manager (RPM) found
+ in various Qualcomm platforms. The RPM allows each component in the system
+ to vote for state of the system resources, such as clocks, regulators and bus
+ frequencies.
+
+ The SMD or GLINK information for the RPM edge should be filled out. See
+ qcom,smd.yaml for the required edge properties. All SMD/GLINK related
+ properties will reside within the RPM node itself.
+
+ The RPM exposes resources to its subnodes. The rpm_requests node must be
+ present and this subnode may contain children that designate regulator
+ resources.
+
+ Refer to Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml
+ for information on the regulator subnodes that can exist under the
+ rpm_requests.
+
+maintainers:
+ - Andy Gross <agross@kernel.org>
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+properties:
+ compatible:
+ enum:
+ - qcom,rpm-apq8084
+ - qcom,rpm-ipq6018
+ - qcom,rpm-ipq9574
+ - qcom,rpm-mdm9607
+ - qcom,rpm-msm8226
+ - qcom,rpm-msm8610
+ - qcom,rpm-msm8909
+ - qcom,rpm-msm8916
+ - qcom,rpm-msm8917
+ - qcom,rpm-msm8936
+ - qcom,rpm-msm8937
+ - qcom,rpm-msm8952
+ - qcom,rpm-msm8953
+ - qcom,rpm-msm8974
+ - qcom,rpm-msm8976
+ - qcom,rpm-msm8994
+ - qcom,rpm-msm8996
+ - qcom,rpm-msm8998
+ - qcom,rpm-qcm2290
+ - qcom,rpm-qcs404
+ - qcom,rpm-sdm660
+ - qcom,rpm-sm6115
+ - qcom,rpm-sm6125
+ - qcom,rpm-sm6375
+
+ clock-controller:
+ $ref: /schemas/clock/qcom,rpmcc.yaml#
+ unevaluatedProperties: false
+
+ power-controller:
+ $ref: /schemas/power/qcom,rpmpd.yaml#
+
+ qcom,glink-channels:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description: Channel name used for the RPM communication
+ items:
+ - const: rpm_requests
+
+ qcom,smd-channels:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description: Channel name used for the RPM communication
+ items:
+ - const: rpm_requests
+
+patternProperties:
+ "^regulators(-[01])?$":
+ $ref: /schemas/regulator/qcom,smd-rpm-regulator.yaml#
+ unevaluatedProperties: false
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,rpm-apq8084
+ - qcom,rpm-mdm9607
+ - qcom,rpm-msm8226
+ - qcom,rpm-msm8610
+ - qcom,rpm-msm8909
+ - qcom,rpm-msm8916
+ - qcom,rpm-msm8917
+ - qcom,rpm-msm8936
+ - qcom,rpm-msm8937
+ - qcom,rpm-msm8952
+ - qcom,rpm-msm8953
+ - qcom,rpm-msm8974
+ - qcom,rpm-msm8976
+ - qcom,rpm-msm8994
+then:
+ properties:
+ qcom,glink-channels: false
+ required:
+ - qcom,smd-channels
+else:
+ properties:
+ qcom,smd-channels: false
+ required:
+ - qcom,glink-channels
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ remoteproc {
+ compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc";
+
+ smd-edge {
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs 8 0>;
+ qcom,smd-edge = <15>;
+
+ rpm-requests {
+ compatible = "qcom,rpm-msm8916";
+ qcom,smd-channels = "rpm_requests";
+
+ clock-controller {
+ compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
+ #clock-cells = <1>;
+ clocks = <&xo_board>;
+ clock-names = "xo";
+ };
+
+ power-controller {
+ compatible = "qcom,msm8916-rpmpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmpd_opp_table>;
+
+ rpmpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-1 {
+ opp-level = <1>;
+ };
+ opp-2 {
+ opp-level = <2>;
+ };
+ };
+ };
+ };
+ };
+ };
diff --git a/Bindings/soc/qcom/qcom,smd.yaml b/Bindings/soc/qcom/qcom,smd.yaml
new file mode 100644
index 0000000..4819ce9
--- /dev/null
+++ b/Bindings/soc/qcom/qcom,smd.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,smd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Shared Memory Driver
+
+maintainers:
+ - Andy Gross <agross@kernel.org>
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+description:
+ The Qualcomm Shared Memory Driver is a FIFO based communication channel for
+ sending data between the various subsystems in Qualcomm platforms.
+
+ Using the top-level SMD node is deprecated. Instead, the SMD edges are defined
+ directly below the device node representing the respective remote subsystem
+ or remote processor.
+
+deprecated: true
+
+properties:
+ compatible:
+ const: qcom,smd
+
+patternProperties:
+ "^smd-edge|rpm$":
+ $ref: /schemas/remoteproc/qcom,smd-edge.yaml#
+ unevaluatedProperties: false
+ description:
+ Each subnode of the SMD node represents a remote subsystem or a remote
+ processor of some sort - or in SMD language an "edge". The name of the
+ edges are not important.
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ # The following example represents a smd node, with one edge representing the
+ # "rpm" subsystem. For the "rpm" subsystem we have a device tied to the
+ # "rpm_request" channel.
+ # NOTE: This is deprecated, represent the RPM using "qcom,rpm-proc" instead.
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ shared-memory {
+ compatible = "qcom,smd";
+
+ rpm {
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs 8 0>;
+ qcom,smd-edge = <15>;
+
+ rpm-requests {
+ compatible = "qcom,rpm-msm8974";
+ qcom,smd-channels = "rpm_requests";
+
+ clock-controller {
+ compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
+ #clock-cells = <1>;
+ };
+
+ };
+ };
+ };
diff --git a/Bindings/soc/qcom/qcom,smem.yaml b/Bindings/soc/qcom/qcom,smem.yaml
new file mode 100644
index 0000000..bc7815d
--- /dev/null
+++ b/Bindings/soc/qcom/qcom,smem.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,smem.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Shared Memory Manager
+
+maintainers:
+ - Andy Gross <agross@kernel.org>
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description:
+ This binding describes the Qualcomm Shared Memory Manager, a region of
+ reserved-memory used to share data between various subsystems and OSes in
+ Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,smem
+
+ reg:
+ maxItems: 1
+
+ memory-region:
+ maxItems: 1
+ description: handle to memory reservation for main SMEM memory region.
+
+ hwlocks:
+ maxItems: 1
+
+ qcom,rpm-msg-ram:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: handle to RPM message memory resource
+
+ no-map: true
+
+required:
+ - compatible
+ - hwlocks
+
+oneOf:
+ - required:
+ - reg
+ - no-map
+ - required:
+ - memory-region
+
+additionalProperties: false
+
+examples:
+ - |
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ smem@fa00000 {
+ compatible = "qcom,smem";
+ reg = <0xfa00000 0x200000>;
+ no-map;
+
+ hwlocks = <&tcsr_mutex 3>;
+ };
+ };
+ - |
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ smem_region: smem@fa00000 {
+ reg = <0xfa00000 0x200000>;
+ no-map;
+ };
+ };
+
+ smem {
+ compatible = "qcom,smem";
+
+ memory-region = <&smem_region>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ rpm_msg_ram: sram@fc428000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0xfc428000 0x4000>;
+ };
+ };
+
+...
diff --git a/Bindings/soc/qcom/qcom,smp2p.yaml b/Bindings/soc/qcom/qcom,smp2p.yaml
new file mode 100644
index 0000000..5850052
--- /dev/null
+++ b/Bindings/soc/qcom/qcom,smp2p.yaml
@@ -0,0 +1,145 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,smp2p.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Shared Memory Point 2 Point
+
+maintainers:
+ - Andy Gross <agross@kernel.org>
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+description:
+ The Shared Memory Point to Point (SMP2P) protocol facilitates communication
+ of a single 32-bit value between two processors. Each value has a single
+ writer (the local side) and a single reader (the remote side). Values are
+ uniquely identified in the system by the directed edge (local processor ID to
+ remote processor ID) and a string identifier.
+
+properties:
+ compatible:
+ const: qcom,smp2p
+
+ interrupts:
+ maxItems: 1
+
+ mboxes:
+ maxItems: 1
+ description:
+ Reference to the mailbox representing the outgoing doorbell in APCS for
+ this client.
+
+ qcom,ipc:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to a syscon node representing the APCS registers
+ - description: u32 representing offset to the register within the syscon
+ - description: u32 representing the ipc bit within the register
+ description:
+ Three entries specifying the outgoing ipc bit used for signaling the
+ remote end of the smp2p edge.
+
+ qcom,local-pid:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The identifier of the local endpoint of this edge.
+
+ qcom,remote-pid:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The identifier of the remote endpoint of this edge.
+
+ qcom,smem:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ maxItems: 2
+ description:
+ Two identifiers of the inbound and outbound smem items used for this edge.
+
+patternProperties:
+ "^master-kernel|slave-kernel|ipa-ap-to-modem|ipa-modem-to-ap|wlan-ap-to-wpss|wlan-wpss-to-ap$":
+ type: object
+ description:
+ Each SMP2P pair contain a set of inbound and outbound entries, these are
+ described in subnodes of the smp2p device node. The node names are not
+ important.
+
+ properties:
+ interrupt-controller:
+ description:
+ Marks the entry as inbound; the node should be specified as a two
+ cell interrupt-controller. If not specified this node will denote
+ the outgoing entry.
+
+ '#interrupt-cells':
+ const: 2
+
+ qcom,entry-name:
+ $ref: /schemas/types.yaml#/definitions/string
+ description:
+ The name of this entry, for inbound entries this will be used to
+ match against the remotely allocated entry and for outbound entries
+ this name is used for allocating entries.
+
+ '#qcom,smem-state-cells':
+ $ref: /schemas/types.yaml#/definitions/uint32
+ const: 1
+ description:
+ Required for outgoing entries.
+
+ required:
+ - qcom,entry-name
+
+ oneOf:
+ - required:
+ - interrupt-controller
+ - '#interrupt-cells'
+ - required:
+ - '#qcom,smem-state-cells'
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - interrupts
+ - qcom,local-pid
+ - qcom,remote-pid
+ - qcom,smem
+
+oneOf:
+ - required:
+ - mboxes
+ - required:
+ - qcom,ipc
+
+additionalProperties: false
+
+examples:
+ # The following example shows the SMP2P setup with the wireless processor,
+ # defined from the 8974 apps processor's point-of-view. It encompasses one
+ # inbound and one outbound entry.
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ shared-memory {
+ compatible = "qcom,smp2p";
+ qcom,smem = <431>, <451>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs 8 18>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <4>;
+
+ wcnss_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ wcnss_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
diff --git a/Bindings/soc/qcom/qcom,smsm.yaml b/Bindings/soc/qcom/qcom,smsm.yaml
new file mode 100644
index 0000000..db67cf0
--- /dev/null
+++ b/Bindings/soc/qcom/qcom,smsm.yaml
@@ -0,0 +1,138 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,smsm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Shared Memory State Machine
+
+maintainers:
+ - Andy Gross <agross@kernel.org>
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+description:
+ The Shared Memory State Machine facilitates broadcasting of single bit state
+ information between the processors in a Qualcomm SoC. Each processor is
+ assigned 32 bits of state that can be modified. A processor can through a
+ matrix of bitmaps signal subscription of notifications upon changes to a
+ certain bit owned by a certain remote processor.
+
+properties:
+ compatible:
+ const: qcom,smsm
+
+ '#address-cells':
+ const: 1
+
+ qcom,local-host:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+ description:
+ Identifier of the local processor in the list of hosts, or in other words
+ specifier of the column in the subscription matrix representing the local
+ processor.
+
+ '#size-cells':
+ const: 0
+
+patternProperties:
+ "^qcom,ipc-[1-4]$":
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to a syscon node representing the APCS registers
+ - description: u32 representing offset to the register within the syscon
+ - description: u32 representing the ipc bit within the register
+ description:
+ Three entries specifying the outgoing ipc bit used for signaling the N:th
+ remote processor.
+
+ "@[0-9a-f]$":
+ type: object
+ description:
+ Each processor's state bits are described by a subnode of the SMSM device
+ node. Nodes can either be flagged as an interrupt-controller to denote a
+ remote processor's state bits or the local processors bits. The node
+ names are not important.
+
+ properties:
+ reg:
+ maxItems: 1
+
+ interrupt-controller:
+ description:
+ Marks the entry as a interrupt-controller and the state bits to
+ belong to a remote processor.
+
+ '#interrupt-cells':
+ const: 2
+
+ interrupts:
+ maxItems: 1
+ description:
+ One entry specifying remote IRQ used by the remote processor to
+ signal changes of its state bits.
+
+ '#qcom,smem-state-cells':
+ $ref: /schemas/types.yaml#/definitions/uint32
+ const: 1
+ description:
+ Required for local entry. Denotes bit number.
+
+ required:
+ - reg
+
+ oneOf:
+ - required:
+ - '#qcom,smem-state-cells'
+ - required:
+ - interrupt-controller
+ - '#interrupt-cells'
+ - interrupts
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - '#address-cells'
+ - '#size-cells'
+
+anyOf:
+ - required:
+ - qcom,ipc-1
+ - required:
+ - qcom,ipc-2
+ - required:
+ - qcom,ipc-3
+ - required:
+ - qcom,ipc-4
+
+additionalProperties: false
+
+examples:
+ # The following example shows the SMEM setup for controlling properties of
+ # the wireless processor, defined from the 8974 apps processor's
+ # point-of-view. It encompasses one outbound entry and the outgoing interrupt
+ # for the wireless processor.
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ shared-memory {
+ compatible = "qcom,smsm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,ipc-3 = <&apcs 8 19>;
+
+ apps_smsm: apps@0 {
+ reg = <0>;
+ #qcom,smem-state-cells = <1>;
+ };
+
+ wcnss_smsm: wcnss@7 {
+ reg = <7>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
diff --git a/Bindings/soc/qcom/qcom,spm.yaml b/Bindings/soc/qcom/qcom,spm.yaml
new file mode 100644
index 0000000..20c8cd3
--- /dev/null
+++ b/Bindings/soc/qcom/qcom,spm.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,spm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Subsystem Power Manager
+
+maintainers:
+ - Andy Gross <agross@kernel.org>
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description: |
+ This binding describes the Qualcomm Subsystem Power Manager, used to control
+ the peripheral logic surrounding the application cores in Qualcomm platforms.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,sdm660-gold-saw2-v4.1-l2
+ - qcom,sdm660-silver-saw2-v4.1-l2
+ - qcom,msm8998-gold-saw2-v4.1-l2
+ - qcom,msm8998-silver-saw2-v4.1-l2
+ - qcom,msm8909-saw2-v3.0-cpu
+ - qcom,msm8916-saw2-v3.0-cpu
+ - qcom,msm8939-saw2-v3.0-cpu
+ - qcom,msm8226-saw2-v2.1-cpu
+ - qcom,msm8974-saw2-v2.1-cpu
+ - qcom,msm8976-gold-saw2-v2.3-l2
+ - qcom,msm8976-silver-saw2-v2.3-l2
+ - qcom,apq8084-saw2-v2.1-cpu
+ - qcom,apq8064-saw2-v1.1-cpu
+ - const: qcom,saw2
+
+ reg:
+ description: Base address and size of the SPM register region
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+
+ /* Example 1: SoC using SAW2 and kpss-acc-v2 CPUIdle */
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "qcom,kryo";
+ device_type = "cpu";
+ enable-method = "qcom,kpss-acc-v2";
+ qcom,saw = <&saw0>;
+ reg = <0x0>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+ };
+
+ saw0: power-manager@f9089000 {
+ compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
+ reg = <0xf9089000 0x1000>;
+ };
+
+ - |
+
+ /*
+ * Example 2: New-gen multi cluster SoC using SAW only for L2;
+ * This does not require any cpuidle driver, nor any cpu phandle.
+ */
+ power-manager@17812000 {
+ compatible = "qcom,msm8998-gold-saw2-v4.1-l2", "qcom,saw2";
+ reg = <0x17812000 0x1000>;
+ };
+
+ power-manager@17912000 {
+ compatible = "qcom,msm8998-silver-saw2-v4.1-l2", "qcom,saw2";
+ reg = <0x17912000 0x1000>;
+ };
+
+...
diff --git a/Bindings/soc/qcom/qcom,wcnss.yaml b/Bindings/soc/qcom/qcom,wcnss.yaml
new file mode 100644
index 0000000..74bb92e
--- /dev/null
+++ b/Bindings/soc/qcom/qcom,wcnss.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,wcnss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm WCNSS
+
+maintainers:
+ - Andy Gross <agross@kernel.org>
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description:
+ The Qualcomm WCNSS hardware consists of control block and a BT, WiFi and FM
+ radio block, all using SMD as command channels.
+
+properties:
+ compatible:
+ const: qcom,wcnss
+
+ firmware-name:
+ $ref: /schemas/types.yaml#/definitions/string
+ default: wlan/prima/WCNSS_qcom_wlan_nv.bin
+ description:
+ Relative firmware image path for the WLAN NV blob.
+
+ qcom,mmio:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ Reference to a node specifying the wcnss "ccu" and "dxe" register blocks.
+ The node must be compatible with one of the following::
+ - qcom,riva"
+ - qcom,pronto"
+
+ qcom,smd-channels:
+ $ref: /schemas/types.yaml#/definitions/string
+ const: WCNSS_CTRL
+ description:
+ Standard SMD property specifying the SMD channel used for communication
+ with the WiFi firmware.
+
+ bluetooth:
+ type: object
+ additionalProperties: false
+ allOf:
+ - $ref: /schemas/net/bluetooth/bluetooth-controller.yaml#
+ properties:
+ compatible:
+ const: qcom,wcnss-bt
+
+ local-bd-address: true
+
+ required:
+ - compatible
+
+ wifi:
+ additionalProperties: false
+ type: object
+ properties:
+ compatible:
+ const: qcom,wcnss-wlan
+
+ interrupts:
+ maxItems: 2
+
+ interrupt-names:
+ items:
+ - const: tx
+ - const: rx
+
+ qcom,smem-states:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 2
+ description:
+ Should reference the tx-enable and tx-rings-empty SMEM states.
+
+ qcom,smem-state-names:
+ items:
+ - const: tx-enable
+ - const: tx-rings-empty
+ description:
+ Names of SMEM states.
+
+ required:
+ - compatible
+ - interrupts
+ - interrupt-names
+ - qcom,smem-states
+ - qcom,smem-state-names
+
+required:
+ - compatible
+ - qcom,mmio
+ - qcom,smd-channels
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ smd-edge {
+ interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 8 17>;
+ qcom,smd-edge = <6>;
+ qcom,remote-pid = <4>;
+
+ label = "pronto";
+
+ wcnss {
+ compatible = "qcom,wcnss";
+ qcom,smd-channels = "WCNSS_CTRL";
+
+ qcom,mmio = <&pronto>;
+
+ bluetooth {
+ compatible = "qcom,wcnss-bt";
+ /* BD address 00:11:22:33:44:55 */
+ local-bd-address = [ 55 44 33 22 11 00 ];
+ };
+
+ wifi {
+ compatible = "qcom,wcnss-wlan";
+
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
+ qcom,smem-state-names = "tx-enable", "tx-rings-empty";
+ };
+ };
+ };
diff --git a/Bindings/soc/qcom/qcom-stats.yaml b/Bindings/soc/qcom/qcom-stats.yaml
new file mode 100644
index 0000000..96a7f18
--- /dev/null
+++ b/Bindings/soc/qcom/qcom-stats.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom-stats.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. (QTI) Stats
+
+maintainers:
+ - Maulik Shah <quic_mkshah@quicinc.com>
+
+description:
+ Always On Processor/Resource Power Manager maintains statistics of the SoC
+ sleep modes involving powering down of the rails and oscillator clock.
+
+ Statistics includes SoC sleep mode type, number of times low power mode were
+ entered, time of last entry, time of last exit and accumulated sleep duration.
+
+properties:
+ compatible:
+ enum:
+ - qcom,rpmh-stats
+ - qcom,sdm845-rpmh-stats
+ - qcom,rpm-stats
+ # For older RPM firmware versions with fixed offset for the sleep stats
+ - qcom,apq8084-rpm-stats
+ - qcom,msm8226-rpm-stats
+ - qcom,msm8916-rpm-stats
+ - qcom,msm8974-rpm-stats
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ # Example of rpmh sleep stats
+ - |
+ sram@c3f0000 {
+ compatible = "qcom,rpmh-stats";
+ reg = <0x0c3f0000 0x400>;
+ };
+ # Example of rpm sleep stats
+ - |
+ sram@4690000 {
+ compatible = "qcom,rpm-stats";
+ reg = <0x04690000 0x10000>;
+ };
+...