Squashed 'dts/upstream/' content from commit aaba2d45dc2a
git-subtree-dir: dts/upstream
git-subtree-split: aaba2d45dc2a1b3bbb710f2a3808ee1c9f340abe
diff --git a/Bindings/reset/allwinner,sun6i-a31-clock-reset.yaml b/Bindings/reset/allwinner,sun6i-a31-clock-reset.yaml
new file mode 100644
index 0000000..2a248e5
--- /dev/null
+++ b/Bindings/reset/allwinner,sun6i-a31-clock-reset.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/allwinner,sun6i-a31-clock-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A31 Peripheral Reset Controller
+
+maintainers:
+ - Chen-Yu Tsai <wens@csie.org>
+ - Maxime Ripard <mripard@kernel.org>
+
+deprecated: true
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - allwinner,sun6i-a31-ahb1-reset
+ - allwinner,sun6i-a31-clock-reset
+
+ # The PRCM on the A31 and A23 will have the reg property missing,
+ # since it's set at the upper level node, and will be validated by
+ # PRCM's schema. Make sure we only validate standalone nodes.
+ required:
+ - compatible
+ - reg
+
+properties:
+ "#reset-cells":
+ const: 1
+ description: >
+ This additional argument passed to that reset controller is the
+ offset of the bit controlling this particular reset line in the
+ register.
+
+ compatible:
+ enum:
+ - allwinner,sun6i-a31-ahb1-reset
+ - allwinner,sun6i-a31-clock-reset
+
+ reg:
+ maxItems: 1
+
+required:
+ - "#reset-cells"
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ ahb1_rst: reset@1c202c0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-ahb1-reset";
+ reg = <0x01c202c0 0xc>;
+ };
+
+ - |
+ apbs_rst: reset@80014b0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x080014b0 0x4>;
+ };
+
+...
diff --git a/Bindings/reset/altr,rst-mgr.yaml b/Bindings/reset/altr,rst-mgr.yaml
new file mode 100644
index 0000000..761c70c
--- /dev/null
+++ b/Bindings/reset/altr,rst-mgr.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/altr,rst-mgr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera SOCFPGA Reset Manager
+
+maintainers:
+ - Dinh Nguyen <dinguyen@kernel.org>
+
+properties:
+ compatible:
+ oneOf:
+ - description: Cyclone5/Arria5/Arria10
+ const: altr,rst-mgr
+ - description: Stratix10 ARM64 SoC
+ items:
+ - const: altr,stratix10-rst-mgr
+ - const: altr,rst-mgr
+
+ reg:
+ maxItems: 1
+
+ altr,modrst-offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Offset of the first modrst register
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#reset-cells'
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: altr,stratix10-rst-mgr
+then:
+ properties:
+ altr,modrst-offset: false
+
+additionalProperties: false
+
+examples:
+ - |
+ rstmgr@ffd05000 {
+ compatible = "altr,rst-mgr";
+ reg = <0xffd05000 0x1000>;
+ altr,modrst-offset = <0x10>;
+ #reset-cells = <1>;
+ };
diff --git a/Bindings/reset/amlogic,meson-axg-audio-arb.yaml b/Bindings/reset/amlogic,meson-axg-audio-arb.yaml
new file mode 100644
index 0000000..bc1d284
--- /dev/null
+++ b/Bindings/reset/amlogic,meson-axg-audio-arb.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 BayLibre, SAS
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/amlogic,meson-axg-audio-arb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic audio memory arbiter controller
+
+maintainers:
+ - Jerome Brunet <jbrunet@baylibre.com>
+
+description: The Amlogic Audio ARB is a simple device which enables or disables
+ the access of Audio FIFOs to DDR on AXG based SoC.
+
+properties:
+ compatible:
+ enum:
+ - amlogic,meson-axg-audio-arb
+ - amlogic,meson-sm1-audio-arb
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description: |
+ phandle to the fifo peripheral clock provided by the audio clock
+ controller.
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ // on the A113 SoC:
+ #include <dt-bindings/clock/axg-audio-clkc.h>
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ arb: reset-controller@280 {
+ compatible = "amlogic,meson-axg-audio-arb";
+ reg = <0x0 0x280 0x0 0x4>;
+ #reset-cells = <1>;
+ clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
+ };
+ };
diff --git a/Bindings/reset/amlogic,meson-reset.yaml b/Bindings/reset/amlogic,meson-reset.yaml
new file mode 100644
index 0000000..d3fdee8
--- /dev/null
+++ b/Bindings/reset/amlogic,meson-reset.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 BayLibre, SAS
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/amlogic,meson-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic Meson SoC Reset Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+
+properties:
+ compatible:
+ enum:
+ - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs
+ - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
+ - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
+ - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
+ - amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs
+
+ reg:
+ maxItems: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ reset-controller@c884404 {
+ compatible = "amlogic,meson-gxbb-reset";
+ reg = <0xc884404 0x20>;
+ #reset-cells = <1>;
+ };
diff --git a/Bindings/reset/atmel,at91sam9260-reset.yaml b/Bindings/reset/atmel,at91sam9260-reset.yaml
new file mode 100644
index 0000000..98465d2
--- /dev/null
+++ b/Bindings/reset/atmel,at91sam9260-reset.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/atmel,at91sam9260-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel/Microchip System Reset Controller
+
+maintainers:
+ - Claudiu Beznea <claudiu.beznea@microchip.com>
+
+description: |
+ The system reset controller can be used to reset the CPU. In case of
+ SAMA7G5 it can also reset some devices (e.g. USB PHYs).
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - atmel,at91sam9260-rstc
+ - atmel,at91sam9g45-rstc
+ - atmel,sama5d3-rstc
+ - microchip,sam9x60-rstc
+ - microchip,sama7g5-rstc
+ - items:
+ - const: atmel,sama5d3-rstc
+ - const: atmel,at91sam9g45-rstc
+
+ reg:
+ minItems: 1
+ items:
+ - description: base registers for system reset control
+ - description: registers for device specific reset control
+
+ clocks:
+ maxItems: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - microchip,sama7g5-rstc
+ then:
+ required:
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/at91.h>
+
+ reset-controller@fffffd00 {
+ compatible = "atmel,at91sam9260-rstc";
+ reg = <0xfffffd00 0x10>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
+ };
diff --git a/Bindings/reset/bitmain,bm1880-reset.yaml b/Bindings/reset/bitmain,bm1880-reset.yaml
new file mode 100644
index 0000000..1f40b65
--- /dev/null
+++ b/Bindings/reset/bitmain,bm1880-reset.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 Manivannan Sadhasivam <mani@kernel.org>
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/bitmain,bm1880-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bitmain BM1880 SoC Reset Controller
+
+maintainers:
+ - Manivannan Sadhasivam <mani@kernel.org>
+
+properties:
+ compatible:
+ const: bitmain,bm1880-reset
+
+ reg:
+ maxItems: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ rst: reset-controller@c00 {
+ compatible = "bitmain,bm1880-reset";
+ reg = <0xc00 0x8>;
+ #reset-cells = <1>;
+ };
diff --git a/Bindings/reset/brcm,bcm4908-misc-pcie-reset.yaml b/Bindings/reset/brcm,bcm4908-misc-pcie-reset.yaml
new file mode 100644
index 0000000..88aebb3
--- /dev/null
+++ b/Bindings/reset/brcm,bcm4908-misc-pcie-reset.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/brcm,bcm4908-misc-pcie-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom MISC block PCIe reset controller
+
+description: This document describes reset controller handling PCIe PERST#
+ signals. On BCM4908 it's a part of the MISC block.
+
+maintainers:
+ - Rafał Miłecki <rafal@milecki.pl>
+
+properties:
+ compatible:
+ const: brcm,bcm4908-misc-pcie-reset
+
+ reg:
+ maxItems: 1
+
+ "#reset-cells":
+ description: PCIe core id
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ reset-controller@ff802644 {
+ compatible = "brcm,bcm4908-misc-pcie-reset";
+ reg = <0xff802644 0x04>;
+ #reset-cells = <1>;
+ };
diff --git a/Bindings/reset/brcm,bcm63138-pmb.txt b/Bindings/reset/brcm,bcm63138-pmb.txt
new file mode 100644
index 0000000..a98872d2
--- /dev/null
+++ b/Bindings/reset/brcm,bcm63138-pmb.txt
@@ -0,0 +1,19 @@
+Broadcom BCM63138 Processor Monitor Bus binding
+===============================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Require properties:
+
+- compatible: must be "brcm,bcm63138-pmb"
+- reg: base register address and size for this bus controller
+- #reset-cells: must be 2 first cell is the address within the bus instance designated
+ by the phandle, and the second is the number of zones for this peripheral
+
+Example:
+ pmb0: reset-controller@4800c0 {
+ compatible = "brcm,bcm63138-pmb";
+ reg = <0x4800c0 0x10>;
+ #reset-cells = <2>;
+ };
diff --git a/Bindings/reset/brcm,bcm6345-reset.yaml b/Bindings/reset/brcm,bcm6345-reset.yaml
new file mode 100644
index 0000000..00150b9
--- /dev/null
+++ b/Bindings/reset/brcm,bcm6345-reset.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/brcm,bcm6345-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: BCM6345 reset controller
+
+description: This document describes the BCM6345 reset controller.
+
+maintainers:
+ - Álvaro Fernández Rojas <noltari@gmail.com>
+
+properties:
+ compatible:
+ const: brcm,bcm6345-reset
+
+ reg:
+ maxItems: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ reset-controller@10000010 {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x10000010 0x4>;
+ #reset-cells = <1>;
+ };
diff --git a/Bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml b/Bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml
new file mode 100644
index 0000000..34cfc64
--- /dev/null
+++ b/Bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2020 Broadcom
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/brcm,bcm7216-pcie-sata-rescal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: BCM7216 RESCAL reset controller
+
+description: This document describes the BCM7216 RESCAL reset controller
+ which is responsible for controlling the reset of the SATA and PCIe0/1
+ instances on BCM7216.
+
+maintainers:
+ - Florian Fainelli <f.fainelli@gmail.com>
+ - Jim Quinlan <jim2101024@gmail.com>
+
+properties:
+ compatible:
+ const: brcm,bcm7216-pcie-sata-rescal
+
+ reg:
+ maxItems: 1
+
+ "#reset-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ reset-controller@8b2c800 {
+ compatible = "brcm,bcm7216-pcie-sata-rescal";
+ reg = <0x8b2c800 0x10>;
+ #reset-cells = <0>;
+ };
diff --git a/Bindings/reset/brcm,brcmstb-reset.yaml b/Bindings/reset/brcm,brcmstb-reset.yaml
new file mode 100644
index 0000000..b115b86
--- /dev/null
+++ b/Bindings/reset/brcm,brcmstb-reset.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/brcm,brcmstb-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom STB SW_INIT-style reset controller
+
+description:
+ Broadcom STB SoCs have a SW_INIT-style reset controller with separate
+ SET/CLEAR/STATUS registers and possibly multiple banks, each of 32 bit
+ reset lines.
+
+ Please also refer to reset.txt in this directory for common reset
+ controller binding usage.
+
+maintainers:
+ - Florian Fainelli <f.fainelli@gmail.com>
+
+properties:
+ compatible:
+ const: brcm,brcmstb-reset
+
+ reg:
+ maxItems: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ reset: reset-controller@8404318 {
+ compatible = "brcm,brcmstb-reset";
+ reg = <0x8404318 0x30>;
+ #reset-cells = <1>;
+ };
+
+ ethernet_switch {
+ resets = <&reset 26>;
+ reset-names = "switch";
+ };
diff --git a/Bindings/reset/canaan,k210-rst.yaml b/Bindings/reset/canaan,k210-rst.yaml
new file mode 100644
index 0000000..0c01359
--- /dev/null
+++ b/Bindings/reset/canaan,k210-rst.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/canaan,k210-rst.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Canaan Kendryte K210 Reset Controller
+
+maintainers:
+ - Damien Le Moal <dlemoal@kernel.org>
+
+description: |
+ Canaan Kendryte K210 reset controller driver which supports the SoC
+ system controller supplied reset registers for the various peripherals
+ of the SoC. The K210 reset controller node must be defined as a child
+ node of the K210 system controller node.
+
+ See also:
+ - dt-bindings/reset/k210-rst.h
+
+properties:
+ compatible:
+ const: canaan,k210-rst
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - '#reset-cells'
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/reset/k210-rst.h>
+ sysrst: reset-controller {
+ compatible = "canaan,k210-rst";
+ #reset-cells = <1>;
+ };
diff --git a/Bindings/reset/delta,tn48m-reset.yaml b/Bindings/reset/delta,tn48m-reset.yaml
new file mode 100644
index 0000000..0e5ee8d
--- /dev/null
+++ b/Bindings/reset/delta,tn48m-reset.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/delta,tn48m-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Delta Networks TN48M CPLD reset controller
+
+maintainers:
+ - Robert Marko <robert.marko@sartura.hr>
+
+description: |
+ This module is part of the Delta TN48M multi-function device. For more
+ details see ../mfd/delta,tn48m-cpld.yaml.
+
+ Reset controller modules provides resets for the following:
+ * 88F7040 SoC
+ * 88F6820 SoC
+ * 98DX3265 switch MAC-s
+ * 88E1680 PHY-s
+ * 88E1512 PHY
+ * PoE PSE controller
+
+properties:
+ compatible:
+ const: delta,tn48m-reset
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - "#reset-cells"
+
+additionalProperties: false
diff --git a/Bindings/reset/fsl,imx-src.yaml b/Bindings/reset/fsl,imx-src.yaml
new file mode 100644
index 0000000..b11ac53
--- /dev/null
+++ b/Bindings/reset/fsl,imx-src.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/fsl,imx-src.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX System Reset Controller
+
+maintainers:
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ The system reset controller can be used to reset the GPU, VPU,
+ IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device
+ nodes should specify the reset line on the SRC in their resets
+ property, containing a phandle to the SRC device node and a
+ RESET_INDEX specifying which module to reset, as described in
+ reset.txt
+
+ The following RESET_INDEX values are valid for i.MX5:
+ GPU_RESET 0
+ VPU_RESET 1
+ IPU1_RESET 2
+ OPEN_VG_RESET 3
+ The following additional RESET_INDEX value is valid for i.MX6:
+ IPU2_RESET 4
+
+properties:
+ compatible:
+ oneOf:
+ - const: "fsl,imx51-src"
+ - items:
+ - const: "fsl,imx50-src"
+ - const: "fsl,imx51-src"
+ - items:
+ - const: "fsl,imx53-src"
+ - const: "fsl,imx51-src"
+ - items:
+ - const: "fsl,imx6q-src"
+ - const: "fsl,imx51-src"
+ - items:
+ - const: "fsl,imx6sx-src"
+ - const: "fsl,imx51-src"
+ - items:
+ - const: "fsl,imx6sl-src"
+ - const: "fsl,imx51-src"
+ - items:
+ - const: "fsl,imx6ul-src"
+ - const: "fsl,imx51-src"
+ - items:
+ - const: "fsl,imx6sll-src"
+ - const: "fsl,imx51-src"
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: SRC interrupt
+ - description: CPU WDOG interrupts out of SRC
+ minItems: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ reset-controller@73fd0000 {
+ compatible = "fsl,imx51-src";
+ reg = <0x73fd0000 0x4000>;
+ interrupts = <75>;
+ #reset-cells = <1>;
+ };
diff --git a/Bindings/reset/fsl,imx7-src.yaml b/Bindings/reset/fsl,imx7-src.yaml
new file mode 100644
index 0000000..00430e2
--- /dev/null
+++ b/Bindings/reset/fsl,imx7-src.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/fsl,imx7-src.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX7 System Reset Controller
+
+maintainers:
+ - Andrey Smirnov <andrew.smirnov@gmail.com>
+
+description: |
+ The system reset controller can be used to reset various set of
+ peripherals. Device nodes that need access to reset lines should
+ specify them as a reset phandle in their corresponding node as
+ specified in reset.txt.
+
+ For list of all valid reset indices see
+ <dt-bindings/reset/imx7-reset.h> for i.MX7,
+ <dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ, i.MX8MM and i.MX8MN,
+ <dt-bindings/reset/imx8mp-reset.h> for i.MX8MP.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - fsl,imx7d-src
+ - fsl,imx8mq-src
+ - fsl,imx8mp-src
+ - const: syscon
+ - items:
+ - enum:
+ - fsl,imx8mm-src
+ - fsl,imx8mn-src
+ - const: fsl,imx8mq-src
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ reset-controller@30390000 {
+ compatible = "fsl,imx7d-src", "syscon";
+ reg = <0x30390000 0x2000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ #reset-cells = <1>;
+ };
diff --git a/Bindings/reset/hisilicon,hi3660-reset.yaml b/Bindings/reset/hisilicon,hi3660-reset.yaml
new file mode 100644
index 0000000..cdfcf32
--- /dev/null
+++ b/Bindings/reset/hisilicon,hi3660-reset.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/hisilicon,hi3660-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon System Reset Controller
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: |
+ Please also refer to reset.txt in this directory for common reset
+ controller binding usage.
+ The reset controller registers are part of the system-ctl block on
+ hi3660 and hi3670 SoCs.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: hisilicon,hi3660-reset
+ - items:
+ - const: hisilicon,hi3670-reset
+ - const: hisilicon,hi3660-reset
+
+ hisi,rst-syscon:
+ deprecated: true
+ description: phandle of the reset's syscon, use hisilicon,rst-syscon instead
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ hisilicon,rst-syscon:
+ description: phandle of the reset's syscon.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ '#reset-cells':
+ description: |
+ Specifies the number of cells needed to encode a reset source.
+ Cell #1 : offset of the reset assert control register from the syscon
+ register base
+ offset + 4: deassert control register
+ offset + 8: status control register
+ Cell #2 : bit position of the reset in the reset control register
+ const: 2
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/hi3660-clock.h>
+
+ iomcu: iomcu@ffd7e000 {
+ compatible = "hisilicon,hi3660-iomcu", "syscon";
+ reg = <0xffd7e000 0x1000>;
+ };
+
+ iomcu_rst: iomcu_rst_controller {
+ compatible = "hisilicon,hi3660-reset";
+ hisilicon,rst-syscon = <&iomcu>;
+ #reset-cells = <2>;
+ };
+
+ /* Specifying reset lines connected to IP modules */
+ i2c@ffd71000 {
+ compatible = "snps,designware-i2c";
+ reg = <0xffd71000 0x1000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
+ resets = <&iomcu_rst 0x20 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
+ };
+...
diff --git a/Bindings/reset/img,pistachio-reset.txt b/Bindings/reset/img,pistachio-reset.txt
new file mode 100644
index 0000000..8c05d16
--- /dev/null
+++ b/Bindings/reset/img,pistachio-reset.txt
@@ -0,0 +1,55 @@
+Pistachio Reset Controller
+=============================================================================
+
+This binding describes a reset controller device that is used to enable and
+disable individual IP blocks within the Pistachio SoC using "soft reset"
+control bits found in the Pistachio SoC top level registers.
+
+The actual action taken when soft reset is asserted is hardware dependent.
+However, when asserted it may not be possible to access the hardware's
+registers, and following an assert/deassert sequence the hardware's previous
+state may no longer be valid.
+
+Please refer to Documentation/devicetree/bindings/reset/reset.txt
+for common reset controller binding usage.
+
+Required properties:
+
+- compatible: Contains "img,pistachio-reset"
+
+- #reset-cells: Contains 1
+
+Example:
+
+ cr_periph: clk@18148000 {
+ compatible = "img,pistachio-cr-periph", "syscon", "simple-mfd";
+ reg = <0x18148000 0x1000>;
+ clocks = <&clk_periph PERIPH_CLK_SYS>;
+ clock-names = "sys";
+ #clock-cells = <1>;
+
+ pistachio_reset: reset-controller {
+ compatible = "img,pistachio-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+Specifying reset control of devices
+=======================================
+
+Device nodes should specify the reset channel required in their "resets"
+property, containing a phandle to the pistachio reset device node and an
+index specifying which reset to use, as described in
+Documentation/devicetree/bindings/reset/reset.txt.
+
+Example:
+
+ spdif_out: spdif-out@18100d00 {
+ ...
+ resets = <&pistachio_reset PISTACHIO_RESET_SPDIF_OUT>;
+ reset-names = "rst";
+ ...
+ };
+
+Macro definitions for the supported resets can be found in:
+include/dt-bindings/reset/pistachio-resets.h
diff --git a/Bindings/reset/intel,rcu-gw.yaml b/Bindings/reset/intel,rcu-gw.yaml
new file mode 100644
index 0000000..13bf6bb
--- /dev/null
+++ b/Bindings/reset/intel,rcu-gw.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: System Reset Controller on Intel Gateway SoCs
+
+maintainers:
+ - Dilip Kota <eswara.kota@linux.intel.com>
+
+properties:
+ compatible:
+ enum:
+ - intel,rcu-lgm
+ - intel,rcu-xrx200
+
+ reg:
+ description: Reset controller registers.
+ maxItems: 1
+
+ intel,global-reset:
+ description: Global reset register offset and bit offset.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - description: Register offset
+ - description: Register bit offset
+ minimum: 0
+ maximum: 31
+
+ "#reset-cells":
+ minimum: 2
+ maximum: 3
+ description: |
+ First cell is reset request register offset.
+ Second cell is bit offset in reset request register.
+ Third cell is bit offset in reset status register.
+ For LGM SoC, reset cell count is 2 as bit offset in
+ reset request and reset status registers is same. Whereas
+ 3 for legacy SoCs as bit offset differs.
+
+required:
+ - compatible
+ - reg
+ - intel,global-reset
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ rcu0: reset-controller@e0000000 {
+ compatible = "intel,rcu-lgm";
+ reg = <0xe0000000 0x20000>;
+ intel,global-reset = <0x10 30>;
+ #reset-cells = <2>;
+ };
+
+ pwm: pwm@e0d00000 {
+ compatible = "intel,lgm-pwm";
+ reg = <0xe0d00000 0x30>;
+ clocks = <&cgu0 1>;
+ #pwm-cells = <2>;
+ resets = <&rcu0 0x30 21>;
+ };
diff --git a/Bindings/reset/lantiq,reset.yaml b/Bindings/reset/lantiq,reset.yaml
new file mode 100644
index 0000000..15d65a5
--- /dev/null
+++ b/Bindings/reset/lantiq,reset.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/lantiq,reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lantiq XWAY SoC RCU reset controller
+
+maintainers:
+ - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+
+description: |
+ This binding describes a reset-controller found on the RCU module on Lantiq
+ XWAY SoCs. This node has to be a sub node of the Lantiq RCU block.
+
+properties:
+ compatible:
+ enum:
+ - lantiq,danube-reset
+ - lantiq,xrx200-reset
+
+ reg:
+ description: |
+ Defines the following sets of registers in the parent syscon device
+ Offset of the reset set register
+ Offset of the reset status register
+ maxItems: 2
+
+ '#reset-cells':
+ description: |
+ The first cell takes the reset set bit and the second cell takes the
+ status bit.
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ // On the xRX200 SoCs:
+ reset0: reset-controller@10 {
+ compatible = "lantiq,xrx200-reset";
+ reg = <0x10 0x04>, <0x14 0x04>;
+ #reset-cells = <2>;
+ };
diff --git a/Bindings/reset/marvell,berlin2-reset.yaml b/Bindings/reset/marvell,berlin2-reset.yaml
new file mode 100644
index 0000000..dc86568
--- /dev/null
+++ b/Bindings/reset/marvell,berlin2-reset.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2015 Antoine Tenart <atenart@kernel.org>
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/marvell,berlin2-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell Berlin reset controller
+
+maintainers:
+ - Antoine Tenart <atenart@kernel.org>
+
+description: The reset controller node must be a sub-node of the chip
+ controller node on Berlin SoCs.
+
+properties:
+ compatible:
+ const: marvell,berlin2-reset
+
+ "#reset-cells":
+ const: 2
+
+required:
+ - compatible
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ chip: chip-control@ea0000 {
+ reg = <0xea0000 0x400>;
+
+ chip_rst: reset {
+ compatible = "marvell,berlin2-reset";
+ #reset-cells = <2>;
+ };
+ };
diff --git a/Bindings/reset/microchip,rst.yaml b/Bindings/reset/microchip,rst.yaml
new file mode 100644
index 0000000..f2da069
--- /dev/null
+++ b/Bindings/reset/microchip,rst.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/microchip,rst.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Sparx5 Switch Reset Controller
+
+maintainers:
+ - Steen Hegelund <steen.hegelund@microchip.com>
+ - Lars Povlsen <lars.povlsen@microchip.com>
+
+description: |
+ The Microchip Sparx5 Switch provides reset control and implements the following
+ functions
+ - One Time Switch Core Reset (Soft Reset)
+
+properties:
+ $nodename:
+ pattern: "^reset-controller@[0-9a-f]+$"
+
+ compatible:
+ enum:
+ - microchip,sparx5-switch-reset
+ - microchip,lan966x-switch-reset
+
+ reg:
+ items:
+ - description: global control block registers
+
+ reg-names:
+ items:
+ - const: gcb
+
+ "#reset-cells":
+ const: 1
+
+ cpu-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: syscon used to access CPU reset
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#reset-cells"
+ - cpu-syscon
+
+additionalProperties: false
+
+examples:
+ - |
+ reset: reset-controller@11010008 {
+ compatible = "microchip,sparx5-switch-reset";
+ reg = <0x11010008 0x4>;
+ reg-names = "gcb";
+ #reset-cells = <1>;
+ cpu-syscon = <&cpu_ctrl>;
+ };
diff --git a/Bindings/reset/nuvoton,ma35d1-reset.yaml b/Bindings/reset/nuvoton,ma35d1-reset.yaml
new file mode 100644
index 0000000..34c5c1c
--- /dev/null
+++ b/Bindings/reset/nuvoton,ma35d1-reset.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/nuvoton,ma35d1-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35D1 Reset Controller
+
+maintainers:
+ - Chi-Fang Li <cfli0@nuvoton.com>
+ - Jacky Huang <ychuang3@nuvoton.com>
+
+description:
+ The system reset controller can be used to reset various peripheral
+ controllers in MA35D1 SoC.
+
+properties:
+ compatible:
+ items:
+ - const: nuvoton,ma35d1-reset
+
+ reg:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ # system reset controller node:
+ - |
+
+ system-management@40460000 {
+ compatible = "nuvoton,ma35d1-reset";
+ reg = <0x40460000 0x200>;
+ #reset-cells = <1>;
+ };
+...
+
diff --git a/Bindings/reset/nuvoton,npcm750-reset.yaml b/Bindings/reset/nuvoton,npcm750-reset.yaml
new file mode 100644
index 0000000..d82e65e
--- /dev/null
+++ b/Bindings/reset/nuvoton,npcm750-reset.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/nuvoton,npcm750-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton NPCM Reset controller
+
+maintainers:
+ - Tomer Maimon <tmaimon77@gmail.com>
+
+properties:
+ compatible:
+ enum:
+ - nuvoton,npcm750-reset # Poleg NPCM7XX SoC
+ - nuvoton,npcm845-reset # Arbel NPCM8XX SoC
+
+ reg:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 2
+
+ nuvoton,sysgcr:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: a phandle to access GCR registers.
+
+ nuvoton,sw-reset-number:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 4
+ description: |
+ Contains the software reset number to restart the SoC.
+ If not specified, software reset is disabled.
+
+required:
+ - compatible
+ - reg
+ - '#reset-cells'
+ - nuvoton,sysgcr
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
+ rstc: rstc@f0801000 {
+ compatible = "nuvoton,npcm750-reset";
+ reg = <0xf0801000 0x70>;
+ #reset-cells = <2>;
+ nuvoton,sysgcr = <&gcr>;
+ nuvoton,sw-reset-number = <2>;
+ };
+
+ // Specifying reset lines connected to IP NPCM7XX modules
+ spi0: spi {
+ resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>;
+ };
diff --git a/Bindings/reset/nxp,lpc1850-rgu.txt b/Bindings/reset/nxp,lpc1850-rgu.txt
new file mode 100644
index 0000000..05d5be4
--- /dev/null
+++ b/Bindings/reset/nxp,lpc1850-rgu.txt
@@ -0,0 +1,83 @@
+NXP LPC1850 Reset Generation Unit (RGU)
+========================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: Should be "nxp,lpc1850-rgu"
+- reg: register base and length
+- clocks: phandle and clock specifier to RGU clocks
+- clock-names: should contain "delay" and "reg"
+- #reset-cells: should be 1
+
+See table below for valid peripheral reset numbers. Numbers not
+in the table below are either reserved or not applicable for
+normal operation.
+
+Reset Peripheral
+ 9 System control unit (SCU)
+ 12 ARM Cortex-M0 subsystem core (LPC43xx only)
+ 13 CPU core
+ 16 LCD controller
+ 17 USB0
+ 18 USB1
+ 19 DMA
+ 20 SDIO
+ 21 External memory controller (EMC)
+ 22 Ethernet
+ 25 Flash bank A
+ 27 EEPROM
+ 28 GPIO
+ 29 Flash bank B
+ 32 Timer0
+ 33 Timer1
+ 34 Timer2
+ 35 Timer3
+ 36 Repetitive Interrupt timer (RIT)
+ 37 State Configurable Timer (SCT)
+ 38 Motor control PWM (MCPWM)
+ 39 QEI
+ 40 ADC0
+ 41 ADC1
+ 42 DAC
+ 44 USART0
+ 45 UART1
+ 46 USART2
+ 47 USART3
+ 48 I2C0
+ 49 I2C1
+ 50 SSP0
+ 51 SSP1
+ 52 I2S0 and I2S1
+ 53 Serial Flash Interface (SPIFI)
+ 54 C_CAN1
+ 55 C_CAN0
+ 56 ARM Cortex-M0 application core (LPC4370 only)
+ 57 SGPIO (LPC43xx only)
+ 58 SPI (LPC43xx only)
+ 60 ADCHS (12-bit ADC) (LPC4370 only)
+
+Refer to NXP LPC18xx or LPC43xx user manual for more details about
+the reset signals and the connected block/peripheral.
+
+Reset provider example:
+rgu: reset-controller@40053000 {
+ compatible = "nxp,lpc1850-rgu";
+ reg = <0x40053000 0x1000>;
+ clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
+ clock-names = "delay", "reg";
+ #reset-cells = <1>;
+};
+
+Reset consumer example:
+mac: ethernet@40010000 {
+ compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
+ reg = <0x40010000 0x2000>;
+ interrupts = <5>;
+ interrupt-names = "macirq";
+ clocks = <&ccu1 CLK_CPU_ETHERNET>;
+ clock-names = "stmmaceth";
+ resets = <&rgu 22>;
+ reset-names = "stmmaceth";
+};
diff --git a/Bindings/reset/qca,ar7100-reset.yaml b/Bindings/reset/qca,ar7100-reset.yaml
new file mode 100644
index 0000000..47f8525
--- /dev/null
+++ b/Bindings/reset/qca,ar7100-reset.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2015 Alban Bedel <albeu@free.fr>
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/qca,ar7100-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Atheros AR7xxx/AR9XXX reset controller
+
+maintainers:
+ - Alban Bedel <albeu@free.fr>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qca,ar9132-reset
+ - qca,ar9331-reset
+ - const: qca,ar7100-reset
+
+ reg:
+ maxItems: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ reset-controller@1806001c {
+ compatible = "qca,ar9132-reset", "qca,ar7100-reset";
+ reg = <0x1806001c 0x4>;
+ #reset-cells = <1>;
+ };
diff --git a/Bindings/reset/qcom,aoss-reset.yaml b/Bindings/reset/qcom,aoss-reset.yaml
new file mode 100644
index 0000000..d92e2b3
--- /dev/null
+++ b/Bindings/reset/qcom,aoss-reset.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/qcom,aoss-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm AOSS Reset Controller
+
+maintainers:
+ - Sibi Sankar <quic_sibis@quicinc.com>
+
+description:
+ The bindings describe the reset-controller found on AOSS-CC (always on
+ subsystem) for Qualcomm Technologies Inc SoCs.
+
+properties:
+ compatible:
+ oneOf:
+ - description: on SC7180 SoCs the following compatibles must be specified
+ items:
+ - const: "qcom,sc7180-aoss-cc"
+ - const: "qcom,sdm845-aoss-cc"
+
+ - description: on SC7280 SoCs the following compatibles must be specified
+ items:
+ - const: "qcom,sc7280-aoss-cc"
+ - const: "qcom,sdm845-aoss-cc"
+
+ - description: on SDM845 SoCs the following compatibles must be specified
+ items:
+ - const: "qcom,sdm845-aoss-cc"
+
+ reg:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ aoss_reset: reset-controller@c2a0000 {
+ compatible = "qcom,sdm845-aoss-cc";
+ reg = <0xc2a0000 0x31000>;
+ #reset-cells = <1>;
+ };
diff --git a/Bindings/reset/qcom,pdc-global.yaml b/Bindings/reset/qcom,pdc-global.yaml
new file mode 100644
index 0000000..ca5d793
--- /dev/null
+++ b/Bindings/reset/qcom,pdc-global.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/qcom,pdc-global.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm PDC Global
+
+maintainers:
+ - Sibi Sankar <quic_sibis@quicinc.com>
+
+description:
+ The bindings describes the reset-controller found on PDC-Global (Power Domain
+ Controller) block for Qualcomm Technologies Inc SoCs.
+
+properties:
+ compatible:
+ oneOf:
+ - description: on SC7180 SoCs the following compatibles must be specified
+ items:
+ - const: "qcom,sc7180-pdc-global"
+ - const: "qcom,sdm845-pdc-global"
+
+ - description: on SC7280 SoCs the following compatibles must be specified
+ items:
+ - const: "qcom,sc7280-pdc-global"
+
+ - description: on SDM845 SoCs the following compatibles must be specified
+ items:
+ - const: "qcom,sdm845-pdc-global"
+
+ reg:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ pdc_reset: reset-controller@b2e0000 {
+ compatible = "qcom,sdm845-pdc-global";
+ reg = <0xb2e0000 0x20000>;
+ #reset-cells = <1>;
+ };
diff --git a/Bindings/reset/renesas,rst.yaml b/Bindings/reset/renesas,rst.yaml
new file mode 100644
index 0000000..e7e4872
--- /dev/null
+++ b/Bindings/reset/renesas,rst.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/renesas,rst.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car and RZ/G Reset Controller
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+ - Magnus Damm <magnus.damm@gmail.com>
+
+description: |
+ The R-Car and RZ/G Reset Controllers provide reset control, and implement the
+ following functions:
+ - Latching of the levels on mode pins when PRESET# is negated,
+ - Mode monitoring register,
+ - Reset control of peripheral devices (on R-Car Gen1),
+ - Watchdog timer (on R-Car Gen1),
+ - Register-based reset control and boot address registers for the various
+ CPU cores (on R-Car Gen2 and Gen3, and on RZ/G).
+
+properties:
+ compatible:
+ enum:
+ - renesas,r8a7742-rst # RZ/G1H
+ - renesas,r8a7743-rst # RZ/G1M
+ - renesas,r8a7744-rst # RZ/G1N
+ - renesas,r8a7745-rst # RZ/G1E
+ - renesas,r8a77470-rst # RZ/G1C
+ - renesas,r8a774a1-rst # RZ/G2M
+ - renesas,r8a774b1-rst # RZ/G2N
+ - renesas,r8a774c0-rst # RZ/G2E
+ - renesas,r8a774e1-rst # RZ/G2H
+ - renesas,r8a7778-reset-wdt # R-Car M1A
+ - renesas,r8a7779-reset-wdt # R-Car H1
+ - renesas,r8a7790-rst # R-Car H2
+ - renesas,r8a7791-rst # R-Car M2-W
+ - renesas,r8a7792-rst # R-Car V2H
+ - renesas,r8a7793-rst # R-Car M2-N
+ - renesas,r8a7794-rst # R-Car E2
+ - renesas,r8a7795-rst # R-Car H3
+ - renesas,r8a7796-rst # R-Car M3-W
+ - renesas,r8a77961-rst # R-Car M3-W+
+ - renesas,r8a77965-rst # R-Car M3-N
+ - renesas,r8a77970-rst # R-Car V3M
+ - renesas,r8a77980-rst # R-Car V3H
+ - renesas,r8a77990-rst # R-Car E3
+ - renesas,r8a77995-rst # R-Car D3
+ - renesas,r8a779a0-rst # R-Car V3U
+ - renesas,r8a779f0-rst # R-Car S4-8
+ - renesas,r8a779g0-rst # R-Car V4H
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7795-rst";
+ reg = <0xe6160000 0x0200>;
+ };
diff --git a/Bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/Bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
new file mode 100644
index 0000000..731b8ce
--- /dev/null
+++ b/Bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/{G2L,V2L} USBPHY Control
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description:
+ The RZ/G2L USBPHY Control mainly controls reset and power down of the
+ USB/PHY.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL
+ - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
+ - renesas,r9a07g054-usbphy-ctrl # RZ/V2L
+ - const: renesas,rzg2l-usbphy-ctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+ description: |
+ The phandle's argument in the reset specifier is the PHY reset associated
+ with the USB port.
+ 0 = Port 1 Phy reset
+ 1 = Port 2 Phy reset
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+ - power-domains
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+
+ phyrst: usbphy-ctrl@11c40000 {
+ compatible = "renesas,r9a07g044-usbphy-ctrl",
+ "renesas,rzg2l-usbphy-ctrl";
+ reg = <0x11c40000 0x10000>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
+ resets = <&cpg R9A07G044_USB_PRESETN>;
+ power-domains = <&cpg>;
+ #reset-cells = <1>;
+ };
diff --git a/Bindings/reset/reset.txt b/Bindings/reset/reset.txt
new file mode 100644
index 0000000..31db6ff
--- /dev/null
+++ b/Bindings/reset/reset.txt
@@ -0,0 +1,75 @@
+= Reset Signal Device Tree Bindings =
+
+This binding is intended to represent the hardware reset signals present
+internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
+standalone chips are most likely better represented as GPIOs, although there
+are likely to be exceptions to this rule.
+
+Hardware blocks typically receive a reset signal. This signal is generated by
+a reset provider (e.g. power management or clock module) and received by a
+reset consumer (the module being reset, or a module managing when a sub-
+ordinate module is reset). This binding exists to represent the provider and
+consumer, and provide a way to couple the two together.
+
+A reset signal is represented by the phandle of the provider, plus a reset
+specifier - a list of DT cells that represents the reset signal within the
+provider. The length (number of cells) and semantics of the reset specifier
+are dictated by the binding of the reset provider, although common schemes
+are described below.
+
+A word on where to place reset signal consumers in device tree: It is possible
+in hardware for a reset signal to affect multiple logically separate HW blocks
+at once. In this case, it would be unwise to represent this reset signal in
+the DT node of each affected HW block, since if activated, an unrelated block
+may be reset. Instead, reset signals should be represented in the DT node
+where it makes most sense to control it; this may be a bus node if all
+children of the bus are affected by the reset signal, or an individual HW
+block node for dedicated reset signals. The intent of this binding is to give
+appropriate software access to the reset signals in order to manage the HW,
+rather than to slavishly enumerate the reset signal that affects each HW
+block.
+
+= Reset providers =
+
+Required properties:
+#reset-cells: Number of cells in a reset specifier; Typically 0 for nodes
+ with a single reset output and 1 for nodes with multiple
+ reset outputs.
+
+For example:
+
+ rst: reset-controller {
+ #reset-cells = <1>;
+ };
+
+= Reset consumers =
+
+Required properties:
+resets: List of phandle and reset specifier pairs, one pair
+ for each reset signal that affects the device, or that the
+ device manages. Note: if the reset provider specifies '0' for
+ #reset-cells, then only the phandle portion of the pair will
+ appear.
+
+Optional properties:
+reset-names: List of reset signal name strings sorted in the same order as
+ the resets property. Consumers drivers will use reset-names to
+ match reset signal names with reset specifiers.
+
+For example:
+
+ device {
+ resets = <&rst 20>;
+ reset-names = "reset";
+ };
+
+This represents a device with a single reset signal named "reset".
+
+ bus {
+ resets = <&rst 10> <&rst 11> <&rst 12> <&rst 11>;
+ reset-names = "i2s1", "i2s2", "dma", "mixer";
+ };
+
+This represents a bus that controls the reset signal of each of four sub-
+ordinate devices. Consider for example a bus that fails to operate unless no
+child device has reset asserted.
diff --git a/Bindings/reset/snps,axs10x-reset.yaml b/Bindings/reset/snps,axs10x-reset.yaml
new file mode 100644
index 0000000..a75db3d
--- /dev/null
+++ b/Bindings/reset/snps,axs10x-reset.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/snps,axs10x-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AXS10x reset controller
+
+maintainers:
+ - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+
+description: |
+ This binding describes the ARC AXS10x boards custom IP-block which allows
+ to control reset signals of selected peripherals. For example DW GMAC, etc...
+ This block is controlled via memory-mapped register (AKA CREG) which
+ represents up-to 32 reset lines.
+ As of today only the following lines are used:
+ - DW GMAC - line 5
+
+properties:
+ compatible:
+ const: snps,axs10x-reset
+
+ reg:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ reset: reset-controller@11220 {
+ compatible = "snps,axs10x-reset";
+ #reset-cells = <1>;
+ reg = <0x11220 0x4>;
+ };
+
+ // Specifying reset lines connected to IP modules:
+ ethernet {
+ resets = <&reset 5>;
+ };
diff --git a/Bindings/reset/snps,dw-reset.txt b/Bindings/reset/snps,dw-reset.txt
new file mode 100644
index 0000000..0c241d4
--- /dev/null
+++ b/Bindings/reset/snps,dw-reset.txt
@@ -0,0 +1,30 @@
+Synopsys DesignWare Reset controller
+=======================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+
+- compatible: should be one of the following.
+ "snps,dw-high-reset" - for active high configuration
+ "snps,dw-low-reset" - for active low configuration
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #reset-cells: must be 1.
+
+example:
+
+ dw_rst_1: reset-controller@0000 {
+ compatible = "snps,dw-high-reset";
+ reg = <0x0000 0x4>;
+ #reset-cells = <1>;
+ };
+
+ dw_rst_2: reset-controller@1000 {
+ compatible = "snps,dw-low-reset";
+ reg = <0x1000 0x8>;
+ #reset-cells = <1>;
+ };
diff --git a/Bindings/reset/snps,hsdk-reset.txt b/Bindings/reset/snps,hsdk-reset.txt
new file mode 100644
index 0000000..830069b
--- /dev/null
+++ b/Bindings/reset/snps,hsdk-reset.txt
@@ -0,0 +1,28 @@
+Binding for the Synopsys HSDK reset controller
+
+This binding uses the common reset binding[1].
+
+[1] Documentation/devicetree/bindings/reset/reset.txt
+
+Required properties:
+- compatible: should be "snps,hsdk-reset".
+- reg: should always contain 2 pairs address - length: first for reset
+ configuration register and second for corresponding SW reset and status bits
+ register.
+- #reset-cells: from common reset binding; Should always be set to 1.
+
+Example:
+ reset: reset@880 {
+ compatible = "snps,hsdk-reset";
+ #reset-cells = <1>;
+ reg = <0x8A0 0x4>, <0xFF0 0x4>;
+ };
+
+Specifying reset lines connected to IP modules:
+ ethernet@.... {
+ ....
+ resets = <&reset HSDK_V1_ETH_RESET>;
+ ....
+ };
+
+The index could be found in <dt-bindings/reset/snps,hsdk-reset.h>
diff --git a/Bindings/reset/socionext,uniphier-glue-reset.yaml b/Bindings/reset/socionext,uniphier-glue-reset.yaml
new file mode 100644
index 0000000..fa253c5
--- /dev/null
+++ b/Bindings/reset/socionext,uniphier-glue-reset.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier peripheral core reset in glue layer
+
+description: |
+ Some peripheral core reset belongs to its own glue layer. Before using
+ this core reset, it is necessary to control the clocks and resets to
+ enable this layer. These clocks and resets should be described in each
+ property.
+
+maintainers:
+ - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+properties:
+ compatible:
+ enum:
+ - socionext,uniphier-pro4-usb3-reset
+ - socionext,uniphier-pro5-usb3-reset
+ - socionext,uniphier-pxs2-usb3-reset
+ - socionext,uniphier-ld20-usb3-reset
+ - socionext,uniphier-pxs3-usb3-reset
+ - socionext,uniphier-nx1-usb3-reset
+ - socionext,uniphier-pro4-ahci-reset
+ - socionext,uniphier-pxs2-ahci-reset
+ - socionext,uniphier-pxs3-ahci-reset
+
+ reg:
+ maxItems: 1
+
+ "#reset-cells":
+ const: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names: true
+
+ resets:
+ minItems: 1
+ maxItems: 2
+
+ reset-names: true
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - socionext,uniphier-pro4-usb3-reset
+ - socionext,uniphier-pro5-usb3-reset
+ - socionext,uniphier-pro4-ahci-reset
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: gio
+ - const: link
+ resets:
+ minItems: 2
+ maxItems: 2
+ reset-names:
+ items:
+ - const: gio
+ - const: link
+ else:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names:
+ const: link
+ resets:
+ maxItems: 1
+ reset-names:
+ const: link
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+examples:
+ - |
+ usb_rst: reset-controller@0 {
+ compatible = "socionext,uniphier-ld20-usb3-reset";
+ reg = <0x0 0x4>;
+ #reset-cells = <1>;
+ clock-names = "link";
+ clocks = <&sys_clk 14>;
+ reset-names = "link";
+ resets = <&sys_rst 14>;
+ };
diff --git a/Bindings/reset/socionext,uniphier-reset.yaml b/Bindings/reset/socionext,uniphier-reset.yaml
new file mode 100644
index 0000000..033b252
--- /dev/null
+++ b/Bindings/reset/socionext,uniphier-reset.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/socionext,uniphier-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UniPhier reset controller
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+
+properties:
+ compatible:
+ oneOf:
+ - description: System reset
+ enum:
+ - socionext,uniphier-ld4-reset
+ - socionext,uniphier-pro4-reset
+ - socionext,uniphier-sld8-reset
+ - socionext,uniphier-pro5-reset
+ - socionext,uniphier-pxs2-reset
+ - socionext,uniphier-ld6b-reset
+ - socionext,uniphier-ld11-reset
+ - socionext,uniphier-ld20-reset
+ - socionext,uniphier-pxs3-reset
+ - socionext,uniphier-nx1-reset
+ - description: Media I/O (MIO) reset, SD reset
+ enum:
+ - socionext,uniphier-ld4-mio-reset
+ - socionext,uniphier-pro4-mio-reset
+ - socionext,uniphier-sld8-mio-reset
+ - socionext,uniphier-pro5-sd-reset
+ - socionext,uniphier-pxs2-sd-reset
+ - socionext,uniphier-ld11-mio-reset
+ - socionext,uniphier-ld11-sd-reset
+ - socionext,uniphier-ld20-sd-reset
+ - socionext,uniphier-pxs3-sd-reset
+ - socionext,uniphier-nx1-sd-reset
+ - description: Peripheral reset
+ enum:
+ - socionext,uniphier-ld4-peri-reset
+ - socionext,uniphier-pro4-peri-reset
+ - socionext,uniphier-sld8-peri-reset
+ - socionext,uniphier-pro5-peri-reset
+ - socionext,uniphier-pxs2-peri-reset
+ - socionext,uniphier-ld11-peri-reset
+ - socionext,uniphier-ld20-peri-reset
+ - socionext,uniphier-pxs3-peri-reset
+ - socionext,uniphier-nx1-peri-reset
+ - description: Analog signal amplifier reset
+ enum:
+ - socionext,uniphier-ld11-adamv-reset
+ - socionext,uniphier-ld20-adamv-reset
+
+ "#reset-cells":
+ const: 1
+
+ resets:
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - "#reset-cells"
+
+examples:
+ - |
+ reset-controller {
+ compatible = "socionext,uniphier-ld11-reset";
+ #reset-cells = <1>;
+ };
diff --git a/Bindings/reset/st,sti-softreset.txt b/Bindings/reset/st,sti-softreset.txt
new file mode 100644
index 0000000..3661e61
--- /dev/null
+++ b/Bindings/reset/st,sti-softreset.txt
@@ -0,0 +1,44 @@
+STMicroelectronics STi family Sysconfig Peripheral SoftReset Controller
+=============================================================================
+
+This binding describes a reset controller device that is used to enable and
+disable on-chip peripheral controllers such as USB and SATA, using
+"softreset" control bits found in the STi family SoC system configuration
+registers.
+
+The actual action taken when softreset is asserted is hardware dependent.
+However, when asserted it may not be possible to access the hardware's
+registers and after an assert/deassert sequence the hardware's previous state
+may no longer be valid.
+
+Please refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: Should be "st,stih407-softreset";
+- #reset-cells: 1, see below
+
+example:
+
+ softreset: softreset-controller {
+ #reset-cells = <1>;
+ compatible = "st,stih407-softreset";
+ };
+
+
+Specifying softreset control of devices
+=======================================
+
+Device nodes should specify the reset channel required in their "resets"
+property, containing a phandle to the softreset device node and an
+index specifying which channel to use, as described in reset.txt
+
+example:
+
+ ethernet0{
+ resets = <&softreset STIH415_ETH0_SOFTRESET>;
+ };
+
+Macro definitions for the supported reset channels can be found in:
+
+include/dt-bindings/reset/stih407-resets.h
diff --git a/Bindings/reset/st,stih407-picophyreset.yaml b/Bindings/reset/st,stih407-picophyreset.yaml
new file mode 100644
index 0000000..329ae4a
--- /dev/null
+++ b/Bindings/reset/st,stih407-picophyreset.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/st,stih407-picophyreset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STi family Sysconfig Picophy SoftReset Controller
+
+maintainers:
+ - Peter Griffin <peter.griffin@linaro.org>
+
+description: |
+ This binding describes a reset controller device that is used to enable and
+ disable on-chip PicoPHY USB2 phy(s) using "softreset" control bits found in
+ the STi family SoC system configuration registers.
+
+ The actual action taken when softreset is asserted is hardware dependent.
+ However, when asserted it may not be possible to access the hardware's
+ registers and after an assert/deassert sequence the hardware's previous state
+ may no longer be valid.
+
+properties:
+ compatible:
+ const: st,stih407-picophyreset
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/reset/stih407-resets.h>
+
+ picophyreset: picophyreset-controller {
+ compatible = "st,stih407-picophyreset";
+ #reset-cells = <1>;
+ };
+
+ // Specifying picophyreset control of devices
+ usb2_picophy0: usbpicophy {
+ resets = <&picophyreset STIH407_PICOPHY0_RESET>;
+ };
diff --git a/Bindings/reset/st,stih407-powerdown.yaml b/Bindings/reset/st,stih407-powerdown.yaml
new file mode 100644
index 0000000..d3790e6
--- /dev/null
+++ b/Bindings/reset/st,stih407-powerdown.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/st,stih407-powerdown.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STi family Sysconfig Peripheral Powerdown Reset Controller
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@st.com>
+
+description: |
+ This binding describes a reset controller device that is used to enable and
+ disable on-chip peripheral controllers such as USB and SATA, using
+ "powerdown" control bits found in the STi family SoC system configuration
+ registers. These have been grouped together into a single reset controller
+ device for convenience.
+
+ The actual action taken when powerdown is asserted is hardware dependent.
+ However, when asserted it may not be possible to access the hardware's
+ registers and after an assert/deassert sequence the hardware's previous state
+ may no longer be valid.
+
+properties:
+ compatible:
+ const: st,stih407-powerdown
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/reset/stih407-resets.h>
+
+ powerdown: powerdown-controller {
+ compatible = "st,stih407-powerdown";
+ #reset-cells = <1>;
+ };
+
+ // Specifying powerdown control of devices:
+ st_dwc3: dwc3 {
+ resets = <&powerdown STIH407_USB3_POWERDOWN>;
+ };
diff --git a/Bindings/reset/st,stm32-rcc.txt b/Bindings/reset/st,stm32-rcc.txt
new file mode 100644
index 0000000..01db343
--- /dev/null
+++ b/Bindings/reset/st,stm32-rcc.txt
@@ -0,0 +1,6 @@
+STMicroelectronics STM32 Peripheral Reset Controller
+====================================================
+
+The RCC IP is both a reset and a clock controller.
+
+Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
diff --git a/Bindings/reset/st,stm32mp1-rcc.txt b/Bindings/reset/st,stm32mp1-rcc.txt
new file mode 100644
index 0000000..2880d5d
--- /dev/null
+++ b/Bindings/reset/st,stm32mp1-rcc.txt
@@ -0,0 +1,6 @@
+STMicroelectronics STM32MP1 Peripheral Reset Controller
+=======================================================
+
+The RCC IP is both a reset and a clock controller.
+
+Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
diff --git a/Bindings/reset/starfive,jh7100-reset.yaml b/Bindings/reset/starfive,jh7100-reset.yaml
new file mode 100644
index 0000000..2f5bd61
--- /dev/null
+++ b/Bindings/reset/starfive,jh7100-reset.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/starfive,jh7100-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7100 SoC Reset Controller
+
+maintainers:
+ - Emil Renner Berthing <kernel@esmil.dk>
+
+properties:
+ compatible:
+ enum:
+ - starfive,jh7100-reset
+
+ reg:
+ maxItems: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ reset-controller@11840000 {
+ compatible = "starfive,jh7100-reset";
+ reg = <0x11840000 0x10000>;
+ #reset-cells = <1>;
+ };
+
+...
diff --git a/Bindings/reset/sunplus,reset.yaml b/Bindings/reset/sunplus,reset.yaml
new file mode 100644
index 0000000..205918c
--- /dev/null
+++ b/Bindings/reset/sunplus,reset.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) Sunplus Co., Ltd. 2021
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/sunplus,reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sunplus SoC Reset Controller
+
+maintainers:
+ - Qin Jian <qinjian@cqplus1.com>
+
+properties:
+ compatible:
+ const: sunplus,sp7021-reset
+
+ reg:
+ maxItems: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ rstc: reset@9c000054 {
+ compatible = "sunplus,sp7021-reset";
+ reg = <0x9c000054 0x28>;
+ #reset-cells = <1>;
+ };
+
+...
diff --git a/Bindings/reset/ti,sci-reset.yaml b/Bindings/reset/ti,sci-reset.yaml
new file mode 100644
index 0000000..e10eb98
--- /dev/null
+++ b/Bindings/reset/ti,sci-reset.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/ti,sci-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI-SCI reset controller
+
+maintainers:
+ - Nishanth Menon <nm@ti.com>
+
+description: |
+ Some TI SoCs contain a system controller (like the Power Management Micro
+ Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
+ the state of the various hardware modules present on the SoC. Communication
+ between the host processor running an OS and the system controller happens
+ through a protocol called TI System Control Interface (TI-SCI protocol).
+
+ This reset controller node uses the TI SCI protocol to perform the reset
+ management of various hardware modules present on the SoC. Must be a child
+ node of the associated TI-SCI system controller node.
+
+properties:
+ $nodename:
+ pattern: "^reset-controller$"
+
+ compatible:
+ const: ti,sci-reset
+
+ "#reset-cells":
+ const: 2
+ description:
+ The two cells represent values that the TI-SCI controller defines.
+
+ The first cell should contain the device ID.
+
+ The second cell should contain the reset mask corresponding to the device
+ used by system controller.
+
+ Please see http://processors.wiki.ti.com/index.php/TISCI for
+ protocol documentation for the values to be used for different devices.
+
+
+additionalProperties: false
+
+examples:
+ - |
+ k3_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
diff --git a/Bindings/reset/ti,tps380x-reset.yaml b/Bindings/reset/ti,tps380x-reset.yaml
new file mode 100644
index 0000000..6063784
--- /dev/null
+++ b/Bindings/reset/ti,tps380x-reset.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/ti,tps380x-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI TPS380x reset controller
+
+maintainers:
+ - Marco Felsch <kernel@pengutronix.de>
+
+description: |
+ The TPS380x family [1] of supervisory circuits monitor supply voltages to
+ provide circuit initialization and timing supervision. The devices assert a
+ RESET signal if the voltage drops below a preset threshold or upon a manual
+ reset input (MR). The RESET output remains asserted for the factory
+ programmed delay after the voltage return above its threshold or after the
+ manual reset input is released.
+
+ [1] https://www.ti.com/product/TPS3801
+
+properties:
+ compatible:
+ enum:
+ - ti,tps3801
+
+ reset-gpios:
+ maxItems: 1
+ description: Reference to the GPIO connected to the MR pin.
+
+ "#reset-cells":
+ const: 0
+
+required:
+ - compatible
+ - reset-gpios
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ reset: reset-controller {
+ compatible = "ti,tps3801";
+ #reset-cells = <0>;
+ reset-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
+ };
+...
diff --git a/Bindings/reset/ti-syscon-reset.txt b/Bindings/reset/ti-syscon-reset.txt
new file mode 100644
index 0000000..61a0ff3
--- /dev/null
+++ b/Bindings/reset/ti-syscon-reset.txt
@@ -0,0 +1,91 @@
+TI SysCon Reset Controller
+=======================
+
+Almost all SoCs have hardware modules that require reset control in addition
+to clock and power control for their functionality. The reset control is
+typically provided by means of memory-mapped I/O registers. These registers are
+sometimes a part of a larger register space region implementing various
+functionalities. This register range is best represented as a syscon node to
+allow multiple entities to access their relevant registers in the common
+register space.
+
+A SysCon Reset Controller node defines a device that uses a syscon node
+and provides reset management functionality for various hardware modules
+present on the SoC.
+
+SysCon Reset Controller Node
+============================
+Each of the reset provider/controller nodes should be a child of a syscon
+node and have the following properties.
+
+Required properties:
+--------------------
+ - compatible : Should be,
+ "ti,k2e-pscrst"
+ "ti,k2l-pscrst"
+ "ti,k2hk-pscrst"
+ "ti,syscon-reset"
+ - #reset-cells : Should be 1. Please see the reset consumer node below
+ for usage details
+ - ti,reset-bits : Contains the reset control register information
+ Should contain 7 cells for each reset exposed to
+ consumers, defined as:
+ Cell #1 : offset of the reset assert control
+ register from the syscon register base
+ Cell #2 : bit position of the reset in the reset
+ assert control register
+ Cell #3 : offset of the reset deassert control
+ register from the syscon register base
+ Cell #4 : bit position of the reset in the reset
+ deassert control register
+ Cell #5 : offset of the reset status register
+ from the syscon register base
+ Cell #6 : bit position of the reset in the
+ reset status register
+ Cell #7 : Flags used to control reset behavior,
+ available flags defined in the DT include
+ file <dt-bindings/reset/ti-syscon.h>
+
+SysCon Reset Consumer Nodes
+===========================
+Each of the reset consumer nodes should have the following properties,
+in addition to their own properties.
+
+Required properties:
+--------------------
+ - resets : A phandle to the reset controller node and an index number
+ to a reset specifier as defined above.
+
+Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
+common reset controller usage by consumers.
+
+Example:
+--------
+The following example demonstrates a syscon node, the reset controller node
+using the syscon node, and a consumer (a DSP device) on the TI Keystone 2
+66AK2E SoC.
+
+/ {
+ soc {
+ psc: power-sleep-controller@2350000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x02350000 0x1000>;
+
+ pscrst: reset-controller {
+ compatible = "ti,k2e-pscrst", "ti,syscon-reset";
+ #reset-cells = <1>;
+
+ ti,reset-bits = <
+ 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
+ 0xa40 5 0xa44 3 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE) /* 1: example */
+ >;
+ };
+ };
+
+ dsp0: dsp0 {
+ ...
+ resets = <&pscrst 0>;
+ ...
+ };
+ };
+};
diff --git a/Bindings/reset/xlnx,zynqmp-reset.yaml b/Bindings/reset/xlnx,zynqmp-reset.yaml
new file mode 100644
index 0000000..49db668
--- /dev/null
+++ b/Bindings/reset/xlnx,zynqmp-reset.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/xlnx,zynqmp-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Zynq UltraScale+ MPSoC and Versal reset
+
+maintainers:
+ - Piyush Mehta <piyush.mehta@amd.com>
+
+description: |
+ The Zynq UltraScale+ MPSoC and Versal has several different resets.
+
+ The PS reset subsystem is responsible for handling the external reset
+ input to the device and that all internal reset requirements are met
+ for the system (as a whole) and for the functional units.
+
+ Please also refer to reset.txt in this directory for common reset
+ controller binding usage. Device nodes that need access to reset
+ lines should specify them as a reset phandle in their corresponding
+ node as specified in reset.txt.
+
+ For list of all valid reset indices for Zynq UltraScale+ MPSoC
+ <dt-bindings/reset/xlnx-zynqmp-resets.h>
+
+ For list of all valid reset indices for Versal
+ <dt-bindings/reset/xlnx-versal-resets.h>
+
+properties:
+ compatible:
+ enum:
+ - xlnx,zynqmp-reset
+ - xlnx,versal-reset
+ - xlnx,versal-net-reset
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ zynqmp_reset: reset-controller {
+ compatible = "xlnx,zynqmp-reset";
+ #reset-cells = <1>;
+ };
+
+...
diff --git a/Bindings/reset/zynq-reset.txt b/Bindings/reset/zynq-reset.txt
new file mode 100644
index 0000000..5860120
--- /dev/null
+++ b/Bindings/reset/zynq-reset.txt
@@ -0,0 +1,68 @@
+Xilinx Zynq Reset Manager
+
+The Zynq AP-SoC has several different resets.
+
+See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
+
+Required properties:
+- compatible: "xlnx,zynq-reset"
+- reg: SLCR offset and size taken via syscon <0x200 0x48>
+- syscon: <&slcr>
+ This should be a phandle to the Zynq's SLCR registers.
+- #reset-cells: Must be 1
+
+The Zynq Reset Manager needs to be a childnode of the SLCR.
+
+Example:
+ rstc: rstc@200 {
+ compatible = "xlnx,zynq-reset";
+ reg = <0x200 0x48>;
+ #reset-cells = <1>;
+ syscon = <&slcr>;
+ };
+
+Reset outputs:
+ 0 : soft reset
+ 32 : ddr reset
+ 64 : topsw reset
+ 96 : dmac reset
+ 128: usb0 reset
+ 129: usb1 reset
+ 160: gem0 reset
+ 161: gem1 reset
+ 164: gem0 rx reset
+ 165: gem1 rx reset
+ 166: gem0 ref reset
+ 167: gem1 ref reset
+ 192: sdio0 reset
+ 193: sdio1 reset
+ 196: sdio0 ref reset
+ 197: sdio1 ref reset
+ 224: spi0 reset
+ 225: spi1 reset
+ 226: spi0 ref reset
+ 227: spi1 ref reset
+ 256: can0 reset
+ 257: can1 reset
+ 258: can0 ref reset
+ 259: can1 ref reset
+ 288: i2c0 reset
+ 289: i2c1 reset
+ 320: uart0 reset
+ 321: uart1 reset
+ 322: uart0 ref reset
+ 323: uart1 ref reset
+ 352: gpio reset
+ 384: lqspi reset
+ 385: qspi ref reset
+ 416: smc reset
+ 417: smc ref reset
+ 448: ocm reset
+ 512: fpga0 out reset
+ 513: fpga1 out reset
+ 514: fpga2 out reset
+ 515: fpga3 out reset
+ 544: a9 reset 0
+ 545: a9 reset 1
+ 552: peri reset
+