Squashed 'dts/upstream/' content from commit aaba2d45dc2a
git-subtree-dir: dts/upstream
git-subtree-split: aaba2d45dc2a1b3bbb710f2a3808ee1c9f340abe
diff --git a/Bindings/mmc/cdns,sdhci.yaml b/Bindings/mmc/cdns,sdhci.yaml
new file mode 100644
index 0000000..6c40611
--- /dev/null
+++ b/Bindings/mmc/cdns,sdhci.yaml
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - amd,pensando-elba-sd4hc
+ - microchip,mpfs-sd4hc
+ - socionext,uniphier-sd4hc
+ - const: cdns,sd4hc
+
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ # PHY DLL input delays:
+ # They are used to delay the data valid window, and align the window to
+ # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
+ # and it is increased by 2.5ns in each step.
+
+ cdns,phy-input-delay-sd-highspeed:
+ description: Value of the delay in the input path for SD high-speed timing
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0x1f
+
+ cdns,phy-input-delay-legacy:
+ description: Value of the delay in the input path for legacy timing
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0x1f
+
+ cdns,phy-input-delay-sd-uhs-sdr12:
+ description: Value of the delay in the input path for SD UHS SDR12 timing
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0x1f
+
+ cdns,phy-input-delay-sd-uhs-sdr25:
+ description: Value of the delay in the input path for SD UHS SDR25 timing
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0x1f
+
+ cdns,phy-input-delay-sd-uhs-sdr50:
+ description: Value of the delay in the input path for SD UHS SDR50 timing
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0x1f
+
+ cdns,phy-input-delay-sd-uhs-ddr50:
+ description: Value of the delay in the input path for SD UHS DDR50 timing
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0x1f
+
+ cdns,phy-input-delay-mmc-highspeed:
+ description: Value of the delay in the input path for MMC high-speed timing
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0x1f
+
+ cdns,phy-input-delay-mmc-ddr:
+ description: Value of the delay in the input path for eMMC high-speed DDR timing
+
+ # PHY DLL clock delays:
+ # Each delay property represents the fraction of the clock period.
+ # The approximate delay value will be
+ # (<delay property value>/128)*sdmclk_clock_period.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0x1f
+
+ cdns,phy-dll-delay-sdclk:
+ description: |
+ Value of the delay introduced on the sdclk output for all modes except
+ HS200, HS400 and HS400_ES.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0x7f
+
+ cdns,phy-dll-delay-sdclk-hsmmc:
+ description: |
+ Value of the delay introduced on the sdclk output for HS200, HS400 and
+ HS400_ES speed modes.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0x7f
+
+ cdns,phy-dll-delay-strobe:
+ description: |
+ Value of the delay introduced on the dat_strobe input used in
+ HS400 / HS400_ES speed modes.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0x7f
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+allOf:
+ - $ref: mmc-controller.yaml
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: amd,pensando-elba-sd4hc
+ then:
+ properties:
+ reg:
+ items:
+ - description: Host controller registers
+ - description: Elba byte-lane enable register for writes
+ required:
+ - resets
+ else:
+ properties:
+ reg:
+ maxItems: 1
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ emmc: mmc@5a000000 {
+ compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
+ reg = <0x5a000000 0x400>;
+ interrupts = <0 78 4>;
+ clocks = <&clk 4>;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ cdns,phy-dll-delay-sdclk = <0>;
+ };