Squashed 'dts/upstream/' content from commit aaba2d45dc2a
git-subtree-dir: dts/upstream
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diff --git a/Bindings/iio/adc/adc.yaml b/Bindings/iio/adc/adc.yaml
new file mode 100644
index 0000000..2616017
--- /dev/null
+++ b/Bindings/iio/adc/adc.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: IIO Common Properties for ADC Channels
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description:
+ A few properties are defined in a common way ADC channels.
+
+properties:
+ $nodename:
+ pattern: "^channel(@[0-9a-f]+)?$"
+ description:
+ A channel index should match reg.
+
+ reg:
+ maxItems: 1
+
+ label:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: Unique name to identify which channel this is.
+
+ bipolar:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: If provided, the channel is to be used in bipolar mode.
+
+ diff-channels:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ maxItems: 2
+ minItems: 2
+ description:
+ Many ADCs have dual Muxes to allow different input pins to be routed
+ to both the positive and negative inputs of a differential ADC.
+ The first value specifies the positive input pin, the second
+ specifies the negative input pin.
+
+ settling-time-us:
+ description:
+ Time between enabling the channel and first stable readings.
+
+ oversampling-ratio:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Oversampling is used as replacement of or addition to the low-pass filter.
+ In some cases, the desired filtering characteristics are a function the
+ device design and can interact with other characteristics such as
+ settling time.
+
+additionalProperties: true
diff --git a/Bindings/iio/adc/adi,ad4130.yaml b/Bindings/iio/adc/adi,ad4130.yaml
new file mode 100644
index 0000000..d00690a
--- /dev/null
+++ b/Bindings/iio/adc/adi,ad4130.yaml
@@ -0,0 +1,262 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2022 Analog Devices Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad4130.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD4130 ADC device driver
+
+maintainers:
+ - Cosmin Tanislav <cosmin.tanislav@analog.com>
+
+description: |
+ Bindings for the Analog Devices AD4130 ADC. Datasheet can be found here:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD4130-8.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,ad4130
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description: phandle to the master clock (mclk)
+
+ clock-names:
+ items:
+ - const: mclk
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ description: |
+ Specify which interrupt pin should be configured as Data Ready / FIFO
+ interrupt.
+ Default if not supplied is int.
+ enum:
+ - int
+ - clk
+ - p2
+ - dout
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ '#clock-cells':
+ const: 0
+
+ clock-output-names:
+ maxItems: 1
+
+ refin1-supply:
+ description: refin1 supply. Can be used as reference for conversion.
+
+ refin2-supply:
+ description: refin2 supply. Can be used as reference for conversion.
+
+ avdd-supply:
+ description: AVDD voltage supply. Can be used as reference for conversion.
+
+ iovdd-supply:
+ description: IOVDD voltage supply. Used for the chip interface.
+
+ spi-max-frequency:
+ maximum: 5000000
+
+ adi,ext-clk-freq-hz:
+ description: Specify the frequency of the external clock.
+ enum: [76800, 153600]
+ default: 76800
+
+ adi,bipolar:
+ description: Specify if the device should be used in bipolar mode.
+ type: boolean
+
+ adi,vbias-pins:
+ description: Analog inputs to apply a voltage bias of (AVDD − AVSS) / 2 to.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 16
+ items:
+ minimum: 0
+ maximum: 15
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+patternProperties:
+ "^channel@([0-9a-f])$":
+ type: object
+ $ref: adc.yaml
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ description: The channel number.
+ minimum: 0
+ maximum: 15
+
+ diff-channels:
+ description: |
+ Besides the analog inputs available, internal inputs can be used.
+ 16: Internal temperature sensor.
+ 17: AVSS
+ 18: Internal reference
+ 19: DGND
+ 20: (AVDD − AVSS)/6+
+ 21: (AVDD − AVSS)/6-
+ 22: (IOVDD − DGND)/6+
+ 23: (IOVDD − DGND)/6-
+ 24: (ALDO − AVSS)/6+
+ 25: (ALDO − AVSS)/6-
+ 26: (DLDO − DGND)/6+
+ 27: (DLDO − DGND)/6-
+ 28: V_MV_P
+ 29: V_MV_M
+ items:
+ minimum: 0
+ maximum: 29
+
+ adi,reference-select:
+ description: |
+ Select the reference source to use when converting on the
+ specific channel. Valid values are:
+ 0: REFIN1(+)/REFIN1(−)
+ 1: REFIN2(+)/REFIN2(−)
+ 2: REFOUT/AVSS (Internal reference)
+ 3: AVDD/AVSS
+ If not specified, REFIN1 is used.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 0
+
+ adi,excitation-pin-0:
+ description: |
+ Analog input to apply excitation current to while the channel
+ is active.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 15
+ default: 0
+
+ adi,excitation-pin-1:
+ description: |
+ Analog input to apply excitation current to while this channel
+ is active.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 15
+ default: 0
+
+ adi,excitation-current-0-nanoamp:
+ description: |
+ Excitation current in nanoamps to be applied to pin specified in
+ adi,excitation-pin-0 while this channel is active.
+ enum: [0, 100, 10000, 20000, 50000, 100000, 150000, 200000]
+ default: 0
+
+ adi,excitation-current-1-nanoamp:
+ description: |
+ Excitation current in nanoamps to be applied to pin specified in
+ adi,excitation-pin-1 while this channel is active.
+ enum: [0, 100, 10000, 20000, 50000, 100000, 150000, 200000]
+ default: 0
+
+ adi,burnout-current-nanoamp:
+ description: |
+ Burnout current in nanoamps to be applied for this channel.
+ enum: [0, 500, 2000, 4000]
+ default: 0
+
+ adi,buffered-positive:
+ description: Enable buffered mode for positive input.
+ type: boolean
+
+ adi,buffered-negative:
+ description: Enable buffered mode for negative input.
+ type: boolean
+
+ required:
+ - reg
+ - diff-channels
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad4130";
+ reg = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ spi-max-frequency = <5000000>;
+ interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpio>;
+
+ channel@0 {
+ reg = <0>;
+
+ adi,reference-select = <2>;
+
+ /* AIN8, AIN9 */
+ diff-channels = <8 9>;
+ };
+
+ channel@1 {
+ reg = <1>;
+
+ adi,reference-select = <2>;
+
+ /* AIN10, AIN11 */
+ diff-channels = <10 11>;
+ };
+
+ channel@2 {
+ reg = <2>;
+
+ adi,reference-select = <2>;
+
+ /* Temperature Sensor, DGND */
+ diff-channels = <16 19>;
+ };
+
+ channel@3 {
+ reg = <3>;
+
+ adi,reference-select = <2>;
+
+ /* Internal reference, DGND */
+ diff-channels = <18 19>;
+ };
+
+ channel@4 {
+ reg = <4>;
+
+ adi,reference-select = <2>;
+
+ /* DGND, DGND */
+ diff-channels = <19 19>;
+ };
+ };
+ };
diff --git a/Bindings/iio/adc/adi,ad7091r5.yaml b/Bindings/iio/adc/adi,ad7091r5.yaml
new file mode 100644
index 0000000..ce7ba63
--- /dev/null
+++ b/Bindings/iio/adc/adi,ad7091r5.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad7091r5.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD7091R5 4-Channel 12-Bit ADC
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+
+description: |
+ Analog Devices AD7091R5 4-Channel 12-Bit ADC
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad7091r-5.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,ad7091r5
+
+ reg:
+ maxItems: 1
+
+ vref-supply:
+ description:
+ Phandle to the vref power supply
+
+ interrupts:
+ maxItems: 1
+
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@2f {
+ compatible = "adi,ad7091r5";
+ reg = <0x2f>;
+
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpio>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/adi,ad7124.yaml b/Bindings/iio/adc/adi,ad7124.yaml
new file mode 100644
index 0000000..35ed043
--- /dev/null
+++ b/Bindings/iio/adc/adi,ad7124.yaml
@@ -0,0 +1,157 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 Analog Devices Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad7124.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD7124 ADC device driver
+
+maintainers:
+ - Stefan Popa <stefan.popa@analog.com>
+
+description: |
+ Bindings for the Analog Devices AD7124 ADC device. Datasheet can be
+ found here:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7124-8.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,ad7124-4
+ - adi,ad7124-8
+
+ reg:
+ description: SPI chip select number for the device
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description: phandle to the master clock (mclk)
+
+ clock-names:
+ items:
+ - const: mclk
+
+ interrupts:
+ description: IRQ line for the ADC
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ refin1-supply:
+ description: refin1 supply can be used as reference for conversion.
+
+ refin2-supply:
+ description: refin2 supply can be used as reference for conversion.
+
+ avdd-supply:
+ description: avdd supply can be used as reference for conversion.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+patternProperties:
+ "^channel@([0-9]|1[0-5])$":
+ $ref: adc.yaml
+ type: object
+ description: |
+ Represents the external channels which are connected to the ADC.
+
+ properties:
+ reg:
+ description: |
+ The channel number. It can have up to 8 channels on ad7124-4
+ and 16 channels on ad7124-8, numbered from 0 to 15.
+ items:
+ minimum: 0
+ maximum: 15
+
+ adi,reference-select:
+ description: |
+ Select the reference source to use when converting on
+ the specific channel. Valid values are:
+ 0: REFIN1(+)/REFIN1(−).
+ 1: REFIN2(+)/REFIN2(−).
+ 3: AVDD
+ If this field is left empty, internal reference is selected.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 3]
+
+ diff-channels: true
+
+ bipolar: true
+
+ adi,buffered-positive:
+ description: Enable buffered mode for positive input.
+ type: boolean
+
+ adi,buffered-negative:
+ description: Enable buffered mode for negative input.
+ type: boolean
+
+ required:
+ - reg
+ - diff-channels
+
+ additionalProperties: false
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad7124-4";
+ reg = <0>;
+ spi-max-frequency = <5000000>;
+ interrupts = <25 2>;
+ interrupt-parent = <&gpio>;
+ refin1-supply = <&adc_vref>;
+ clocks = <&ad7124_mclk>;
+ clock-names = "mclk";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ diff-channels = <0 1>;
+ adi,reference-select = <0>;
+ adi,buffered-positive;
+ };
+
+ channel@1 {
+ reg = <1>;
+ bipolar;
+ diff-channels = <2 3>;
+ adi,reference-select = <0>;
+ adi,buffered-positive;
+ adi,buffered-negative;
+ };
+
+ channel@2 {
+ reg = <2>;
+ diff-channels = <4 5>;
+ };
+
+ channel@3 {
+ reg = <3>;
+ diff-channels = <6 7>;
+ };
+ };
+ };
diff --git a/Bindings/iio/adc/adi,ad7192.yaml b/Bindings/iio/adc/adi,ad7192.yaml
new file mode 100644
index 0000000..16def29
--- /dev/null
+++ b/Bindings/iio/adc/adi,ad7192.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 Analog Devices Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad7192.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD7192 ADC device driver
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+
+description: |
+ Bindings for the Analog Devices AD7192 ADC device. Datasheet can be
+ found here:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7192.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,ad7190
+ - adi,ad7192
+ - adi,ad7193
+ - adi,ad7195
+
+ reg:
+ maxItems: 1
+
+ spi-cpol: true
+
+ spi-cpha: true
+
+ clocks:
+ maxItems: 1
+ description: phandle to the master clock (mclk)
+
+ clock-names:
+ items:
+ - const: mclk
+
+ interrupts:
+ maxItems: 1
+
+ dvdd-supply:
+ description: DVdd voltage supply
+
+ avdd-supply:
+ description: AVdd voltage supply
+
+ vref-supply:
+ description: VRef voltage supply
+
+ adi,rejection-60-Hz-enable:
+ description: |
+ This bit enables a notch at 60 Hz when the first notch of the sinc
+ filter is at 50 Hz. When REJ60 is set, a filter notch is placed at
+ 60 Hz when the sinc filter first notch is at 50 Hz. This allows
+ simultaneous 50 Hz/ 60 Hz rejection.
+ type: boolean
+
+ adi,refin2-pins-enable:
+ description: |
+ External reference applied between the P1/REFIN2(+) and P0/REFIN2(−) pins.
+ type: boolean
+
+ adi,buffer-enable:
+ description: |
+ Enables the buffer on the analog inputs. If cleared, the analog inputs
+ are unbuffered, lowering the power consumption of the device. If this
+ bit is set, the analog inputs are buffered, allowing the user to place
+ source impedances on the front end without contributing gain errors to
+ the system.
+ type: boolean
+
+ adi,burnout-currents-enable:
+ description: |
+ When this bit is set to 1, the 500 nA current sources in the signal
+ path are enabled. When BURN = 0, the burnout currents are disabled.
+ The burnout currents can be enabled only when the buffer is active
+ and when chop is disabled.
+ type: boolean
+
+ bipolar:
+ description: see Documentation/devicetree/bindings/iio/adc/adc.yaml
+ type: boolean
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - dvdd-supply
+ - avdd-supply
+ - vref-supply
+ - spi-cpol
+ - spi-cpha
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad7192";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cpol;
+ spi-cpha;
+ clocks = <&ad7192_mclk>;
+ clock-names = "mclk";
+ interrupts = <25 0x2>;
+ interrupt-parent = <&gpio>;
+ dvdd-supply = <&dvdd>;
+ avdd-supply = <&avdd>;
+ vref-supply = <&vref>;
+
+ adi,refin2-pins-enable;
+ adi,rejection-60-Hz-enable;
+ adi,buffer-enable;
+ adi,burnout-currents-enable;
+ };
+ };
diff --git a/Bindings/iio/adc/adi,ad7280a.yaml b/Bindings/iio/adc/adi,ad7280a.yaml
new file mode 100644
index 0000000..dfb8f30
--- /dev/null
+++ b/Bindings/iio/adc/adi,ad7280a.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad7280a.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD7280a Lithium Ion Battery Monitoring System
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+ - Jonathan Cameron <jic23@kernel.org>
+
+description: |
+ Bindings for the Analog Devices AD7280a Battery Monitoring System.
+ Used in devices such as hybrid electric cars, battery backup and power tools.
+ Multiple chips can be daisy chained and accessed via a single SPI interface.
+ Data sheet found here:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7280A.pdf
+
+properties:
+ compatible:
+ const: adi,ad7280a
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: IRQ line for the ADC
+ maxItems: 1
+
+ adi,voltage-alert-last-chan:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Allows limiting of scope of which channels are considered for voltage
+ alerts, typically because not all are wired to anything. Only applies to
+ last device in the daisy chain.
+ default: 5
+ enum: [3, 4, 5]
+
+ adi,acquisition-time-ns:
+ description:
+ Additional time may be needed to charge the sampling capacitors depending
+ on external writing.
+ default: 400
+ enum: [400, 800, 1200, 1600]
+
+ adi,thermistor-termination:
+ type: boolean
+ description:
+ Enable the thermistor termination function.
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad7280a";
+ reg = <0>;
+ spi-max-frequency = <700000>;
+ interrupt-parent = <&gpio>;
+ interrupts = <25 2>;
+ adi,thermistor-termination;
+ adi,acquisition-time-ns = <800>;
+ adi,voltage-alert-last-chan = <5>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/adi,ad7291.yaml b/Bindings/iio/adc/adi,ad7291.yaml
new file mode 100644
index 0000000..0b2f5dc
--- /dev/null
+++ b/Bindings/iio/adc/adi,ad7291.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad7291.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AD7291 8-Channel, I2C, 12-Bit SAR ADC with Temperature Sensor
+
+maintainers:
+ - Michael Auchter <michael.auchter@ni.com>
+
+description: |
+ Analog Devices AD7291 8-Channel I2C 12-Bit SAR ADC with Temperature Sensor
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad7291.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,ad7291
+
+ reg:
+ maxItems: 1
+
+ vref-supply:
+ description: |
+ The regulator supply for ADC reference voltage.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ad7291: adc@0 {
+ compatible = "adi,ad7291";
+ reg = <0>;
+ vref-supply = <&adc_vref>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/adi,ad7292.yaml b/Bindings/iio/adc/adi,ad7292.yaml
new file mode 100644
index 0000000..2aa1f4b
--- /dev/null
+++ b/Bindings/iio/adc/adi,ad7292.yaml
@@ -0,0 +1,110 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad7292.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD7292 10-Bit Monitor and Control System
+
+maintainers:
+ - Marcelo Schmitt <marcelo.schmitt1@gmail.com>
+
+description: |
+ Analog Devices AD7292 10-Bit Monitor and Control System with ADC, DACs,
+ Temperature Sensor, and GPIOs
+
+ Specifications about the part can be found at:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad7292.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,ad7292
+
+ reg:
+ maxItems: 1
+
+ vref-supply:
+ description: |
+ The regulator supply for ADC and DAC reference voltage.
+
+ spi-cpha: true
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - spi-cpha
+
+patternProperties:
+ "^channel@[0-7]$":
+ $ref: adc.yaml
+ type: object
+ description: |
+ Represents the external channels which are connected to the ADC.
+
+ properties:
+ reg:
+ description: |
+ The channel number. It can have up to 8 channels numbered from 0 to 7.
+ items:
+ - minimum: 0
+ maximum: 7
+
+ diff-channels: true
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ad7292: adc@0 {
+ compatible = "adi,ad7292";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ vref-supply = <&adc_vref>;
+ spi-cpha;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ diff-channels = <0 1>;
+ };
+ channel@2 {
+ reg = <2>;
+ };
+ channel@3 {
+ reg = <3>;
+ };
+ channel@4 {
+ reg = <4>;
+ };
+ channel@5 {
+ reg = <5>;
+ };
+ channel@6 {
+ reg = <6>;
+ };
+ channel@7 {
+ reg = <7>;
+ };
+ };
+ };
diff --git a/Bindings/iio/adc/adi,ad7298.yaml b/Bindings/iio/adc/adi,ad7298.yaml
new file mode 100644
index 0000000..cd8ac51
--- /dev/null
+++ b/Bindings/iio/adc/adi,ad7298.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 Analog Devices Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad7298.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD7298 ADC
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+
+description: |
+ Bindings for the Analog Devices AD7298 ADC device. Datasheet can be
+ found here:
+ https://www.analog.com/en/products/ad7298.html
+
+properties:
+ compatible:
+ const: adi,ad7298
+
+ reg:
+ maxItems: 1
+
+ vref-supply: true
+ vdd-supply: true
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad7298";
+ reg = <0>;
+ spi-max-frequency = <5000000>;
+ vref-supply = <&adc_vref>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/adi,ad7476.yaml b/Bindings/iio/adc/adi,ad7476.yaml
new file mode 100644
index 0000000..44c671e
--- /dev/null
+++ b/Bindings/iio/adc/adi,ad7476.yaml
@@ -0,0 +1,175 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 Analog Devices Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad7476.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AD7476 and similar simple SPI ADCs from multiple manufacturers.
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+
+description: |
+ A lot of simple SPI ADCs have very straight forward interfaces.
+ They typically don't provide a MOSI pin, simply reading out data
+ on MISO when the clock toggles.
+
+properties:
+ compatible:
+ enum:
+ - adi,ad7091
+ - adi,ad7091r
+ - adi,ad7273
+ - adi,ad7274
+ - adi,ad7276
+ - adi,ad7277
+ - adi,ad7278
+ - adi,ad7466
+ - adi,ad7467
+ - adi,ad7468
+ - adi,ad7475
+ - adi,ad7476
+ - adi,ad7476a
+ - adi,ad7477
+ - adi,ad7477a
+ - adi,ad7478
+ - adi,ad7478a
+ - adi,ad7495
+ - adi,ad7910
+ - adi,ad7920
+ - adi,ad7940
+ - ti,adc081s
+ - ti,adc101s
+ - ti,adc121s
+ - ti,ads7866
+ - ti,ads7867
+ - ti,ads7868
+ - lltc,ltc2314-14
+
+ reg:
+ maxItems: 1
+
+ vcc-supply:
+ description:
+ Main powersupply voltage for the chips, sometimes referred to as VDD on
+ datasheets. If there is no separate vref-supply, then this is needed
+ to establish channel scaling.
+
+ vdrive-supply:
+ description:
+ Some devices have separate supply for their digital control side.
+
+ vref-supply:
+ description:
+ Some devices have a specific reference voltage supplied on a different pin
+ to the other supplies. Needed to be able to establish channel scaling
+ unless there is also an internal reference available (e.g. ad7091r)
+
+ adi,conversion-start-gpios:
+ description: A GPIO used to trigger the start of a conversion
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+ # Devices where reference is vcc
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,ad7091
+ - adi,ad7276
+ - adi,ad7277
+ - adi,ad7278
+ - adi,ad7466
+ - adi,ad7467
+ - adi,ad7468
+ - adi,ad7940
+ - ti,adc081s
+ - ti,adc101s
+ - ti,adc121s
+ - ti,ads7866
+ - ti,ads7868
+ then:
+ required:
+ - vcc-supply
+ # Devices with a vref
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,ad7091r
+ - adi,ad7273
+ - adi,ad7274
+ - adi,ad7475
+ - lltc,ltc2314-14
+ then:
+ properties:
+ vref-supply: true
+ else:
+ properties:
+ vref-supply: false
+ # Devices with a vref where it is not optional
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,ad7273
+ - adi,ad7274
+ - adi,ad7475
+ - lltc,ltc2314-14
+ then:
+ required:
+ - vref-supply
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,ad7475
+ - adi,ad7495
+ then:
+ properties:
+ vdrive-supply: true
+ else:
+ properties:
+ vdrive-supply: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,ad7091
+ - adi,ad7091r
+ then:
+ properties:
+ adi,conversion-start-gpios: true
+ else:
+ properties:
+ adi,conversion-start-gpios: false
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad7091r";
+ reg = <0>;
+ spi-max-frequency = <5000000>;
+ vcc-supply = <&adc_vcc>;
+ vref-supply = <&adc_vref>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/adi,ad7606.yaml b/Bindings/iio/adc/adi,ad7606.yaml
new file mode 100644
index 0000000..7fa46df
--- /dev/null
+++ b/Bindings/iio/adc/adi,ad7606.yaml
@@ -0,0 +1,141 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad7606.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD7606 Simultaneous Sampling ADC
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+
+description: |
+ Analog Devices AD7606 Simultaneous Sampling ADC
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606_7606-6_7606-4.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7606B.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7616.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,ad7605-4
+ - adi,ad7606-8
+ - adi,ad7606-6
+ - adi,ad7606-4
+ - adi,ad7606b
+ - adi,ad7616
+
+ reg:
+ maxItems: 1
+
+ spi-cpha: true
+
+ spi-cpol: true
+
+ avcc-supply: true
+
+ interrupts:
+ maxItems: 1
+
+ adi,conversion-start-gpios:
+ description:
+ Must be the device tree identifier of the CONVST pin.
+ This logic input is used to initiate conversions on the analog
+ input channels. As the line is active high, it should be marked
+ GPIO_ACTIVE_HIGH.
+ maxItems: 1
+
+ reset-gpios:
+ description:
+ Must be the device tree identifier of the RESET pin. If specified,
+ it will be asserted during driver probe. As the line is active high,
+ it should be marked GPIO_ACTIVE_HIGH.
+ maxItems: 1
+
+ standby-gpios:
+ description:
+ Must be the device tree identifier of the STBY pin. This pin is used
+ to place the AD7606 into one of two power-down modes, Standby mode or
+ Shutdown mode. As the line is active low, it should be marked
+ GPIO_ACTIVE_LOW.
+ maxItems: 1
+
+ adi,first-data-gpios:
+ description:
+ Must be the device tree identifier of the FRSTDATA pin.
+ The FRSTDATA output indicates when the first channel, V1, is
+ being read back on either the parallel, byte or serial interface.
+ As the line is active high, it should be marked GPIO_ACTIVE_HIGH.
+ maxItems: 1
+
+ adi,range-gpios:
+ description:
+ Must be the device tree identifier of the RANGE pin. The polarity on
+ this pin determines the input range of the analog input channels. If
+ this pin is tied to a logic high, the analog input range is ±10V for
+ all channels. If this pin is tied to a logic low, the analog input range
+ is ±5V for all channels. As the line is active high, it should be marked
+ GPIO_ACTIVE_HIGH.
+ maxItems: 1
+
+ adi,oversampling-ratio-gpios:
+ description:
+ Must be the device tree identifier of the over-sampling
+ mode pins. As the line is active high, it should be marked
+ GPIO_ACTIVE_HIGH.
+ maxItems: 3
+
+ adi,sw-mode:
+ description:
+ Software mode of operation, so far available only for ad7616 and ad7606b.
+ It is enabled when all three oversampling mode pins are connected to
+ high level. The device is configured by the corresponding registers. If the
+ adi,oversampling-ratio-gpios property is defined, then the driver will set the
+ oversampling gpios to high. Otherwise, it is assumed that the pins are hardwired
+ to VDD.
+ type: boolean
+
+required:
+ - compatible
+ - reg
+ - spi-cpha
+ - avcc-supply
+ - interrupts
+ - adi,conversion-start-gpios
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad7606-8";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cpol;
+ spi-cpha;
+
+ avcc-supply = <&adc_vref>;
+
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpio>;
+
+ adi,conversion-start-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio 27 GPIO_ACTIVE_HIGH>;
+ adi,first-data-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ adi,oversampling-ratio-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>,
+ <&gpio 23 GPIO_ACTIVE_HIGH>,
+ <&gpio 26 GPIO_ACTIVE_HIGH>;
+ standby-gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
+ adi,sw-mode;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/adi,ad7768-1.yaml b/Bindings/iio/adc/adi,ad7768-1.yaml
new file mode 100644
index 0000000..3ce59d4
--- /dev/null
+++ b/Bindings/iio/adc/adi,ad7768-1.yaml
@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad7768-1.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD7768-1 ADC device driver
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+
+description: |
+ Datasheet at:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad7768-1.pdf
+
+properties:
+ compatible:
+ const: adi,ad7768-1
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: mclk
+
+ interrupts:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ vref-supply:
+ description:
+ ADC reference voltage supply
+
+ adi,sync-in-gpios:
+ maxItems: 1
+ description:
+ Enables synchronization of multiple devices that require simultaneous
+ sampling. A pulse is always required if the configuration is changed
+ in any way, for example if the filter decimation rate changes.
+ As the line is active low, it should be marked GPIO_ACTIVE_LOW.
+
+ reset-gpios:
+ maxItems: 1
+
+ spi-cpol: true
+
+ spi-cpha: true
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - vref-supply
+ - spi-cpol
+ - spi-cpha
+ - adi,sync-in-gpios
+
+patternProperties:
+ "^channel@([0-9]|1[0-5])$":
+ type: object
+ description: |
+ Represents the external channels which are connected to the device.
+
+ properties:
+ reg:
+ maxItems: 1
+ description: |
+ The channel number.
+
+ label:
+ description: |
+ Unique name to identify which channel this is.
+ required:
+ - reg
+ additionalProperties: false
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad7768-1";
+ reg = <0>;
+ spi-max-frequency = <2000000>;
+ spi-cpol;
+ spi-cpha;
+ vref-supply = <&adc_vref>;
+ interrupts = <25 IRQ_TYPE_EDGE_RISING>;
+ interrupt-parent = <&gpio>;
+ adi,sync-in-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+ clocks = <&ad7768_mclk>;
+ clock-names = "mclk";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ label = "channel_0";
+ };
+ };
+ };
+...
diff --git a/Bindings/iio/adc/adi,ad7780.yaml b/Bindings/iio/adc/adi,ad7780.yaml
new file mode 100644
index 0000000..5fcc8dd
--- /dev/null
+++ b/Bindings/iio/adc/adi,ad7780.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad7780.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD7170/AD7171/AD7780/AD7781 analog to digital converters
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+
+description: |
+ The ad7780 is a sigma-delta analog to digital converter. This driver provides
+ reading voltage values and status bits from both the ad778x and ad717x series.
+ Its interface also allows writing on the FILTER and GAIN GPIO pins on the
+ ad778x.
+
+ Specifications on the converters can be found at:
+ AD7170:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7170.pdf
+ AD7171:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7171.pdf
+ AD7780:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad7780.pdf
+ AD7781:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7781.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,ad7170
+ - adi,ad7171
+ - adi,ad7780
+ - adi,ad7781
+
+ reg:
+ maxItems: 1
+
+ avdd-supply:
+ description:
+ The regulator supply for the ADC reference voltage.
+
+ powerdown-gpios:
+ description:
+ Must be the device tree identifier of the PDRST pin. If
+ specified, it will be asserted during driver probe. As the
+ line is active high, it should be marked GPIO_ACTIVE_HIGH.
+ maxItems: 1
+
+ adi,gain-gpios:
+ description:
+ Must be the device tree identifier of the GAIN pin. Only for
+ the ad778x chips. If specified, it will be asserted during
+ driver probe. As the line is active low, it should be marked
+ GPIO_ACTIVE_LOW.
+ maxItems: 1
+
+ adi,filter-gpios:
+ description:
+ Must be the device tree identifier of the FILTER pin. Only
+ for the ad778x chips. If specified, it will be asserted
+ during driver probe. As the line is active low, it should be
+ marked GPIO_ACTIVE_LOW.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad7780";
+ reg = <0>;
+
+ avdd-supply = <&vdd_supply>;
+ powerdown-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ adi,gain-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+ adi,filter-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+ };
+ };
diff --git a/Bindings/iio/adc/adi,ad7923.yaml b/Bindings/iio/adc/adi,ad7923.yaml
new file mode 100644
index 0000000..8514833
--- /dev/null
+++ b/Bindings/iio/adc/adi,ad7923.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad7923.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD7923 and similars with 4 and 8 Channel ADCs.
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+
+description: |
+ Analog Devices AD7904, AD7914, AD7923, AD7924 4 Channel ADCs, and AD7908,
+ AD7918, AD7927, AD7928 8 Channels ADCs.
+
+ Specifications about the part can be found at:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7923.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7904_7914_7924.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7908_7918_7928.pdf
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - adi,ad7904
+ - adi,ad7908
+ - adi,ad7914
+ - adi,ad7918
+ - adi,ad7923
+ - adi,ad7928
+ - const: adi,ad7924
+ deprecated: true
+ - items:
+ - const: adi,ad7924
+ - const: adi,ad7923
+ - items:
+ - const: adi,ad7927
+ - const: adi,ad7928
+
+ reg:
+ maxItems: 1
+
+ refin-supply:
+ description: |
+ The regulator supply for ADC reference voltage.
+
+ adi,range-double:
+ description: Sets the analog input range from 0 to 2xVREF.
+ type: boolean
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ad7928: adc@0 {
+ compatible = "adi,ad7928";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ refin-supply = <&adc_vref>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
diff --git a/Bindings/iio/adc/adi,ad7949.yaml b/Bindings/iio/adc/adi,ad7949.yaml
new file mode 100644
index 0000000..9ee4d97
--- /dev/null
+++ b/Bindings/iio/adc/adi,ad7949.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad7949.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD7949/AD7682/AD7689 analog to digital converters
+
+maintainers:
+ - Charles-Antoine Couret <charles-antoine.couret@essensium.com>
+
+description: |
+ Specifications on the converters can be found at:
+ AD7949:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7949.pdf
+ AD7682/AD7698:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7682_7689.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,ad7682
+ - adi,ad7689
+ - adi,ad7949
+
+ reg:
+ maxItems: 1
+
+ vrefin-supply:
+ description:
+ Buffered ADC reference voltage supply.
+
+ vref-supply:
+ description:
+ Unbuffered ADC reference voltage supply.
+
+ adi,internal-ref-microvolt:
+ description: |
+ Internal reference voltage selection in microvolts.
+
+ If no internal reference is specified, the channel will default to the
+ external reference defined by vrefin-supply (or vref-supply).
+ vrefin-supply will take precedence over vref-supply if both are defined.
+
+ If no supplies are defined, the reference selection will default to
+ 4096mV internal reference.
+
+ enum: [2500000, 4096000]
+ default: 4096000
+
+
+ '#io-channel-cells':
+ const: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "adi,ad7949";
+ reg = <0>;
+ vref-supply = <&vdd_supply>;
+ };
+
+ adc@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "adi,ad7949";
+ reg = <1>;
+ vrefin-supply = <&vdd_supply>;
+ };
+
+ adc@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "adi,ad7949";
+ reg = <2>;
+ adi,internal-ref-microvolt = <4096000>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/adi,ad799x.yaml b/Bindings/iio/adc/adi,ad799x.yaml
new file mode 100644
index 0000000..433ed2c
--- /dev/null
+++ b/Bindings/iio/adc/adi,ad799x.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad799x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD799x analog to digital converters
+
+maintainers:
+ - Michael Hennerich <Michael.Hennerich@analog.com>
+
+description: |
+ Support for Analog Devices AD7991, AD7992, AD7993, AD7994, AD7995, AD7997, AD7998,
+ AD7999 and similar analog to digital converters.
+ Specifications on the converters can be found at:
+ AD7991, AD7995, AD7999:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7991_7995_7999.pdf
+ AD7992:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7992.pdf
+ AD7993, AD7994:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7993_7994.pdf
+ AD7997, AD7998:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7997_7998.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,ad7991
+ - adi,ad7992
+ - adi,ad7993
+ - adi,ad7994
+ - adi,ad7995
+ - adi,ad7997
+ - adi,ad7998
+ - adi,ad7999
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ vcc-supply:
+ description:
+ ADC power supply
+
+ vref-supply:
+ description:
+ ADC reference voltage supply, optional for AD7991, AD7995 and AD7999
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc1: adc@28 {
+ reg = <0x28>;
+ compatible = "adi,ad7991";
+ interrupts = <13 2>;
+ interrupt-parent = <&gpio6>;
+
+ vcc-supply = <&vcc_3v3>;
+ vref-supply = <&adc_vref>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/adi,ad9467.yaml b/Bindings/iio/adc/adi,ad9467.yaml
new file mode 100644
index 0000000..7aa748d
--- /dev/null
+++ b/Bindings/iio/adc/adi,ad9467.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad9467.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD9467 and similar High-Speed ADCs
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+
+description: |
+ The AD9467 and the parts similar with it, are high-speed analog-to-digital
+ converters (ADCs), operating in the range of 100 to 500 mega samples
+ per second (MSPS). Some parts support higher MSPS and some
+ lower MSPS, suitable for the intended application of each part.
+
+ All the parts support the register map described by Application Note AN-877
+ https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf
+
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD9265.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD9434.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD9467.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,ad9265
+ - adi,ad9434
+ - adi,ad9467
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: adc-clk
+
+ powerdown-gpios:
+ description:
+ Pin that controls the powerdown mode of the device.
+ maxItems: 1
+
+ reset-gpios:
+ description:
+ Reset pin for the device.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad9467";
+ reg = <0>;
+ clocks = <&adc_clk>;
+ clock-names = "adc-clk";
+ };
+ };
+...
diff --git a/Bindings/iio/adc/adi,axi-adc.yaml b/Bindings/iio/adc/adi,axi-adc.yaml
new file mode 100644
index 0000000..9996dd9
--- /dev/null
+++ b/Bindings/iio/adc/adi,axi-adc.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AXI ADC IP core
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+
+description: |
+ Analog Devices Generic AXI ADC IP core for interfacing an ADC device
+ with a high speed serial (JESD204B/C) or source synchronous parallel
+ interface (LVDS/CMOS).
+ Usually, some other interface type (i.e SPI) is used as a control
+ interface for the actual ADC, while this IP core will interface
+ to the data-lines of the ADC and handle the streaming of data into
+ memory via DMA.
+
+ https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
+
+properties:
+ compatible:
+ enum:
+ - adi,axi-adc-10.0.a
+
+ reg:
+ maxItems: 1
+
+ dmas:
+ maxItems: 1
+
+ dma-names:
+ items:
+ - const: rx
+
+ adi,adc-dev:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ A reference to a the actual ADC to which this FPGA ADC interfaces to.
+
+required:
+ - compatible
+ - dmas
+ - reg
+ - adi,adc-dev
+
+additionalProperties: false
+
+examples:
+ - |
+ axi-adc@44a00000 {
+ compatible = "adi,axi-adc-10.0.a";
+ reg = <0x44a00000 0x10000>;
+ dmas = <&rx_dma 0>;
+ dma-names = "rx";
+
+ adi,adc-dev = <&spi_adc>;
+ };
+...
diff --git a/Bindings/iio/adc/adi,max11410.yaml b/Bindings/iio/adc/adi,max11410.yaml
new file mode 100644
index 0000000..53f9fef
--- /dev/null
+++ b/Bindings/iio/adc/adi,max11410.yaml
@@ -0,0 +1,177 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2022 Analog Devices Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,max11410.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices MAX11410 ADC device driver
+
+maintainers:
+ - Ibrahim Tilki <Ibrahim.Tilki@analog.com>
+
+description: |
+ Bindings for the Analog Devices MAX11410 ADC device. Datasheet can be
+ found here:
+ https://datasheets.maximintegrated.com/en/ds/MAX11410.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,max11410
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+
+ interrupt-names:
+ description: Name of the gpio pin of max11410 used for IRQ
+ minItems: 1
+ items:
+ - enum: [gpio0, gpio1]
+ - const: gpio1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ avdd-supply:
+ description: Optional avdd supply. Used as reference when no explicit reference supplied.
+
+ vref0p-supply:
+ description: vref0p supply can be used as reference for conversion.
+
+ vref1p-supply:
+ description: vref1p supply can be used as reference for conversion.
+
+ vref2p-supply:
+ description: vref2p supply can be used as reference for conversion.
+
+ vref0n-supply:
+ description: vref0n supply can be used as reference for conversion.
+
+ vref1n-supply:
+ description: vref1n supply can be used as reference for conversion.
+
+ vref2n-supply:
+ description: vref2n supply can be used as reference for conversion.
+
+ spi-max-frequency:
+ maximum: 8000000
+
+patternProperties:
+ "^channel(@[0-9])?$":
+ $ref: adc.yaml
+ type: object
+ description: Represents the external channels which are connected to the ADC.
+
+ properties:
+ reg:
+ description: The channel number in single-ended mode.
+ minimum: 0
+ maximum: 9
+
+ adi,reference:
+ description: |
+ Select the reference source to use when converting on
+ the specific channel. Valid values are:
+ 0: VREF0P/VREF0N
+ 1: VREF1P/VREF1N
+ 2: VREF2P/VREF2N
+ 3: AVDD/AGND
+ 4: VREF0P/AGND
+ 5: VREF1P/AGND
+ 6: VREF2P/AGND
+ If this field is left empty, AVDD/AGND is selected.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3, 4, 5, 6]
+ default: 3
+
+ adi,input-mode:
+ description: |
+ Select signal path of input channels. Valid values are:
+ 0: Buffered, low-power, unity-gain path (default)
+ 1: Bypass path
+ 2: PGA path
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+ default: 0
+
+ diff-channels: true
+
+ bipolar: true
+
+ settling-time-us: true
+
+ adi,buffered-vrefp:
+ description: Enable buffered mode for positive reference.
+ type: boolean
+
+ adi,buffered-vrefn:
+ description: Enable buffered mode for negative reference.
+ type: boolean
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ reg = <0>;
+ compatible = "adi,max11410";
+ spi-max-frequency = <8000000>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "gpio1";
+
+ avdd-supply = <&adc_avdd>;
+
+ vref1p-supply = <&adc_vref1p>;
+ vref1n-supply = <&adc_vref1n>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ };
+
+ channel@1 {
+ reg = <1>;
+ diff-channels = <2 3>;
+ adi,reference = <1>;
+ bipolar;
+ settling-time-us = <100000>;
+ };
+
+ channel@2 {
+ reg = <2>;
+ diff-channels = <7 9>;
+ adi,reference = <5>;
+ adi,input-mode = <2>;
+ settling-time-us = <50000>;
+ };
+ };
+ };
diff --git a/Bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml b/Bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml
new file mode 100644
index 0000000..7ef46c9
--- /dev/null
+++ b/Bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/allwinner,sun20i-d1-gpadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner D1 General Purpose ADC
+
+maintainers:
+ - Maksim Kiselev <bigunclemax@gmail.com>
+
+properties:
+ compatible:
+ enum:
+ - allwinner,sun20i-d1-gpadc
+
+ "#io-channel-cells":
+ const: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+patternProperties:
+ "^channel@[0-9a-f]+$":
+ $ref: adc.yaml
+ type: object
+ description:
+ Represents the internal channels of the ADC.
+
+ properties:
+ reg:
+ items:
+ minimum: 0
+ maximum: 15
+
+ required:
+ - reg
+
+ unevaluatedProperties: false
+
+required:
+ - "#io-channel-cells"
+ - clocks
+ - compatible
+ - interrupts
+ - reg
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/sun20i-d1-ccu.h>
+ #include <dt-bindings/reset/sun20i-d1-ccu.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ gpadc: adc@2009000 {
+ compatible = "allwinner,sun20i-d1-gpadc";
+ reg = <0x2009000 0x400>;
+ clocks = <&ccu CLK_BUS_GPADC>;
+ resets = <&ccu RST_BUS_GPADC>;
+ interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ };
+
+ channel@1 {
+ reg = <1>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/allwinner,sun8i-a33-ths.yaml b/Bindings/iio/adc/allwinner,sun8i-a33-ths.yaml
new file mode 100644
index 0000000..a73a355
--- /dev/null
+++ b/Bindings/iio/adc/allwinner,sun8i-a33-ths.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/allwinner,sun8i-a33-ths.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A33 Thermal Sensor
+
+maintainers:
+ - Chen-Yu Tsai <wens@csie.org>
+ - Maxime Ripard <mripard@kernel.org>
+
+properties:
+ "#io-channel-cells":
+ const: 0
+
+ "#thermal-sensor-cells":
+ const: 0
+
+ compatible:
+ const: allwinner,sun8i-a33-ths
+
+ reg:
+ maxItems: 1
+
+required:
+ - "#io-channel-cells"
+ - "#thermal-sensor-cells"
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ ths: ths@1c25000 {
+ compatible = "allwinner,sun8i-a33-ths";
+ reg = <0x01c25000 0x100>;
+ #thermal-sensor-cells = <0>;
+ #io-channel-cells = <0>;
+ };
+
+...
diff --git a/Bindings/iio/adc/amlogic,meson-saradc.yaml b/Bindings/iio/adc/amlogic,meson-saradc.yaml
new file mode 100644
index 0000000..7e8328e
--- /dev/null
+++ b/Bindings/iio/adc/amlogic,meson-saradc.yaml
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/amlogic,meson-saradc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic Meson SAR (Successive Approximation Register) A/D converter
+
+maintainers:
+ - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+
+description:
+ Binding covers a range of ADCs found on Amlogic Meson SoCs.
+
+properties:
+ compatible:
+ oneOf:
+ - const: amlogic,meson-saradc
+ - items:
+ - enum:
+ - amlogic,meson8-saradc
+ - amlogic,meson8b-saradc
+ - amlogic,meson8m2-saradc
+ - amlogic,meson-gxbb-saradc
+ - amlogic,meson-gxl-saradc
+ - amlogic,meson-gxm-saradc
+ - amlogic,meson-axg-saradc
+ - amlogic,meson-g12a-saradc
+ - const: amlogic,meson-saradc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: Interrupt indicates end of sampling.
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 4
+
+ clock-names:
+ minItems: 2
+ items:
+ - const: clkin
+ - const: core
+ - const: adc_clk
+ - const: adc_sel
+
+ vref-supply: true
+
+ "#io-channel-cells":
+ const: 1
+
+ amlogic,hhi-sysctrl:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Syscon which contains the 5th bit of the TSC (temperature sensor
+ coefficient) on Meson8b and Meson8m2 (which used to calibrate the
+ temperature sensor)
+
+ nvmem-cells:
+ description: phandle to the temperature_calib eFuse cells
+ maxItems: 1
+
+ nvmem-cell-names:
+ const: temperature_calib
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - amlogic,meson8-saradc
+ - amlogic,meson8b-saradc
+ - amlogic,meson8m2-saradc
+ then:
+ properties:
+ clocks:
+ maxItems: 2
+ clock-names:
+ maxItems: 2
+ else:
+ properties:
+ nvmem-cells: false
+ mvmem-cel-names: false
+ clocks:
+ minItems: 4
+ clock-names:
+ minItems: 4
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - amlogic,meson8b-saradc
+ - amlogic,meson8m2-saradc
+ then:
+ properties:
+ amlogic,hhi-sysctrl: true
+ else:
+ properties:
+ amlogic,hhi-sysctrl: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/gxbb-clkc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ adc@8680 {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ reg = <0x0 0x8680 0x0 0x34>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "adc_clk", "adc_sel";
+ };
+ adc@9680 {
+ compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ reg = <0x0 0x9680 0x0 0x34>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
+ clock-names = "clkin", "core";
+ nvmem-cells = <&tsens_caldata>;
+ nvmem-cell-names = "temperature_calib";
+ amlogic,hhi-sysctrl = <&hhi>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/aspeed,ast2400-adc.yaml b/Bindings/iio/adc/aspeed,ast2400-adc.yaml
new file mode 100644
index 0000000..a726b6c
--- /dev/null
+++ b/Bindings/iio/adc/aspeed,ast2400-adc.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/aspeed,ast2400-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ADC that forms part of an ASPEED server management processor.
+
+maintainers:
+ - Joel Stanley <joel@jms.id.au>
+
+description:
+ This device is a 10-bit converter for 16 voltage channels. All inputs are
+ single ended.
+
+properties:
+ compatible:
+ enum:
+ - aspeed,ast2400-adc
+ - aspeed,ast2500-adc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description:
+ Input clock used to derive the sample clock. Expected to be the
+ SoC's APB clock.
+
+ resets:
+ maxItems: 1
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/aspeed-clock.h>
+ adc@1e6e9000 {
+ compatible = "aspeed,ast2400-adc";
+ reg = <0x1e6e9000 0xb0>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_ADC>;
+ #io-channel-cells = <1>;
+ };
+...
diff --git a/Bindings/iio/adc/aspeed,ast2600-adc.yaml b/Bindings/iio/adc/aspeed,ast2600-adc.yaml
new file mode 100644
index 0000000..5c08d8b
--- /dev/null
+++ b/Bindings/iio/adc/aspeed,ast2600-adc.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/aspeed,ast2600-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ADC that forms part of an ASPEED server management processor.
+
+maintainers:
+ - Billy Tsai <billy_tsai@aspeedtech.com>
+
+description: |
+ • 10-bits resolution for 16 voltage channels.
+ • The device split into two individual engine and each contains 8 voltage
+ channels.
+ • Channel scanning can be non-continuous.
+ • Programmable ADC clock frequency.
+ • Programmable upper and lower threshold for each channels.
+ • Interrupt when larger or less than threshold for each channels.
+ • Support hysteresis for each channels.
+ • Built-in a compensating method.
+ • Built-in a register to trim internal reference voltage.
+ • Internal or External reference voltage.
+ • Support 2 Internal reference voltage 1.2v or 2.5v.
+ • Integrate dividing circuit for battery sensing.
+
+properties:
+ compatible:
+ enum:
+ - aspeed,ast2600-adc0
+ - aspeed,ast2600-adc1
+ description:
+ Their trimming data, which is used to calibrate internal reference volage,
+ locates in different address of OTP.
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description:
+ Input clock used to derive the sample clock. Expected to be the
+ SoC's APB clock.
+
+ resets:
+ maxItems: 1
+
+ "#io-channel-cells":
+ const: 1
+
+ vref-supply:
+ description:
+ The external regulator supply ADC reference voltage.
+
+ aspeed,int-vref-microvolt:
+ enum: [1200000, 2500000]
+ description:
+ ADC internal reference voltage in microvolts.
+
+ aspeed,battery-sensing:
+ type: boolean
+ description:
+ Inform the driver that last channel will be used to sensor battery.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/ast2600-clock.h>
+ adc0: adc@1e6e9000 {
+ compatible = "aspeed,ast2600-adc0";
+ reg = <0x1e6e9000 0x100>;
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_ADC>;
+ #io-channel-cells = <1>;
+ aspeed,int-vref-microvolt = <2500000>;
+ };
+ adc1: adc@1e6e9100 {
+ compatible = "aspeed,ast2600-adc1";
+ reg = <0x1e6e9100 0x100>;
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_ADC>;
+ #io-channel-cells = <1>;
+ aspeed,int-vref-microvolt = <2500000>;
+ };
+...
diff --git a/Bindings/iio/adc/atmel,sama5d2-adc.yaml b/Bindings/iio/adc/atmel,sama5d2-adc.yaml
new file mode 100644
index 0000000..4817b84
--- /dev/null
+++ b/Bindings/iio/adc/atmel,sama5d2-adc.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/atmel,sama5d2-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AT91 SAMA5D2 Analog to Digital Converter (ADC)
+
+maintainers:
+ - Eugen Hristev <eugen.hristev@microchip.com>
+
+properties:
+ compatible:
+ enum:
+ - atmel,sama5d2-adc
+ - microchip,sam9x60-adc
+ - microchip,sama7g5-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: adc_clk
+
+ vref-supply: true
+ vddana-supply: true
+
+ atmel,min-sample-rate-hz:
+ description: Minimum sampling rate, it depends on SoC.
+
+ atmel,max-sample-rate-hz:
+ description: Maximum sampling rate, it depends on SoC.
+
+ atmel,startup-time-ms:
+ description: Startup time expressed in ms, it depends on SoC.
+
+ atmel,trigger-edge-type:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ One of possible edge types for the ADTRG hardware trigger pin.
+ When the specific edge type is detected, the conversion will
+ start. Should be one of IRQ_TYPE_EDGE_RISING, IRQ_TYPE_EDGE_FALLING
+ or IRQ_TYPE_EDGE_BOTH.
+ enum: [1, 2, 3]
+
+ dmas:
+ maxItems: 1
+
+ dma-names:
+ const: rx
+
+ "#io-channel-cells":
+ const: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - vref-supply
+ - vddana-supply
+ - atmel,min-sample-rate-hz
+ - atmel,max-sample-rate-hz
+ - atmel,startup-time-ms
+
+examples:
+ - |
+ #include <dt-bindings/dma/at91.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ adc@fc030000 {
+ compatible = "atmel,sama5d2-adc";
+ reg = <0xfc030000 0x100>;
+ interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&adc_clk>;
+ clock-names = "adc_clk";
+ atmel,min-sample-rate-hz = <200000>;
+ atmel,max-sample-rate-hz = <20000000>;
+ atmel,startup-time-ms = <4>;
+ vddana-supply = <&vdd_3v3_lp_reg>;
+ vref-supply = <&vdd_3v3_lp_reg>;
+ atmel,trigger-edge-type = <IRQ_TYPE_EDGE_BOTH>;
+ dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
+ dma-names = "rx";
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/atmel,sama9260-adc.yaml b/Bindings/iio/adc/atmel,sama9260-adc.yaml
new file mode 100644
index 0000000..1f30a85
--- /dev/null
+++ b/Bindings/iio/adc/atmel,sama9260-adc.yaml
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/atmel,sama9260-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AT91 sama9260 and similar Analog to Digital Converter (ADC)
+
+maintainers:
+ - Alexandre Belloni <alexandre.belloni@bootlin.com>
+
+properties:
+ compatible:
+ enum:
+ - atmel,at91sam9260-adc
+ - atmel,at91sam9rl-adc
+ - atmel,at91sam9g45-adc
+ - atmel,at91sam9x5-adc
+ - atmel,at91sama5d3-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: adc_clk
+ - const: adc_op_clk
+
+ atmel,adc-channels-used:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Bitmask of the channels muxed and enabled for this device
+
+ atmel,adc-startup-time:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Startup Time of the ADC in microseconds as defined in the datasheet
+
+ atmel,adc-vref:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Reference voltage in millivolts for the conversions
+
+ atmel,adc-use-external-triggers:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Enable the external triggers
+
+ atmel,adc-use-res:
+ $ref: /schemas/types.yaml#/definitions/string
+ description:
+ String corresponding to an identifier from atmel,adc-res-names property.
+ If not specified, the highest resolution will be used.
+ enum:
+ - lowres
+ - highres
+
+ atmel,adc-sleep-mode:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Enable sleep mode when no conversion
+
+ atmel,adc-sample-hold-time:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Sample and Hold Time in microseconds
+
+ atmel,adc-ts-wires:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Number of touchscreen wires. Must be set to enable touchscreen.
+ NOTE: when adc touchscreen is enabled, the adc hardware trigger will be
+ disabled. Since touchscreen will occupy the trigger register.
+ enum:
+ - 4
+ - 5
+
+ atmel,adc-ts-pressure-threshold:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Pressure threshold for touchscreen.
+
+ "#io-channel-cells":
+ const: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - atmel,adc-channels-used
+ - atmel,adc-startup-time
+ - atmel,adc-vref
+
+examples:
+ - |
+ #include <dt-bindings/dma/at91.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ adc@fffb0000 {
+ compatible = "atmel,at91sam9260-adc";
+ reg = <0xfffb0000 0x100>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&adc_clk>, <&adc_op_clk>;
+ clock-names = "adc_clk", "adc_op_clk";
+ atmel,adc-channels-used = <0xff>;
+ atmel,adc-startup-time = <40>;
+ atmel,adc-use-external-triggers;
+ atmel,adc-vref = <3300>;
+ atmel,adc-use-res = "lowres";
+ };
+ };
+...
diff --git a/Bindings/iio/adc/avia-hx711.yaml b/Bindings/iio/adc/avia-hx711.yaml
new file mode 100644
index 0000000..9c57eb1
--- /dev/null
+++ b/Bindings/iio/adc/avia-hx711.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/avia-hx711.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AVIA HX711 ADC chip for weight cells
+
+maintainers:
+ - Andreas Klinger <ak@it-klinger.de>
+
+description: |
+ Bit-banging driver using two GPIOs:
+ - sck-gpio gives a clock to the sensor with 24 cycles for data retrieval
+ and up to 3 cycles for selection of the input channel and gain for the
+ next measurement
+ - dout-gpio is the sensor data the sensor responds to the clock
+
+ Specifications about the driver can be found at:
+ http://www.aviaic.com/ENProducts.aspx
+
+properties:
+ compatible:
+ enum:
+ - avia,hx711
+
+ sck-gpios:
+ description:
+ Definition of the GPIO for the clock (output). In the datasheet it is
+ named PD_SCK
+ maxItems: 1
+
+ dout-gpios:
+ description:
+ Definition of the GPIO for the data-out sent by the sensor in
+ response to the clock (input).
+ See Documentation/devicetree/bindings/gpio/gpio.txt for information
+ on how to specify a consumer gpio.
+ maxItems: 1
+
+ avdd-supply:
+ description:
+ Definition of the regulator used as analog supply
+
+ clock-frequency:
+ minimum: 20000
+ maximum: 2500000
+ default: 400000
+
+required:
+ - compatible
+ - sck-gpios
+ - dout-gpios
+ - avdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ weight {
+ compatible = "avia,hx711";
+ sck-gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
+ dout-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+ avdd-supply = <&avdd>;
+ clock-frequency = <100000>;
+ };
diff --git a/Bindings/iio/adc/brcm,iproc-static-adc.yaml b/Bindings/iio/adc/brcm,iproc-static-adc.yaml
new file mode 100644
index 0000000..547697e
--- /dev/null
+++ b/Bindings/iio/adc/brcm,iproc-static-adc.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/brcm,iproc-static-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom's IPROC Static ADC controller
+
+maintainers:
+ - Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
+
+description: |
+ Broadcom iProc ADC controller has 8 10bit channels
+
+properties:
+ compatible:
+ const: brcm,iproc-static-adc
+
+ adc-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ syscon node defining physical base address of the controller and length
+ of memory mapped region.
+
+ "#io-channel-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: tsc_clk
+
+ interrupts:
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - adc-syscon
+ - "#io-channel-cells"
+ - clocks
+ - clock-names
+ - interrupts
+
+examples:
+ - |
+ #include <dt-bindings/clock/bcm-cygnus.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ adc {
+ compatible = "brcm,iproc-static-adc";
+ adc-syscon = <&ts_adc_syscon>;
+ #io-channel-cells = <1>;
+ clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
+ clock-names = "tsc_clk";
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/cirrus,ep9301-adc.yaml b/Bindings/iio/adc/cirrus,ep9301-adc.yaml
new file mode 100644
index 0000000..6d4fb3e
--- /dev/null
+++ b/Bindings/iio/adc/cirrus,ep9301-adc.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/cirrus,ep9301-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cirrus Logic EP930x internal ADC
+
+description: |
+ Cirrus Logic EP9301/EP9302 SoCs' internal ADC block.
+
+ User's manual:
+ https://cdn.embeddedts.com/resource-attachments/ts-7000_ep9301-ug.pdf
+
+maintainers:
+ - Alexander Sverdlin <alexander.sverdlin@gmail.com>
+
+properties:
+ compatible:
+ const: cirrus,ep9301-adc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ adc: adc@80900000 {
+ compatible = "cirrus,ep9301-adc";
+ reg = <0x80900000 0x28>;
+ clocks = <&syscon 24>;
+ interrupt-parent = <&vic1>;
+ interrupts = <30>;
+ };
+...
diff --git a/Bindings/iio/adc/cosmic,10001-adc.yaml b/Bindings/iio/adc/cosmic,10001-adc.yaml
new file mode 100644
index 0000000..4e695b9
--- /dev/null
+++ b/Bindings/iio/adc/cosmic,10001-adc.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/cosmic,10001-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cosmic Circuits CC-10001 ADC
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description:
+ Cosmic Circuits 10001 10-bit ADC device.
+
+properties:
+ compatible:
+ const: cosmic,10001-adc
+
+ reg:
+ maxItems: 1
+
+ adc-reserved-channels:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Bitmask of reserved channels, i.e. channels that cannot be
+ used by the OS.
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: adc
+
+ vref-supply: true
+
+ "#io-channel-cells":
+ const: 1
+
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - vref-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ adc@18101600 {
+ compatible = "cosmic,10001-adc";
+ reg = <0x18101600 0x24>;
+ adc-reserved-channels = <0x2>;
+ clocks = <&adc_clk>;
+ clock-names = "adc";
+ vref-supply = <®_1v8>;
+ };
+...
diff --git a/Bindings/iio/adc/dlg,da9150-gpadc.yaml b/Bindings/iio/adc/dlg,da9150-gpadc.yaml
new file mode 100644
index 0000000..cc29a2f
--- /dev/null
+++ b/Bindings/iio/adc/dlg,da9150-gpadc.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/dlg,da9150-gpadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Dialog Semiconductor DA9150 IIO GPADC
+
+maintainers:
+ - Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
+
+description:
+ This patch adds support for general purpose ADC within the
+ DA9150 Charger & Fuel-Gauge IC.
+
+properties:
+ compatible:
+ const: dlg,da9150-gpadc
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ adc {
+ compatible = "dlg,da9150-gpadc";
+ #io-channel-cells = <1>;
+ };
+...
diff --git a/Bindings/iio/adc/envelope-detector.yaml b/Bindings/iio/adc/envelope-detector.yaml
new file mode 100644
index 0000000..296d545
--- /dev/null
+++ b/Bindings/iio/adc/envelope-detector.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/envelope-detector.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ADC envelope detector using a DAC and a comparator
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |
+ The DAC is used to find the peak level of an alternating voltage input
+ signal by a binary search using the output of a comparator wired to
+ an interrupt pin. Like so:
+ _
+ | \
+ input +------>-------|+ \
+ | \
+ .-------. | }---.
+ | | | / |
+ | dac|-->--|- / |
+ | | |_/ |
+ | | |
+ | | |
+ | irq|------<-------'
+ | |
+ '-------'
+
+properties:
+ compatible:
+ const: axentia,tse850-envelope-detector
+
+ io-channels:
+ maxItems: 1
+ description: Channel node of the dac to be used for comparator input.
+
+ io-channel-names:
+ const: dac
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ const: comp
+
+required:
+ - compatible
+ - io-channels
+ - io-channel-names
+ - interrupts
+ - interrupt-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dpot: dpot@28 {
+ compatible = "microchip,mcp4651-104";
+ reg = <0x28>;
+ #io-channel-cells = <1>;
+ };
+ };
+
+ dac: dac {
+ compatible = "dpot-dac";
+ vref-supply = <®_3v3>;
+ io-channels = <&dpot 0>;
+ io-channel-names = "dpot";
+ #io-channel-cells = <1>;
+ };
+
+ envelope-detector {
+ compatible = "axentia,tse850-envelope-detector";
+ io-channels = <&dac 0>;
+ io-channel-names = "dac";
+
+ interrupt-parent = <&gpio>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "comp";
+ };
+...
diff --git a/Bindings/iio/adc/fsl,imx25-gcq.yaml b/Bindings/iio/adc/fsl,imx25-gcq.yaml
new file mode 100644
index 0000000..e910349
--- /dev/null
+++ b/Bindings/iio/adc/fsl,imx25-gcq.yaml
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/fsl,imx25-gcq.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale ADC GCQ device
+
+description:
+ This is a generic conversion queue device that can convert any of the
+ analog inputs using the ADC unit of the i.MX25.
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+properties:
+ compatible:
+ const: fsl,imx25-gcq
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ vref-ext-supply:
+ description:
+ The regulator supplying the ADC reference voltage.
+ Required when at least one subnode uses the this reference.
+
+ vref-xp-supply:
+ description:
+ The regulator supplying the ADC reference voltage on pin XP.
+ Required when at least one subnode uses this reference.
+
+ vref-yp-supply:
+ description:
+ The regulator supplying the ADC reference voltage on pin YP.
+ Required when at least one subnode uses this reference.
+
+ "#io-channel-cells":
+ const: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#address-cells"
+ - "#size-cells"
+
+patternProperties:
+ "[a-z][a-z0-9]+@[0-9a-f]+$":
+ type: object
+ description:
+ Child nodes used to define the reference voltages used for each channel
+
+ properties:
+ reg:
+ description: |
+ Number of the analog input.
+ 0: xp
+ 1: yp
+ 2: xn
+ 3: yn
+ 4: wiper
+ 5: inaux0
+ 6: inaux1
+ 7: inaux2
+ items:
+ - minimum: 0
+ maximum: 7
+
+ fsl,adc-refp:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Specifies the positive reference input as defined in
+ <dt-bindings/iio/adc/fsl-imx25-gcq.h>
+ 0: YP voltage reference
+ 1: XP voltage reference
+ 2: External voltage reference
+ 3: Internal voltage reference (default)
+ minimum: 0
+ maximum: 3
+
+ fsl,adc-refn:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Specifies the negative reference input as defined in
+ <dt-bindings/iio/adc/fsl-imx25-gcq.h>
+ 0: XN ground reference
+ 1: YN ground reference
+ 2: Internal ground reference
+ 3: External ground reference (default)
+ minimum: 0
+ maximum: 3
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/iio/adc/fsl-imx25-gcq.h>
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ adc@50030800 {
+ compatible = "fsl,imx25-gcq";
+ reg = <0x50030800 0x60>;
+ interrupt-parent = <&tscadc>;
+ interrupts = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ inaux@5 {
+ reg = <5>;
+ fsl,adc-refp = <MX25_ADC_REFP_INT>;
+ fsl,adc-refn = <MX25_ADC_REFN_NGND>;
+ };
+ };
+ };
+...
diff --git a/Bindings/iio/adc/fsl,imx7d-adc.yaml b/Bindings/iio/adc/fsl,imx7d-adc.yaml
new file mode 100644
index 0000000..afc5cc4
--- /dev/null
+++ b/Bindings/iio/adc/fsl,imx7d-adc.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/fsl,imx7d-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale ADC found on the imx7d SoC
+
+maintainers:
+ - Haibo Chen <haibo.chen@nxp.com>
+
+properties:
+ compatible:
+ const: fsl,imx7d-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: adc
+
+ vref-supply: true
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - vref-supply
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/imx7d-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ adc@30610000 {
+ compatible = "fsl,imx7d-adc";
+ reg = <0x30610000 0x10000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ADC_ROOT_CLK>;
+ clock-names = "adc";
+ vref-supply = <®_vcc_3v3_mcu>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/fsl,vf610-adc.yaml b/Bindings/iio/adc/fsl,vf610-adc.yaml
new file mode 100644
index 0000000..c770ff4
--- /dev/null
+++ b/Bindings/iio/adc/fsl,vf610-adc.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/fsl,vf610-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ADC found on Freescale vf610 and similar SoCs
+
+maintainers:
+ - Haibo Chen <haibo.chen@nxp.com>
+
+description:
+ ADCs found on vf610/i.MX6slx and upward SoCs from Freescale.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - fsl,imx6sx-adc
+ - fsl,imx6ul-adc
+ - const: fsl,vf610-adc
+ - items:
+ - const: fsl,vf610-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ description: ADC source clock (ipg clock)
+ maxItems: 1
+
+ clock-names:
+ const: adc
+
+ vref-supply:
+ description: ADC reference voltage supply.
+
+ fsl,adck-max-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 3
+ maxItems: 3
+ description: |
+ Maximum frequencies from datasheet operating requirements.
+ Three values necessary to cover the 3 conversion modes.
+ * Frequency in normal mode (ADLPC=0, ADHSC=0)
+ * Frequency in high-speed mode (ADLPC=0, ADHSC=1)
+ * Frequency in low-power mode (ADLPC=1, ADHSC=0)
+
+ min-sample-time:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Minimum sampling time in nanoseconds. This value has
+ to be chosen according to the conversion mode and the connected analog
+ source resistance (R_as) and capacitance (C_as). Refer the datasheet's
+ operating requirements. A safe default across a wide range of R_as and
+ C_as as well as conversion modes is 1000ns.
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - vref-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/vf610-clock.h>
+ adc@4003b000 {
+ compatible = "fsl,vf610-adc";
+ reg = <0x4003b000 0x1000>;
+ interrupts = <0 53 0x04>;
+ clocks = <&clks VF610_CLK_ADC0>;
+ clock-names = "adc";
+ fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>;
+ vref-supply = <®_vcc_3v3_mcu>;
+ min-sample-time = <10000>;
+ };
+...
diff --git a/Bindings/iio/adc/holt,hi8435.yaml b/Bindings/iio/adc/holt,hi8435.yaml
new file mode 100644
index 0000000..56bcbe5
--- /dev/null
+++ b/Bindings/iio/adc/holt,hi8435.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/holt,hi8435.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Holt Integrated Circuits HI-8435 SPI threshold detector
+
+maintainers:
+ - Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+
+description: |
+ Datasheet: http://www.holtic.com/documents/427-hi-8435_v-rev-lpdf.do
+
+properties:
+ compatible:
+ const: holt,hi8435
+
+ reg:
+ maxItems: 1
+
+ gpios:
+ description:
+ GPIO used for controlling the reset pin
+ maxItems: 1
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ threshold-detector@0 {
+ compatible = "holt,hi8435";
+ reg = <0>;
+ gpios = <&gpio6 1 0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/ingenic,adc.yaml b/Bindings/iio/adc/ingenic,adc.yaml
new file mode 100644
index 0000000..9cd0fd5
--- /dev/null
+++ b/Bindings/iio/adc/ingenic,adc.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019-2020 Artur Rojek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ingenic,adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ingenic JZ47xx ADC controller IIO
+
+maintainers:
+ - Artur Rojek <contact@artur-rojek.eu>
+
+description: >
+ Industrial I/O subsystem bindings for ADC controller found in
+ Ingenic JZ47xx SoCs.
+
+ ADC clients must use the format described in
+ https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml,
+ giving a phandle and IIO specifier pair ("io-channels") to the ADC controller.
+
+properties:
+ compatible:
+ enum:
+ - ingenic,jz4725b-adc
+ - ingenic,jz4740-adc
+ - ingenic,jz4760-adc
+ - ingenic,jz4760b-adc
+ - ingenic,jz4770-adc
+
+ '#io-channel-cells':
+ const: 1
+ description:
+ Must be set to <1> to indicate channels are selected by index.
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: adc
+
+ interrupts:
+ maxItems: 1
+
+ ingenic,use-internal-divider:
+ description:
+ If present, battery voltage is read from the VBAT_IR pin, which has an
+ internal 1/4 divider. If absent, it is read through the VBAT_ER pin,
+ which does not have such a divider.
+ type: boolean
+
+if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: ingenic,jz4760b-adc
+then:
+ properties:
+ ingenic,use-internal-divider: false
+
+required:
+ - compatible
+ - '#io-channel-cells'
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
+ #include <dt-bindings/iio/adc/ingenic,adc.h>
+
+ adc@10070000 {
+ compatible = "ingenic,jz4740-adc";
+ #io-channel-cells = <1>;
+
+ reg = <0x10070000 0x30>;
+
+ clocks = <&cgu JZ4740_CLK_ADC>;
+ clock-names = "adc";
+
+ interrupt-parent = <&intc>;
+ interrupts = <18>;
+ };
diff --git a/Bindings/iio/adc/lltc,ltc2496.yaml b/Bindings/iio/adc/lltc,ltc2496.yaml
new file mode 100644
index 0000000..5207c91
--- /dev/null
+++ b/Bindings/iio/adc/lltc,ltc2496.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/lltc,ltc2496.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Linear Technology / Analog Devices LTC2496 ADC
+
+maintainers:
+ - Lars-Peter Clausen <lars@metafoo.de>
+ - Michael Hennerich <Michael.Hennerich@analog.com>
+ - Stefan Popa <stefan.popa@analog.com>
+
+properties:
+ compatible:
+ enum:
+ - lltc,ltc2496
+
+ vref-supply:
+ description: Power supply for the reference voltage
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - vref-supply
+ - reg
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "lltc,ltc2496";
+ reg = <0>;
+ vref-supply = <<c2496_reg>;
+ spi-max-frequency = <2000000>;
+ };
+ };
diff --git a/Bindings/iio/adc/lltc,ltc2497.yaml b/Bindings/iio/adc/lltc,ltc2497.yaml
new file mode 100644
index 0000000..5cc6a96
--- /dev/null
+++ b/Bindings/iio/adc/lltc,ltc2497.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/lltc,ltc2497.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Linear Technology / Analog Devices LTC2497 and LTC2309 ADC
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+ - Liam Beguin <liambeguin@gmail.com>
+
+description: |
+ LTC2309:
+ low noise, low power, 8-channel, 12-bit successive approximation ADC with an
+ I2C compatible serial interface.
+
+ https://www.analog.com/media/en/technical-documentation/data-sheets/2309fd.pdf
+
+ LTC2497:
+ LTC2499:
+ 16bit ADC supporting up to 16 single ended or 8 differential inputs.
+ I2C interface.
+
+ https://www.analog.com/media/en/technical-documentation/data-sheets/2497fb.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/2499fe.pdf
+
+properties:
+ compatible:
+ enum:
+ - lltc,ltc2309
+ - lltc,ltc2497
+ - lltc,ltc2499
+
+ reg: true
+ vref-supply: true
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@76 {
+ compatible = "lltc,ltc2497";
+ reg = <0x76>;
+ vref-supply = <<c2497_reg>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/marvell,berlin2-adc.yaml b/Bindings/iio/adc/marvell,berlin2-adc.yaml
new file mode 100644
index 0000000..b3b292f
--- /dev/null
+++ b/Bindings/iio/adc/marvell,berlin2-adc.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/marvell,berlin2-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Berlin 2 Analog to Digital Converter (ADC)
+
+maintainers:
+ - Antoine Tenart <antoine.tenart@free-electrons.com>
+
+description:
+ The Berlin ADC has 8 channels, with one connected to a temperature sensor.
+ It is part of the system controller register set. The ADC node should be a
+ sub-node of the system controller node.
+
+properties:
+ compatible:
+ const: marvell,berlin2-adc
+
+ interrupts:
+ minItems: 2
+ maxItems: 2
+
+ interrupt-names:
+ items:
+ - const: adc
+ - const: tsen
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - interrupts
+ - interrupt-names
+
+additionalProperties: false
+
+examples:
+ - |
+ sysctrl {
+ adc {
+ compatible = "marvell,berlin2-adc";
+ interrupt-parent = <&sic>;
+ interrupts = <12>, <14>;
+ interrupt-names = "adc", "tsen";
+ };
+ };
+...
diff --git a/Bindings/iio/adc/maxim,max1027.yaml b/Bindings/iio/adc/maxim,max1027.yaml
new file mode 100644
index 0000000..e4b3621
--- /dev/null
+++ b/Bindings/iio/adc/maxim,max1027.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/maxim,max1027.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX1027 and similar ADCs
+
+maintainers:
+ - Miquel Raynal <miquel.raynal@bootlin.com>
+ - Philippe Reynes <tremyfr@yahoo.fr>
+
+description: |
+ 300ks/s SPI ADCs with temperature sensors.
+
+properties:
+ compatible:
+ enum:
+ # 10-bit 8 channels
+ - maxim,max1027
+ # 10-bit 12 channels
+ - maxim,max1029
+ # 10-bit 16 channels
+ - maxim,max1031
+ # 12-bit 8 channels
+ - maxim,max1227
+ # 12-bit 12 channels
+ - maxim,max1229
+ # 12-bit 16 channels
+ - maxim,max1231
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 10000000
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ maxadc: adc@0 {
+ compatible = "maxim,max1027";
+ reg = <0>;
+ #io-channel-cells = <1>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <15 IRQ_TYPE_EDGE_RISING>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/maxim,max11100.yaml b/Bindings/iio/adc/maxim,max11100.yaml
new file mode 100644
index 0000000..4f74cb3
--- /dev/null
+++ b/Bindings/iio/adc/maxim,max11100.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/maxim,max11100.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX11100 ADC
+
+maintainers:
+ - Jacopo Mondi <jacopo@jmondi.org>
+
+description: |
+ Single channel 16 bit ADC with SPI interface.
+
+properties:
+ compatible:
+ const: maxim,max11100
+
+ reg:
+ maxItems: 1
+
+ vref-supply:
+ description: External reference, needed to establish input scaling.
+
+ spi-max-frequency:
+ minimum: 100000
+ maximum: 4800000
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "maxim,max11100";
+ reg = <0>;
+ vref-supply = <&adc_vref>;
+ spi-max-frequency = <240000>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/maxim,max1118.yaml b/Bindings/iio/adc/maxim,max1118.yaml
new file mode 100644
index 0000000..bb336e3
--- /dev/null
+++ b/Bindings/iio/adc/maxim,max1118.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/maxim,max1118.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX1118 and similar ADCs
+
+maintainers:
+ - Akinobu Mita <akinobu.mita@gmail.com>
+
+description: |
+ Dual channel 8bit ADCs.
+
+properties:
+ compatible:
+ enum:
+ - maxim,max1117
+ - maxim,max1118
+ - maxim,max1119
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 5000000
+
+ vref-supply:
+ description: External reference, needed to establish input scaling
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: maxim,max1118
+ then:
+ required:
+ - vref-supply
+ else:
+ properties:
+ vref-supply: false
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "maxim,max1118";
+ reg = <0>;
+ vref-supply = <&adc_vref>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/maxim,max11205.yaml b/Bindings/iio/adc/maxim,max11205.yaml
new file mode 100644
index 0000000..5f9e043
--- /dev/null
+++ b/Bindings/iio/adc/maxim,max11205.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/maxim,max11205.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX11205 ADC
+
+maintainers:
+ - Ramona Bolboaca <ramona.bolboaca@analog.com>
+
+description: |
+ The MAX11205 is an ultra-low-power (< 300FA max active current),
+ high-resolution, serial-output ADC.
+
+ https://datasheets.maximintegrated.com/en/ds/MAX11205.pdf
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+ compatible:
+ enum:
+ - maxim,max11205a
+ - maxim,max11205b
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 5000000
+
+ spi-cpha: true
+
+ vref-supply:
+ description:
+ The regulator supply for the ADC reference voltage. This is a differential
+ reference. It is equal to the V_REFP - V_REFN. The maximum value is 3.6V.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - spi-max-frequency
+ - spi-cpha
+ - vref-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ adc@0 {
+ compatible = "maxim,max11205a";
+ reg = <0>;
+ spi-max-frequency = <5000000>;
+ spi-cpha;
+ interrupt-parent = <&gpio>;
+ interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
+ vref-supply = <&max11205_vref>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/maxim,max1238.yaml b/Bindings/iio/adc/maxim,max1238.yaml
new file mode 100644
index 0000000..60d7b34
--- /dev/null
+++ b/Bindings/iio/adc/maxim,max1238.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/maxim,max1238.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX1238 and similar ADCs
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description: |
+ Family of simple ADCs with i2c interface and internal references.
+
+properties:
+ compatible:
+ enum:
+ - maxim,max1036
+ - maxim,max1037
+ - maxim,max1038
+ - maxim,max1039
+ - maxim,max1136
+ - maxim,max1137
+ - maxim,max1138
+ - maxim,max1139
+ - maxim,max1236
+ - maxim,max1237
+ - maxim,max1238
+ - maxim,max1239
+ - maxim,max11600
+ - maxim,max11601
+ - maxim,max11602
+ - maxim,max11603
+ - maxim,max11604
+ - maxim,max11605
+ - maxim,max11606
+ - maxim,max11607
+ - maxim,max11608
+ - maxim,max11609
+ - maxim,max11610
+ - maxim,max11611
+ - maxim,max11612
+ - maxim,max11613
+ - maxim,max11614
+ - maxim,max11615
+ - maxim,max11616
+ - maxim,max11617
+ - maxim,max11644
+ - maxim,max11645
+ - maxim,max11646
+ - maxim,max11647
+
+ reg:
+ maxItems: 1
+
+ vcc-supply: true
+ vref-supply:
+ description: Optional external reference. If not supplied, internal
+ reference will be used.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@36 {
+ compatible = "maxim,max1238";
+ reg = <0x36>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/maxim,max1241.yaml b/Bindings/iio/adc/maxim,max1241.yaml
new file mode 100644
index 0000000..ef8d51e
--- /dev/null
+++ b/Bindings/iio/adc/maxim,max1241.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2020 Alexandru Lazar
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/maxim,max1241.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX1241 12-bit, single-channel analog to digital converter
+
+maintainers:
+ - Alexandru Lazar <alazar@startmail.com>
+
+description: |
+ Bindings for the max1241 12-bit, single-channel ADC device. Datasheet
+ can be found at:
+ https://datasheets.maximintegrated.com/en/ds/MAX1240-MAX1241.pdf
+
+properties:
+ compatible:
+ enum:
+ - maxim,max1241
+
+ reg:
+ maxItems: 1
+
+ vdd-supply:
+ description:
+ Device tree identifier of the regulator that powers the ADC.
+
+ vref-supply:
+ description:
+ Device tree identifier of the regulator that provides the external
+ reference voltage.
+
+ shutdown-gpios:
+ description:
+ GPIO spec for the GPIO pin connected to the ADC's /SHDN pin. If
+ specified, the /SHDN pin will be asserted between conversions,
+ thus enabling power-down mode.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+ - vref-supply
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "maxim,max1241";
+ reg = <0>;
+ vdd-supply = <&adc_vdd>;
+ vref-supply = <&adc_vref>;
+ spi-max-frequency = <1000000>;
+ shutdown-gpios = <&gpio 26 1>;
+ };
+ };
diff --git a/Bindings/iio/adc/maxim,max1363.yaml b/Bindings/iio/adc/maxim,max1363.yaml
new file mode 100644
index 0000000..96f3f53
--- /dev/null
+++ b/Bindings/iio/adc/maxim,max1363.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/maxim,max1363.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX1363 and similar ADCs
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description: |
+ Family of ADCs with i2c interface, internal references and threshold
+ monitoring.
+
+properties:
+ compatible:
+ enum:
+ - maxim,max1361
+ - maxim,max1362
+ - maxim,max1363
+ - maxim,max1364
+
+ reg:
+ maxItems: 1
+
+ vcc-supply: true
+ vref-supply:
+ description: Optional external reference. If not supplied, internal
+ reference will be used.
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@36 {
+ compatible = "maxim,max1363";
+ reg = <0x36>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/maxim,max9611.yaml b/Bindings/iio/adc/maxim,max9611.yaml
new file mode 100644
index 0000000..95774a5
--- /dev/null
+++ b/Bindings/iio/adc/maxim,max9611.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/maxim,max9611.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX9611 and similar current sense amplifiers with integrated ADCs
+
+maintainers:
+ - Jacopo Mondi <jacopo@jmondi.org>
+
+description: |
+ These devices combine a high-side current sense amplifier with a 12 bit ADC.
+ They have an i2c interface.
+
+properties:
+ compatible:
+ enum:
+ - maxim,max9611
+ - maxim,max9612
+
+ reg:
+ maxItems: 1
+
+ shunt-resistor-micro-ohms:
+ description: |
+ Value in micro Ohms of the shunt resistor connected between the RS+ and
+ RS- inputs, across which the current is measured. Value needed to compute
+ the scaling of the measured current.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - shunt-resistor-micro-ohms
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@7c {
+ compatible = "maxim,max9611";
+ reg = <0x7c>;
+ shunt-resistor-micro-ohms = <5000>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml b/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml
new file mode 100644
index 0000000..6168b44
--- /dev/null
+++ b/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/mediatek,mt2701-auxadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek AUXADC - ADC on Mediatek mobile SoC (mt65xx/mt81xx/mt27xx)
+
+maintainers:
+ - Zhiyong Tao <zhiyong.tao@mediatek.com>
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ The Auxiliary Analog/Digital Converter (AUXADC) is an ADC found
+ in some Mediatek SoCs which among other things measures the temperatures
+ in the SoC. It can be used directly with register accesses, but it is also
+ used by thermal controller which reads the temperatures from the AUXADC
+ directly via its own bus interface. See mediatek-thermal bindings
+ for the Thermal Controller which holds a phandle to the AUXADC.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - mediatek,mt2701-auxadc
+ - mediatek,mt2712-auxadc
+ - mediatek,mt6765-auxadc
+ - mediatek,mt7622-auxadc
+ - mediatek,mt7986-auxadc
+ - mediatek,mt8173-auxadc
+ - items:
+ - enum:
+ - mediatek,mt7623-auxadc
+ - const: mediatek,mt2701-auxadc
+ - items:
+ - enum:
+ - mediatek,mt8183-auxadc
+ - mediatek,mt8186-auxadc
+ - mediatek,mt8188-auxadc
+ - mediatek,mt8195-auxadc
+ - mediatek,mt8516-auxadc
+ - const: mediatek,mt8173-auxadc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: main
+
+ "#io-channel-cells":
+ const: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#io-channel-cells"
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ adc@11001000 {
+ compatible = "mediatek,mt8183-auxadc",
+ "mediatek,mt8173-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/mediatek,mt6360-adc.yaml b/Bindings/iio/adc/mediatek,mt6360-adc.yaml
new file mode 100644
index 0000000..db4e361
--- /dev/null
+++ b/Bindings/iio/adc/mediatek,mt6360-adc.yaml
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/mediatek,mt6360-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MT6360 and similar ADCs
+
+maintainers:
+ - Gene Chen <gene_chen@richtek.com>
+
+properties:
+ compatible:
+ const: mediatek,mt6360-adc
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ adc {
+ compatible = "mediatek,mt6360-adc";
+ #io-channel-cells = <1>;
+ };
+...
diff --git a/Bindings/iio/adc/microchip,mcp3201.yaml b/Bindings/iio/adc/microchip,mcp3201.yaml
new file mode 100644
index 0000000..18108f0
--- /dev/null
+++ b/Bindings/iio/adc/microchip,mcp3201.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/microchip,mcp3201.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip mcp3201 and similar ADCs
+
+maintainers:
+ - Oskar Andero <oskar.andero@gmail.com>
+
+description: |
+ Family of simple ADCs with a SPI interface.
+
+properties:
+ compatible:
+ enum:
+ - microchip,mcp3001
+ - microchip,mcp3002
+ - microchip,mcp3004
+ - microchip,mcp3008
+ - microchip,mcp3201
+ - microchip,mcp3202
+ - microchip,mcp3204
+ - microchip,mcp3208
+ - microchip,mcp3301
+ - microchip,mcp3550-50
+ - microchip,mcp3550-60
+ - microchip,mcp3551
+ - microchip,mcp3553
+
+ reg:
+ maxItems: 1
+
+ spi-cpha: true
+ spi-cpol: true
+
+ vref-supply:
+ description: External reference.
+
+ "#io-channel-cells":
+ const: 1
+
+dependencies:
+ spi-cpol: [ spi-cpha ]
+ spi-cpha: [ spi-cpol ]
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "microchip,mcp3002";
+ reg = <0>;
+ vref-supply = <&vref_reg>;
+ spi-cpha;
+ spi-cpol;
+ #io-channel-cells = <1>;
+ };
+ adc@1 {
+ compatible = "microchip,mcp3002";
+ reg = <1>;
+ vref-supply = <&vref_reg>;
+ spi-max-frequency = <1500000>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/microchip,mcp3564.yaml b/Bindings/iio/adc/microchip,mcp3564.yaml
new file mode 100644
index 0000000..6753192
--- /dev/null
+++ b/Bindings/iio/adc/microchip,mcp3564.yaml
@@ -0,0 +1,205 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/microchip,mcp3564.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MCP346X and MCP356X ADC Family
+
+maintainers:
+ - Marius Cristea <marius.cristea@microchip.com>
+
+description: |
+ Bindings for the Microchip family of 153.6 ksps, Low-Noise 16/24-Bit
+ Delta-Sigma ADCs with an SPI interface. Datasheet can be found here:
+ Datasheet for MCP3561, MCP3562, MCP3564 can be found here:
+ https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/ProductDocuments/DataSheets/MCP3561-2-4-Family-Data-Sheet-DS20006181C.pdf
+ Datasheet for MCP3561R, MCP3562R, MCP3564R can be found here:
+ https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/MCP3561_2_4R-Data-Sheet-DS200006391C.pdf
+ Datasheet for MCP3461, MCP3462, MCP3464 can be found here:
+ https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/MCP3461-2-4-Two-Four-Eight-Channel-153.6-ksps-Low-Noise-16-Bit-Delta-Sigma-ADC-Data-Sheet-20006180D.pdf
+ Datasheet for MCP3461R, MCP3462R, MCP3464R can be found here:
+ https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/MCP3461-2-4R-Family-Data-Sheet-DS20006404C.pdf
+
+properties:
+ compatible:
+ enum:
+ - microchip,mcp3461
+ - microchip,mcp3462
+ - microchip,mcp3464
+ - microchip,mcp3461r
+ - microchip,mcp3462r
+ - microchip,mcp3464r
+ - microchip,mcp3561
+ - microchip,mcp3562
+ - microchip,mcp3564
+ - microchip,mcp3561r
+ - microchip,mcp3562r
+ - microchip,mcp3564r
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 20000000
+
+ spi-cpha: true
+
+ spi-cpol: true
+
+ vdd-supply: true
+
+ avdd-supply: true
+
+ clocks:
+ description:
+ Phandle and clock identifier for external sampling clock.
+ If not specified, the internal crystal oscillator will be used.
+ maxItems: 1
+
+ interrupts:
+ description: IRQ line of the ADC
+ maxItems: 1
+
+ drive-open-drain:
+ description:
+ Whether to drive the IRQ signal as push-pull (default) or open-drain. Note
+ that the device requires this pin to become "high", otherwise it will stop
+ converting.
+ type: boolean
+
+ vref-supply:
+ description:
+ Some devices have a specific reference voltage supplied on a different
+ pin to the other supplies. Needed to be able to establish channel scaling
+ unless there is also an internal reference available (e.g. mcp3564r). In
+ case of "r" devices (e. g. mcp3564r), if it does not exists the internal
+ reference will be used.
+
+ microchip,hw-device-address:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3
+ description:
+ The address is set on a per-device basis by fuses in the factory,
+ configured on request. If not requested, the fuses are set for 0x1.
+ The device address is part of the device markings to avoid
+ potential confusion. This address is coded on two bits, so four possible
+ addresses are available when multiple devices are present on the same
+ SPI bus with only one Chip Select line for all devices.
+ Each device communication starts by a CS falling edge, followed by the
+ clocking of the device address (BITS[7:6] - top two bits of COMMAND BYTE
+ which is first one on the wire).
+
+ "#io-channel-cells":
+ const: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+patternProperties:
+ "^channel@([0-9]|([1-7][0-9]))$":
+ $ref: adc.yaml
+ type: object
+ unevaluatedProperties: false
+ description: Represents the external channels which are connected to the ADC.
+
+ properties:
+ reg:
+ description: The channel number in single-ended and differential mode.
+ minimum: 0
+ maximum: 79
+
+ required:
+ - reg
+
+dependencies:
+ spi-cpol: [ spi-cpha ]
+ spi-cpha: [ spi-cpol ]
+
+required:
+ - compatible
+ - reg
+ - microchip,hw-device-address
+ - spi-max-frequency
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+ - # External vref, no internal reference
+ if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - microchip,mcp3461
+ - microchip,mcp3462
+ - microchip,mcp3464
+ - microchip,mcp3561
+ - microchip,mcp3562
+ - microchip,mcp3564
+ then:
+ required:
+ - vref-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "microchip,mcp3564r";
+ reg = <0>;
+ vref-supply = <&vref_reg>;
+ spi-cpha;
+ spi-cpol;
+ spi-max-frequency = <10000000>;
+ microchip,hw-device-address = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ /* CH0 to AGND */
+ reg = <0>;
+ label = "CH0";
+ };
+
+ channel@1 {
+ /* CH1 to AGND */
+ reg = <1>;
+ label = "CH1";
+ };
+
+ /* diff-channels */
+ channel@11 {
+ reg = <11>;
+
+ /* CN0, CN1 */
+ diff-channels = <0 1>;
+ label = "CH0_CH1";
+ };
+
+ channel@22 {
+ reg = <0x22>;
+
+ /* CN1, CN2 */
+ diff-channels = <1 2>;
+ label = "CH1_CH3";
+ };
+
+ channel@23 {
+ reg = <0x23>;
+
+ /* CN1, CN3 */
+ diff-channels = <1 3>;
+ label = "CH1_CH3";
+ };
+ };
+ };
+...
diff --git a/Bindings/iio/adc/microchip,mcp3911.yaml b/Bindings/iio/adc/microchip,mcp3911.yaml
new file mode 100644
index 0000000..06951ec
--- /dev/null
+++ b/Bindings/iio/adc/microchip,mcp3911.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+# Copyright 2019 Marcus Folkesson <marcus.folkesson@gmail.com>
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/microchip,mcp3911.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MCP3911 Dual channel analog front end (ADC)
+
+maintainers:
+ - Marcus Folkesson <marcus.folkesson@gmail.com>
+ - Kent Gustavsson <nedo80@gmail.com>
+
+description: |
+ Bindings for the Microchip MCP3911 Dual channel ADC device. Datasheet can be
+ found here: https://ww1.microchip.com/downloads/en/DeviceDoc/20002286C.pdf
+
+properties:
+ compatible:
+ enum:
+ - microchip,mcp3910
+ - microchip,mcp3911
+ - microchip,mcp3912
+ - microchip,mcp3913
+ - microchip,mcp3914
+ - microchip,mcp3918
+ - microchip,mcp3919
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 20000000
+
+ clocks:
+ description: |
+ Phandle and clock identifier for external sampling clock.
+ If not specified, the internal crystal oscillator will be used.
+ maxItems: 1
+
+ interrupts:
+ description: IRQ line of the ADC
+ maxItems: 1
+
+ microchip,data-ready-hiz:
+ description:
+ Data Ready Pin Inactive State Control
+ true = The DR pin state is high-impedance
+ false = The DR pin state is logic high
+ type: boolean
+
+ microchip,device-addr:
+ description: Device address when multiple MCP3911 chips are present on the same SPI bus.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 0
+
+ vref-supply:
+ description: |
+ Phandle to the external reference voltage supply.
+ If not specified, the internal voltage reference (1.2V) will be used.
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "microchip,mcp3911";
+ reg = <0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <15 2>;
+ spi-max-frequency = <20000000>;
+ microchip,device-addr = <0>;
+ vref-supply = <&vref_reg>;
+ clocks = <&xtal>;
+ };
+ };
diff --git a/Bindings/iio/adc/motorola,cpcap-adc.yaml b/Bindings/iio/adc/motorola,cpcap-adc.yaml
new file mode 100644
index 0000000..9ceb6f1
--- /dev/null
+++ b/Bindings/iio/adc/motorola,cpcap-adc.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/motorola,cpcap-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Motorola CPCAP PMIC ADC
+
+maintainers:
+ - Tony Lindgren <tony@atomide.com>
+
+description:
+ On Motorola phones like droid 4 there is a custom CPCAP PMIC. This PMIC
+ has ADCs that are used for battery charging and USB PHY VBUS and ID pin
+ detection.
+
+properties:
+ compatible:
+ enum:
+ - motorola,cpcap-adc
+ - motorola,mapphone-cpcap-adc
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ const: adcdone
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - interrupts
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ pmic {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ adc {
+ compatible = "motorola,mapphone-cpcap-adc";
+ interrupt-parent = <&cpcap>;
+ interrupts = <8 IRQ_TYPE_NONE>;
+ interrupt-names = "adcdone";
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/nuvoton,nau7802.yaml b/Bindings/iio/adc/nuvoton,nau7802.yaml
new file mode 100644
index 0000000..04566ff
--- /dev/null
+++ b/Bindings/iio/adc/nuvoton,nau7802.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/nuvoton,nau7802.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton NAU7802 I2c Analog to Digital Converter (ADC)
+
+maintainers:
+ - Alexandre Belloni <alexandre.belloni@bootlin.com>
+ - Maxime Ripard <mripard@kernel.org>
+
+properties:
+ compatible:
+ const: nuvoton,nau7802
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ nuvoton,vldo:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Internal reference voltage in millivolts to be configured.
+ minimum: 2400
+ maximum: 4500
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nau7802@2a {
+ compatible = "nuvoton,nau7802";
+ reg = <0x2a>;
+ nuvoton,vldo = <3000>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/nuvoton,npcm750-adc.yaml b/Bindings/iio/adc/nuvoton,npcm750-adc.yaml
new file mode 100644
index 0000000..fede2aa
--- /dev/null
+++ b/Bindings/iio/adc/nuvoton,npcm750-adc.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/nuvoton,npcm750-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton NPCM BMC Analog to Digital Converter (ADC)
+
+maintainers:
+ - Tomer Maimon <tmaimon77@gmail.com>
+
+description:
+ The NPCM7XX ADC is a 10-bit converter and NPCM8XX ADC is a 12-bit converter,
+ both have eight channel inputs.
+
+properties:
+ compatible:
+ enum:
+ - nuvoton,npcm750-adc
+ - nuvoton,npcm845-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+ description: ADC interrupt, should be set for falling edge.
+
+ resets:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description: If not provided the defulat ADC sample rate will be used.
+
+ vref-supply:
+ description: If not supplied, the internal voltage reference will be used.
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
+ #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ adc@f000c000 {
+ compatible = "nuvoton,npcm750-adc";
+ reg = <0xf000c000 0x8>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk NPCM7XX_CLK_ADC>;
+ resets = <&rstc NPCM7XX_RESET_IPSRST1 NPCM7XX_RESET_ADC>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/nxp,imx8qxp-adc.yaml b/Bindings/iio/adc/nxp,imx8qxp-adc.yaml
new file mode 100644
index 0000000..0a192ca
--- /dev/null
+++ b/Bindings/iio/adc/nxp,imx8qxp-adc.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/nxp,imx8qxp-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP IMX8QXP ADC
+
+maintainers:
+ - Cai Huoqing <caihuoqing@baidu.com>
+
+description:
+ Supports the ADC found on the IMX8QXP SoC.
+
+properties:
+ compatible:
+ const: nxp,imx8qxp-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: per
+ - const: ipg
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-rates:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ vref-supply:
+ description: |
+ External ADC reference voltage supply on VREFH pad. If VERID[MVI] is
+ set, there are additional, internal reference voltages selectable.
+ VREFH1 is always from VREFH pad.
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - assigned-clocks
+ - assigned-clock-rates
+ - power-domains
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ adc@5a880000 {
+ compatible = "nxp,imx8qxp-adc";
+ reg = <0x0 0x5a880000 0x0 0x10000>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX_SC_R_ADC_0>,
+ <&clk IMX_SC_R_ADC_0>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_ADC_0>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_ADC_0>;
+ vref-supply = <®_1v8>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/nxp,imx93-adc.yaml b/Bindings/iio/adc/nxp,imx93-adc.yaml
new file mode 100644
index 0000000..dacc526
--- /dev/null
+++ b/Bindings/iio/adc/nxp,imx93-adc.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/nxp,imx93-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP iMX93 ADC
+
+maintainers:
+ - Haibo Chen <haibo.chen@nxp.com>
+
+description:
+ The ADC on iMX93 is a 8-channel 12-bit 1MS/s ADC with 4 channels
+ connected to pins. it support normal and inject mode, include
+ One-Shot and Scan (continuous) conversions. Programmable DMA
+ enables for each channel Also this ADC contain alternate analog
+ watchdog thresholds, select threshold through input ports. And
+ also has Self-test logic and Software-initiated calibration.
+
+properties:
+ compatible:
+ const: nxp,imx93-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: WDGnL, watchdog threshold interrupt requests.
+ - description: WDGnH, watchdog threshold interrupt requests.
+ - description: normal conversion, include EOC (End of Conversion),
+ ECH (End of Chain), JEOC (End of Injected Conversion) and
+ JECH (End of injected Chain).
+ - description: Self-testing Interrupts.
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: ipg
+
+ vref-supply:
+ description:
+ The reference voltage which used to establish channel scaling.
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - vref-supply
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/imx93-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ adc@44530000 {
+ compatible = "nxp,imx93-adc";
+ reg = <0x44530000 0x10000>;
+ interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_ADC1_GATE>;
+ clock-names = "ipg";
+ vref-supply = <®_vref_1v8>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/nxp,lpc1850-adc.yaml b/Bindings/iio/adc/nxp,lpc1850-adc.yaml
new file mode 100644
index 0000000..70b3803
--- /dev/null
+++ b/Bindings/iio/adc/nxp,lpc1850-adc.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/nxp,lpc1850-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP LPC1850 ADC
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description:
+ Supports the ADC found on the LPC1850 SoC.
+
+properties:
+ compatible:
+ const: nxp,lpc1850-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ vref-supply: true
+
+ resets:
+ maxItems: 1
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - vref-supply
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/lpc18xx-ccu.h>
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ adc@400e3000 {
+ compatible = "nxp,lpc1850-adc";
+ reg = <0x400e3000 0x1000>;
+ interrupts = <17>;
+ clocks = <&ccu1 CLK_APB3_ADC0>;
+ vref-supply = <®_vdda>;
+ resets = <&rgu 40>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/nxp,lpc3220-adc.yaml b/Bindings/iio/adc/nxp,lpc3220-adc.yaml
new file mode 100644
index 0000000..2c5032b
--- /dev/null
+++ b/Bindings/iio/adc/nxp,lpc3220-adc.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/nxp,lpc3220-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP LPC3220 SoC ADC controller
+
+maintainers:
+ - Gregory Clement <gregory.clement@bootlin.com>
+
+description:
+ This hardware block has been used on several LPC32XX SoCs.
+
+properties:
+ compatible:
+ const: nxp,lpc3220-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ vref-supply: true
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ adc@40048000 {
+ compatible = "nxp,lpc3220-adc";
+ reg = <0x40048000 0x1000>;
+ interrupt-parent = <&mic>;
+ interrupts = <39 0>;
+ vref-supply = <&vcc>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/qcom,pm8018-adc.yaml b/Bindings/iio/adc/qcom,pm8018-adc.yaml
new file mode 100644
index 0000000..58ea1ca
--- /dev/null
+++ b/Bindings/iio/adc/qcom,pm8018-adc.yaml
@@ -0,0 +1,166 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/qcom,pm8018-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm's PM8xxx voltage XOADC
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description: |
+ The Qualcomm PM8xxx PMICs contain a HK/XO ADC (Housekeeping/Crystal
+ oscillator ADC) encompassing PM8018, PM8038, PM8058 and PM8921.
+
+properties:
+ compatible:
+ enum:
+ - qcom,pm8018-adc
+ - qcom,pm8038-adc
+ - qcom,pm8058-adc
+ - qcom,pm8921-adc
+
+ reg:
+ maxItems: 1
+ description:
+ ADC base address in the PMIC, typically 0x197.
+
+ xoadc-ref-supply:
+ description:
+ The reference voltage may vary with PMIC variant but is typically
+ something like 2.2 or 1.8V.
+
+ interrupts:
+ maxItems: 1
+
+ "#address-cells":
+ const: 2
+ description:
+ The first cell is the prescaler (on PM8058) or premux (on PM8921)
+ with two valid bits so legal values are 0x00, 0x01 or 0x02.
+ The second cell is the main analog mux setting (0x00..0x0f).
+ The combination of prescaler/premux and analog mux uniquely addresses
+ a hardware channel on all systems.
+
+ "#size-cells":
+ const: 0
+
+ "#io-channel-cells":
+ const: 2
+ description:
+ The cells are precaler or premux followed by the analog muxing line.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#io-channel-cells"
+ - "#address-cells"
+ - "#size-cells"
+ - adc-channel@c
+ - adc-channel@d
+ - adc-channel@f
+
+patternProperties:
+ "^(adc-channel@)[0-9a-f]$":
+ type: object
+ description: |
+ ADC channel specific configuration.
+ Note that channels c, d and f must be present for calibration.
+ These three nodes are used for absolute and ratiometric calibration
+ and only need to have these reg values: they are by hardware definition
+ 1:1 ratio converters that sample 625, 1250 and 0 milliV and create
+ an interpolation calibration for all other ADCs.
+
+ properties:
+ reg:
+ maxItems: 1
+
+ qcom,decimation:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ This parameter is used to decrease the ADC sampling rate.
+ Quicker measurements can be made by reducing the decimation ratio.
+ Valid values are 512, 1024, 2048, 4096.
+ If the property is not found, a default value of 512 will be used.
+
+ qcom,ratiometric:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Channel calibration type. If this property is specified
+ VADC will use a special voltage references for channel
+ calibration. The available references are specified in the
+ as a u32 value setting (see below) and it is compulsory
+ to also specify this reference if ratiometric calibration
+ is selected.
+
+ If the property is not found, the channel will be
+ calibrated with the 0.625V and 1.25V reference channels, also
+ known as an absolute calibration.
+
+ The reference voltage pairs when using ratiometric calibration:
+ 0 = XO_IN/XOADC_GND
+ 1 = PMIC_IN/XOADC_GND
+ 2 = PMIC_IN/BMS_CSP
+ 3 (invalid)
+ 4 = XOADC_GND/XOADC_GND
+ 5 = XOADC_VREF/XOADC_GND
+
+ additionalProperties: false
+
+ required:
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ pmic {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@197 {
+ compatible = "qcom,pm8058-adc";
+ reg = <0x197>;
+ interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #io-channel-cells = <2>;
+
+ vcoin: adc-channel@0 {
+ reg = <0x00 0x00>;
+ };
+ vbat: adc-channel@1 {
+ reg = <0x00 0x01>;
+ };
+ dcin: adc-channel@2 {
+ reg = <0x00 0x02>;
+ };
+ ichg: adc-channel@3 {
+ reg = <0x00 0x03>;
+ };
+ vph_pwr: adc-channel@4 {
+ reg = <0x00 0x04>;
+ };
+ usb_vbus: adc-channel@a {
+ reg = <0x00 0x0a>;
+ };
+ die_temp: adc-channel@b {
+ reg = <0x00 0x0b>;
+ };
+ ref_625mv: adc-channel@c {
+ reg = <0x00 0x0c>;
+ };
+ ref_1250mv: adc-channel@d {
+ reg = <0x00 0x0d>;
+ };
+ ref_325mv: adc-channel@e {
+ reg = <0x00 0x0e>;
+ };
+ ref_muxoff: adc-channel@f {
+ reg = <0x00 0x0f>;
+ };
+ };
+ };
+...
diff --git a/Bindings/iio/adc/qcom,spmi-iadc.yaml b/Bindings/iio/adc/qcom,spmi-iadc.yaml
new file mode 100644
index 0000000..73def67
--- /dev/null
+++ b/Bindings/iio/adc/qcom,spmi-iadc.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-iadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm's SPMI PMIC current ADC
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description: |
+ QPNP PMIC current ADC (IADC) provides interface to clients to read current.
+ A 16 bit ADC is used for current measurements. IADC can measure the current
+ through an external resistor (channel 1) or internal (built-in) resistor
+ (channel 0). When using an external resistor it is to be described by
+ qcom,external-resistor-micro-ohms property.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,pm8226-iadc
+ - qcom,pm8941-iadc
+ - const: qcom,spmi-iadc
+
+ reg:
+ description: IADC base address and length in the SPMI PMIC register map
+ maxItems: 1
+
+ qcom,external-resistor-micro-ohms:
+ description:
+ Sensor resistor value. If not defined value of 10000 micro Ohms
+ will be used.
+
+ interrupts:
+ maxItems: 1
+ description:
+ End of conversion interrupt.
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spmi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pmic_iadc: adc@3600 {
+ compatible = "qcom,pm8941-iadc", "qcom,spmi-iadc";
+ reg = <0x3600>;
+ interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>;
+ qcom,external-resistor-micro-ohms = <10000>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/qcom,spmi-rradc.yaml b/Bindings/iio/adc/qcom,spmi-rradc.yaml
new file mode 100644
index 0000000..b3a6263
--- /dev/null
+++ b/Bindings/iio/adc/qcom,spmi-rradc.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-rradc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm's SPMI PMIC Round Robin ADC
+
+maintainers:
+ - Caleb Connolly <caleb.connolly@linaro.org>
+
+description: |
+ The Qualcomm SPMI Round Robin ADC (RRADC) provides interface to clients to
+ read the voltage, current and temperature for supported peripherals such as
+ the battery thermistor die temperature, charger temperature, USB and DC input
+ voltage / current and battery ID resistor.
+
+properties:
+ compatible:
+ enum:
+ - qcom,pmi8998-rradc
+ - qcom,pm660-rradc
+
+ reg:
+ maxItems: 1
+
+ qcom,batt-id-delay-ms:
+ description: Sets the hardware settling time for the battery ID resistor.
+ enum: [0, 1, 4, 12, 20, 40, 60, 80]
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ pmic {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic_rradc: adc@4500 {
+ compatible = "qcom,pmi8998-rradc";
+ reg = <0x4500>;
+ #io-channel-cells = <1>;
+ };
+ };
diff --git a/Bindings/iio/adc/qcom,spmi-vadc.yaml b/Bindings/iio/adc/qcom,spmi-vadc.yaml
new file mode 100644
index 0000000..ad7d6fc
--- /dev/null
+++ b/Bindings/iio/adc/qcom,spmi-vadc.yaml
@@ -0,0 +1,309 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm's SPMI PMIC ADC
+
+maintainers:
+ - Andy Gross <agross@kernel.org>
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description: |
+ SPMI PMIC voltage ADC (VADC) provides interface to clients to read
+ voltage. The VADC is a 15-bit sigma-delta ADC.
+ SPMI PMIC5/PMIC7 voltage ADC (ADC) provides interface to clients to read
+ voltage. The VADC is a 16-bit sigma-delta ADC.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: qcom,pms405-adc
+ - const: qcom,spmi-adc-rev2
+ - enum:
+ - qcom,spmi-vadc
+ - qcom,spmi-adc5
+ - qcom,spmi-adc-rev2
+ - qcom,spmi-adc7
+
+ reg:
+ description: VADC base address in the SPMI PMIC register map
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ '#io-channel-cells':
+ const: 1
+
+ interrupts:
+ maxItems: 1
+ description:
+ End of conversion interrupt.
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+ - '#io-channel-cells'
+
+patternProperties:
+ "^channel@[0-9a-f]+$":
+ type: object
+ additionalProperties: false
+ description: |
+ Represents the external channels which are connected to the ADC.
+ For compatible property "qcom,spmi-vadc" following channels, also known as
+ reference point channels, are used for result calibration and their channel
+ configuration nodes should be defined:
+ VADC_REF_625MV and/or VADC_SPARE1(based on PMIC version) VADC_REF_1250MV,
+ VADC_GND_REF and VADC_VDD_VADC.
+
+ properties:
+ reg:
+ maxItems: 1
+ description: |
+ ADC channel number.
+ See include/dt-bindings/iio/qcom,spmi-vadc.h
+ For PMIC7 ADC, the channel numbers are specified separately per PMIC
+ in the PMIC-specific files in include/dt-bindings/iio/.
+
+ label:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: |
+ ADC input of the platform as seen in the schematics.
+ For thermistor inputs connected to generic AMUX or GPIO inputs
+ these can vary across platform for the same pins. Hence select
+ the platform schematics name for this channel.
+
+ qcom,decimation:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ This parameter is used to decrease ADC sampling rate.
+ Quicker measurements can be made by reducing decimation ratio.
+
+ qcom,pre-scaling:
+ description: |
+ Used for scaling the channel input signal before the signal is
+ fed to VADC. The configuration for this node is to know the
+ pre-determined ratio and use it for post scaling. It is a pair of
+ integers, denoting the numerator and denominator of the fraction by which
+ input signal is multiplied. For example, <1 3> indicates the signal is scaled
+ down to 1/3 of its value before ADC measurement.
+ If property is not found default value depending on chip will be used.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ oneOf:
+ - items:
+ - const: 1
+ - enum: [ 1, 3, 4, 6, 20, 8, 10, 16 ]
+ - items:
+ - const: 10
+ - const: 81
+
+ qcom,ratiometric:
+ description: |
+ Channel calibration type.
+ - For compatible property "qcom,spmi-vadc", if this property is
+ specified VADC will use the VDD reference (1.8V) and GND for
+ channel calibration. If property is not found, channel will be
+ calibrated with 0.625V and 1.25V reference channels, also
+ known as absolute calibration.
+ - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" and
+ "qcom,spmi-adc-rev2", if this property is specified VADC will use
+ the VDD reference (1.875V) and GND for channel calibration. If
+ property is not found, channel will be calibrated with 0V and 1.25V
+ reference channels, also known as absolute calibration.
+ type: boolean
+
+ qcom,hw-settle-time:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Time between AMUX getting configured and the ADC starting
+ conversion. The 'hw_settle_time' is an index used from valid values
+ and programmed in hardware to achieve the hardware settling delay.
+
+ qcom,avg-samples:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Number of samples to be used for measurement.
+ Averaging provides the option to obtain a single measurement
+ from the ADC that is an average of multiple samples. The value
+ selected is 2^(value).
+
+ required:
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,spmi-vadc
+
+ then:
+ patternProperties:
+ "^channel@[0-9a-f]+$":
+ properties:
+ qcom,decimation:
+ enum: [ 512, 1024, 2048, 4096 ]
+ default: 512
+
+ qcom,hw-settle-time:
+ enum: [ 0, 100, 200, 300, 400, 500, 600, 700, 800, 900, 1, 2,
+ 4, 6, 8, 10 ]
+ default: 0
+
+ qcom,avg-samples:
+ enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 ]
+ default: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,spmi-adc-rev2
+
+ then:
+ patternProperties:
+ "^channel@[0-9a-f]+$":
+ properties:
+ qcom,decimation:
+ enum: [ 256, 512, 1024 ]
+ default: 1024
+
+ qcom,hw-settle-time:
+ enum: [ 0, 100, 200, 300, 400, 500, 600, 700, 800, 900, 1, 2,
+ 4, 6, 8, 10 ]
+ default: 0
+
+ qcom,avg-samples:
+ enum: [ 1, 2, 4, 8, 16 ]
+ default: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,spmi-adc5
+
+ then:
+ patternProperties:
+ "^channel@[0-9a-f]+$":
+ properties:
+ qcom,decimation:
+ enum: [ 250, 420, 840 ]
+ default: 840
+
+ qcom,hw-settle-time:
+ enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 800, 900, 1, 2,
+ 4, 6, 8, 10, 16, 32, 64, 128 ]
+ default: 15
+
+ qcom,avg-samples:
+ enum: [ 1, 2, 4, 8, 16 ]
+ default: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,spmi-adc7
+
+ then:
+ patternProperties:
+ "^channel@[0-9a-f]+$":
+ properties:
+ qcom,decimation:
+ enum: [ 85, 340, 1360 ]
+ default: 1360
+
+ qcom,hw-settle-time:
+ enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000,
+ 8000, 16000, 32000, 64000, 128000 ]
+ default: 15
+
+ qcom,avg-samples:
+ enum: [ 1, 2, 4, 8, 16 ]
+ default: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ spmi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* VADC node */
+ pmic_vadc: adc@3100 {
+ compatible = "qcom,spmi-vadc";
+ reg = <0x3100>;
+ interrupts = <0x0 0x31 0x0 0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ /* Channel node */
+ channel@39 {
+ reg = <0x39>;
+ qcom,decimation = <512>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,avg-samples = <1>;
+ qcom,pre-scaling = <1 3>;
+ };
+
+ channel@9 {
+ reg = <0x9>;
+ };
+
+ channel@a {
+ reg = <0xa>;
+ };
+
+ channel@e {
+ reg = <0xe>;
+ };
+
+ channel@f {
+ reg = <0xf>;
+ };
+ };
+ };
+
+ - |
+ #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+ #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ spmi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ adc@3100 {
+ reg = <0x3100>;
+ compatible = "qcom,spmi-adc7";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ /* Other properties are omitted */
+ channel@44 {
+ reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ label = "xo_therm";
+ };
+
+ channel@47 {
+ reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ label = "conn_therm";
+ };
+ };
+ };
diff --git a/Bindings/iio/adc/renesas,rcar-gyroadc.yaml b/Bindings/iio/adc/renesas,rcar-gyroadc.yaml
new file mode 100644
index 0000000..36dff32
--- /dev/null
+++ b/Bindings/iio/adc/renesas,rcar-gyroadc.yaml
@@ -0,0 +1,141 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/renesas,rcar-gyroadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car GyroADC
+
+maintainers:
+ - Marek Vasut <marek.vasut+renesas@gmail.com>
+
+description: |
+ The GyroADC block is a reduced SPI block with up to 8 chipselect lines,
+ which supports the SPI protocol of a selected few SPI ADCs. The SPI ADCs
+ are sampled by the GyroADC block in a round-robin fashion and the result
+ presented in the GyroADC registers.
+ The ADC bindings should match with that of the devices connected to a
+ full featured SPI bus.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r8a7791-gyroadc
+ - renesas,r8a7792-gyroadc
+ - const: renesas,rcar-gyroadc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: fck
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+ - "#address-cells"
+ - "#size-cells"
+
+patternProperties:
+ "@[0-7]$":
+ type: object
+ properties:
+ compatible:
+ description: |
+ fujitsu,mb88101a
+ - Fujitsu MB88101A compatible mode,
+ 12bit sampling, up to 4 channels can be sampled in round-robin
+ fashion. One Fujitsu chip supplies four GyroADC channels with
+ data as it contains four ADCs on the chip and thus for 4-channel
+ operation, single MB88101A is required. The Cx chipselect lines
+ of the MB88101A connect directly to two CHS lines of the GyroADC,
+ no demuxer is required. The data out line of each MB88101A
+ connects to a shared input pin of the GyroADC.
+ ti,adcs7476 or ti,adc121 or adi,ad7476
+ - TI ADCS7476 / TI ADC121 / ADI AD7476 compatible mode, 15bit
+ sampling, up to 8 channels can be sampled in round-robin
+ fashion. One TI/ADI chip supplies single ADC channel with data,
+ thus for 8-channel operation, 8 chips are required.
+ A 3:8 chipselect demuxer is required to connect the nCS line
+ of the TI/ADI chips to the GyroADC, while MISO line of each
+ TI/ADI ADC connects to a shared input pin of the GyroADC.
+ maxim,max1162 or maxim,max11100
+ - Maxim MAX1162 / Maxim MAX11100 compatible mode, 16bit sampling,
+ up to 8 channels can be sampled in round-robin fashion. One
+ Maxim chip supplies single ADC channel with data, thus for
+ 8-channel operation, 8 chips are required.
+ A 3:8 chipselect demuxer is required to connect the nCS line
+ of the MAX chips to the GyroADC, while MISO line of each Maxim
+ ADC connects to a shared input pin of the GyroADC.
+ enum:
+ - adi,ad7476
+ - fujitsu,mb88101a
+ - maxim,max1162
+ - maxim,max11100
+ - ti,adcs7476
+ - ti,adc121
+
+ reg:
+ minimum: 0
+ maximum: 7
+
+ vref-supply: true
+
+ additionalProperties: false
+
+ required:
+ - compatible
+ - reg
+ - vref-supply
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
+ #include <dt-bindings/power/r8a7791-sysc.h>
+
+ adc@e6e54000 {
+ compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc";
+ reg = <0xe6e54000 64>;
+ clocks = <&cpg CPG_MOD 901>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 901>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ reg = <0>;
+ compatible = "maxim,max1162";
+ vref-supply = <&vref_max1162>;
+ };
+
+ adc@1 {
+ reg = <1>;
+ compatible = "maxim,max1162";
+ vref-supply = <&vref_max1162>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/renesas,rzg2l-adc.yaml b/Bindings/iio/adc/renesas,rzg2l-adc.yaml
new file mode 100644
index 0000000..ba86c7b
--- /dev/null
+++ b/Bindings/iio/adc/renesas,rzg2l-adc.yaml
@@ -0,0 +1,155 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L ADC
+
+maintainers:
+ - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+
+description: |
+ A/D Converter block is a successive approximation analog-to-digital converter
+ with a 12-bit accuracy. Up to eight analog input channels can be selected.
+ Conversions can be performed in single or repeat mode. Result of the ADC is
+ stored in a 32-bit data register corresponding to each channel.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a07g043-adc # RZ/G2UL and RZ/Five
+ - renesas,r9a07g044-adc # RZ/G2L
+ - renesas,r9a07g054-adc # RZ/V2L
+ - const: renesas,rzg2l-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: converter clock
+ - description: peripheral clock
+
+ clock-names:
+ items:
+ - const: adclk
+ - const: pclk
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: presetn
+ - const: adrst-n
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+ - reset-names
+
+patternProperties:
+ "^channel@[0-7]$":
+ $ref: adc.yaml
+ type: object
+ description: |
+ Represents the external channels which are connected to the ADC.
+
+ properties:
+ reg:
+ description: |
+ The channel number.
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a07g043-adc
+ then:
+ patternProperties:
+ "^channel@[2-7]$": false
+ "^channel@[0-1]$":
+ properties:
+ reg:
+ minimum: 0
+ maximum: 1
+ else:
+ patternProperties:
+ "^channel@[0-7]$":
+ properties:
+ reg:
+ minimum: 0
+ maximum: 7
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ adc: adc@10059000 {
+ compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
+ reg = <0x10059000 0x400>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
+ <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
+ clock-names = "adclk", "pclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_ADC_PRESETN>,
+ <&cpg R9A07G044_ADC_ADRST_N>;
+ reset-names = "presetn", "adrst-n";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ };
+ channel@1 {
+ reg = <1>;
+ };
+ channel@2 {
+ reg = <2>;
+ };
+ channel@3 {
+ reg = <3>;
+ };
+ channel@4 {
+ reg = <4>;
+ };
+ channel@5 {
+ reg = <5>;
+ };
+ channel@6 {
+ reg = <6>;
+ };
+ channel@7 {
+ reg = <7>;
+ };
+ };
diff --git a/Bindings/iio/adc/richtek,rtq6056.yaml b/Bindings/iio/adc/richtek,rtq6056.yaml
new file mode 100644
index 0000000..88e0086
--- /dev/null
+++ b/Bindings/iio/adc/richtek,rtq6056.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/richtek,rtq6056.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RTQ6056 Bi-Directional Current and Power Monitor with 16-bit ADC
+
+maintainers:
+ - ChiYuan Huang <cy_huang@richtek.com>
+
+description: |
+ The RTQ6056 is a high accuracy current-sense monitor with I2C and SMBus
+ interface, and the device provides full information for system by reading
+ out the loading current and power.
+
+ The device monitors both of the drops across sense resistor and the BUS
+ voltage, converts into the current in amperes, and power in watts through
+ internal analog-to-digital converter ADC. The programmable calibration,
+ adjustable conversion time, and averaging function are also built in for
+ more design flexibility.
+
+ Datasheet is available at
+ https://www.richtek.com/assets/product_file/RTQ6056/DSQ6056-00.pdf
+
+properties:
+ compatible:
+ const: richtek,rtq6056
+
+ reg:
+ maxItems: 1
+
+ "#io-channel-cells":
+ const: 1
+
+ shunt-resistor-micro-ohms:
+ description: Shunt IN+/IN- sensing node resistor
+
+required:
+ - compatible
+ - reg
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ adc@40 {
+ compatible = "richtek,rtq6056";
+ reg = <0x40>;
+ #io-channel-cells = <1>;
+ };
+ };
diff --git a/Bindings/iio/adc/rockchip-saradc.yaml b/Bindings/iio/adc/rockchip-saradc.yaml
new file mode 100644
index 0000000..aa24b84
--- /dev/null
+++ b/Bindings/iio/adc/rockchip-saradc.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/rockchip-saradc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip Successive Approximation Register (SAR) A/D Converter
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ oneOf:
+ - const: rockchip,saradc
+ - const: rockchip,rk3066-tsadc
+ - const: rockchip,rk3399-saradc
+ - const: rockchip,rk3588-saradc
+ - items:
+ - enum:
+ - rockchip,px30-saradc
+ - rockchip,rk3308-saradc
+ - rockchip,rk3328-saradc
+ - rockchip,rk3568-saradc
+ - rockchip,rv1108-saradc
+ - rockchip,rv1126-saradc
+ - const: rockchip,rk3399-saradc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: converter clock
+ - description: peripheral clock
+
+ clock-names:
+ items:
+ - const: saradc
+ - const: apb_pclk
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: saradc-apb
+
+ vref-supply:
+ description:
+ The regulator supply for the ADC reference voltage.
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - vref-supply
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3288-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ saradc: saradc@2006c000 {
+ compatible = "rockchip,saradc";
+ reg = <0x2006c000 0x100>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_SARADC>;
+ reset-names = "saradc-apb";
+ vref-supply = <&vcc18>;
+ #io-channel-cells = <1>;
+ };
diff --git a/Bindings/iio/adc/samsung,exynos-adc.yaml b/Bindings/iio/adc/samsung,exynos-adc.yaml
new file mode 100644
index 0000000..582d0a0
--- /dev/null
+++ b/Bindings/iio/adc/samsung,exynos-adc.yaml
@@ -0,0 +1,163 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/samsung,exynos-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos Analog to Digital Converter (ADC)
+
+maintainers:
+ - Krzysztof Kozlowski <krzk@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos-adc-v1 # Exynos5250
+ - samsung,exynos-adc-v2
+ - samsung,exynos3250-adc
+ - samsung,exynos4212-adc # Exynos4212 and Exynos4412
+ - samsung,exynos7-adc
+ - samsung,s3c2410-adc
+ - samsung,s3c2416-adc
+ - samsung,s3c2440-adc
+ - samsung,s3c2443-adc
+ - samsung,s3c6410-adc
+ - samsung,s5pv210-adc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description:
+ Phandle to ADC bus clock. For Exynos3250 additional clock is needed.
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ description:
+ Must contain clock names (adc, sclk) matching phandles in clocks
+ property.
+ minItems: 1
+ maxItems: 2
+
+ interrupts:
+ description:
+ ADC interrupt followed by optional touchscreen interrupt.
+ minItems: 1
+ maxItems: 2
+
+ "#io-channel-cells":
+ const: 1
+
+ vdd-supply: true
+
+ samsung,syscon-phandle:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the PMU system controller node (to access the ADC_PHY
+ register on Exynos3250/4x12/5250/5420/5800).
+
+ has-touchscreen:
+ description:
+ If present, indicates that a touchscreen is connected and usable.
+ type: boolean
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - "#io-channel-cells"
+ - vdd-supply
+
+additionalProperties:
+ type: object
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynos-adc-v1
+ - samsung,exynos-adc-v2
+ - samsung,exynos3250-adc
+ - samsung,exynos4212-adc
+ then:
+ required:
+ - samsung,syscon-phandle
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynos3250-adc
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: adc
+ - const: sclk
+ else:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+ clock-names:
+ items:
+ - const: adc
+
+ - if:
+ required:
+ - has-touchscreen
+ then:
+ properties:
+ interrupts:
+ minItems: 2
+ maxItems: 2
+
+examples:
+ - |
+ adc: adc@12d10000 {
+ compatible = "samsung,exynos-adc-v1";
+ reg = <0x12d10000 0x100>;
+ interrupts = <0 106 0>;
+ #io-channel-cells = <1>;
+
+ clocks = <&clock 303>;
+ clock-names = "adc";
+
+ vdd-supply = <&buck5_reg>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+
+ /* NTC thermistor is a hwmon device */
+ thermistor {
+ compatible = "murata,ncp15wb473";
+ pullup-uv = <1800000>;
+ pullup-ohm = <47000>;
+ pulldown-ohm = <0>;
+ io-channels = <&adc 4>;
+ };
+ };
+
+ - |
+ #include <dt-bindings/clock/exynos3250.h>
+
+ adc@126c0000 {
+ compatible = "samsung,exynos3250-adc";
+ reg = <0x126c0000 0x100>;
+ interrupts = <0 137 0>;
+ #io-channel-cells = <1>;
+
+ clocks = <&cmu CLK_TSADC>,
+ <&cmu CLK_SCLK_TSADC>;
+ clock-names = "adc", "sclk";
+
+ vdd-supply = <&buck5_reg>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ };
diff --git a/Bindings/iio/adc/sigma-delta-modulator.yaml b/Bindings/iio/adc/sigma-delta-modulator.yaml
new file mode 100644
index 0000000..cab0d42
--- /dev/null
+++ b/Bindings/iio/adc/sigma-delta-modulator.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/sigma-delta-modulator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sigma delta modulator
+
+maintainers:
+ - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
+
+properties:
+ compatible:
+ description: |
+ "sd-modulator" can be used as a generic SD modulator,
+ if the modulator is not specified in the compatible list.
+ enum:
+ - sd-modulator
+ - ads1201
+
+ '#io-channel-cells':
+ const: 0
+
+required:
+ - compatible
+ - '#io-channel-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ ads1202: adc {
+ compatible = "sd-modulator";
+ #io-channel-cells = <0>;
+ };
+
+...
diff --git a/Bindings/iio/adc/sprd,sc2720-adc.yaml b/Bindings/iio/adc/sprd,sc2720-adc.yaml
new file mode 100644
index 0000000..8181cf9
--- /dev/null
+++ b/Bindings/iio/adc/sprd,sc2720-adc.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/sprd,sc2720-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Spreadtrum SC27XX series PMICs ADC
+
+maintainers:
+ - Baolin Wang <baolin.wang7@gmail.com>
+
+description:
+ Supports the ADC found on these PMICs.
+
+properties:
+ compatible:
+ enum:
+ - sprd,sc2720-adc
+ - sprd,sc2721-adc
+ - sprd,sc2723-adc
+ - sprd,sc2730-adc
+ - sprd,sc2731-adc
+ - sprd,ump9620-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#io-channel-cells":
+ const: 1
+
+ hwlocks:
+ maxItems: 1
+
+ nvmem-cells: true
+
+ nvmem-cell-names: true
+
+allOf:
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - sprd,ump9620-adc
+ then:
+ properties:
+ nvmem-cells:
+ maxItems: 2
+ nvmem-cell-names:
+ items:
+ - const: big_scale_calib
+ - const: small_scale_calib
+
+ else:
+ properties:
+ nvmem-cells:
+ maxItems: 6
+ nvmem-cell-names:
+ items:
+ - const: big_scale_calib1
+ - const: big_scale_calib2
+ - const: small_scale_calib1
+ - const: small_scale_calib2
+ - const: vbat_det_cal1
+ - const: vbat_det_cal2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#io-channel-cells"
+ - hwlocks
+ - nvmem-cells
+ - nvmem-cell-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ pmic {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ adc@480 {
+ compatible = "sprd,sc2731-adc";
+ reg = <0x480>;
+ interrupt-parent = <&sc2731_pmic>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ hwlocks = <&hwlock 4>;
+ nvmem-cells = <&adc_big_scale>, <&adc_small_scale>;
+ nvmem-cell-names = "big_scale_calib", "small_scale_calib";
+ };
+ };
+
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ pmic {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ adc@504 {
+ compatible = "sprd,ump9620-adc";
+ reg = <0x504>;
+ interrupt-parent = <&ump9620_pmic>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ hwlocks = <&hwlock 4>;
+ nvmem-cells = <&adc_bcal1>, <&adc_bcal2>,
+ <&adc_scal1>, <&adc_scal2>,
+ <&vbat_det_cal1>, <&vbat_det_cal2>;
+ nvmem-cell-names = "big_scale_calib1", "big_scale_calib2",
+ "small_scale_calib1", "small_scale_calib2",
+ "vbat_det_cal1", "vbat_det_cal2";
+ };
+ };
+...
diff --git a/Bindings/iio/adc/st,stm32-adc.yaml b/Bindings/iio/adc/st,stm32-adc.yaml
new file mode 100644
index 0000000..995cbf8
--- /dev/null
+++ b/Bindings/iio/adc/st,stm32-adc.yaml
@@ -0,0 +1,608 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 ADC
+
+description: |
+ STM32 ADC is a successive approximation analog-to-digital converter.
+ It has several multiplexed input channels. Conversions can be performed
+ in single, continuous, scan or discontinuous mode. Result of the ADC is
+ stored in a left-aligned or right-aligned 32-bit data register.
+ Conversions can be launched in software or using hardware triggers.
+
+ The analog watchdog feature allows the application to detect if the input
+ voltage goes beyond the user-defined, higher or lower thresholds.
+
+ Each STM32 ADC block can have up to 3 ADC instances.
+
+maintainers:
+ - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
+
+properties:
+ compatible:
+ enum:
+ - st,stm32f4-adc-core
+ - st,stm32h7-adc-core
+ - st,stm32mp1-adc-core
+ - st,stm32mp13-adc-core
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: |
+ One or more interrupts for ADC block, depending on part used:
+ - stm32f4 and stm32h7 share a common ADC interrupt line.
+ - stm32mp1 has two separate interrupt lines, one for each ADC within
+ ADC block.
+ - stm32mp13 has an interrupt line per ADC block.
+ minItems: 1
+ maxItems: 2
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+ description: |
+ Core can use up to two clocks, depending on part used:
+ - "adc" clock: for the analog circuitry, common to all ADCs.
+ It's required on stm32f4.
+ It's optional on stm32h7 and stm32mp1.
+ - "bus" clock: for registers access, common to all ADCs.
+ It's not present on stm32f4.
+ It's required on stm32h7 and stm32mp1.
+
+ clock-names: true
+
+ st,max-clk-rate-hz:
+ description:
+ Allow to specify desired max clock rate used by analog circuitry.
+
+ vdda-supply:
+ description: Phandle to the vdda input analog voltage.
+
+ vref-supply:
+ description: Phandle to the vref input analog reference voltage.
+
+ booster-supply:
+ description:
+ Phandle to the embedded booster regulator that can be used to supply ADC
+ analog input switches on stm32h7 and stm32mp1.
+
+ vdd-supply:
+ description:
+ Phandle to the vdd input voltage. It can be used to supply ADC analog
+ input switches on stm32mp1.
+
+ st,syscfg:
+ description:
+ Phandle to system configuration controller. It can be used to control the
+ analog circuitry on stm32mp1.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32f4-adc-core
+
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: adc
+
+ interrupts:
+ items:
+ - description: interrupt line common for all ADCs
+
+ st,max-clk-rate-hz:
+ minimum: 600000
+ maximum: 36000000
+ default: 36000000
+
+ booster-supply: false
+
+ vdd-supply: false
+
+ st,syscfg: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32h7-adc-core
+
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: bus
+ - const: adc
+ minItems: 1
+
+ interrupts:
+ items:
+ - description: interrupt line common for all ADCs
+
+ st,max-clk-rate-hz:
+ minimum: 120000
+ maximum: 36000000
+ default: 36000000
+
+ vdd-supply: false
+
+ st,syscfg: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32mp1-adc-core
+
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: bus
+ - const: adc
+ minItems: 1
+
+ interrupts:
+ items:
+ - description: interrupt line for ADC1
+ - description: interrupt line for ADC2
+
+ st,max-clk-rate-hz:
+ minimum: 120000
+ maximum: 36000000
+ default: 36000000
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32mp13-adc-core
+
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: bus
+ - const: adc
+ minItems: 1
+
+ interrupts:
+ items:
+ - description: ADC interrupt line
+
+ st,max-clk-rate-hz:
+ minimum: 150000
+ maximum: 75000000
+ default: 75000000
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - vdda-supply
+ - vref-supply
+ - interrupt-controller
+ - '#interrupt-cells'
+ - '#address-cells'
+ - '#size-cells'
+
+patternProperties:
+ "^adc@[0-9]+$":
+ type: object
+ description:
+ An ADC block node should contain at least one subnode, representing an
+ ADC instance available on the machine.
+
+ properties:
+ compatible:
+ enum:
+ - st,stm32f4-adc
+ - st,stm32h7-adc
+ - st,stm32mp1-adc
+ - st,stm32mp13-adc
+
+ reg:
+ description: |
+ Offset of ADC instance in ADC block. Valid values are:
+ - 0x0: ADC1
+ - 0x100: ADC2
+ - 0x200: ADC3 (stm32f4 only)
+ maxItems: 1
+
+ '#io-channel-cells':
+ const: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ interrupts:
+ description: |
+ IRQ Line for the ADC instance. Valid values are:
+ - 0 for adc@0 (single adc for stm32mp13)
+ - 1 for adc@100
+ - 2 for adc@200 (stm32f4 only)
+ maxItems: 1
+
+ clocks:
+ description:
+ Input clock private to this ADC instance. It's required only on
+ stm32f4, that has per instance clock input for registers access.
+ maxItems: 1
+
+ dmas:
+ description: RX DMA Channel
+ maxItems: 1
+
+ dma-names:
+ const: rx
+
+ assigned-resolution-bits:
+ description: |
+ Resolution (bits) to use for conversions:
+ - can be 6, 8, 10 or 12 on stm32f4 and stm32mp13
+ - can be 8, 10, 12, 14 or 16 on stm32h7 and stm32mp1
+
+ st,adc-channels:
+ description: |
+ List of single-ended channels muxed for this ADC. It can have up to:
+ - 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4
+ - 19 channels, numbered from 0 to 18 (for in0..in18) on stm32mp13.
+ - 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and
+ stm32mp1.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ deprecated: true
+
+ st,adc-diff-channels:
+ description: |
+ List of differential channels muxed for this ADC. Some channels can
+ be configured as differential instead of single-ended on stm32h7 and
+ on stm32mp1. Positive and negative inputs pairs are listed:
+ <vinp vinn>, <vinp vinn>,... vinp and vinn are numbered from 0 to 19.
+
+ Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is
+ required if no adc generic channel is defined. These legacy channel
+ properties are exclusive with adc generic channel bindings.
+ Both properties can be used together. Some channels can be
+ used as single-ended and some other ones as differential (mixed). But
+ channels can't be configured both as single-ended and differential.
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ items:
+ items:
+ - description: |
+ "vinp" indicates positive input number
+ minimum: 0
+ maximum: 19
+ - description: |
+ "vinn" indicates negative input number
+ minimum: 0
+ maximum: 19
+ deprecated: true
+
+ st,min-sample-time-nsecs:
+ description:
+ Minimum sampling time in nanoseconds. Depending on hardware (board)
+ e.g. high/low analog input source impedance, fine tune of ADC
+ sampling time may be recommended. This can be either one value or an
+ array that matches "st,adc-channels" and/or "st,adc-diff-channels"
+ list, to set sample time resp. for all channels, or independently for
+ each channel.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ deprecated: true
+
+ nvmem-cells:
+ items:
+ - description: Phandle to the calibration vrefint data provided by otp
+
+ nvmem-cell-names:
+ items:
+ - const: vrefint
+
+ patternProperties:
+ "^channel@([0-9]|1[0-9])$":
+ type: object
+ $ref: adc.yaml
+ description: Represents the external channels which are connected to the ADC.
+
+ properties:
+ reg:
+ items:
+ minimum: 0
+ maximum: 19
+
+ label:
+ description: |
+ Unique name to identify which channel this is.
+ Reserved label names "vddcore", "vddcpu", "vddq_ddr", "vrefint" and "vbat"
+ are used to identify internal channels with matching names.
+
+ diff-channels:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ minimum: 0
+ maximum: 19
+
+ st,min-sample-time-ns:
+ description: |
+ Minimum sampling time in nanoseconds. Depending on hardware (board)
+ e.g. high/low analog input source impedance, fine tune of ADC
+ sampling time may be recommended.
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+ allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32f4-adc
+
+ then:
+ properties:
+ reg:
+ enum:
+ - 0x0
+ - 0x100
+ - 0x200
+
+ interrupts:
+ minimum: 0
+ maximum: 2
+
+ assigned-resolution-bits:
+ enum: [6, 8, 10, 12]
+ default: 12
+
+ st,adc-channels:
+ minItems: 1
+ maxItems: 16
+ items:
+ minimum: 0
+ maximum: 15
+
+ st,adc-diff-channels: false
+
+ st,min-sample-time-nsecs:
+ minItems: 1
+ maxItems: 16
+ items:
+ minimum: 80
+
+ required:
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - st,stm32h7-adc
+ - st,stm32mp1-adc
+
+ then:
+ properties:
+ reg:
+ enum:
+ - 0x0
+ - 0x100
+
+ interrupts:
+ minimum: 0
+ maximum: 1
+
+ assigned-resolution-bits:
+ enum: [8, 10, 12, 14, 16]
+ default: 16
+
+ st,adc-channels:
+ minItems: 1
+ maxItems: 20
+ items:
+ minimum: 0
+ maximum: 19
+
+ st,min-sample-time-nsecs:
+ minItems: 1
+ maxItems: 20
+ items:
+ minimum: 40
+
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32mp13-adc
+
+ then:
+ properties:
+ reg:
+ const: 0x0
+
+ interrupts:
+ const: 0
+
+ assigned-resolution-bits:
+ enum: [6, 8, 10, 12]
+ default: 12
+
+ st,adc-channels:
+ minItems: 1
+ maxItems: 19
+ items:
+ minimum: 0
+ maximum: 18
+
+ st,min-sample-time-nsecs:
+ minItems: 1
+ maxItems: 19
+ items:
+ minimum: 40
+ additionalProperties: false
+
+ required:
+ - compatible
+ - reg
+ - interrupts
+ - '#io-channel-cells'
+
+examples:
+ - |
+ // Example 1: with stm32f429, ADC1, single-ended channel 8
+ adc123: adc@40012000 {
+ compatible = "st,stm32f4-adc-core";
+ reg = <0x40012000 0x400>;
+ interrupts = <18>;
+ clocks = <&rcc 0 168>;
+ clock-names = "adc";
+ st,max-clk-rate-hz = <36000000>;
+ vdda-supply = <&vdda>;
+ vref-supply = <&vref>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ adc@0 {
+ compatible = "st,stm32f4-adc";
+ #io-channel-cells = <1>;
+ reg = <0x0>;
+ clocks = <&rcc 0 168>;
+ interrupt-parent = <&adc123>;
+ interrupts = <0>;
+ st,adc-channels = <8>;
+ dmas = <&dma2 0 0 0x400 0x0>;
+ dma-names = "rx";
+ assigned-resolution-bits = <8>;
+ };
+ // ...
+ // other adc child nodes follow...
+ };
+
+ - |
+ // Example 2: with stm32mp157c to setup ADC1 with:
+ // - channels 0 & 1 as single-ended
+ // - channels 2 & 3 as differential (with resp. 6 & 7 negative inputs)
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/stm32mp1-clks.h>
+ adc12: adc@48003000 {
+ compatible = "st,stm32mp1-adc-core";
+ reg = <0x48003000 0x400>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc ADC12>, <&rcc ADC12_K>;
+ clock-names = "bus", "adc";
+ booster-supply = <&booster>;
+ vdd-supply = <&vdd>;
+ vdda-supply = <&vdda>;
+ vref-supply = <&vref>;
+ st,syscfg = <&syscfg>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ adc@0 {
+ compatible = "st,stm32mp1-adc";
+ #io-channel-cells = <1>;
+ reg = <0x0>;
+ interrupt-parent = <&adc12>;
+ interrupts = <0>;
+ st,adc-channels = <0 1>;
+ st,adc-diff-channels = <2 6>, <3 7>;
+ st,min-sample-time-nsecs = <5000>;
+ dmas = <&dmamux1 9 0x400 0x05>;
+ dma-names = "rx";
+ };
+ // ...
+ // other adc child node follow...
+ };
+
+ - |
+ // Example 3: with stm32mp157c to setup ADC2 with:
+ // - internal channels 13, 14, 15.
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/stm32mp1-clks.h>
+ adc122: adc@48003000 {
+ compatible = "st,stm32mp1-adc-core";
+ reg = <0x48003000 0x400>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc ADC12>, <&rcc ADC12_K>;
+ clock-names = "bus", "adc";
+ booster-supply = <&booster>;
+ vdd-supply = <&vdd>;
+ vdda-supply = <&vdda>;
+ vref-supply = <&vref>;
+ st,syscfg = <&syscfg>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ adc@100 {
+ compatible = "st,stm32mp1-adc";
+ #io-channel-cells = <1>;
+ reg = <0x100>;
+ interrupts = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel@13 {
+ reg = <13>;
+ label = "vrefint";
+ st,min-sample-time-ns = <9000>;
+ };
+ channel@14 {
+ reg = <14>;
+ label = "vddcore";
+ st,min-sample-time-ns = <9000>;
+ };
+ channel@15 {
+ reg = <15>;
+ label = "vbat";
+ st,min-sample-time-ns = <9000>;
+ };
+ };
+ };
+
+...
diff --git a/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml
new file mode 100644
index 0000000..1970503
--- /dev/null
+++ b/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml
@@ -0,0 +1,329 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 DFSDM ADC device driver
+
+maintainers:
+ - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
+ - Olivier Moysan <olivier.moysan@foss.st.com>
+
+description: |
+ STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
+ interface external sigma delta modulators to STM32 micro controllers.
+ It is mainly targeted for:
+ - Sigma delta modulators (motor control, metering...)
+ - PDM microphones (audio digital microphone)
+
+ It features up to 8 serial digital interfaces (SPI or Manchester) and
+ up to 4 filters on stm32h7 or 6 filters on stm32mp1.
+
+ Each child node matches with a filter instance.
+
+properties:
+ compatible:
+ enum:
+ - st,stm32h7-dfsdm
+ - st,stm32mp1-dfsdm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description:
+ Internal clock used for DFSDM digital processing and control blocks.
+ dfsdm clock can also feed CLKOUT, when CLKOUT is used.
+ - description: audio clock can be used as an alternate to feed CLKOUT.
+ minItems: 1
+
+ clock-names:
+ items:
+ - const: dfsdm
+ - const: audio
+ minItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ spi-max-frequency:
+ description:
+ SPI clock OUT frequency (Hz). Requested only for SPI master mode.
+ This clock must be set according to the "clock" property.
+ Frequency must be a multiple of the rcc clock frequency.
+ If not, SPI CLKOUT frequency will not be accurate.
+ maximum: 20000000
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+patternProperties:
+ "^filter@[0-9]+$":
+ type: object
+ unevaluatedProperties: false
+ description: child node
+
+ properties:
+ compatible:
+ enum:
+ - st,stm32-dfsdm-adc
+ - st,stm32-dfsdm-dmic
+
+ reg:
+ description: Specifies the DFSDM filter instance used.
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ st,adc-channels:
+ description: |
+ List of single-ended channels muxed for this ADC.
+ On stm32h7 and stm32mp1:
+ - For st,stm32-dfsdm-adc: up to 8 channels numbered from 0 to 7.
+ - For st,stm32-dfsdm-dmic: 1 channel numbered from 0 to 7.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ minimum: 0
+ maximum: 7
+
+ st,adc-channel-names:
+ description: List of single-ended channel names.
+
+ st,filter-order:
+ description: |
+ SinC filter order from 0 to 5.
+ - 0: FastSinC
+ - [1-5]: order 1 to 5.
+ For audio purpose it is recommended to use order 3 to 5.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 5
+
+ "#io-channel-cells":
+ const: 1
+
+ st,adc-channel-types:
+ description: |
+ Single-ended channel input type.
+ - "SPI_R": SPI with data on rising edge (default)
+ - "SPI_F": SPI with data on falling edge
+ - "MANCH_R": manchester codec, rising edge = logic 0, falling edge = logic 1
+ - "MANCH_F": manchester codec, rising edge = logic 1, falling edge = logic 0
+ items:
+ enum: [ SPI_R, SPI_F, MANCH_R, MANCH_F ]
+ $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+
+ st,adc-channel-clk-src:
+ description: |
+ Conversion clock source.
+ - "CLKIN": external SPI clock (CLKIN x)
+ - "CLKOUT": internal SPI clock (CLKOUT) (default)
+ - "CLKOUT_F": internal SPI clock divided by 2 (falling edge).
+ - "CLKOUT_R": internal SPI clock divided by 2 (rising edge).
+ items:
+ enum: [ CLKIN, CLKOUT, CLKOUT_F, CLKOUT_R ]
+ $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+
+ st,adc-alt-channel:
+ description:
+ Must be defined if two sigma delta modulators are
+ connected on same SPI input.
+ If not set, channel n is connected to SPI input n.
+ If set, channel n is connected to SPI input n + 1.
+ type: boolean
+
+ st,filter0-sync:
+ description:
+ Set to 1 to synchronize with DFSDM filter instance 0.
+ Used for multi microphones synchronization.
+ type: boolean
+
+ dmas:
+ maxItems: 1
+
+ dma-names:
+ items:
+ - const: rx
+
+ required:
+ - compatible
+ - reg
+ - interrupts
+ - st,adc-channels
+ - st,adc-channel-names
+ - st,filter-order
+ - "#io-channel-cells"
+
+ allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32-dfsdm-adc
+
+ then:
+ properties:
+ st,adc-channels:
+ minItems: 1
+ maxItems: 8
+
+ st,adc-channel-names:
+ minItems: 1
+ maxItems: 8
+
+ st,adc-channel-types:
+ minItems: 1
+ maxItems: 8
+
+ st,adc-channel-clk-src:
+ minItems: 1
+ maxItems: 8
+
+ io-channels:
+ description:
+ From common IIO binding. Used to pipe external sigma delta
+ modulator or internal ADC output to DFSDM channel.
+
+ required:
+ - io-channels
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32-dfsdm-dmic
+
+ then:
+ properties:
+ st,adc-channels:
+ maxItems: 1
+
+ st,adc-channel-names:
+ maxItems: 1
+
+ st,adc-channel-types:
+ maxItems: 1
+
+ st,adc-channel-clk-src:
+ maxItems: 1
+
+ required:
+ - dmas
+ - dma-names
+
+ patternProperties:
+ "^dfsdm-dai+$":
+ type: object
+ additionalProperties: false
+ description: child node
+
+ properties:
+ compatible:
+ enum:
+ - st,stm32h7-dfsdm-dai
+
+ "#sound-dai-cells":
+ const: 0
+
+ io-channels:
+ description:
+ From common IIO binding. Used to pipe external sigma delta
+ modulator or internal ADC output to DFSDM channel.
+
+ required:
+ - compatible
+ - "#sound-dai-cells"
+ - io-channels
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32h7-dfsdm
+
+ then:
+ patternProperties:
+ "^filter@[0-9]+$":
+ properties:
+ reg:
+ items:
+ minimum: 0
+ maximum: 3
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32mp1-dfsdm
+
+ then:
+ patternProperties:
+ "^filter@[0-9]+$":
+ properties:
+ reg:
+ items:
+ minimum: 0
+ maximum: 5
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/stm32mp1-clks.h>
+ dfsdm: dfsdm@4400d000 {
+ compatible = "st,stm32mp1-dfsdm";
+ reg = <0x4400d000 0x800>;
+ clocks = <&rcc DFSDM_K>, <&rcc ADFSDM_K>;
+ clock-names = "dfsdm", "audio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dfsdm0: filter@0 {
+ compatible = "st,stm32-dfsdm-dmic";
+ reg = <0>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 101 0x400 0x01>;
+ dma-names = "rx";
+ #io-channel-cells = <1>;
+ st,adc-channels = <1>;
+ st,adc-channel-names = "dmic0";
+ st,adc-channel-types = "SPI_R";
+ st,adc-channel-clk-src = "CLKOUT";
+ st,filter-order = <5>;
+
+ asoc_pdm0: dfsdm-dai {
+ compatible = "st,stm32h7-dfsdm-dai";
+ #sound-dai-cells = <0>;
+ io-channels = <&dfsdm0 0>;
+ };
+ };
+
+ dfsdm_pdm1: filter@1 {
+ compatible = "st,stm32-dfsdm-adc";
+ reg = <1>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 102 0x400 0x01>;
+ dma-names = "rx";
+ #io-channel-cells = <1>;
+ st,adc-channels = <2 3>;
+ st,adc-channel-names = "in2", "in3";
+ st,adc-channel-types = "SPI_R", "SPI_R";
+ st,adc-channel-clk-src = "CLKOUT_F", "CLKOUT_F";
+ io-channels = <&sd_adc2 &sd_adc3>;
+ st,filter-order = <1>;
+ };
+ };
+
+...
diff --git a/Bindings/iio/adc/st,stmpe-adc.yaml b/Bindings/iio/adc/st,stmpe-adc.yaml
new file mode 100644
index 0000000..474e35c
--- /dev/null
+++ b/Bindings/iio/adc/st,stmpe-adc.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/st,stmpe-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ADC on an STMPE multifunction device.
+
+maintainers:
+ - Stefan Agner <stefan@agner.ch>
+
+description:
+ This ADC forms part of an ST microelectronics STMPE multifunction device .
+ The ADC is shared with the STMPE touchscreen. As a result some ADC related
+ settings are specified in the parent node.
+ The node should be a child node of the stmpe node to which it belongs.
+
+properties:
+ compatible:
+ const: st,stmpe-adc
+
+ st,norequest-mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Bitmask specifying which ADC channels should _not_ be
+ requestable due to different usage (e.g. touch).
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ adc {
+ compatible = "st,stmpe-adc";
+ st,norequest-mask = <0x0f>; /* dont use ADC CH3-0 */
+ };
+...
diff --git a/Bindings/iio/adc/ti,adc081c.yaml b/Bindings/iio/adc/ti,adc081c.yaml
new file mode 100644
index 0000000..caaad77
--- /dev/null
+++ b/Bindings/iio/adc/ti,adc081c.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,adc081c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI Single-channel I2C ADCs
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+ - Lars-Peter Clausen <lars@metafoo.de>
+
+description: |
+ Single-channel ADC supporting 8, 10, or 12-bit samples and high/low alerts.
+
+properties:
+ compatible:
+ enum:
+ - ti,adc081c
+ - ti,adc101c
+ - ti,adc121c
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ vref-supply:
+ description:
+ Regulator for the combined power supply and voltage reference
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@52 {
+ compatible = "ti,adc081c";
+ reg = <0x52>;
+ vref-supply = <®_2p5v>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/ti,adc0832.yaml b/Bindings/iio/adc/ti,adc0832.yaml
new file mode 100644
index 0000000..6867211
--- /dev/null
+++ b/Bindings/iio/adc/ti,adc0832.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,adc0832.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADC0832 and similar ADCs
+
+maintainers:
+ - Akinobu Mita <akinobu.mita@gmail.com>
+
+description: |
+ 8 bit ADCs with 1, 2, 4 or 8 inputs for single ended or differential
+ conversion.
+
+properties:
+ compatible:
+ enum:
+ - ti,adc0831
+ - ti,adc0832
+ - ti,adc0834
+ - ti,adc0838
+
+ reg:
+ maxItems: 1
+
+ vref-supply:
+ description: External reference, needed to establish input scaling
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,adc0832";
+ reg = <0>;
+ vref-supply = <&vdd_supply>;
+ spi-max-frequency = <200000>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/ti,adc084s021.yaml b/Bindings/iio/adc/ti,adc084s021.yaml
new file mode 100644
index 0000000..726d2cb
--- /dev/null
+++ b/Bindings/iio/adc/ti,adc084s021.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,adc084s021.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADC084S021 ADC
+
+maintainers:
+ - Mårten Lindahl <martenli@axis.com>
+
+description: |
+ 8 bit ADC with 4 channels
+
+properties:
+ compatible:
+ const: ti,adc084s021
+
+ reg:
+ maxItems: 1
+
+ vref-supply:
+ description: External reference, needed to establish input scaling
+
+ spi-cpol: true
+ spi-cpha: true
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+ - spi-cpol
+ - spi-cpha
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,adc084s021";
+ reg = <0>;
+ vref-supply = <&adc_vref>;
+ spi-cpol;
+ spi-cpha;
+ spi-max-frequency = <16000000>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/ti,adc108s102.yaml b/Bindings/iio/adc/ti,adc108s102.yaml
new file mode 100644
index 0000000..a60b1e1
--- /dev/null
+++ b/Bindings/iio/adc/ti,adc108s102.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,adc108s102.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADC108S102 and ADC128S102
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description: |
+ Family of 8 channel, 10/12 bit, SPI, single ended ADCs.
+
+properties:
+ compatible:
+ const:
+ ti,adc108s102
+
+ reg: true
+ vref-supply: true
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,adc108s102";
+ reg = <0>;
+ vref-supply = <&vdd_supply>;
+ spi-max-frequency = <1000000>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/ti,adc12138.yaml b/Bindings/iio/adc/ti,adc12138.yaml
new file mode 100644
index 0000000..076088a
--- /dev/null
+++ b/Bindings/iio/adc/ti,adc12138.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,adc12138.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADC12138 and similar self-calibrating ADCs
+
+maintainers:
+ - Akinobu Mita <akinobu.mita@gmail.com>
+
+description: |
+ 13 bit ADCs with 1, 2 or 8 inputs and self calibrating circuitry to
+ correct for linearity, zero and full scale errors.
+
+properties:
+ compatible:
+ enum:
+ - ti,adc12130
+ - ti,adc12132
+ - ti,adc12138
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+ description: End of Conversion (EOC) interrupt
+
+ clocks:
+ maxItems: 1
+ description: Conversion clock input.
+
+ vref-p-supply:
+ description: The regulator supply for positive analog voltage reference
+
+ vref-n-supply:
+ description: |
+ The regulator supply for negative analog voltage reference
+ (Note that this must not go below GND or exceed vref-p)
+ If not specified, this is assumed to be analog ground.
+
+ ti,acquisition-time:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 6, 10, 18, 34 ]
+ description: |
+ The number of conversion clock periods for the S/H's acquisition time.
+ For high source impedances, this value can be increased to 18 or 34.
+ For less ADC accuracy and/or slower CCLK frequencies this value may be
+ decreased to 6. See section 6.0 INPUT SOURCE RESISTANCE in the
+ datasheet for details.
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - vref-p-supply
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,adc12138";
+ reg = <0>;
+ interrupts = <28 IRQ_TYPE_EDGE_RISING>;
+ interrupt-parent = <&gpio1>;
+ clocks = <&cclk>;
+ vref-p-supply = <&ldo4_reg>;
+ spi-max-frequency = <5000000>;
+ ti,acquisition-time = <6>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/ti,adc128s052.yaml b/Bindings/iio/adc/ti,adc128s052.yaml
new file mode 100644
index 0000000..775eee9
--- /dev/null
+++ b/Bindings/iio/adc/ti,adc128s052.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,adc128s052.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADC128S052 and similar ADCs
+
+maintainers:
+ - Angelo Compagnucci <angelo.compagnucci@gmail.com>
+
+description: |
+ Family of 12 bit SPI ADCs with 2 to 8 channels with a range of different
+ target sample rates.
+
+properties:
+ compatible:
+ enum:
+ - ti,adc122s021
+ - ti,adc122s051
+ - ti,adc122s101
+ - ti,adc124s021
+ - ti,adc124s051
+ - ti,adc124s101
+ - ti,adc128s052
+
+ reg:
+ maxItems: 1
+
+ vref-supply: true
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,adc128s052";
+ reg = <0>;
+ vref-supply = <&vdd_supply>;
+ spi-max-frequency = <1000000>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/ti,adc161s626.yaml b/Bindings/iio/adc/ti,adc161s626.yaml
new file mode 100644
index 0000000..afe7825
--- /dev/null
+++ b/Bindings/iio/adc/ti,adc161s626.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,adc161s626.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADC141S626 and ADC161S626 ADCs
+
+maintainers:
+ - Matt Ranostay <matt.ranostay@konsulko.com>
+
+description: |
+ Single channel 14/16bit differential ADCs
+
+properties:
+ compatible:
+ enum:
+ - ti,adc141s626
+ - ti,adc161s626
+
+ reg:
+ maxItems: 1
+
+ vdda-supply: true
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,adc161s626";
+ vdda-supply = <&vdda_fixed>;
+ reg = <0>;
+ spi-max-frequency = <4300000>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/ti,ads1015.yaml b/Bindings/iio/adc/ti,ads1015.yaml
new file mode 100644
index 0000000..d605999
--- /dev/null
+++ b/Bindings/iio/adc/ti,ads1015.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,ads1015.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI ADS1015/ADS1115 4 channel I2C analog to digital converter
+
+maintainers:
+ - Daniel Baluta <daniel.baluta@nxp.com>
+
+description: |
+ Datasheet at: https://www.ti.com/lit/gpn/ads1015
+ Supports both single ended and differential channels.
+
+properties:
+ compatible:
+ enum:
+ - ti,ads1015
+ - ti,ads1115
+ - ti,tla2024
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+patternProperties:
+ "^channel@[0-7]+$":
+ type: object
+ additionalProperties: false
+ description:
+ Child nodes needed for each channel that the platform uses.
+
+ properties:
+ reg:
+ description: |
+ 0: Voltage over AIN0 and AIN1.
+ 1: Voltage over AIN0 and AIN3.
+ 2: Voltage over AIN1 and AIN3.
+ 3: Voltage over AIN2 and AIN3.
+ 4: Voltage over AIN0 and GND.
+ 5: Voltage over AIN1 and GND.
+ 6: Voltage over AIN2 and GND.
+ 7: Voltage over AIN3 and GND.
+ items:
+ - minimum: 0
+ maximum: 7
+
+ ti,gain:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 5
+ description: |
+ pga is the programmable gain amplifier (values are full scale)
+ 0: +/- 6.144 V
+ 1: +/- 4.096 V
+ 2: +/- 2.048 V (default)
+ 3: +/- 1.024 V
+ 4: +/- 0.512 V
+ 5: +/- 0.256 V
+
+ ti,datarate:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 7
+ description: |
+ Data acquisition rate in samples per second for ADS1015, TLA2024
+ 0: 128
+ 1: 250
+ 2: 490
+ 3: 920
+ 4: 1600 (default)
+ 5: 2400
+ 6: 3300
+ 7: 3300
+
+ Data acquisition rate in samples per second for ADS1115
+ 0: 8
+ 1: 16
+ 2: 32
+ 3: 64
+ 4: 128 (default)
+ 5: 250
+ 6: 475
+ 7: 860
+
+ required:
+ - reg
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@49 {
+ compatible = "ti,ads1015";
+ reg = <0x49>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel@0 {
+ reg = <0>;
+ };
+ channel@4 {
+ reg = <4>;
+ ti,gain = <3>;
+ ti,datarate = <5>;
+ };
+ };
+ };
+...
diff --git a/Bindings/iio/adc/ti,ads1100.yaml b/Bindings/iio/adc/ti,ads1100.yaml
new file mode 100644
index 0000000..970ccab
--- /dev/null
+++ b/Bindings/iio/adc/ti,ads1100.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,ads1100.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI ADS1100/ADS1000 single channel I2C analog to digital converter
+
+maintainers:
+ - Mike Looijmans <mike.looijmans@topic.nl>
+
+description: |
+ Datasheet at: https://www.ti.com/lit/gpn/ads1100
+
+properties:
+ compatible:
+ enum:
+ - ti,ads1100
+ - ti,ads1000
+
+ reg:
+ maxItems: 1
+
+ vdd-supply: true
+
+ "#io-channel-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@49 {
+ compatible = "ti,ads1100";
+ reg = <0x49>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/ti,ads124s08.yaml b/Bindings/iio/adc/ti,ads124s08.yaml
new file mode 100644
index 0000000..56a3f17
--- /dev/null
+++ b/Bindings/iio/adc/ti,ads124s08.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,ads124s08.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments' ads124s08 and ads124s06 ADC chip
+
+maintainers:
+ - Andrew Davis <afd@ti.com>
+
+properties:
+ compatible:
+ enum:
+ - ti,ads124s06
+ - ti,ads124s08
+
+ reg:
+ maxItems: 1
+
+ spi-cpha: true
+
+ reset-gpios:
+ maxItems: 1
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,ads124s08";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cpha;
+ reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/ti,ads131e08.yaml b/Bindings/iio/adc/ti,ads131e08.yaml
new file mode 100644
index 0000000..890f125
--- /dev/null
+++ b/Bindings/iio/adc/ti,ads131e08.yaml
@@ -0,0 +1,182 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,ads131e08.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADS131E0x 4-, 6- and 8-Channel ADCs
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description: |
+ The ADS131E0x are a family of multichannel, simultaneous sampling,
+ 24-bit, delta-sigma, analog-to-digital converters (ADCs) with a
+ built-in programmable gain amplifier (PGA), internal reference
+ and an onboard oscillator.
+ The communication with ADC chip is via the SPI bus (mode 1).
+
+ https://www.ti.com/lit/ds/symlink/ads131e08.pdf
+
+properties:
+ compatible:
+ enum:
+ - ti,ads131e04
+ - ti,ads131e06
+ - ti,ads131e08
+
+ reg:
+ maxItems: 1
+
+ spi-cpha: true
+
+ clocks:
+ description: |
+ Device tree identifier to the clock source (2.048 MHz).
+ Note: clock source is selected using CLKSEL pin.
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: adc-clk
+
+ interrupts:
+ description: |
+ IRQ line for the ADC data ready.
+ maxItems: 1
+
+ vref-supply:
+ description: |
+ Optional external voltage reference. If not supplied, internal voltage
+ reference is used.
+
+ ti,vref-internal:
+ description: |
+ Select the internal voltage reference value.
+ 0: 2.4V
+ 1: 4.0V
+ If this field is left empty, 2.4V is selected.
+ Note: internal voltage reference is used only if vref-supply is not supplied.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+ default: 0
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - spi-cpha
+ - clocks
+ - clock-names
+ - interrupts
+
+patternProperties:
+ "^channel@([0-7])$":
+ $ref: adc.yaml
+ type: object
+ description: |
+ Represents the external channels which are connected to the ADC.
+
+ properties:
+ reg:
+ description: |
+ The channel number.
+ Up to 4 channels, numbered from 0 to 3 for ti,ads131e04.
+ Up to 6 channels, numbered from 0 to 5 for ti,ads131e06.
+ Up to 8 channels, numbered from 0 to 7 for ti,ads131e08.
+ items:
+ minimum: 0
+ maximum: 7
+
+ ti,gain:
+ description: |
+ The PGA gain value for the channel.
+ If this field is left empty, PGA gain 1 is used.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 4, 8, 12]
+ default: 1
+
+ ti,mux:
+ description: |
+ Channel input selection(muliplexer).
+ 0: Normal input.
+ 1: Input shorted to (VREFP + VREFN) / 2 (for offset or noise measurements).
+ 3: MVDD (for supply measurement)
+ 4: Temperature sensor
+ If this field is left empty, normal input is selected.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 3, 4]
+ default: 0
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,ads131e08";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cpha;
+ clocks = <&clk2048k>;
+ clock-names = "adc-clk";
+ interrupt-parent = <&gpio5>;
+ interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
+ vref-supply = <&adc_vref>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ };
+
+ channel@1 {
+ reg = <1>;
+ };
+
+ channel@2 {
+ reg = <2>;
+ ti,gain = <2>;
+ };
+
+ channel@3 {
+ reg = <3>;
+ };
+
+ channel@4 {
+ reg = <4>;
+ };
+
+ channel@5 {
+ reg = <5>;
+ };
+
+ channel@6 {
+ reg = <6>;
+ };
+
+ channel@7 {
+ reg = <7>;
+ ti,mux = <4>;
+ };
+ };
+ };
diff --git a/Bindings/iio/adc/ti,ads7924.yaml b/Bindings/iio/adc/ti,ads7924.yaml
new file mode 100644
index 0000000..0d8d06a
--- /dev/null
+++ b/Bindings/iio/adc/ti,ads7924.yaml
@@ -0,0 +1,110 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,ads7924.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI ADS7924 4 channels 12 bits I2C analog to digital converter
+
+maintainers:
+ - Hugo Villeneuve <hvilleneuve@dimonoff.com>
+
+description: |
+ Texas Instruments ADS7924 4 channels 12 bits I2C analog to digital converter
+
+ Specifications:
+ https://www.ti.com/lit/gpn/ads7924
+
+properties:
+ compatible:
+ const: ti,ads7924
+
+ reg:
+ maxItems: 1
+
+ vref-supply:
+ description:
+ The regulator supply for the ADC reference voltage (AVDD)
+
+ reset-gpios:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ "#io-channel-cells":
+ const: 1
+
+patternProperties:
+ "^channel@[0-3]+$":
+ $ref: adc.yaml
+
+ description: |
+ Represents the external channels which are connected to the ADC.
+
+ properties:
+ reg:
+ description: |
+ The channel number. It can have up to 4 channels numbered from 0 to 3.
+ items:
+ - minimum: 0
+ maximum: 3
+
+ label: true
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+ - "#address-cells"
+ - "#size-cells"
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@48 {
+ compatible = "ti,ads7924";
+ reg = <0x48>;
+ vref-supply = <&ads7924_reg>;
+ reset-gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel@0 {
+ reg = <0>;
+ label = "CH0";
+ };
+ channel@1 {
+ reg = <1>;
+ label = "CH1";
+ };
+ channel@2 {
+ reg = <2>;
+ label = "CH2";
+ };
+ channel@3 {
+ reg = <3>;
+ label = "CH3";
+ };
+ };
+ };
+...
diff --git a/Bindings/iio/adc/ti,ads7950.yaml b/Bindings/iio/adc/ti,ads7950.yaml
new file mode 100644
index 0000000..5ab5027
--- /dev/null
+++ b/Bindings/iio/adc/ti,ads7950.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,ads7950.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADS7950 and similar ADCs
+
+maintainers:
+ - David Lechner <david@lechnology.com>
+
+description: |
+ Family of 4-16 channel, 8-12 bit ADCs with SPI interface.
+
+properties:
+ compatible:
+ enum:
+ - ti,ads7950
+ - ti,ads7951
+ - ti,ads7952
+ - ti,ads7953
+ - ti,ads7954
+ - ti,ads7955
+ - ti,ads7956
+ - ti,ads7957
+ - ti,ads7958
+ - ti,ads7959
+ - ti,ads7960
+ - ti,ads7961
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 20000000
+
+ vref-supply:
+ description: Supplies the 2.5V or 5V reference voltage
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,ads7957";
+ reg = <0>;
+ vref-supply = <&refin_supply>;
+ spi-max-frequency = <10000000>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/ti,ads8344.yaml b/Bindings/iio/adc/ti,ads8344.yaml
new file mode 100644
index 0000000..f75b2c7
--- /dev/null
+++ b/Bindings/iio/adc/ti,ads8344.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,ads8344.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADS8344 ADC
+
+maintainers:
+ - Gregory Clement <gregory.clement@bootlin.com>
+
+description: |
+ 16bit 8-channel ADC with single ended inputs.
+
+properties:
+ compatible:
+ const: ti,ads8344
+
+ reg:
+ maxItems: 1
+
+ vref-supply:
+ description: Supply the 2.5V or 5V reference voltage
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,ads8344";
+ reg = <0>;
+ vref-supply = <&refin_supply>;
+ spi-max-frequency = <10000000>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/ti,ads8688.yaml b/Bindings/iio/adc/ti,ads8688.yaml
new file mode 100644
index 0000000..f26fdbc
--- /dev/null
+++ b/Bindings/iio/adc/ti,ads8688.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,ads8688.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments' ADS8684 and ADS8688 ADC chip
+
+maintainers:
+ - Sean Nyekjaer <sean@geanix.com>
+
+description: |
+ SPI 16bit ADCs with 4/8 channels.
+
+properties:
+ compatible:
+ enum:
+ - ti,ads8684
+ - ti,ads8688
+
+ reg:
+ maxItems: 1
+
+ vref-supply:
+ description: Optional external reference. If not supplied, assume
+ REFSEL input tied low to enable the internal reference.
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,ads8688";
+ reg = <0>;
+ vref-supply = <&vdd_supply>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/ti,am3359-adc.yaml b/Bindings/iio/adc/ti,am3359-adc.yaml
new file mode 100644
index 0000000..b32be24
--- /dev/null
+++ b/Bindings/iio/adc/ti,am3359-adc.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,am3359-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI AM3359 ADC
+
+maintainers:
+ - Miquel Raynal <miquel.raynal@bootlin.com>
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - ti,am3359-adc
+ - ti,am4372-adc
+ - items:
+ - enum:
+ - ti,am654-adc
+ - const: ti,am3359-adc
+
+ '#io-channel-cells':
+ const: 1
+
+ ti,adc-channels:
+ description: List of analog inputs available for ADC. AIN0 = 0, AIN1 = 1 and
+ so on until AIN7 = 7.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 8
+
+ ti,chan-step-opendelay:
+ description: List of open delays for each channel of ADC in the order of
+ ti,adc-channels. The value corresponds to the number of ADC clock cycles
+ to wait after applying the step configuration registers and before sending
+ the start of ADC conversion. Maximum value is 0x3FFFF.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 8
+
+ ti,chan-step-sampledelay:
+ description: List of sample delays for each channel of ADC in the order of
+ ti,adc-channels. The value corresponds to the number of ADC clock cycles
+ to sample (to hold start of conversion high). Maximum value is 0xFF.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 8
+
+ ti,chan-step-avg:
+ description: Number of averages to be performed for each channel of ADC. If
+ average is 16 (this is also the maximum) then input is sampled 16 times
+ and averaged to get more accurate value. This increases the time taken by
+ ADC to generate a sample. Maximum value is 16.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 8
+
+required:
+ - compatible
+ - '#io-channel-cells'
+ - ti,adc-channels
+
+additionalProperties: false
+
+examples:
+ - |
+ adc {
+ compatible = "ti,am3359-adc";
+ #io-channel-cells = <1>;
+ ti,adc-channels = <4 5 6 7>;
+ ti,chan-step-opendelay = <0x098 0x3ffff 0x098 0x0>;
+ ti,chan-step-sampledelay = <0xff 0x0 0xf 0x0>;
+ ti,chan-step-avg = <16 2 4 8>;
+ };
diff --git a/Bindings/iio/adc/ti,lmp92064.yaml b/Bindings/iio/adc/ti,lmp92064.yaml
new file mode 100644
index 0000000..5fb65bf
--- /dev/null
+++ b/Bindings/iio/adc/ti,lmp92064.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,lmp92064.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments LMP92064 Precision Current and Voltage Sensor.
+
+maintainers:
+ - Leonard Göhrs <l.goehrs@pengutronix.de>
+
+description: |
+ The LMP92064 is a two channel ADC intended for combined voltage and current
+ measurements.
+
+ The device contains two ADCs to allow simultaneous sampling of voltage and
+ current and thus of instantaneous power consumption.
+
+properties:
+ compatible:
+ enum:
+ - ti,lmp92064
+
+ reg:
+ maxItems: 1
+
+ vdd-supply:
+ description: Regulator that provides power to the main part of the chip
+
+ vdig-supply:
+ description: |
+ Regulator that provides power to the digital I/O part of the chip
+
+ shunt-resistor-micro-ohms:
+ description: |
+ Value of the shunt resistor (in µΩ) connected between INCP and INCN,
+ across which current is measured. Used to provide correct scaling of the
+ raw ADC measurement.
+
+ reset-gpios:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - shunt-resistor-micro-ohms
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,lmp92064";
+ reg = <0>;
+ vdd-supply = <&vdd>;
+ vdig-supply = <&vdd>;
+ spi-max-frequency = <20000000>;
+ shunt-resistor-micro-ohms = <15000>;
+ reset-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/ti,palmas-gpadc.yaml b/Bindings/iio/adc/ti,palmas-gpadc.yaml
new file mode 100644
index 0000000..720c16a
--- /dev/null
+++ b/Bindings/iio/adc/ti,palmas-gpadc.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,palmas-gpadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Palmas general purpose ADC IP block
+
+maintainers:
+ - Tony Lindgren <tony@atomide.com>
+
+description: |
+ This ADC is often used to provide channels via the io-channels
+ consumer framework.
+ Channels list:
+ 0 battery type
+ 1 battery temp NTC (optional current source)
+ 2 GP
+ 3 temp (with ext. diode, optional current source)
+ 4 GP
+ 5 GP
+ 6 VBAT_SENSE
+ 7 VCC_SENSE
+ 8 Backup Battery voltage
+ 9 external charger (VCHG)
+ 10 VBUS
+ 11 DC-DC current probe (how does this work?)
+ 12 internal die temp
+ 13 internal die temp
+ 14 USB ID pin voltage
+ 15 test network
+
+properties:
+ compatible:
+ const: ti,palmas-gpadc
+
+ interrupts:
+ minItems: 1
+ maxItems: 3
+
+ "#io-channel-cells":
+ const: 1
+
+ ti,channel0-current-microamp:
+ description: Channel 0 current in uA.
+ enum:
+ - 0
+ - 5
+ - 15
+ - 20
+
+ ti,channel3-current-microamp:
+ description: Channel 3 current in uA.
+ enum:
+ - 0
+ - 10
+ - 400
+ - 800
+
+ ti,enable-extended-delay:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Enable extended delay.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - "#io-channel-cells"
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ pmic {
+ compatible = "ti,twl6035-pmic", "ti,palmas-pmic";
+ adc {
+ compatible = "ti,palmas-gpadc";
+ interrupts = <18 0>,
+ <16 0>,
+ <17 0>;
+ #io-channel-cells = <1>;
+ ti,channel0-current-microamp = <5>;
+ ti,channel3-current-microamp = <10>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/ti,tlc4541.yaml b/Bindings/iio/adc/ti,tlc4541.yaml
new file mode 100644
index 0000000..314d1d9
--- /dev/null
+++ b/Bindings/iio/adc/ti,tlc4541.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,tlc4541.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments TLC4541 and similar ADCs
+
+maintainers:
+ - Phil Reid <preid@electromag.com.au>
+
+description: |
+ 14/16bit single channel ADC with SPI interface.
+
+properties:
+ compatible:
+ enum:
+ - ti,tlc3541
+ - ti,tlc4541
+
+ reg:
+ maxItems: 1
+
+ vref-supply: true
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,tlc4541";
+ reg = <0>;
+ vref-supply = <&vdd_supply>;
+ spi-max-frequency = <200000>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/ti,tsc2046.yaml b/Bindings/iio/adc/ti,tsc2046.yaml
new file mode 100644
index 0000000..866a05c
--- /dev/null
+++ b/Bindings/iio/adc/ti,tsc2046.yaml
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,tsc2046.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments TSC2046 touch screen controller.
+
+maintainers:
+ - Oleksij Rempel <o.rempel@pengutronix.de>
+
+description: |
+ TSC2046 is a touch screen controller with 8 channels ADC.
+
+properties:
+ compatible:
+ enum:
+ - ti,tsc2046e-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ vref-supply:
+ description: Optional supply of the reference voltage
+
+ "#io-channel-cells":
+ const: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+
+patternProperties:
+ "^channel@[0-7]$":
+ $ref: adc.yaml
+ type: object
+
+ properties:
+ reg:
+ description: |
+ The channel number. It can have up to 8 channels
+ items:
+ minimum: 0
+ maximum: 7
+
+ settling-time-us: true
+ oversampling-ratio: true
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,tsc2046e-adc";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>;
+ #io-channel-cells = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ };
+ channel@1 {
+ reg = <1>;
+ settling-time-us = <700>;
+ oversampling-ratio = <5>;
+ };
+ channel@2 {
+ reg = <2>;
+ };
+ channel@3 {
+ reg = <3>;
+ settling-time-us = <700>;
+ oversampling-ratio = <5>;
+ };
+ channel@4 {
+ reg = <4>;
+ settling-time-us = <700>;
+ oversampling-ratio = <5>;
+ };
+ channel@5 {
+ reg = <5>;
+ settling-time-us = <700>;
+ oversampling-ratio = <5>;
+ };
+ channel@6 {
+ reg = <6>;
+ };
+ channel@7 {
+ reg = <7>;
+ };
+ };
+ };
+...
diff --git a/Bindings/iio/adc/ti,twl4030-madc.yaml b/Bindings/iio/adc/ti,twl4030-madc.yaml
new file mode 100644
index 0000000..6781ad2
--- /dev/null
+++ b/Bindings/iio/adc/ti,twl4030-madc.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,twl4030-madc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MADC subsystem in the TWL4030 power module
+
+maintainers:
+ - Sebastian Reichel <sre@kernel.org>
+
+description:
+ The MADC subsystem in the TWL4030 consists of a 10-bit ADC
+ combined with a 16-input analog multiplexer.
+
+properties:
+ compatible:
+ const: ti,twl4030-madc
+
+ interrupts:
+ maxItems: 1
+
+ ti,system-uses-second-madc-irq:
+ type: boolean
+ description:
+ Set if the second madc irq register should be used, which is intended
+ to be used by Co-Processors (e.g. a modem).
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - interrupts
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ twl {
+ madc {
+ compatible = "ti,twl4030-madc";
+ interrupts = <3>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/ti,twl6030-gpadc.yaml b/Bindings/iio/adc/ti,twl6030-gpadc.yaml
new file mode 100644
index 0000000..e779a89
--- /dev/null
+++ b/Bindings/iio/adc/ti,twl6030-gpadc.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,twl6030-gpadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: GPADC subsystem in the TWL6030 power module
+
+maintainers:
+ - Andreas Kemnade <andreas@kemnade.info>
+
+description:
+ The GPADC subsystem in the TWL603X consists of a 10-bit ADC
+ combined with a 15-input analog multiplexer in the TWL6030 resp. a
+ 19-input analog muliplexer in the TWL6032.
+
+properties:
+ compatible:
+ enum:
+ - ti,twl6030-gpadc
+ - ti,twl6032-gpadc
+
+ interrupts:
+ maxItems: 1
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - interrupts
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ gpadc {
+ compatible = "ti,twl6030-gpadc";
+ interrupts = <3>;
+ #io-channel-cells = <1>;
+ };
+...
diff --git a/Bindings/iio/adc/x-powers,axp209-adc.yaml b/Bindings/iio/adc/x-powers,axp209-adc.yaml
new file mode 100644
index 0000000..d40689f
--- /dev/null
+++ b/Bindings/iio/adc/x-powers,axp209-adc.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/x-powers,axp209-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: X-Powers AXP ADC
+
+maintainers:
+ - Chen-Yu Tsai <wens@csie.org>
+
+description: |
+ ADC is frequently used as a provider to consumers of the ADC channels.
+ Device is a child of an axp209 multifunction device
+ ADC channels and their indexes per variant:
+
+ AXP209
+ ------
+ 0 | acin_v
+ 1 | acin_i
+ 2 | vbus_v
+ 3 | vbus_i
+ 4 | pmic_temp
+ 5 | gpio0_v
+ 6 | gpio1_v
+ 7 | ipsout_v
+ 8 | batt_v
+ 9 | batt_chrg_i
+ 10 | batt_dischrg_i
+ 11 | ts_v
+
+ AXP22x
+ ------
+ 0 | pmic_temp
+ 1 | batt_v
+ 2 | batt_chrg_i
+ 3 | batt_dischrg_i
+ 4 | ts_v
+
+ AXP813
+ ------
+ 0 | pmic_temp
+ 1 | gpio0_v
+ 2 | batt_v
+ 3 | batt_chrg_i
+ 4 | batt_dischrg_i
+ 5 | ts_v
+
+
+properties:
+ compatible:
+ oneOf:
+ - const: x-powers,axp209-adc
+ - const: x-powers,axp221-adc
+ - const: x-powers,axp813-adc
+
+ - items:
+ - const: x-powers,axp803-adc
+ - const: x-powers,axp813-adc
+
+ "#io-channel-cells":
+ const: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ axp221 {
+ adc {
+ compatible = "x-powers,axp221-adc";
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/xilinx-xadc.txt b/Bindings/iio/adc/xilinx-xadc.txt
new file mode 100644
index 0000000..f42e180
--- /dev/null
+++ b/Bindings/iio/adc/xilinx-xadc.txt
@@ -0,0 +1,141 @@
+Xilinx XADC device driver
+
+This binding document describes the bindings for the Xilinx 7 Series XADC as well
+as the UltraScale/UltraScale+ System Monitor.
+
+The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
+The XADC has a DRP interface for communication. Currently two different
+frontends for the DRP interface exist. One that is only available on the ZYNQ
+family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
+on all series 7 platforms and is a softmacro with a AXI interface. This binding
+document describes the bindings for both of them since the bindings are very
+similar.
+
+The Xilinx System Monitor is an ADC that is found in the UltraScale and
+UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
+communication. Xilinx provides a standard IP core that can be used to access the
+System Monitor through an AXI interface in the FPGA fabric. This IP core is
+called the Xilinx System Management Wizard. This document describes the bindings
+for this IP.
+
+Required properties:
+ - compatible: Should be one of
+ * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
+ configuration interface to interface to the XADC hardmacro.
+ * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
+ interface to the XADC hardmacro.
+ * "xlnx,system-management-wiz-1.3": When using the
+ Xilinx System Management Wizard fabric IP core to access the
+ UltraScale and UltraScale+ System Monitor.
+ - reg: Address and length of the register set for the device
+ - interrupts: Interrupt for the XADC control interface.
+ - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
+ when using the axi-xadc or the axi-system-management-wizard this must be
+ the clock that provides the clock to the AXI bus interface of the core.
+
+Optional properties:
+ - xlnx,external-mux:
+ * "none": No external multiplexer is used, this is the default
+ if the property is omitted.
+ * "single": External multiplexer mode is used with one
+ multiplexer.
+ * "dual": External multiplexer mode is used with two
+ multiplexers for simultaneous sampling.
+ - xlnx,external-mux-channel: Configures which pair of pins is used to
+ sample data in external mux mode.
+ Valid values for single external multiplexer mode are:
+ 0: VP/VN
+ 1: VAUXP[0]/VAUXN[0]
+ 2: VAUXP[1]/VAUXN[1]
+ ...
+ 16: VAUXP[15]/VAUXN[15]
+ Valid values for dual external multiplexer mode are:
+ 1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
+ 2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
+ ...
+ 8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
+
+ This property needs to be present if the device is configured for
+ external multiplexer mode (either single or dual). If the device is
+ not using external multiplexer mode the property is ignored.
+ - xnlx,channels: List of external channels that are connected to the ADC
+ Required properties:
+ * #address-cells: Should be 1.
+ * #size-cells: Should be 0.
+
+ The child nodes of this node represent the external channels which are
+ connected to the ADC. If the property is no present no external
+ channels will be assumed to be connected.
+
+ Each child node represents one channel and has the following
+ properties:
+ Required properties:
+ * reg: Pair of pins the channel is connected to.
+ 0: VP/VN
+ 1: VAUXP[0]/VAUXN[0]
+ 2: VAUXP[1]/VAUXN[1]
+ ...
+ 16: VAUXP[15]/VAUXN[15]
+ Note each channel number should only be used at most
+ once.
+ Optional properties:
+ * xlnx,bipolar: If set the channel is used in bipolar
+ mode.
+
+
+Examples:
+ xadc@f8007100 {
+ compatible = "xlnx,zynq-xadc-1.00.a";
+ reg = <0xf8007100 0x20>;
+ interrupts = <0 7 4>;
+ interrupt-parent = <&gic>;
+ clocks = <&pcap_clk>;
+
+ xlnx,channels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel@0 {
+ reg = <0>;
+ };
+ channel@1 {
+ reg = <1>;
+ };
+ channel@8 {
+ reg = <8>;
+ };
+ };
+ };
+
+ xadc@43200000 {
+ compatible = "xlnx,axi-xadc-1.00.a";
+ reg = <0x43200000 0x1000>;
+ interrupts = <0 53 4>;
+ interrupt-parent = <&gic>;
+ clocks = <&fpga1_clk>;
+
+ xlnx,channels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel@0 {
+ reg = <0>;
+ xlnx,bipolar;
+ };
+ };
+ };
+
+ adc@80000000 {
+ compatible = "xlnx,system-management-wiz-1.3";
+ reg = <0x80000000 0x1000>;
+ interrupts = <0 81 4>;
+ interrupt-parent = <&gic>;
+ clocks = <&fpga1_clk>;
+
+ xlnx,channels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel@0 {
+ reg = <0>;
+ xlnx,bipolar;
+ };
+ };
+ };
diff --git a/Bindings/iio/adc/xlnx,zynqmp-ams.yaml b/Bindings/iio/adc/xlnx,zynqmp-ams.yaml
new file mode 100644
index 0000000..8cbad7e
--- /dev/null
+++ b/Bindings/iio/adc/xlnx,zynqmp-ams.yaml
@@ -0,0 +1,236 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/xlnx,zynqmp-ams.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynq Ultrascale AMS controller
+
+maintainers:
+ - Anand Ashok Dumbre <anand.ashok.dumbre@xilinx.com>
+
+description: |
+ The AMS (Analog Monitoring System) includes an ADC as well as on-chip sensors
+ that can be used to sample external voltages and monitor on-die operating
+ conditions, such as temperature and supply voltage levels.
+ The AMS has two SYSMON blocks which are PL (Programmable Logic) SYSMON and
+ PS (Processing System) SYSMON.
+ All designs should have AMS registers, but PS and PL are optional. The
+ AMS controller can work with only PS, only PL and both PS and PL
+ configurations. Please specify registers according to your design. Devicetree
+ should always have AMS module property. Providing PS & PL module is optional.
+
+ AMS Channel Details
+ ```````````````````
+ Sysmon Block |Channel| Details |Measurement
+ |Number | |Type
+ ---------------------------------------------------------------------------------------------------------
+ AMS CTRL |0 |System PLLs voltage measurement, VCC_PSPLL. |Voltage
+ |1 |Battery voltage measurement, VCC_PSBATT. |Voltage
+ |2 |PL Internal voltage measurement, VCCINT. |Voltage
+ |3 |Block RAM voltage measurement, VCCBRAM. |Voltage
+ |4 |PL Aux voltage measurement, VCCAUX. |Voltage
+ |5 |Voltage measurement for six DDR I/O PLLs, VCC_PSDDR_PLL. |Voltage
+ |6 |VCC_PSINTFP_DDR voltage measurement. |Voltage
+ ---------------------------------------------------------------------------------------------------------
+ PS Sysmon |7 |LPD temperature measurement. |Temperature
+ |8 |FPD temperature measurement (REMOTE). |Temperature
+ |9 |VCC PS LPD voltage measurement (supply1). |Voltage
+ |10 |VCC PS FPD voltage measurement (supply2). |Voltage
+ |11 |PS Aux voltage reference (supply3). |Voltage
+ |12 |DDR I/O VCC voltage measurement. |Voltage
+ |13 |PS IO Bank 503 voltage measurement (supply5). |Voltage
+ |14 |PS IO Bank 500 voltage measurement (supply6). |Voltage
+ |15 |VCCO_PSIO1 voltage measurement. |Voltage
+ |16 |VCCO_PSIO2 voltage measurement. |Voltage
+ |17 |VCC_PS_GTR voltage measurement (VPS_MGTRAVCC). |Voltage
+ |18 |VTT_PS_GTR voltage measurement (VPS_MGTRAVTT). |Voltage
+ |19 |VCC_PSADC voltage measurement. |Voltage
+ ---------------------------------------------------------------------------------------------------------
+ PL Sysmon |20 |PL temperature measurement. |Temperature
+ |21 |PL Internal voltage measurement, VCCINT. |Voltage
+ |22 |PL Auxiliary voltage measurement, VCCAUX. |Voltage
+ |23 |ADC Reference P+ voltage measurement. |Voltage
+ |24 |ADC Reference N- voltage measurement. |Voltage
+ |25 |PL Block RAM voltage measurement, VCCBRAM. |Voltage
+ |26 |LPD Internal voltage measurement, VCC_PSINTLP (supply4). |Voltage
+ |27 |FPD Internal voltage measurement, VCC_PSINTFP (supply5). |Voltage
+ |28 |PS Auxiliary voltage measurement (supply6). |Voltage
+ |29 |PL VCCADC voltage measurement (vccams). |Voltage
+ |30 |Differential analog input signal voltage measurement. |Voltage
+ |31 |VUser0 voltage measurement (supply7). |Voltage
+ |32 |VUser1 voltage measurement (supply8). |Voltage
+ |33 |VUser2 voltage measurement (supply9). |Voltage
+ |34 |VUser3 voltage measurement (supply10). |Voltage
+ |35 |Auxiliary ch 0 voltage measurement (VAux0). |Voltage
+ |36 |Auxiliary ch 1 voltage measurement (VAux1). |Voltage
+ |37 |Auxiliary ch 2 voltage measurement (VAux2). |Voltage
+ |38 |Auxiliary ch 3 voltage measurement (VAux3). |Voltage
+ |39 |Auxiliary ch 4 voltage measurement (VAux4). |Voltage
+ |40 |Auxiliary ch 5 voltage measurement (VAux5). |Voltage
+ |41 |Auxiliary ch 6 voltage measurement (VAux6). |Voltage
+ |42 |Auxiliary ch 7 voltage measurement (VAux7). |Voltage
+ |43 |Auxiliary ch 8 voltage measurement (VAux8). |Voltage
+ |44 |Auxiliary ch 9 voltage measurement (VAux9). |Voltage
+ |45 |Auxiliary ch 10 voltage measurement (VAux10). |Voltage
+ |46 |Auxiliary ch 11 voltage measurement (VAux11). |Voltage
+ |47 |Auxiliary ch 12 voltage measurement (VAux12). |Voltage
+ |48 |Auxiliary ch 13 voltage measurement (VAux13). |Voltage
+ |49 |Auxiliary ch 14 voltage measurement (VAux14). |Voltage
+ |50 |Auxiliary ch 15 voltage measurement (VAux15). |Voltage
+ --------------------------------------------------------------------------------------------------------
+
+properties:
+ compatible:
+ enum:
+ - xlnx,zynqmp-ams
+
+ interrupts:
+ maxItems: 1
+
+ reg:
+ description: AMS Controller register space
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: AMS reference clock
+
+ ranges:
+ description:
+ Maps the child address space for PS and/or PL.
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+ '#io-channel-cells':
+ const: 1
+
+ ams-ps@0:
+ type: object
+ description: |
+ PS (Processing System) SYSMON is memory mapped to PS. This block has
+ built-in alarm generation logic that is used to interrupt the processor
+ based on condition set.
+
+ properties:
+ compatible:
+ enum:
+ - xlnx,zynqmp-ams-ps
+
+ reg:
+ description: Register Space for PS-SYSMON
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+
+ additionalProperties: false
+
+ ams-pl@400:
+ type: object
+ additionalProperties: false
+ description:
+ PL-SYSMON is capable of monitoring off chip voltage and temperature.
+ PL-SYSMON block has DRP, JTAG and I2C interface to enable monitoring
+ from external master. Out of this interface currently only DRP is
+ supported. This block has alarm generation logic that is used to
+ interrupt the processor based on condition set.
+
+ properties:
+ compatible:
+ items:
+ - enum:
+ - xlnx,zynqmp-ams-pl
+
+ reg:
+ description: Register Space for PL-SYSMON.
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ patternProperties:
+ "^channel@([2-4][0-9]|50)$":
+ type: object
+ description:
+ Describes the external channels connected.
+
+ properties:
+ reg:
+ description:
+ Pair of pins the channel is connected to. This value is
+ same as Channel Number for a particular channel.
+ minimum: 20
+ maximum: 50
+
+ xlnx,bipolar:
+ $ref: /schemas/types.yaml#/definitions/flag
+ type: boolean
+ description:
+ If the set channel is used in bipolar mode.
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ xilinx_ams: ams@ffa50000 {
+ compatible = "xlnx,zynqmp-ams";
+ interrupt-parent = <&gic>;
+ interrupts = <0 56 4>;
+ reg = <0x0 0xffa50000 0x0 0x800>;
+ clocks = <&zynqmp_clk AMS_REF>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #io-channel-cells = <1>;
+ ranges = <0 0 0xffa50800 0x800>;
+
+ ams_ps: ams-ps@0 {
+ compatible = "xlnx,zynqmp-ams-ps";
+ reg = <0 0x400>;
+ };
+
+ ams_pl: ams-pl@400 {
+ compatible = "xlnx,zynqmp-ams-pl";
+ reg = <0x400 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel@30 {
+ reg = <30>;
+ xlnx,bipolar;
+ };
+ channel@31 {
+ reg = <31>;
+ };
+ channel@38 {
+ reg = <38>;
+ xlnx,bipolar;
+ };
+ };
+ };
+ };