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+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dvfs/performance-domain.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic performance domains
+
+maintainers:
+ - Sudeep Holla <sudeep.holla@arm.com>
+
+description: |+
+ This binding is intended for performance management of groups of devices or
+ CPUs that run in the same performance domain. Performance domains must not
+ be confused with power domains. A performance domain is defined by a set
+ of devices that always have to run at the same performance level. For a given
+ performance domain, there is a single point of control that affects all the
+ devices in the domain, making it impossible to set the performance level of
+ an individual device in the domain independently from other devices in
+ that domain. For example, a set of CPUs that share a voltage domain, and
+ have a common frequency control, is said to be in the same performance
+ domain.
+
+ This device tree binding can be used to bind performance domain consumer
+ devices with their performance domains provided by performance domain
+ providers. A performance domain provider can be represented by any node in
+ the device tree and can provide one or more performance domains. A consumer
+ node can refer to the provider by a phandle and a set of phandle arguments
+ (so called performance domain specifiers) of length specified by the
+ \#performance-domain-cells property in the performance domain provider node.
+
+select: true
+
+properties:
+ "#performance-domain-cells":
+ description:
+ Number of cells in a performance domain specifier. Typically 0 for nodes
+ representing a single performance domain and 1 for nodes providing
+ multiple performance domains (e.g. performance controllers), but can be
+ any value as specified by device tree binding documentation of particular
+ provider.
+ enum: [ 0, 1 ]
+
+ performance-domains:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ A phandle and performance domain specifier as defined by bindings of the
+ performance controller/provider specified by phandle.
+
+additionalProperties: true
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ performance: performance-controller@11bc00 {
+ compatible = "mediatek,cpufreq-hw";
+ reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+
+ #performance-domain-cells = <1>;
+ };
+ };
+
+ // The node above defines a performance controller that is a performance
+ // domain provider and expects one cell as its phandle argument.
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x0>;
+ performance-domains = <&performance 1>;
+ };
+ };