| commit | 534a9b3c37400cc7d98bf269b6d8c7d0f9d20791 | [log] [tgz] |
|---|---|---|
| author | York Sun <yorksun@freescale.com> | Fri Oct 26 16:40:14 2012 +0000 |
| committer | Andy Fleming <afleming@freescale.com> | Tue Nov 27 18:28:06 2012 -0600 |
| tree | 5483a1fbc3b8e885b3a16cf60149c888609e6ce8 | |
| parent | e3ab8c133d41e2182705a27ce28bd168e1571fc4 [diff] |
powerpc/corenet_ds: Update DDR timing for single-rank DIMMs Single rank UDIMM timing has been verified with HMT325U7BFR8C-H9 for speed 800, 900, 1000, 1200, 1300MT/s. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>