nds32: Remove the architecture
As removal of nds32 has been ack'd for the Linux kernel, remove support
here as well.
Cc: Rick Chen <rick@andestech.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
diff --git a/doc/README.standalone b/doc/README.standalone
index 874ca2f..3306c30 100644
--- a/doc/README.standalone
+++ b/doc/README.standalone
@@ -56,7 +56,6 @@
ARM 0x0c100000 0x0c100000
MIPS 0x80200000 0x80200000
Blackfin 0x00001000 0x00001000
- NDS32 0x00300000 0x00300000
Nios II 0x02000000 0x02000000
RISC-V 0x00600000 0x00600000
diff --git a/doc/README.watchdog b/doc/README.watchdog
index f23c923..c50dc79 100644
--- a/doc/README.watchdog
+++ b/doc/README.watchdog
@@ -17,12 +17,6 @@
CONFIG_WDT_AT91
Available for AT91SAM9 to service the watchdog.
-CONFIG_FTWDT010_WATCHDOG
- Available for FTWDT010 to service the watchdog.
-
-CONFIG_FTWDT010_HW_TIMEOUT
- Can be used to change the timeout for FTWDT010.
-
CONFIG_IMX_WATCHDOG
Available for i.mx31/35/5x/6x to service the watchdog. This is not
automatically set because some boards (vision2) still need to define
diff --git a/doc/arch/index.rst b/doc/arch/index.rst
index 369d8ee..792d918 100644
--- a/doc/arch/index.rst
+++ b/doc/arch/index.rst
@@ -10,7 +10,6 @@
arm64
m68k
mips
- nds32
nios2
sandbox
sh
diff --git a/doc/arch/nds32.rst b/doc/arch/nds32.rst
deleted file mode 100644
index 502397c..0000000
--- a/doc/arch/nds32.rst
+++ /dev/null
@@ -1,101 +0,0 @@
-.. SPDX-License-Identifier: GPL-2.0+
-
-NDS32
-=====
-
-NDS32 is a new high-performance 32-bit RISC microprocessor core.
-
-http://www.andestech.com/
-
-AndeStar ISA
-------------
-AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to
-achieve optimal system performance, code density, and power efficiency.
-
-It contains the following features:
- - Intermixable 32-bit and 16-bit instruction sets without the need for
- mode switch.
- - 16-bit instructions as a frequently used subset of 32-bit instructions.
- - RISC-style register-based instruction set.
- - 32 32-bit General Purpose Registers (GPR).
- - Upto 1024 User Special Registers (USR) for existing and extension
- instructions.
- - Rich load/store instructions for...
- - Single memory access with base address update.
- - Multiple aligned and unaligned memory accesses for memory copy and stack
- operations.
- - Data prefetch to improve data cache performance.
- - Non-bus locking synchronization instructions.
- - PC relative jump and PC read instructions for efficient position independent
- code.
- - Multiply-add and multiple-sub with 64-bit accumulator.
- - Instruction for efficient power management.
- - Bi-endian support.
- - Three instruction extension space for application acceleration:
- - Performance extension.
- - Andes future extensions (for floating-point, multimedia, etc.)
- - Customer extensions.
-
-AndesCore CPU
--------------
-Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
-
-For details about N12 CPU family, please check below N1213 features.
-N1213 is a configurable hard/soft core of NDS32's N12 CPU family.
-
-N1213 Features
-^^^^^^^^^^^^^^
-
-CPU Core
- - 16-/32-bit mixable instruction format.
- - 32 general-purpose 32-bit registers.
- - 8-stage pipeline.
- - Dynamic branch prediction.
- - 32/64/128/256 BTB.
- - Return address stack (RAS).
- - Vector interrupts for internal/external.
- interrupt controller with 6 hardware interrupt signals.
- - 3 HW-level nested interruptions.
- - User and super-user mode support.
- - Memory-mapped I/O.
- - Address space up to 4GB.
-
-Memory Management Unit
- - TLB
- - 4/8-entry fully associative iTLB/dTLB.
- - 32/64/128-entry 4-way set-associati.ve main TLB.
- - TLB locking support
- - Optional hardware page table walker.
- - Two groups of page size support.
- - 4KB & 1MB.
- - 8KB & 1MB.
-
-Memory Subsystem
- - I & D cache.
- - Virtually indexed and physically tagged.
- - Cache size: 8KB/16KB/32KB/64KB.
- - Cache line size: 16B/32B.
- - Set associativity: 2-way, 4-way or direct-mapped.
- - Cache locking support.
- - I & D local memory (LM).
- - Size: 4KB to 1MB.
- - Bank numbers: 1 or 2.
- - Optional 1D/2D DMA engine.
- - Internal or external to CPU core.
-
-Bus Interface
- - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports.
- - Synchronous High speed memory port.
- (HSMP): 0, 1 or 2 ports.
-
-Debug
- - JTAG debug interface.
- - Embedded debug module (EDM).
- - Optional embedded program tracer interface.
-
-Miscellaneous
- - Programmable data endian control.
- - Performance monitoring mechanism.
-
-The NDS32 ports of u-boot, the Linux kernel, the GNU toolchain and other
-associated software are actively supported by Andes Technology Corporation.
diff --git a/doc/develop/global_data.rst b/doc/develop/global_data.rst
index 230ebcd..2ac893d 100644
--- a/doc/develop/global_data.rst
+++ b/doc/develop/global_data.rst
@@ -23,8 +23,6 @@
+------------+----------+
| MicroBlaze | r31 |
+------------+----------+
-| NDS32 | r10 |
-+------------+----------+
| Nios II | gp |
+------------+----------+
| PowerPC | r2 |
diff --git a/doc/git-mailrc b/doc/git-mailrc
index 410be38..63c2f6e 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -52,7 +52,7 @@
alias priyankajain Priyanka Jain <priyanka.jain@nxp.com>
# Architecture aliases
-alias arch arc, arm, m68k, microblaze, mips, nds32, nios2, powerpc, sandbox, superh, x86
+alias arch arc, arm, m68k, microblaze, mips, nios2, powerpc, sandbox, superh, x86
alias arches arch
alias arc uboot, abrodkin
@@ -90,8 +90,6 @@
alias mips uboot, danielschwierzeck
-alias nds32 uboot, macpaul
-
alias nios uboot, Thomas Chou <thomas@wytron.com.tw>, smcnutt
alias nios2 nios