clk: ast2600: Keep PLL power on
According to the PLL vendor, we should keep the PLL power on, so we
shouldn't toggle the power-down bit during PLL initialization.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c
index 0df1dc3..e5ada5b 100644
--- a/drivers/clk/aspeed/clk_ast2600.c
+++ b/drivers/clk/aspeed/clk_ast2600.c
@@ -538,7 +538,7 @@
}
p_cfg->reg.b.bypass = 0;
- p_cfg->reg.b.off = 1;
+ p_cfg->reg.b.off = 0;
p_cfg->reg.b.reset = 1;
reg = readl(addr);
@@ -549,7 +549,6 @@
/* write extend parameter */
writel(p_cfg->ext_reg, addr_ext);
udelay(100);
- p_cfg->reg.b.off = 0;
p_cfg->reg.b.reset = 0;
reg &= ~GENMASK(25, 0);
reg |= p_cfg->reg.w;