Coding style cleanup, update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
diff --git a/cpu/mpc512x/cpu_init.c b/cpu/mpc512x/cpu_init.c
index 566e08b..d6949f6 100644
--- a/cpu/mpc512x/cpu_init.c
+++ b/cpu/mpc512x/cpu_init.c
@@ -76,7 +76,7 @@
*
* NOTICE: TB needs to be enabled as early as possible in order to
* have udelay() working; if not enabled, usually leads to a hang, like
- * during FLASH chip identification etc.
+ * during FLASH chip identification etc.
*/
im->sysconf.spcr |= SPCR_TBEN;
}
diff --git a/cpu/mpc512x/fec.c b/cpu/mpc512x/fec.c
index f1b7a25..1c87a53 100644
--- a/cpu/mpc512x/fec.c
+++ b/cpu/mpc512x/fec.c
@@ -77,20 +77,20 @@
* Trasmit BDs init
*/
for (ix = 0; ix < FEC_TBD_NUM; ix++) {
- fec->bdBase->tbd[ix].status = 0;
- }
+ fec->bdBase->tbd[ix].status = 0;
+ }
- /*
- * Have the last TBD to close the ring
- */
- fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;
+ /*
+ * Have the last TBD to close the ring
+ */
+ fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;
- /*
- * Initialize some indices
- */
- fec->tbdIndex = 0;
- fec->usedTbdIndex = 0;
- fec->cleanTbdNum = FEC_TBD_NUM;
+ /*
+ * Initialize some indices
+ */
+ fec->tbdIndex = 0;
+ fec->usedTbdIndex = 0;
+ fec->cleanTbdNum = FEC_TBD_NUM;
return 0;
}
@@ -238,7 +238,7 @@
fec->eth->r_cntrl = 0x05ee000c;
/* Half-duplex, heartbeat disabled */
- fec->eth->x_cntrl = 0x00000000;
+ fec->eth->x_cntrl = 0x00000000;
/* Enable MIB counters */
fec->eth->mib_control = 0x0;
@@ -260,7 +260,7 @@
/* Initilize addresses and status words of BDs */
mpc512x_fec_bd_init (fec);
- /* Descriptor polling active */
+ /* Descriptor polling active */
fec->eth->r_des_active = 0x01000000;
#if (DEBUG & 0x1)
@@ -296,7 +296,7 @@
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
* and do not drop the Preamble.
*/
- fec->eth->mii_speed = (((gd->ipb_clk / 1000000) / 5) + 1) << 1;
+ fec->eth->mii_speed = (((gd->ipb_clk / 1000000) / 5) + 1) << 1;
/*
* Reset PHY, then delay 300ns
@@ -312,7 +312,7 @@
printf ("Forcing 10 Mbps ethernet link... ");
#endif
miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
-
+
miiphy_write (dev->name, phyAddr, 0x0, 0x0180);
timeout = 20;
@@ -346,7 +346,7 @@
#if (DEBUG & 0x2)
printf ("done.\n");
#endif
- } else { /* MII100 */
+ } else { /* MII100 */
/*
* Set the auto-negotiation advertisement register bits
*/
@@ -487,7 +487,7 @@
pTbd->dataPointer = (uint32)eth_data;
pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
-
+
/* Activate transmit Buffer Descriptor polling */
fec->eth->x_des_active = 0x01000000; /* Descriptor polling active */
@@ -529,7 +529,7 @@
#if (DEBUG & 0x8)
printf( "-" );
#endif
-
+
/*
* Check if any critical events have happened
*/
@@ -555,10 +555,10 @@
}
if (!(pRbd->status & FEC_RBD_EMPTY)) {
- if ((pRbd->status & FEC_RBD_LAST) &&
+ if ((pRbd->status & FEC_RBD_LAST) &&
!(pRbd->status & FEC_RBD_ERR) &&
((pRbd->dataLength - 4) > 14)) {
-
+
/*
* Get buffer size
*/
@@ -635,7 +635,7 @@
* Initialize I\O pins
*/
reg = (uint32 *) &(im->io_ctrl.regs[PSC0_0_IDX]);
-
+
for (i = 0; i < 15; i++)
reg[i] = IOCTRL_MUX_FEC | 0x00000001;
@@ -645,13 +645,13 @@
/* Clean up space FEC's MIB and FIFO RAM ...*/
memset ((void *) MPC512X_FEC + 0x200, 0x00, 0x400);
-
- /*
+
+ /*
* Malloc space for BDs (must be quad word-aligned)
- * this pointer is lost, so cannot be freed
+ * this pointer is lost, so cannot be freed
*/
bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f);
- fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0);
+ fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0);
memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f);
/*
diff --git a/cpu/mpc512x/fec.h b/cpu/mpc512x/fec.h
index 7145919..d2d877a 100644
--- a/cpu/mpc512x/fec.h
+++ b/cpu/mpc512x/fec.h
@@ -28,7 +28,7 @@
volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */
volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */
volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */
-
+
volatile uint32 RES1[3]; /* MBAR_ETH + 0x018-020 */
volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */
@@ -42,10 +42,10 @@
volatile uint32 RES4[7]; /* MBAR_ETH + 0x068-80 */
volatile uint32 r_cntrl; /* MBAR_ETH + 0x084 */
volatile uint32 r_hash; /* MBAR_ETH + 0x088 */
-
+
volatile uint32 RES5[14]; /* MBAR_ETH + 0x08c-0C0 */
volatile uint32 x_cntrl; /* MBAR_ETH + 0x0C4 */
-
+
volatile uint32 RES6[7]; /* MBAR_ETH + 0x0C8-0E0 */
volatile uint32 paddr1; /* MBAR_ETH + 0x0E4 */
volatile uint32 paddr2; /* MBAR_ETH + 0x0E8 */
@@ -63,7 +63,7 @@
volatile uint32 RES9[1]; /* MBAR_ETH + 0x148 */
volatile uint32 r_bound; /* MBAR_ETH + 0x14C */
volatile uint32 r_fstart; /* MBAR_ETH + 0x150 */
-
+
volatile uint32 RES10[11]; /* MBAR_ETH + 0x154-17C */
volatile uint32 r_des_start; /* MBAR_ETH + 0x180 */
volatile uint32 x_des_start; /* MBAR_ETH + 0x184 */
diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c
index 9a31155..a609827 100644
--- a/cpu/mpc512x/speed.c
+++ b/cpu/mpc512x/speed.c
@@ -79,14 +79,14 @@
spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
spll = ref_clk * spmf_mult[spmf];
-
+
sys_div = (im->clk.scfr[1] & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT;
sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0];
csb_clk = sys_clk / 2;
- cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
- core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
+ cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
+ core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
ips_div = (im->clk.scfr[0] & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
if (ips_div != 0) {
diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S
index 8b749ac..244c69b 100644
--- a/cpu/mpc512x/start.S
+++ b/cpu/mpc512x/start.S
@@ -208,8 +208,8 @@
*/
/* Boot CS/CS0 window range */
- lis r3, CFG_IMMR@h
- ori r3, r3, CFG_IMMR@l
+ lis r3, CFG_IMMR@h
+ ori r3, r3, CFG_IMMR@l
lis r4, START_REG(CFG_FLASH_BASE)
ori r4, r4, STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE)
@@ -222,11 +222,11 @@
lis r4, START_REG(CFG_SRAM_BASE) & 0xff00
stw r4, SRAMBAR(r3)
- /*
+ /*
* According to MPC5121e RM, configuring local access windows should
- * be followed by a dummy read of the config register that was
+ * be followed by a dummy read of the config register that was
* modified last and an isync
- */
+ */
lwz r4, SRAMBAR(r3)
isync
@@ -235,11 +235,11 @@
* config register so no params can be set for it
*/
lis r3, (CFG_IMMR + LPC_OFFSET)@h
- ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l
+ ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l
- lis r4, CFG_CS0_CFG@h
- ori r4, r4, CFG_CS0_CFG@l
- stw r4, CS0_CONFIG(r3)
+ lis r4, CFG_CS0_CFG@h
+ ori r4, r4, CFG_CS0_CFG@l
+ stw r4, CS0_CONFIG(r3)
/* Master enable all CS's */
lis r4, CS_CTRL_ME@h