| commit | 0e690fd2f9eb5a81e556c7985193520917ccf16c | [log] [tgz] |
|---|---|---|
| author | Ian Campbell <ijc@hellion.org.uk> | Thu May 08 22:26:33 2014 +0100 |
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | Sun May 25 17:23:15 2014 +0200 |
| tree | 2a4acf997080d86479677a9a7d17cb2a4e0101da | |
| parent | 07c92fc19a71964a2dc5f6aed8666b5635efd825 [diff] |
net/designware: ensure cache invalidations are aligned to ARCH_DMA_MINALIGN This is required at least on ARM. When sending instead of simply invalidating the entire descriptor, flush as little as possible while still respecting ARCH_DMA_MINALIGN, as requested by Alexey. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Alexey Brodkin <abrodkin@synopsys.com>