diff --git a/Kconfig b/Kconfig
index 3ce5ba1..e7002ed 100644
--- a/Kconfig
+++ b/Kconfig
@@ -177,6 +177,10 @@
 	  images of various types (kernel, FDT blob, ramdisk, etc.)
 	  in a single blob.  To boot this new uImage structure,
 	  pass the address of the blob to the "bootm" command.
+	  FIT is very flexible, supporting compression, multiple images,
+	  multiple configurations, verification through hashing and also
+	  verified boot (secure boot using RSA). This option enables that
+	  feature.
 
 config FIT_VERBOSE
 	bool "Display verbose messages on FIT boot"
@@ -191,8 +195,62 @@
 	  This option enables signature verification of FIT uImages,
 	  using a hash signed and verified using RSA. If
 	  CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
-	  hashing is available using hardware, RSA library will use it.
-	  See doc/uImage.FIT/signature.txt for more details.
+	  hashing is available using hardware, then then RSA library will use
+	  it. See doc/uImage.FIT/signature.txt for more details.
+
+	  WARNING: When relying on signed FIT images with a required signature
+	  check the legacy image format is disabled by default, so that
+	  unsigned images cannot be loaded. If a board needs the legacy image
+	  format support in this case, enable it using
+	  CONFIG_IMAGE_FORMAT_LEGACY.
+
+config FIT_BEST_MATCH
+	bool "Select the best match for the kernel device tree"
+	depends on FIT
+	help
+	  When no configuration is explicitly selected, default to the
+	  one whose fdt's compatibility field best matches that of
+	  U-Boot itself. A match is considered "best" if it matches the
+	  most specific compatibility entry of U-Boot's fdt's root node.
+	  The order of entries in the configuration's fdt is ignored.
+
+config FIT_VERBOSE
+	bool "Show verbose messages when FIT images fails"
+	depends on FIT
+	help
+	  Generally a system will have valid FIT images so debug messages
+	  are a waste of code space. If you are debugging your images then
+	  you can enable this option to get more verbose information about
+	  failures.
+
+config OF_BOARD_SETUP
+	bool "Set up board-specific details in device tree before boot"
+	depends on OF_LIBFDT
+	help
+	  This causes U-Boot to call ft_board_setup() before booting into
+	  the Operating System. This function can set up various
+	  board-specific information in the device tree for use by the OS.
+	  The device tree is then passed to the OS.
+
+config OF_SYSTEM_SETUP
+	bool "Set up system-specific details in device tree before boot"
+	depends on OF_LIBFDT
+	help
+	  This causes U-Boot to call ft_system_setup() before booting into
+	  the Operating System. This function can set up various
+	  system-specific information in the device tree for use by the OS.
+	  The device tree is then passed to the OS.
+
+config OF_STDOUT_VIA_ALIAS
+	bool "Update the device-tree stdout alias from U-Boot"
+	depends on OF_LIBFDT
+	help
+	  This uses U-Boot's serial alias from the aliases node to update
+	  the device tree passed to the OS. The "linux,stdout-path" property
+	  in the chosen node is set to point to the correct serial node.
+	  This option currently references CONFIG_CONS_INDEX, which is
+	  incorrect when used with device tree as this option does not
+	  exist / should not be used.
 
 config SYS_EXTRA_OPTIONS
 	string "Extra Options (DEPRECATED)"
@@ -215,6 +273,17 @@
 	help
 	  TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture
 
+config SPL_LOAD_FIT
+	bool "Enable SPL loading U-Boot as a FIT"
+	depends on FIT
+	help
+	  Normally with the SPL framework a legacy image is generated as part
+	  of the build. This contains U-Boot along with information as to
+	  where it should be loaded. This option instead enables generation
+	  of a FIT (Flat Image Tree) which provides more flexibility. In
+	  particular it can handle selecting from multiple device tree
+	  and passing the correct one to U-Boot.
+
 config SYS_CLK_FREQ
 	depends on ARC || ARCH_SUNXI
 	int "CPU clock frequency"
diff --git a/MAINTAINERS b/MAINTAINERS
index 9d447ea..32f97b2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -230,6 +230,13 @@
 F:	include/dm/
 F:	test/dm/
 
+EFI PAYLOAD
+M:	Alexander Graf <agraf@suse.de>
+S:	Maintained
+F:	include/efi_loader.h
+F:	lib/efi_loader/
+F:	cmd/bootefi.c
+
 FLATTENED DEVICE TREE
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
diff --git a/Makefile b/Makefile
index fadf1a3..53569e8 100644
--- a/Makefile
+++ b/Makefile
@@ -5,7 +5,7 @@
 VERSION = 2016
 PATCHLEVEL = 03
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*
@@ -893,9 +893,16 @@
 cmd_cpp_cfg = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \
 	-DDO_DEPS_ONLY -D__ASSEMBLY__ -x assembler-with-cpp -P -dM -E -o $@ $<
 
+ifdef CONFIG_SPL_LOAD_FIT
+MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
+	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
+	-b $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
+else
 MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
 	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
+endif
 
 MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
 
@@ -908,7 +915,8 @@
 MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
 		-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
 
-u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE
+u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl: \
+		$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin dts/dt.dtb,u-boot.bin) FORCE
 	$(call if_changed,mkimage)
 
 u-boot-spl.kwb: u-boot.img spl/u-boot-spl.bin FORCE
@@ -1044,6 +1052,10 @@
 IFDTOOL_FLAGS += -w $(CONFIG_VGA_BIOS_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_VGA_BIOS_FILE)
 endif
 
+ifneq ($(CONFIG_HAVE_REFCODE),)
+IFDTOOL_FLAGS += -w $(CONFIG_X86_REFCODE_ADDR):refcode.bin
+endif
+
 quiet_cmd_ifdtool = IFDTOOL $@
 cmd_ifdtool  = $(IFDTOOL) -c -r $(CONFIG_ROM_SIZE) u-boot.tmp;
 ifneq ($(CONFIG_HAVE_INTEL_ME),)
@@ -1052,7 +1064,15 @@
 cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_FLAGS) u-boot.tmp;
 cmd_ifdtool += mv u-boot.tmp $@
 
+refcode.bin: $(srctree)/board/$(BOARDDIR)/refcode.bin FORCE
+	$(call if_changed,copy)
+
+quiet_cmd_ldr = LD      $@
+cmd_ldr = $(LD) $(LDFLAGS_$(@F)) \
+	       $(filter-out FORCE,$^) -o $@
+
-u-boot.rom: u-boot-x86-16bit.bin u-boot.bin FORCE
+u-boot.rom: u-boot-x86-16bit.bin u-boot.bin FORCE \
+		$(if $(CONFIG_HAVE_REFCODE),refcode.bin)
 	$(call if_changed,ifdtool)
 
 OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
diff --git a/README b/README
index b2eee19..523941f 100644
--- a/README
+++ b/README
@@ -3093,20 +3093,6 @@
 		will set it back to normal.  This command currently
 		supports i.MX53 and i.MX6.
 
-- Signing support:
-		CONFIG_RSA
-
-		This enables the RSA algorithm used for FIT image verification
-		in U-Boot. See doc/uImage.FIT/signature.txt for more information.
-
-		The Modular Exponentiation algorithm in RSA is implemented using
-		driver model. So CONFIG_DM needs to be enabled by default for this
-		library to function.
-
-		The signing part is build into mkimage regardless of this
-		option. The software based modular exponentiation is built into
-		mkimage irrespective of this option.
-
 - bootcount support:
 		CONFIG_BOOTCOUNT_LIMIT
 
@@ -3306,33 +3292,14 @@
 		enabled per default for backward compatibility.
 
 - FIT image support:
-		CONFIG_FIT
-		Enable support for the FIT uImage format.
-
-		CONFIG_FIT_BEST_MATCH
-		When no configuration is explicitly selected, default to the
-		one whose fdt's compatibility field best matches that of
-		U-Boot itself. A match is considered "best" if it matches the
-		most specific compatibility entry of U-Boot's fdt's root node.
-		The order of entries in the configuration's fdt is ignored.
-
-		CONFIG_FIT_SIGNATURE
-		This option enables signature verification of FIT uImages,
-		using a hash signed and verified using RSA. If
-		CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
-		hashing is available using hardware, RSA library will use it.
-		See doc/uImage.FIT/signature.txt for more details.
-
-		WARNING: When relying on signed FIT images with required
-		signature check the legacy image format is default
-		disabled. If a board need legacy image format support
-		enable this through CONFIG_IMAGE_FORMAT_LEGACY
-
 		CONFIG_FIT_DISABLE_SHA256
 		Supporting SHA256 hashes has quite an impact on binary size.
 		For constrained systems sha256 hash support can be disabled
 		with this option.
 
+		TODO(sjg@chromium.org): Adjust this option to be positive,
+		and move it to Kconfig
+
 - Standalone program support:
 		CONFIG_STANDALONE_LOAD_ADDR
 
diff --git a/api/api.c b/api/api.c
index 6b114f0..457dc36 100644
--- a/api/api.c
+++ b/api/api.c
@@ -189,7 +189,7 @@
  *
  *   - net: &eth_device struct address from list pointed to by eth_devices
  *
- *   - storage: block_dev_desc_t struct address from &ide_dev_desc[n],
+ *   - storage: struct blk_desc struct address from &ide_dev_desc[n],
  *     &scsi_dev_desc[n] and similar tables
  *
  ****************************************************************************/
diff --git a/api/api_storage.c b/api/api_storage.c
index bc2b4d6..8c30c56 100644
--- a/api/api_storage.c
+++ b/api/api_storage.c
@@ -103,10 +103,10 @@
 
 	int i;
 
-	block_dev_desc_t *dd;
+	struct blk_desc *dd;
 
 	if (first) {
-		di->cookie = (void *)get_dev(specs[type].name, 0);
+		di->cookie = (void *)blk_get_dev(specs[type].name, 0);
 		if (di->cookie == NULL)
 			return 0;
 		else
@@ -119,7 +119,8 @@
 
 	} else {
 		for (i = 0; i < specs[type].max_dev; i++)
-			if (di->cookie == (void *)get_dev(specs[type].name, i)) {
+			if (di->cookie ==
+			    (void *)blk_get_dev(specs[type].name, i)) {
 				/* previous cookie found -- advance to the
 				 * next device, if possible */
 
@@ -129,7 +130,8 @@
 					break;
 				}
 
-				di->cookie = (void *)get_dev(specs[type].name, i);
+				di->cookie = (void *)blk_get_dev(
+							specs[type].name, i);
 				if (di->cookie == NULL)
 					return 0;
 				else
@@ -148,7 +150,7 @@
 		di->type = specs[type].type;
 
 		if (di->cookie != NULL) {
-			dd = (block_dev_desc_t *)di->cookie;
+			dd = (struct blk_desc *)di->cookie;
 			if (dd->type == DEV_TYPE_UNKNOWN) {
 				debugf("device instance exists, but is not active..");
 				found = 0;
@@ -166,15 +168,15 @@
 
 
 /*
- * returns:	ENUM_IDE, ENUM_USB etc. based on block_dev_desc_t
+ * returns:	ENUM_IDE, ENUM_USB etc. based on struct blk_desc
  */
-static int dev_stor_type(block_dev_desc_t *dd)
+static int dev_stor_type(struct blk_desc *dd)
 {
 	int i, j;
 
 	for (i = ENUM_IDE; i < ENUM_MAX; i++)
 		for (j = 0; j < specs[i].max_dev; j++)
-			if (dd == get_dev(specs[i].name, j))
+			if (dd == blk_get_dev(specs[i].name, j))
 				return i;
 
 	return ENUM_MAX;
@@ -308,12 +310,12 @@
 	return 0;
 }
 
-static int dev_stor_is_valid(int type, block_dev_desc_t *dd)
+static int dev_stor_is_valid(int type, struct blk_desc *dd)
 {
 	int i;
 
 	for (i = 0; i < specs[type].max_dev; i++)
-		if (dd == get_dev(specs[type].name, i))
+		if (dd == blk_get_dev(specs[type].name, i))
 			if (dd->type != DEV_TYPE_UNKNOWN)
 				return 1;
 
@@ -328,7 +330,7 @@
 	if (type == ENUM_MAX)
 		return API_ENODEV;
 
-	if (dev_stor_is_valid(type, (block_dev_desc_t *)cookie))
+	if (dev_stor_is_valid(type, (struct blk_desc *)cookie))
 		return 0;
 
 	return API_ENODEV;
@@ -348,7 +350,7 @@
 lbasize_t dev_read_stor(void *cookie, void *buf, lbasize_t len, lbastart_t start)
 {
 	int type;
-	block_dev_desc_t *dd = (block_dev_desc_t *)cookie;
+	struct blk_desc *dd = (struct blk_desc *)cookie;
 
 	if ((type = dev_stor_type(dd)) == ENUM_MAX)
 		return 0;
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6e5544f..e5f57ef 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -368,6 +368,7 @@
 	select DM
 	select DM_SERIAL
 	select DM_GPIO
+	select TI_I2C_BOARD_DETECT
 
 config TARGET_AM335X_SL50
 	bool "Support am335x_sl50"
@@ -380,6 +381,7 @@
 	bool "Support am43xx_evm"
 	select CPU_V7
 	select SUPPORT_SPL
+	select TI_I2C_BOARD_DETECT
 
 config TARGET_BAV335X
 	bool "Support bav335x"
@@ -448,6 +450,7 @@
 	bool "TI Keystone"
 	select CPU_V7
 	select SUPPORT_SPL
+	select CMD_POWEROFF
 
 config ARCH_MX7
 	bool "Freescale MX7"
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 8fa57ec..9af6c37 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -122,6 +122,10 @@
 OBJCOPYFLAGS += -j .dtb.init.rodata
 endif
 
+ifdef CONFIG_EFI_LOADER
+OBJCOPYFLAGS += -j .efi_runtime -j .efi_runtime_rel
+endif
+
 ifneq ($(CONFIG_IMX_CONFIG),)
 ifdef CONFIG_SPL
 ifndef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index b6db23e..399b07c 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -45,10 +45,10 @@
 
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 static const struct ns16550_platdata lpc32xx_uart[] = {
-	{ UART3_BASE, 2, CONFIG_SYS_NS16550_CLK },
-	{ UART4_BASE, 2, CONFIG_SYS_NS16550_CLK },
-	{ UART5_BASE, 2, CONFIG_SYS_NS16550_CLK },
-	{ UART6_BASE, 2, CONFIG_SYS_NS16550_CLK },
+	{ .base = UART3_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+	{ .base = UART4_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+	{ .base = UART5_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+	{ .base = UART6_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
 };
 
 #if defined(CONFIG_LPC32XX_HSUART)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index e8d5be3..a99cbf9 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -40,14 +40,14 @@
 
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 static const struct ns16550_platdata am33xx_serial[] = {
-	{ CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK },
+	{ .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
 # ifdef CONFIG_SYS_NS16550_COM2
-	{ CONFIG_SYS_NS16550_COM2, 2, CONFIG_SYS_NS16550_CLK },
+	{ .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
 #  ifdef CONFIG_SYS_NS16550_COM3
-	{ CONFIG_SYS_NS16550_COM3, 2, CONFIG_SYS_NS16550_CLK },
-	{ CONFIG_SYS_NS16550_COM4, 2, CONFIG_SYS_NS16550_CLK },
-	{ CONFIG_SYS_NS16550_COM5, 2, CONFIG_SYS_NS16550_CLK },
-	{ CONFIG_SYS_NS16550_COM6, 2, CONFIG_SYS_NS16550_CLK },
+	{ .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+	{ .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+	{ .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
+	{ .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
 #  endif
 # endif
 };
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index a34675c..91a3deb 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -548,7 +548,8 @@
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-	int reg;
+	int reg, count;
+	u8 val;
 
 	/* Turn on HDMI PHY clock */
 	reg = readl(&mxc_ccm->CCGR2);
@@ -565,6 +566,16 @@
 		 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
 		 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 	writel(reg, &mxc_ccm->chsccdr);
+
+	/* Clear the overflow condition */
+	if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
+		/* TMDS software reset */
+		writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
+		val = readb(&hdmi->fc_invidconf);
+		/* Need minimum 3 times to write to clear the register */
+		for (count = 0 ; count < 5 ; count++)
+			writeb(val, &hdmi->fc_invidconf);
+	}
 }
 #endif
 
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index e28b795..cb41055 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -339,7 +339,8 @@
 	debug("MPU DPLL locked\n");
 }
 
-#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP)
+#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \
+	defined(CONFIG_USB_MUSB_OMAP2PLUS)
 static void setup_usb_dpll(void)
 {
 	const struct dpll_params *params;
@@ -406,7 +407,8 @@
 	/* MPU dpll */
 	configure_mpu_dpll();
 
-#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP)
+#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \
+	defined(CONFIG_USB_MUSB_OMAP2PLUS)
 	setup_usb_dpll();
 #endif
 	params = get_ddr_dpll_params(*dplls_data);
@@ -769,7 +771,7 @@
 	wait_for_lock(base);
 }
 
-void setup_clocks_for_console(void)
+static void setup_clocks_for_console(void)
 {
 	/* Do not add any spl_debug prints in this function */
 	clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
@@ -853,14 +855,31 @@
 		disable_clock_domain(clk_domains[i]);
 }
 
-void prcm_init(void)
+/**
+ * setup_early_clocks() - Setup early clocks needed for SoC
+ *
+ * Setup clocks for console, SPL basic initialization clocks and initialize
+ * the timer. This is invoked prior prcm_init.
+ */
+void setup_early_clocks(void)
 {
 	switch (omap_hw_init_context()) {
 	case OMAP_INIT_CONTEXT_SPL:
 	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
 	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+		setup_clocks_for_console();
 		enable_basic_clocks();
 		timer_init();
+		/* Fall through */
+	}
+}
+
+void prcm_init(void)
+{
+	switch (omap_hw_init_context()) {
+	case OMAP_INIT_CONTEXT_SPL:
+	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
+	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
 		scale_vcores(*omap_vcores);
 		setup_dplls();
 		setup_warmreset_time();
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index bf7bf26..9a9c764 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -163,7 +163,11 @@
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
-	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
+	if (!is_dra7xx())
+		writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
+	else
+		writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw);
+
 	writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
 	writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
 	writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
@@ -191,6 +195,7 @@
 	}
 }
 
+#ifndef CONFIG_OMAP44XX
 static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@@ -246,33 +251,39 @@
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 	u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
-	u32 reg, i;
+	u32 reg, i, phy;
 
 	emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7];
+	phy = readl(&emif->emif_ddr_phy_ctrl_1);
 
 	/* Update PHY_REG_RDDQS_RATIO */
 	emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7;
-	for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
-		reg = readl(emif_phy_status++);
-		writel(reg, emif_ext_phy_ctrl_reg++);
-		writel(reg, emif_ext_phy_ctrl_reg++);
-	}
+	if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK))
+		for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
+			reg = readl(emif_phy_status++);
+			writel(reg, emif_ext_phy_ctrl_reg++);
+			writel(reg, emif_ext_phy_ctrl_reg++);
+		}
 
 	/* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
 	emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
-	for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
-		reg = readl(emif_phy_status++);
-		writel(reg, emif_ext_phy_ctrl_reg++);
-		writel(reg, emif_ext_phy_ctrl_reg++);
-	}
+	emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12];
+	if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK))
+		for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
+			reg = readl(emif_phy_status++);
+			writel(reg, emif_ext_phy_ctrl_reg++);
+			writel(reg, emif_ext_phy_ctrl_reg++);
+		}
 
 	/* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
 	emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
-	for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
-		reg = readl(emif_phy_status++);
-		writel(reg, emif_ext_phy_ctrl_reg++);
-		writel(reg, emif_ext_phy_ctrl_reg++);
-	}
+	emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17];
+	if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK))
+		for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
+			reg = readl(emif_phy_status++);
+			writel(reg, emif_ext_phy_ctrl_reg++);
+			writel(reg, emif_ext_phy_ctrl_reg++);
+		}
 
 	/* Disable Leveling */
 	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
@@ -323,8 +334,10 @@
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
-	if (warm_reset())
+	if (warm_reset()) {
 		emif_reset_phy(base);
+		writel(0x0, &emif->emif_pwr_mgmt_ctrl);
+	}
 	do_ext_phy_settings(base, regs);
 
 	writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
@@ -393,6 +406,7 @@
 	else
 		dra7_ddr3_init(base, regs);
 }
+#endif
 
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
@@ -1166,7 +1180,7 @@
 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 
 	/*
-	 * Initializing the LPDDR2 device can not happen from SDRAM.
+	 * Initializing the DDR device can not happen from SDRAM.
 	 * Changing the timing registers in EMIF can happen(going from one
 	 * OPP to another)
 	 */
@@ -1174,15 +1188,19 @@
 		if (emif_sdram_type(regs->sdram_config) ==
 		    EMIF_SDRAM_TYPE_LPDDR2)
 			lpddr2_init(base, regs);
+#ifndef CONFIG_OMAP44XX
 		else
 			ddr3_init(base, regs);
+#endif
 	}
+#ifdef CONFIG_OMAP54X
 	if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
 	    EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
 		set_lpmode_selfrefresh(base);
 		emif_reset_phy(base);
 		omap5_ddr3_leveling(base, regs);
 	}
+#endif
 
 	/* Write to the shadow registers */
 	emif_update_timings(base, regs);
@@ -1317,6 +1335,8 @@
 			&hw_lisa_map_regs->dmm_lisa_map_1);
 		writel(lisa_map_regs->dmm_lisa_map_0,
 			&hw_lisa_map_regs->dmm_lisa_map_0);
+
+		setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK);
 	}
 
 	/*
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 80794f9..01c2d57 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -35,13 +35,13 @@
 {
 	switch (omap_hw_init_context()) {
 	case OMAP_INIT_CONTEXT_SPL:
-		set_muxconf_regs_essential();
+		set_muxconf_regs();
 		break;
 	case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
 		break;
 	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
 	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
-		set_muxconf_regs_essential();
+		set_muxconf_regs();
 		break;
 	}
 }
@@ -84,34 +84,36 @@
 {
 }
 
-#ifdef CONFIG_ARCH_CPU_INIT
-/*
- * SOC specific cpu init
+/**
+ * do_board_detect() - Detect board description
+ *
+ * Function to detect board description. This is expected to be
+ * overridden in the SoC family board file where desired.
  */
-int arch_cpu_init(void)
+void __weak do_board_detect(void)
 {
-#ifdef CONFIG_SPL
-	save_omap_boot_params();
-#endif
-	return 0;
+}
+
+void s_init(void)
+{
 }
-#endif /* CONFIG_ARCH_CPU_INIT */
 
-/*
- * Routine: s_init
- * Description: Does early system init of watchdog, muxing,  andclocks
+/**
+ * early_system_init - Does Early system initialization.
+ *
+ * Does early system init of watchdog, muxing,  andclocks
  * Watchdog disable is done always. For the rest what gets done
- * depends on the boot mode in which this function is executed
- *   1. s_init of SPL running from SRAM
- *   2. s_init of U-Boot running from FLASH
- *   3. s_init of U-Boot loaded to SDRAM by SPL
- *   4. s_init of U-Boot loaded to SDRAM by ROM code using the
+ * depends on the boot mode in which this function is executed when
+ *   1. SPL running from SRAM
+ *   2. U-Boot running from FLASH
+ *   3. U-Boot loaded to SDRAM by SPL
+ *   4. U-Boot loaded to SDRAM by ROM code using the
  *	Configuration Header feature
  * Please have a look at the respective functions to see what gets
  * done in each of these cases
  * This function is called with SRAM stack.
  */
-void s_init(void)
+void early_system_init(void)
 {
 	init_omap_revision();
 	hw_data_init();
@@ -125,16 +127,17 @@
 	set_mux_conf_regs();
 #ifdef CONFIG_SPL_BUILD
 	srcomp_enable();
-	setup_clocks_for_console();
-
 	do_io_settings();
 #endif
+	setup_early_clocks();
+	do_board_detect();
 	prcm_init();
 }
 
 #ifdef CONFIG_SPL_BUILD
 void board_init_f(ulong dummy)
 {
+	early_system_init();
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 	board_early_init_f();
 #endif
@@ -143,6 +146,12 @@
 }
 #endif
 
+int arch_cpu_init_dm(void)
+{
+	early_system_init();
+	return 0;
+}
+
 /*
  * Routine: wait_for_command_complete
  * Description: Wait for posting to finish on watchdog
diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
index ccd0c83..8fec715 100644
--- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
@@ -35,7 +35,7 @@
 
 	. = ALIGN(4);
 	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*_i2c_*)));
+		KEEP(*(SORT(.u_boot_list*)));
 	} >.sram
 
 	. = ALIGN(4);
diff --git a/arch/arm/cpu/armv7/omap3/boot.c b/arch/arm/cpu/armv7/omap3/boot.c
index 44d7c30..64b242b 100644
--- a/arch/arm/cpu/armv7/omap3/boot.c
+++ b/arch/arm/cpu/armv7/omap3/boot.c
@@ -57,12 +57,16 @@
 	return boot_devices[sys_boot];
 }
 
-char omap_reboot_mode(void)
+int omap_reboot_mode(char *mode, unsigned int length)
 {
 	u32 reboot_mode;
 	char c;
 
-	reboot_mode = readl((u32 *)(OMAP34XX_SCRATCHPAD + 4));
+	if (length < 2)
+		return -1;
+
+	reboot_mode = readl((u32 *)(OMAP34XX_SCRATCHPAD +
+		OMAP_REBOOT_REASON_OFFSET));
 
 	c = (reboot_mode >> 24) & 0xff;
 	if (c != 'B')
@@ -74,23 +78,27 @@
 
 	c = reboot_mode & 0xff;
 
-	return c;
+	mode[0] = c;
+	mode[1] = '\0';
+
+	return 0;
 }
 
 int omap_reboot_mode_clear(void)
 {
-	writel(0, (u32 *)(OMAP34XX_SCRATCHPAD + 4));
+	writel(0, (u32 *)(OMAP34XX_SCRATCHPAD + OMAP_REBOOT_REASON_OFFSET));
 
 	return 0;
 }
 
-int omap_reboot_mode_store(char c)
+int omap_reboot_mode_store(char *mode)
 {
 	u32 reboot_mode;
 
-	reboot_mode = 'B' << 24 | 'M' << 16 | c;
+	reboot_mode = 'B' << 24 | 'M' << 16 | mode[0];
 
-	writel(reboot_mode, (u32 *)(OMAP34XX_SCRATCHPAD + 4));
+	writel(reboot_mode, (u32 *)(OMAP34XX_SCRATCHPAD +
+		OMAP_REBOOT_REASON_OFFSET));
 
 	return 0;
 }
diff --git a/arch/arm/cpu/armv7/omap4/Kconfig b/arch/arm/cpu/armv7/omap4/Kconfig
index df27ea1..49adb8e 100644
--- a/arch/arm/cpu/armv7/omap4/Kconfig
+++ b/arch/arm/cpu/armv7/omap4/Kconfig
@@ -13,6 +13,9 @@
 config TARGET_OMAP4_SDP4430
 	bool "TI OMAP4 SDP4430"
 
+config TARGET_KC1
+	bool "Amazon Kindle Fire (first generation)"
+
 endchoice
 
 config SYS_SOC
@@ -21,5 +24,6 @@
 source "board/gumstix/duovero/Kconfig"
 source "board/ti/panda/Kconfig"
 source "board/ti/sdp4430/Kconfig"
+source "board/amazon/kc1/Kconfig"
 
 endif
diff --git a/arch/arm/cpu/armv7/omap4/boot.c b/arch/arm/cpu/armv7/omap4/boot.c
index 4b5aa77..7f5791e 100644
--- a/arch/arm/cpu/armv7/omap4/boot.c
+++ b/arch/arm/cpu/armv7/omap4/boot.c
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/omap_common.h>
+#include <asm/arch/sys_proto.h>
 #include <spl.h>
 
 static u32 boot_devices[] = {
@@ -58,3 +59,47 @@
 
 	return boot_devices[sys_boot];
 }
+
+int omap_reboot_mode(char *mode, unsigned int length)
+{
+	unsigned int limit;
+	unsigned int i;
+
+	if (length < 2)
+		return -1;
+
+	if (!warm_reset())
+		return -1;
+
+	limit = (length < OMAP_REBOOT_REASON_SIZE) ? length :
+		OMAP_REBOOT_REASON_SIZE;
+
+	for (i = 0; i < (limit - 1); i++)
+		mode[i] = readb((u8 *)(OMAP44XX_SAR_RAM_BASE +
+			OMAP_REBOOT_REASON_OFFSET + i));
+
+	mode[i] = '\0';
+
+	return 0;
+}
+
+int omap_reboot_mode_clear(void)
+{
+	writeb(0, (u8 *)(OMAP44XX_SAR_RAM_BASE + OMAP_REBOOT_REASON_OFFSET));
+
+	return 0;
+}
+
+int omap_reboot_mode_store(char *mode)
+{
+	unsigned int i;
+
+	for (i = 0; i < (OMAP_REBOOT_REASON_SIZE - 1) && mode[i] != '\0'; i++)
+		writeb(mode[i], (u8 *)(OMAP44XX_SAR_RAM_BASE +
+			OMAP_REBOOT_REASON_OFFSET + i));
+
+	writeb('\0', (u8 *)(OMAP44XX_SAR_RAM_BASE +
+		OMAP_REBOOT_REASON_OFFSET + i));
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index e89032b..403c3c6 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -96,7 +96,7 @@
 	&timings_jedec_400_mhz
 };
 
-static const struct lpddr2_device_timings jedec_default_timings = {
+const struct lpddr2_device_timings jedec_default_timings = {
 	.ac_timings = jedec_ac_timings,
 	.min_tck = &min_tck_jedec
 };
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
index 029533c..02c06c1 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -355,6 +355,10 @@
 		(*prcm)->cm_l4per_gptimer2_clkctrl,
 		(*prcm)->cm_wkup_wdtimer2_clkctrl,
 		(*prcm)->cm_l4per_uart3_clkctrl,
+		(*prcm)->cm_l4per_i2c1_clkctrl,
+		(*prcm)->cm_l4per_i2c2_clkctrl,
+		(*prcm)->cm_l4per_i2c3_clkctrl,
+		(*prcm)->cm_l4per_i2c4_clkctrl,
 		0
 	};
 
@@ -372,10 +376,14 @@
 	setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
 			GPTIMER1_CLKCTRL_CLKSEL_MASK);
 
-	/* Enable optional 48M functional clock for USB  PHY */
+	/* Enable optional 48M functional clock for USB PHY */
 	setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
 			USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
 
+	/* Enable 32 KHz clock for USB PHY */
+	setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
+			USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
 	do_enable_clocks(clk_domains_essential,
 			 clk_modules_hw_auto_essential,
 			 clk_modules_explicit_en_essential,
@@ -391,7 +399,6 @@
 	u32 const clk_modules_hw_auto_essential[] = {
 		(*prcm)->cm_l3init_hsusbotg_clkctrl,
 		(*prcm)->cm_l3init_usbphy_clkctrl,
-		(*prcm)->cm_l3init_usbphy_clkctrl,
 		(*prcm)->cm_clksel_usb_60mhz,
 		(*prcm)->cm_l3init_hsusbtll_clkctrl,
 		0
@@ -399,10 +406,6 @@
 
 	u32 const clk_modules_explicit_en_essential[] = {
 		(*prcm)->cm_l4per_mcspi1_clkctrl,
-		(*prcm)->cm_l4per_i2c1_clkctrl,
-		(*prcm)->cm_l4per_i2c2_clkctrl,
-		(*prcm)->cm_l4per_i2c3_clkctrl,
-		(*prcm)->cm_l4per_i2c4_clkctrl,
 		(*prcm)->cm_l3init_hsusbhost_clkctrl,
 		0
 	};
diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c
index a09581e..2f0e1e8 100644
--- a/arch/arm/cpu/armv7/omap4/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c
@@ -129,6 +129,7 @@
 	.cm_div_m2_dpll_unipro = 0x4a0081d0,
 	.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
 	.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
+	.cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640,
 
 	/* cm2.core */
 	.cm_l3_1_clkstctrl = 0x4a008700,
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index 4462c72..78b4f09 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -147,14 +147,14 @@
 
 #else
 
-static const struct lpddr2_device_details elpida_2G_S4_details = {
+const struct lpddr2_device_details elpida_2G_S4_details = {
 	.type		= LPDDR2_TYPE_S4,
 	.density	= LPDDR2_DENSITY_2Gb,
 	.io_width	= LPDDR2_IO_WIDTH_32,
 	.manufacturer	= LPDDR2_MANUFACTURER_ELPIDA
 };
 
-static const struct lpddr2_device_details elpida_4G_S4_details = {
+const struct lpddr2_device_details elpida_4G_S4_details = {
 	.type		= LPDDR2_TYPE_S4,
 	.density	= LPDDR2_DENSITY_4Gb,
 	.io_width	= LPDDR2_IO_WIDTH_32,
@@ -278,7 +278,7 @@
 		&timings_elpida_400_mhz
 };
 
-static const struct lpddr2_device_timings elpida_2G_S4_timings = {
+const struct lpddr2_device_timings elpida_2G_S4_timings = {
 	.ac_timings	= elpida_ac_timings,
 	.min_tck	= &min_tck_elpida,
 };
diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig
index bfa264e..026bf24 100644
--- a/arch/arm/cpu/armv7/omap5/Kconfig
+++ b/arch/arm/cpu/armv7/omap5/Kconfig
@@ -12,9 +12,11 @@
 
 config TARGET_DRA7XX_EVM
 	bool "TI DRA7XX"
+	select TI_I2C_BOARD_DETECT
 
 config TARGET_BEAGLE_X15
 	bool "BeagleBoard X15"
+	select TI_I2C_BOARD_DETECT
 
 endchoice
 
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index a8d63c2..7dc5bb7 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -137,81 +137,6 @@
 	.emif_rd_wr_exec_thresh         = 0x40000305
 };
 
-const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
-	.sdram_config_init              = 0x61851ab2,
-	.sdram_config                   = 0x61851ab2,
-	.sdram_config2			= 0x08000000,
-	.ref_ctrl                       = 0x000040F1,
-	.ref_ctrl_final			= 0x00001035,
-	.sdram_tim1                     = 0xCCCF36B3,
-	.sdram_tim2                     = 0x308F7FDA,
-	.sdram_tim3                     = 0x027F88A8,
-	.read_idle_ctrl                 = 0x00050000,
-	.zq_config                      = 0x0007190B,
-	.temp_alert_config              = 0x00000000,
-	.emif_ddr_phy_ctlr_1_init       = 0x0024400B,
-	.emif_ddr_phy_ctlr_1            = 0x0E24400B,
-	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
-	.emif_ddr_ext_phy_ctrl_2        = 0x00910091,
-	.emif_ddr_ext_phy_ctrl_3        = 0x00950095,
-	.emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
-	.emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
-	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
-	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
-	.emif_rd_wr_lvl_ctl             = 0x00000000,
-	.emif_rd_wr_exec_thresh         = 0x00000305
-};
-
-const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
-	.sdram_config_init              = 0x61851B32,
-	.sdram_config                   = 0x61851B32,
-	.sdram_config2			= 0x08000000,
-	.ref_ctrl                       = 0x000040F1,
-	.ref_ctrl_final			= 0x00001035,
-	.sdram_tim1                     = 0xCCCF36B3,
-	.sdram_tim2                     = 0x308F7FDA,
-	.sdram_tim3                     = 0x027F88A8,
-	.read_idle_ctrl                 = 0x00050000,
-	.zq_config                      = 0x0007190B,
-	.temp_alert_config              = 0x00000000,
-	.emif_ddr_phy_ctlr_1_init       = 0x0024400B,
-	.emif_ddr_phy_ctlr_1            = 0x0E24400B,
-	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
-	.emif_ddr_ext_phy_ctrl_2        = 0x00910091,
-	.emif_ddr_ext_phy_ctrl_3        = 0x00950095,
-	.emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
-	.emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
-	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
-	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
-	.emif_rd_wr_lvl_ctl             = 0x00000000,
-	.emif_rd_wr_exec_thresh         = 0x00000305
-};
-
-const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
-	.sdram_config_init              = 0x61862B32,
-	.sdram_config                   = 0x61862B32,
-	.sdram_config2			= 0x08000000,
-	.ref_ctrl                       = 0x0000514C,
-	.ref_ctrl_final			= 0x0000144A,
-	.sdram_tim1                     = 0xD113781C,
-	.sdram_tim2                     = 0x305A7FDA,
-	.sdram_tim3                     = 0x409F86A8,
-	.read_idle_ctrl                 = 0x00050000,
-	.zq_config                      = 0x5007190B,
-	.temp_alert_config              = 0x00000000,
-	.emif_ddr_phy_ctlr_1_init       = 0x0024400D,
-	.emif_ddr_phy_ctlr_1            = 0x0E24400D,
-	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
-	.emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
-	.emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,
-	.emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
-	.emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
-	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
-	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
-	.emif_rd_wr_lvl_ctl             = 0x00000000,
-	.emif_rd_wr_exec_thresh         = 0x00000305
-};
-
 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
 	.dmm_lisa_map_0 = 0x0,
 	.dmm_lisa_map_1 = 0x0,
@@ -220,53 +145,6 @@
 	.is_ma_present	= 0x1
 };
 
-/*
- * DRA752 EVM board has 1.5 GB of memory
- * EMIF1 --> 2Gb * 2 =  512MB
- * EMIF2 --> 2Gb * 4 =  1GB
- * so mapping 1GB interleaved and 512MB non-interleaved
- */
-const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = {
-	.dmm_lisa_map_0 = 0x0,
-	.dmm_lisa_map_1 = 0x80640300,
-	.dmm_lisa_map_2 = 0xC0500220,
-	.dmm_lisa_map_3 = 0xFF020100,
-	.is_ma_present	= 0x1
-};
-
-/*
- * DRA752 EVM EMIF1 ONLY CONFIGURATION
- */
-const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
-	.dmm_lisa_map_0 = 0x0,
-	.dmm_lisa_map_1 = 0x0,
-	.dmm_lisa_map_2 = 0x80500100,
-	.dmm_lisa_map_3 = 0xFF020100,
-	.is_ma_present	= 0x1
-};
-
-/*
- * DRA752 EVM EMIF2 ONLY CONFIGURATION
- */
-const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
-	.dmm_lisa_map_0 = 0x0,
-	.dmm_lisa_map_1 = 0x0,
-	.dmm_lisa_map_2 = 0x80600200,
-	.dmm_lisa_map_3 = 0xFF020100,
-	.is_ma_present	= 0x1
-};
-
-/*
- * DRA722 EVM EMIF1 CONFIGURATION
- */
-const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
-	.dmm_lisa_map_0 = 0x0,
-	.dmm_lisa_map_1 = 0x0,
-	.dmm_lisa_map_2 = 0x80600100,
-	.dmm_lisa_map_3 = 0xFF020100,
-	.is_ma_present	= 0x1
-};
-
 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 {
 	switch (omap_revision()) {
@@ -280,25 +158,9 @@
 		*regs = &emif_regs_532_mhz_2cs_es2;
 		break;
 	case OMAP5432_ES2_0:
+	default:
 		*regs = &emif_regs_ddr3_532_mhz_1cs_es2;
 		break;
-	case DRA752_ES1_0:
-	case DRA752_ES1_1:
-	case DRA752_ES2_0:
-		switch (emif_nr) {
-		case 1:
-			*regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
-			break;
-		case 2:
-			*regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1;
-			break;
-		}
-		break;
-	case DRA722_ES1_0:
-		*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
-		break;
-	default:
-		*regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
 	}
 }
 
@@ -313,16 +175,9 @@
 	case OMAP5430_ES2_0:
 	case OMAP5432_ES1_0:
 	case OMAP5432_ES2_0:
+	default:
 		*dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
 		break;
-	case DRA752_ES1_0:
-	case DRA752_ES1_1:
-	case DRA752_ES2_0:
-		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
-		break;
-	case DRA722_ES1_0:
-	default:
-		*dmm_lisa_regs = &lisa_map_2G_x_2;
 	}
 
 }
@@ -643,11 +498,12 @@
 	u32 *emif_ext_phy_ctrl_base = 0;
 	u32 emif_nr;
 	const u32 *ext_phy_ctrl_const_regs;
-	u32 i, hw_leveling, size;
+	u32 i, hw_leveling, size, phy;
 
 	emif_nr = (base == EMIF1_BASE) ? 1 : 2;
 
 	hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT;
+	phy = regs->emif_ddr_phy_ctlr_1_init;
 
 	emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1);
 
@@ -657,18 +513,35 @@
 	writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]);
 	writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]);
 
-	if (!hw_leveling) {
-		/*
-		 * Copy the predefined PHY register values
-		 * in case of sw leveling
-		 */
-		for (i = 1; i < 25; i++) {
+	/*
+	 * Copy the predefined PHY register values
+	 * if leveling is disabled.
+	 */
+	if (phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)
+		for (i = 1; i < 6; i++) {
+			writel(ext_phy_ctrl_const_regs[i],
+			       &emif_ext_phy_ctrl_base[i * 2]);
+			writel(ext_phy_ctrl_const_regs[i],
+			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
+		}
+
+	if (phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK)
+		for (i = 6; i < 11; i++) {
 			writel(ext_phy_ctrl_const_regs[i],
 			       &emif_ext_phy_ctrl_base[i * 2]);
 			writel(ext_phy_ctrl_const_regs[i],
 			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
 		}
-	} else {
+
+	if (phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)
+		for (i = 11; i < 25; i++) {
+			writel(ext_phy_ctrl_const_regs[i],
+			       &emif_ext_phy_ctrl_base[i * 2]);
+			writel(ext_phy_ctrl_const_regs[i],
+			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
+		}
+
+	if (hw_leveling) {
 		/*
 		 * Write the init value for HW levling to occur
 		 */
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index ab8c089..a9f4fec 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -10,6 +10,7 @@
 #include <asm-offsets.h>
 #include <config.h>
 #include <asm/macro.h>
+#include <asm/system.h>
 #include <linux/linkage.h>
 
 /*
@@ -160,3 +161,56 @@
 	ret
 ENDPROC(__asm_flush_l3_cache)
 	.weak	__asm_flush_l3_cache
+
+/*
+ * void __asm_switch_ttbr(ulong new_ttbr)
+ *
+ * Safely switches to a new page table.
+ */
+ENTRY(__asm_switch_ttbr)
+	/* x2 = SCTLR (alive throghout the function) */
+	switch_el x4, 3f, 2f, 1f
+3:	mrs	x2, sctlr_el3
+	b	0f
+2:	mrs	x2, sctlr_el2
+	b	0f
+1:	mrs	x2, sctlr_el1
+0:
+
+	/* Unset CR_M | CR_C | CR_I from SCTLR to disable all caches */
+	movn	x1, #(CR_M | CR_C | CR_I)
+	and	x1, x2, x1
+	switch_el x4, 3f, 2f, 1f
+3:	msr	sctlr_el3, x1
+	b	0f
+2:	msr	sctlr_el2, x1
+	b	0f
+1:	msr	sctlr_el1, x1
+0:	isb
+
+	/* This call only clobbers x30 (lr) and x9 (unused) */
+	mov	x3, x30
+	bl	__asm_invalidate_tlb_all
+
+	/* From here on we're running safely with caches disabled */
+
+	/* Set TTBR to our first argument */
+	switch_el x4, 3f, 2f, 1f
+3:	msr	ttbr0_el3, x0
+	b	0f
+2:	msr	ttbr0_el2, x0
+	b	0f
+1:	msr	ttbr0_el1, x0
+0:	isb
+
+	/* Restore original SCTLR and thus enable caches again */
+	switch_el x4, 3f, 2f, 1f
+3:	msr	sctlr_el3, x2
+	b	0f
+2:	msr	sctlr_el2, x2
+	b	0f
+1:	msr	sctlr_el1, x2
+0:	isb
+
+	ret	x3
+ENDPROC(__asm_switch_ttbr)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 71f0020..d1bd06b 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -2,6 +2,9 @@
  * (C) Copyright 2013
  * David Feng <fenghua@phytium.com.cn>
  *
+ * (C) Copyright 2016
+ * Alexander Graf <agraf@suse.de>
+ *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
@@ -13,137 +16,388 @@
 
 #ifndef CONFIG_SYS_DCACHE_OFF
 
-#ifdef CONFIG_SYS_FULL_VA
-static void set_ptl1_entry(u64 index, u64 ptl2_entry)
+/*
+ *  With 4k page granule, a virtual address is split into 4 lookup parts
+ *  spanning 9 bits each:
+ *
+ *    _______________________________________________
+ *   |       |       |       |       |       |       |
+ *   |   0   |  Lv0  |  Lv1  |  Lv2  |  Lv3  |  off  |
+ *   |_______|_______|_______|_______|_______|_______|
+ *     63-48   47-39   38-30   29-21   20-12   11-00
+ *
+ *             mask        page size
+ *
+ *    Lv0: FF8000000000       --
+ *    Lv1:   7FC0000000       1G
+ *    Lv2:     3FE00000       2M
+ *    Lv3:       1FF000       4K
+ *    off:          FFF
+ */
+
+static u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
+{
+	u64 max_addr = 0;
+	u64 ips, va_bits;
+	u64 tcr;
+	int i;
+
+	/* Find the largest address we need to support */
+	for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
+		max_addr = max(max_addr, mem_map[i].base + mem_map[i].size);
+
+	/* Calculate the maximum physical (and thus virtual) address */
+	if (max_addr > (1ULL << 44)) {
+		ips = 5;
+		va_bits = 48;
+	} else  if (max_addr > (1ULL << 42)) {
+		ips = 4;
+		va_bits = 44;
+	} else  if (max_addr > (1ULL << 40)) {
+		ips = 3;
+		va_bits = 42;
+	} else  if (max_addr > (1ULL << 36)) {
+		ips = 2;
+		va_bits = 40;
+	} else  if (max_addr > (1ULL << 32)) {
+		ips = 1;
+		va_bits = 36;
+	} else {
+		ips = 0;
+		va_bits = 32;
+	}
+
+	if (el == 1) {
+		tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
+	} else if (el == 2) {
+		tcr = TCR_EL2_RSVD | (ips << 16);
+	} else {
+		tcr = TCR_EL3_RSVD | (ips << 16);
+	}
+
+	/* PTWs cacheable, inner/outer WBWA and inner shareable */
+	tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
+	tcr |= TCR_T0SZ(va_bits);
+
+	if (pips)
+		*pips = ips;
+	if (pva_bits)
+		*pva_bits = va_bits;
+
+	return tcr;
+}
+
+#define MAX_PTE_ENTRIES 512
+
+static int pte_type(u64 *pte)
 {
-	u64 *pgd = (u64 *)gd->arch.tlb_addr;
-	u64 value;
+	return *pte & PTE_TYPE_MASK;
+}
 
-	value = ptl2_entry | PTL1_TYPE_TABLE;
-	pgd[index] = value;
+/* Returns the LSB number for a PTE on level <level> */
+static int level2shift(int level)
+{
+	/* Page is 12 bits wide, every level translates 9 bits */
+	return (12 + 9 * (3 - level));
 }
 
-static void set_ptl2_block(u64 ptl1, u64 bfn, u64 address, u64 memory_attrs)
+static u64 *find_pte(u64 addr, int level)
 {
-	u64 *pmd = (u64 *)ptl1;
-	u64 value;
+	int start_level = 0;
+	u64 *pte;
+	u64 idx;
+	u64 va_bits;
+	int i;
 
-	value = address | PTL2_TYPE_BLOCK | PTL2_BLOCK_AF;
-	value |= memory_attrs;
-	pmd[bfn] = value;
+	debug("addr=%llx level=%d\n", addr, level);
+
+	get_tcr(0, NULL, &va_bits);
+	if (va_bits < 39)
+		start_level = 1;
+
+	if (level < start_level)
+		return NULL;
+
+	/* Walk through all page table levels to find our PTE */
+	pte = (u64*)gd->arch.tlb_addr;
+	for (i = start_level; i < 4; i++) {
+		idx = (addr >> level2shift(i)) & 0x1FF;
+		pte += idx;
+		debug("idx=%llx PTE %p at level %d: %llx\n", idx, pte, i, *pte);
+
+		/* Found it */
+		if (i == level)
+			return pte;
+		/* PTE is no table (either invalid or block), can't traverse */
+		if (pte_type(pte) != PTE_TYPE_TABLE)
+			return NULL;
+		/* Off to the next level */
+		pte = (u64*)(*pte & 0x0000fffffffff000ULL);
+	}
+
+	/* Should never reach here */
+	return NULL;
 }
 
-static struct mm_region mem_map[] = CONFIG_SYS_MEM_MAP;
+/* Returns and creates a new full table (512 entries) */
+static u64 *create_table(void)
+{
+	u64 *new_table = (u64*)gd->arch.tlb_fillptr;
+	u64 pt_len = MAX_PTE_ENTRIES * sizeof(u64);
 
-#define PTL1_ENTRIES CONFIG_SYS_PTL1_ENTRIES
-#define PTL2_ENTRIES CONFIG_SYS_PTL2_ENTRIES
+	/* Allocate MAX_PTE_ENTRIES pte entries */
+	gd->arch.tlb_fillptr += pt_len;
 
-static void setup_pgtables(void)
+	if (gd->arch.tlb_fillptr - gd->arch.tlb_addr > gd->arch.tlb_size)
+		panic("Insufficient RAM for page table: 0x%lx > 0x%lx. "
+		      "Please increase the size in get_page_table_size()",
+			gd->arch.tlb_fillptr - gd->arch.tlb_addr,
+			gd->arch.tlb_size);
+
+	/* Mark all entries as invalid */
+	memset(new_table, 0, pt_len);
+
+	return new_table;
+}
+
+static void set_pte_table(u64 *pte, u64 *table)
+{
+	/* Point *pte to the new table */
+	debug("Setting %p to addr=%p\n", pte, table);
+	*pte = PTE_TYPE_TABLE | (ulong)table;
+}
+
+/* Add one mm_region map entry to the page tables */
+static void add_map(struct mm_region *map)
+{
+	u64 *pte;
+	u64 addr = map->base;
+	u64 size = map->size;
+	u64 attrs = map->attrs | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
+	u64 blocksize;
+	int level;
+	u64 *new_table;
+
+	while (size) {
+		pte = find_pte(addr, 0);
+		if (pte && (pte_type(pte) == PTE_TYPE_FAULT)) {
+			debug("Creating table for addr 0x%llx\n", addr);
+			new_table = create_table();
+			set_pte_table(pte, new_table);
+		}
+
+		for (level = 1; level < 4; level++) {
+			pte = find_pte(addr, level);
+			blocksize = 1ULL << level2shift(level);
+			debug("Checking if pte fits for addr=%llx size=%llx "
+			      "blocksize=%llx\n", addr, size, blocksize);
+			if (size >= blocksize && !(addr & (blocksize - 1))) {
+				/* Page fits, create block PTE */
+				debug("Setting PTE %p to block addr=%llx\n",
+				      pte, addr);
+				*pte = addr | attrs;
+				addr += blocksize;
+				size -= blocksize;
+				break;
+			} else if ((pte_type(pte) == PTE_TYPE_FAULT)) {
+				/* Page doesn't fit, create subpages */
+				debug("Creating subtable for addr 0x%llx "
+				      "blksize=%llx\n", addr, blocksize);
+				new_table = create_table();
+				set_pte_table(pte, new_table);
+			}
+		}
+	}
+}
+
+/* Splits a block PTE into table with subpages spanning the old block */
+static void split_block(u64 *pte, int level)
 {
-	int l1_e, l2_e;
-	unsigned long pmd = 0;
-	unsigned long address;
+	u64 old_pte = *pte;
+	u64 *new_table;
+	u64 i = 0;
+	/* level describes the parent level, we need the child ones */
+	int levelshift = level2shift(level + 1);
+
+	if (pte_type(pte) != PTE_TYPE_BLOCK)
+		panic("PTE %p (%llx) is not a block. Some driver code wants to "
+		      "modify dcache settings for an range not covered in "
+		      "mem_map.", pte, old_pte);
+
+	new_table = create_table();
+	debug("Splitting pte %p (%llx) into %p\n", pte, old_pte, new_table);
+
+	for (i = 0; i < MAX_PTE_ENTRIES; i++) {
+		new_table[i] = old_pte | (i << levelshift);
 
-	/* Setup the PMD pointers */
-	for (l1_e = 0; l1_e < CONFIG_SYS_MEM_MAP_SIZE; l1_e++) {
-		gd->arch.pmd_addr[l1_e] = gd->arch.tlb_addr +
-						PTL1_ENTRIES * sizeof(u64);
-		gd->arch.pmd_addr[l1_e] += PTL2_ENTRIES * sizeof(u64) * l1_e;
-		gd->arch.pmd_addr[l1_e] = ALIGN(gd->arch.pmd_addr[l1_e],
-						0x10000UL);
+		/* Level 3 block PTEs have the table type */
+		if ((level + 1) == 3)
+			new_table[i] |= PTE_TYPE_TABLE;
+
+		debug("Setting new_table[%lld] = %llx\n", i, new_table[i]);
 	}
 
+	/* Set the new table into effect */
+	set_pte_table(pte, new_table);
+}
+
+enum pte_type {
+	PTE_INVAL,
+	PTE_BLOCK,
+	PTE_LEVEL,
+};
+
-	/* Setup the page tables */
-	for (l1_e = 0; l1_e < PTL1_ENTRIES; l1_e++) {
-		if (mem_map[pmd].base ==
-			(uintptr_t)l1_e << PTL2_BITS) {
-			set_ptl1_entry(l1_e, gd->arch.pmd_addr[pmd]);
+/*
+ * This is a recursively called function to count the number of
+ * page tables we need to cover a particular PTE range. If you
+ * call this with level = -1 you basically get the full 48 bit
+ * coverage.
+ */
+static int count_required_pts(u64 addr, int level, u64 maxaddr)
+{
+	int levelshift = level2shift(level);
+	u64 levelsize = 1ULL << levelshift;
+	u64 levelmask = levelsize - 1;
+	u64 levelend = addr + levelsize;
+	int r = 0;
+	int i;
+	enum pte_type pte_type = PTE_INVAL;
+
+	for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) {
+		struct mm_region *map = &mem_map[i];
+		u64 start = map->base;
+		u64 end = start + map->size;
+
+		/* Check if the PTE would overlap with the map */
+		if (max(addr, start) <= min(levelend, end)) {
+			start = max(addr, start);
+			end = min(levelend, end);
+
+			/* We need a sub-pt for this level */
+			if ((start & levelmask) || (end & levelmask)) {
+				pte_type = PTE_LEVEL;
+				break;
+			}
 
-			for (l2_e = 0; l2_e < PTL2_ENTRIES; l2_e++) {
-				address = mem_map[pmd].base
-					+ (uintptr_t)l2_e * BLOCK_SIZE;
-				set_ptl2_block(gd->arch.pmd_addr[pmd], l2_e,
-					       address, mem_map[pmd].attrs);
+			/* Lv0 can not do block PTEs, so do levels here too */
+			if (level <= 0) {
+				pte_type = PTE_LEVEL;
+				break;
 			}
 
-			pmd++;
-		} else {
-			set_ptl1_entry(l1_e, 0);
+			/* PTE is active, but fits into a block */
+			pte_type = PTE_BLOCK;
 		}
 	}
+
+	/*
+	 * Block PTEs at this level are already covered by the parent page
+	 * table, so we only need to count sub page tables.
+	 */
+	if (pte_type == PTE_LEVEL) {
+		int sublevel = level + 1;
+		u64 sublevelsize = 1ULL << level2shift(sublevel);
+
+		/* Account for the new sub page table ... */
+		r = 1;
+
+		/* ... and for all child page tables that one might have */
+		for (i = 0; i < MAX_PTE_ENTRIES; i++) {
+			r += count_required_pts(addr, sublevel, maxaddr);
+			addr += sublevelsize;
+
+			if (addr >= maxaddr) {
+				/*
+				 * We reached the end of address space, no need
+				 * to look any further.
+				 */
+				break;
+			}
+		}
+	}
+
+	return r;
 }
 
-#else
+/* Returns the estimated required size of all page tables */
+u64 get_page_table_size(void)
+{
+	u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
+	u64 size = 0;
+	u64 va_bits;
+	int start_level = 0;
+
+	get_tcr(0, NULL, &va_bits);
+	if (va_bits < 39)
+		start_level = 1;
+
+	/* Account for all page tables we would need to cover our memory map */
+	size = one_pt * count_required_pts(0, start_level - 1, 1ULL << va_bits);
+
+	/*
+	 * We need to duplicate our page table once to have an emergency pt to
+	 * resort to when splitting page tables later on
+	 */
+	size *= 2;
+
+	/*
+	 * We may need to split page tables later on if dcache settings change,
+	 * so reserve up to 4 (random pick) page tables for that.
+	 */
+	size += one_pt * 4;
+
+	return size;
+}
 
-inline void set_pgtable_section(u64 *page_table, u64 index, u64 section,
-			 u64 memory_type, u64 attribute)
+static void setup_pgtables(void)
 {
-	u64 value;
+	int i;
+
+	/*
+	 * Allocate the first level we're on with invalidate entries.
+	 * If the starting level is 0 (va_bits >= 39), then this is our
+	 * Lv0 page table, otherwise it's the entry Lv1 page table.
+	 */
+	create_table();
 
-	value = section | PMD_TYPE_SECT | PMD_SECT_AF;
-	value |= PMD_ATTRINDX(memory_type);
-	value |= attribute;
-	page_table[index] = value;
+	/* Now add all MMU table entries one after another to the table */
+	for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
+		add_map(&mem_map[i]);
+
+	/* Create the same thing once more for our emergency page table */
+	create_table();
 }
 
-inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr)
+static void setup_all_pgtables(void)
 {
-	u64 value;
+	u64 tlb_addr = gd->arch.tlb_addr;
+
+	/* Reset the fill ptr */
+	gd->arch.tlb_fillptr = tlb_addr;
 
-	value = (u64)table_addr | PMD_TYPE_TABLE;
-	page_table[index] = value;
+	/* Create normal system page tables */
+	setup_pgtables();
+
+	/* Create emergency page tables */
+	gd->arch.tlb_addr = gd->arch.tlb_fillptr;
+	setup_pgtables();
+	gd->arch.tlb_emerg = gd->arch.tlb_addr;
+	gd->arch.tlb_addr = tlb_addr;
 }
-#endif
 
 /* to activate the MMU we need to set up virtual memory */
 __weak void mmu_setup(void)
 {
-#ifndef CONFIG_SYS_FULL_VA
-	bd_t *bd = gd->bd;
-	u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j;
-#endif
 	int el;
 
-#ifdef CONFIG_SYS_FULL_VA
-	unsigned long coreid = read_mpidr() & CONFIG_COREID_MASK;
+	/* Set up page tables only once */
+	if (!gd->arch.tlb_fillptr)
+		setup_all_pgtables();
 
-	/* Set up page tables only on BSP */
-	if (coreid == BSP_COREID)
-		setup_pgtables();
-#else
-	/* Setup an identity-mapping for all spaces */
-	for (i = 0; i < (PGTABLE_SIZE >> 3); i++) {
-		set_pgtable_section(page_table, i, i << SECTION_SHIFT,
-				    MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE);
-	}
-
-	/* Setup an identity-mapping for all RAM space */
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		ulong start = bd->bi_dram[i].start;
-		ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size;
-		for (j = start >> SECTION_SHIFT;
-		     j < end >> SECTION_SHIFT; j++) {
-			set_pgtable_section(page_table, j, j << SECTION_SHIFT,
-					    MT_NORMAL, PMD_SECT_NON_SHARE);
-		}
-	}
-
-#endif
-	/* load TTBR0 */
 	el = current_el();
-	if (el == 1) {
-		set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
-				  TCR_EL1_RSVD | TCR_FLAGS | TCR_EL1_IPS_BITS,
-				  MEMORY_ATTRIBUTES);
-	} else if (el == 2) {
-		set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
-				  TCR_EL2_RSVD | TCR_FLAGS | TCR_EL2_IPS_BITS,
-				  MEMORY_ATTRIBUTES);
-	} else {
-		set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
-				  TCR_EL3_RSVD | TCR_FLAGS | TCR_EL3_IPS_BITS,
-				  MEMORY_ATTRIBUTES);
-	}
+	set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
+			  MEMORY_ATTRIBUTES);
+
 	/* enable the mmu */
 	set_sctlr(get_sctlr() | CR_M);
 }
@@ -228,36 +482,99 @@
 	return NULL;
 }
 
+static bool is_aligned(u64 addr, u64 size, u64 align)
+{
+	return !(addr & (align - 1)) && !(size & (align - 1));
+}
+
+static u64 set_one_region(u64 start, u64 size, u64 attrs, int level)
+{
+	int levelshift = level2shift(level);
+	u64 levelsize = 1ULL << levelshift;
+	u64 *pte = find_pte(start, level);
+
+	/* Can we can just modify the current level block PTE? */
+	if (is_aligned(start, size, levelsize)) {
+		*pte &= ~PMD_ATTRINDX_MASK;
+		*pte |= attrs;
+		debug("Set attrs=%llx pte=%p level=%d\n", attrs, pte, level);
+
+		return levelsize;
+	}
+
+	/* Unaligned or doesn't fit, maybe split block into table */
+	debug("addr=%llx level=%d pte=%p (%llx)\n", start, level, pte, *pte);
+
+	/* Maybe we need to split the block into a table */
+	if (pte_type(pte) == PTE_TYPE_BLOCK)
+		split_block(pte, level);
+
+	/* And then double-check it became a table or already is one */
+	if (pte_type(pte) != PTE_TYPE_TABLE)
+		panic("PTE %p (%llx) for addr=%llx should be a table",
+		      pte, *pte, start);
+
+	/* Roll on to the next page table level */
+	return 0;
+}
+
-#ifndef CONFIG_SYS_FULL_VA
 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 				     enum dcache_option option)
 {
-	u64 *page_table = arch_get_page_table();
-	u64 upto, end;
+	u64 attrs = PMD_ATTRINDX(option);
+	u64 real_start = start;
+	u64 real_size = size;
 
-	if (page_table == NULL)
-		return;
+	debug("start=%lx size=%lx\n", (ulong)start, (ulong)size);
+
+	/*
+	 * We can not modify page tables that we're currently running on,
+	 * so we first need to switch to the "emergency" page tables where
+	 * we can safely modify our primary page tables and then switch back
+	 */
+	__asm_switch_ttbr(gd->arch.tlb_emerg);
+
+	/*
+	 * Loop through the address range until we find a page granule that fits
+	 * our alignment constraints, then set it to the new cache attributes
+	 */
+	while (size > 0) {
+		int level;
+		u64 r;
 
-	end = ALIGN(start + size, (1 << MMU_SECTION_SHIFT)) >>
-	      MMU_SECTION_SHIFT;
-	start = start >> MMU_SECTION_SHIFT;
-	for (upto = start; upto < end; upto++) {
-		page_table[upto] &= ~PMD_ATTRINDX_MASK;
-		page_table[upto] |= PMD_ATTRINDX(option);
+		for (level = 1; level < 4; level++) {
+			r = set_one_region(start, size, attrs, level);
+			if (r) {
+				/* PTE successfully replaced */
+				size -= r;
+				start += r;
+				break;
+			}
+		}
+
 	}
-	asm volatile("dsb sy");
-	__asm_invalidate_tlb_all();
-	asm volatile("dsb sy");
-	asm volatile("isb");
-	start = start << MMU_SECTION_SHIFT;
-	end = end << MMU_SECTION_SHIFT;
-	flush_dcache_range(start, end);
-	asm volatile("dsb sy");
+
+	/* We're done modifying page tables, switch back to our primary ones */
+	__asm_switch_ttbr(gd->arch.tlb_addr);
+
+	/*
+	 * Make sure there's nothing stale in dcache for a region that might
+	 * have caches off now
+	 */
+	flush_dcache_range(real_start, real_start + real_size);
 }
-#endif
 
 #else	/* CONFIG_SYS_DCACHE_OFF */
 
+/*
+ * For SPL builds, we may want to not have dcache enabled. Any real U-Boot
+ * running however really wants to have dcache and the MMU active. Check that
+ * everything is sane and give the developer a hint if it isn't.
+ */
+#ifndef CONFIG_SPL_BUILD
+#error Please describe your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache.
+#endif
+
 void invalidate_dcache_all(void)
 {
 }
diff --git a/arch/arm/cpu/armv8/exceptions.S b/arch/arm/cpu/armv8/exceptions.S
index baf9401..4f4f526 100644
--- a/arch/arm/cpu/armv8/exceptions.S
+++ b/arch/arm/cpu/armv8/exceptions.S
@@ -82,31 +82,65 @@
 _do_bad_sync:
 	exception_entry
 	bl	do_bad_sync
+	b	exception_exit
 
 _do_bad_irq:
 	exception_entry
 	bl	do_bad_irq
+	b	exception_exit
 
 _do_bad_fiq:
 	exception_entry
 	bl	do_bad_fiq
+	b	exception_exit
 
 _do_bad_error:
 	exception_entry
 	bl	do_bad_error
+	b	exception_exit
 
 _do_sync:
 	exception_entry
 	bl	do_sync
+	b	exception_exit
 
 _do_irq:
 	exception_entry
 	bl	do_irq
+	b	exception_exit
 
 _do_fiq:
 	exception_entry
 	bl	do_fiq
+	b	exception_exit
 
 _do_error:
 	exception_entry
 	bl	do_error
+	b	exception_exit
+
+exception_exit:
+	ldp	x2, x0, [sp],#16
+	switch_el x11, 3f, 2f, 1f
+3:	msr	elr_el3, x2
+	b	0f
+2:	msr	elr_el2, x2
+	b	0f
+1:	msr	elr_el1, x2
+0:
+	ldp	x1, x2, [sp],#16
+	ldp	x3, x4, [sp],#16
+	ldp	x5, x6, [sp],#16
+	ldp	x7, x8, [sp],#16
+	ldp	x9, x10, [sp],#16
+	ldp	x11, x12, [sp],#16
+	ldp	x13, x14, [sp],#16
+	ldp	x15, x16, [sp],#16
+	ldp	x17, x18, [sp],#16
+	ldp	x19, x20, [sp],#16
+	ldp	x21, x22, [sp],#16
+	ldp	x23, x24, [sp],#16
+	ldp	x25, x26, [sp],#16
+	ldp	x27, x28, [sp],#16
+	ldp	x29, x30, [sp],#16
+	eret
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 6ea28ed..7404bd9 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -26,6 +26,14 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static struct mm_region layerscape_mem_map[] = {
+	{
+		/* List terminator */
+		0,
+	}
+};
+struct mm_region *mem_map = layerscape_mem_map;
+
 void cpu_name(char *name)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -48,6 +56,25 @@
 }
 
 #ifndef CONFIG_SYS_DCACHE_OFF
+static void set_pgtable_section(u64 *page_table, u64 index, u64 section,
+			u64 memory_type, u64 attribute)
+{
+       u64 value;
+
+       value = section | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
+       value |= PMD_ATTRINDX(memory_type);
+       value |= attribute;
+       page_table[index] = value;
+}
+
+static void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr)
+{
+       u64 value;
+
+       value = (u64)table_addr | PTE_TYPE_TABLE;
+       page_table[index] = value;
+}
+
 /*
  * Set the block entries according to the information of the table.
  */
@@ -114,10 +141,10 @@
 
 		temp_base -= block_size;
 
-		if ((level_table[index - 1] & PMD_TYPE_MASK) ==
-		    PMD_TYPE_TABLE) {
+		if ((level_table[index - 1] & PTE_TYPE_MASK) ==
+		    PTE_TYPE_TABLE) {
 			level_table = (u64 *)(level_table[index - 1] &
-				      ~PMD_TYPE_MASK);
+				      ~PTE_TYPE_MASK);
 			level++;
 			continue;
 		} else {
@@ -220,7 +247,7 @@
 	struct table_info table = {};
 	struct sys_mmu_table ddr_entry = {
 		0, 0, BLOCK_SIZE_L1, MT_NORMAL,
-		PMD_SECT_OUTER_SHARE | PMD_SECT_NS
+		PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	};
 	u64 index;
 
@@ -243,7 +270,7 @@
 	ddr_entry.virt_addr = phys_addr;
 	ddr_entry.phys_addr = phys_addr;
 	ddr_entry.size = CONFIG_SYS_MEM_RESERVE_SECURE;
-	ddr_entry.attribute = PMD_SECT_OUTER_SHARE;
+	ddr_entry.attribute = PTE_BLOCK_OUTER_SHARE;
 	ret = find_table(&ddr_entry, &table, level0_table);
 	if (ret) {
 		printf("MMU error: could not find secure ddr table\n");
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds
index 4df339c..cc427c3 100644
--- a/arch/arm/cpu/armv8/u-boot-spl.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -54,6 +54,8 @@
 		*(.__end)
 	} >.sram
 
+	_image_binary_end = .;
+
 	.bss_start : {
 		. = ALIGN(8);
 		KEEP(*(.__bss_start));
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index 4c12222..fd15ad5 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -42,6 +42,22 @@
 
 	. = ALIGN(8);
 
+	.efi_runtime : {
+                __efi_runtime_start = .;
+		*(efi_runtime_text)
+		*(efi_runtime_data)
+                __efi_runtime_stop = .;
+	}
+
+	.efi_runtime_rel : {
+                __efi_runtime_rel_start = .;
+		*(.relaefi_runtime_text)
+		*(.relaefi_runtime_data)
+                __efi_runtime_rel_stop = .;
+	}
+
+	. = ALIGN(8);
+
 	.image_copy_end :
 	{
 		*(.__image_copy_end)
diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index c71f291..5dd3cd8 100644
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -8,6 +8,7 @@
 #include <common.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/armv8/mmu.h>
 #include <asm/io.h>
 
 #define ZYNQ_SILICON_VER_MASK	0xF000
@@ -15,6 +16,53 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static struct mm_region zynqmp_mem_map[] = {
+	{
+		.base = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.base = 0x80000000UL,
+		.size = 0x70000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.base = 0xf8000000UL,
+		.size = 0x07e00000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.base = 0xffe00000UL,
+		.size = 0x00200000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.base = 0x400000000UL,
+		.size = 0x200000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.base = 0x600000000UL,
+		.size = 0x800000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.base = 0xe00000000UL,
+		.size = 0xf200000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+struct mm_region *mem_map = zynqmp_mem_map;
+
 static unsigned int zynqmp_get_silicon_version_secure(void)
 {
 	u32 ver;
@@ -44,172 +92,3 @@
 
 	return ZYNQMP_CSU_VERSION_SILICON;
 }
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-#include <asm/armv8/mmu.h>
-
-#define SECTION_SHIFT_L1	30UL
-#define SECTION_SHIFT_L2	21UL
-#define BLOCK_SIZE_L0		0x8000000000UL
-#define BLOCK_SIZE_L1		(1 << SECTION_SHIFT_L1)
-#define BLOCK_SIZE_L2		(1 << SECTION_SHIFT_L2)
-
-#define TCR_TG1_4K		(1 << 31)
-#define TCR_EPD1_DISABLE	(1 << 23)
-#define ZYNQMO_VA_BITS		40
-#define ZYNQMP_TCR		TCR_TG1_4K | \
-				TCR_EPD1_DISABLE | \
-				TCR_SHARED_OUTER | \
-				TCR_SHARED_INNER | \
-				TCR_IRGN_WBWA | \
-				TCR_ORGN_WBWA | \
-				TCR_T0SZ(ZYNQMO_VA_BITS)
-
-#define MEMORY_ATTR	PMD_SECT_AF | PMD_SECT_INNER_SHARE |	\
-			PMD_ATTRINDX(MT_NORMAL) |	\
-			PMD_TYPE_SECT
-#define DEVICE_ATTR	PMD_SECT_AF | PMD_SECT_PXN |	\
-			PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) |	\
-			PMD_TYPE_SECT
-
-/* 4K size is required to place 512 entries in each level */
-#define TLB_TABLE_SIZE	0x1000
-
-struct attr_tbl {
-	u32 num;
-	u64 attr;
-};
-
-static struct attr_tbl attr_tbll1t0[4] = { {16, 0x0},
-					   {8, DEVICE_ATTR},
-					   {32, MEMORY_ATTR},
-					   {456, DEVICE_ATTR}
-					 };
-static struct attr_tbl attr_tbll2t3[4] = { {0x180, DEVICE_ATTR},
-					   {0x40, 0x0},
-					   {0x3F, DEVICE_ATTR},
-					   {0x1, MEMORY_ATTR}
-					 };
-
-/*
- * This mmu table looks as below
- * Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0
- * and other Level1 Table1.
- * Level1 Table0 contains entries for each 1GB from 0 to 511GB.
- * Level1 Table1 contains entries for each 1GB from 512GB to 1TB.
- * Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains
- * entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively.
- */
-static void zynqmp_mmu_setup(void)
-{
-	int el;
-	u32 index_attr;
-	u64 i, section_l1t0, section_l1t1;
-	u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3;
-	u64 *level0_table = (u64 *)gd->arch.tlb_addr;
-	u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE);
-	u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE));
-	u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE));
-	u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE));
-	u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE));
-	u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE));
-
-	level0_table[0] =
-		(u64)level1_table_0 | PMD_TYPE_TABLE;
-	level0_table[1] =
-		(u64)level1_table_1 | PMD_TYPE_TABLE;
-
-	/*
-	 * set level 1 table 0, covering 0 to 512GB
-	 * set level 1 table 1, covering 512GB to 1TB
-	 */
-	section_l1t0 = 0;
-	section_l1t1 = BLOCK_SIZE_L0;
-
-	index_attr = 0;
-	for (i = 0; i < 512; i++) {
-		level1_table_0[i] = section_l1t0;
-		level1_table_0[i] |= attr_tbll1t0[index_attr].attr;
-		attr_tbll1t0[index_attr].num--;
-		if (attr_tbll1t0[index_attr].num == 0)
-			index_attr++;
-		level1_table_1[i] = section_l1t1;
-		level1_table_1[i] |= DEVICE_ATTR;
-		section_l1t0 += BLOCK_SIZE_L1;
-		section_l1t1 += BLOCK_SIZE_L1;
-	}
-
-	level1_table_0[0] =
-		(u64)level2_table_0 | PMD_TYPE_TABLE;
-	level1_table_0[1] =
-		(u64)level2_table_1 | PMD_TYPE_TABLE;
-	level1_table_0[2] =
-		(u64)level2_table_2 | PMD_TYPE_TABLE;
-	level1_table_0[3] =
-		(u64)level2_table_3 | PMD_TYPE_TABLE;
-
-	section_l2t0 = 0;
-	section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */
-	section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */
-	section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */
-
-	index_attr = 0;
-
-	for (i = 0; i < 512; i++) {
-		level2_table_0[i] = section_l2t0 | MEMORY_ATTR;
-		level2_table_1[i] = section_l2t1 | MEMORY_ATTR;
-		level2_table_2[i] = section_l2t2 | DEVICE_ATTR;
-		level2_table_3[i] = section_l2t3 |
-				    attr_tbll2t3[index_attr].attr;
-		attr_tbll2t3[index_attr].num--;
-		if (attr_tbll2t3[index_attr].num == 0)
-			index_attr++;
-		section_l2t0 += BLOCK_SIZE_L2;
-		section_l2t1 += BLOCK_SIZE_L2;
-		section_l2t2 += BLOCK_SIZE_L2;
-		section_l2t3 += BLOCK_SIZE_L2;
-	}
-
-	/* flush new MMU table */
-	flush_dcache_range(gd->arch.tlb_addr,
-			   gd->arch.tlb_addr + gd->arch.tlb_size);
-
-	/* point TTBR to the new table */
-	el = current_el();
-	set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
-			  ZYNQMP_TCR, MEMORY_ATTRIBUTES);
-
-	set_sctlr(get_sctlr() | CR_M);
-}
-
-int arch_cpu_init(void)
-{
-	icache_enable();
-	__asm_invalidate_dcache_all();
-	__asm_invalidate_tlb_all();
-	return 0;
-}
-
-/*
- * This function is called from lib/board.c.
- * It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
- * There is no need to disable d-cache for this operation.
- */
-void enable_caches(void)
-{
-	/* The data cache is not active unless the mmu is enabled */
-	if (!(get_sctlr() & CR_M)) {
-		invalidate_dcache_all();
-		__asm_invalidate_tlb_all();
-		zynqmp_mmu_setup();
-	}
-	puts("Enabling Caches...\n");
-
-	set_sctlr(get_sctlr() | CR_C);
-}
-
-u64 *arch_get_page_table(void)
-{
-	return (u64 *)(gd->arch.tlb_addr + 0x3000);
-}
-#endif
diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds
index c5b4f7c..068163b 100644
--- a/arch/arm/cpu/u-boot-spl.lds
+++ b/arch/arm/cpu/u-boot-spl.lds
@@ -32,15 +32,8 @@
 	}
 
 	. = ALIGN(4);
-#ifdef CONFIG_SPL_DM
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list_*_driver_*)));
-		KEEP(*(SORT(.u_boot_list_*_uclass_*)));
-	}
-#endif
-	. = .;
 	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*_i2c_*)));
+		KEEP(*(SORT(.u_boot_list*)));
 	}
 
 	. = ALIGN(4);
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index e148ab7..13aa4fa 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -90,6 +90,36 @@
 
 	. = ALIGN(4);
 
+	.__efi_runtime_start : {
+		*(.__efi_runtime_start)
+	}
+
+	.efi_runtime : {
+		*(efi_runtime_text)
+		*(efi_runtime_data)
+	}
+
+	.__efi_runtime_stop : {
+		*(.__efi_runtime_stop)
+	}
+
+	.efi_runtime_rel_start :
+	{
+		*(.__efi_runtime_rel_start)
+	}
+
+	.efi_runtime_rel : {
+		*(.relefi_runtime_text)
+		*(.relefi_runtime_data)
+	}
+
+	.efi_runtime_rel_stop :
+	{
+		*(.__efi_runtime_rel_stop)
+	}
+
+	. = ALIGN(4);
+
 	.image_copy_end :
 	{
 		*(.__image_copy_end)
diff --git a/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
index 0ff41d0..b76c77d 100644
--- a/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
+++ b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
@@ -9,21 +9,21 @@
 /{
 	pinctrl_0: pinctrl@11400000 {
 		#address-cells = <1>;
-		#size-cells = <0>;
+		#size-cells = <1>;
 		compatible = "samsung,exynos4210-pinctrl";
 	};
 
 	pinctrl_1: pinctrl@11000000 {
 		#address-cells = <1>;
-		#size-cells = <0>;
+		#size-cells = <1>;
 		gpx0: gpx0 {
-			reg = <0xc00>;
+			reg = <0xc00 0x20>;
 		};
 	};
 
 	pinctrl_2: pinctrl@03860000 {
 		#address-cells = <1>;
-		#size-cells = <0>;
+		#size-cells = <1>;
 	};
 
 };
diff --git a/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
index 8e5a6c6..33ecc14 100644
--- a/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
+++ b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
@@ -9,37 +9,37 @@
 /{
 	pinctrl_0: pinctrl@11400000 {
 		#address-cells = <1>;
-		#size-cells = <0>;
+		#size-cells = <1>;
 		gpf0: gpf0 {
-			reg = <0x180>;
+			reg = <0x180 0x20>;
 		};
 		gpj0: gpj0 {
-			reg = <0x240>;
+			reg = <0x240 0x20>;
 		};
 	};
 
 	pinctrl_1: pinctrl@11000000 {
 		#address-cells = <1>;
-		#size-cells = <0>;
+		#size-cells = <1>;
 		gpk0: gpk0 {
-			reg = <0x40>;
+			reg = <0x40 0x20>;
 		};
 		gpm0: gpm0 {
-			reg = <0x260>;
+			reg = <0x260 0x20>;
 		};
 		gpx0: gpx0 {
-			reg = <0xc00>;
+			reg = <0xc00 0x20>;
 		};
 	};
 
 	pinctrl_2: pinctrl@03860000 {
 		#address-cells = <1>;
-		#size-cells = <0>;
+		#size-cells = <1>;
 	};
 
 	pinctrl_3: pinctrl@106E0000 {
 		#address-cells = <1>;
-		#size-cells = <0>;
+		#size-cells = <1>;
 	};
 
 };
diff --git a/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi b/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi
index 068c5f6..b8c0526 100644
--- a/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi
+++ b/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi
@@ -9,34 +9,34 @@
 /{
 	pinctrl_0: pinctrl@11400000 {
 		#address-cells = <1>;
-		#size-cells = <0>;
+		#size-cells = <1>;
 		gpc4: gpc4 {
-			reg = <0x2e0>;
+			reg = <0x2e0 0x20>;
 		};
 		gpx0: gpx0 {
-			reg = <0xc00>;
+			reg = <0xc00 0x20>;
 		};
 	};
 
 	pinctrl_1: pinctrl@13400000 {
 		#address-cells = <1>;
-		#size-cells = <0>;
+		#size-cells = <1>;
 	};
 
 	pinctrl_2: pinctrl@10d10000 {
 		#address-cells = <1>;
-		#size-cells = <0>;
+		#size-cells = <1>;
 		gpv2: gpv2 {
-			reg = <0x060>;
+			reg = <0x060 0x20>;
 		};
 		gpv4: gpv4 {
-			reg = <0xc0>;
+			reg = <0xc0 0x20>;
 		};
 	};
 
 	pinctrl_3: pinctrl@03860000 {
 		#address-cells = <1>;
-		#size-cells = <0>;
+		#size-cells = <1>;
 	};
 
 };
diff --git a/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi b/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi
index 635a1b0..341194f 100644
--- a/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi
+++ b/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi
@@ -14,29 +14,29 @@
 	 */
 	pinctrl@14010000 {
 		#address-cells = <1>;
-		#size-cells = <0>;
+		#size-cells = <1>;
 	};
 	pinctrl@13400000 {
 		#address-cells = <1>;
-		#size-cells = <0>;
+		#size-cells = <1>;
 		gpy7 {
 		};
 
 		gpx0 {
-			reg = <0xc00>;
+			reg = <0xc00 0x0>;
 		};
 	};
 	pinctrl@13410000 {
 		#address-cells = <1>;
-		#size-cells = <0>;
+		#size-cells = <1>;
 	};
 	pinctrl@14000000 {
 		#address-cells = <1>;
-		#size-cells = <0>;
+		#size-cells = <1>;
 	};
 	pinctrl@03860000 {
 		#address-cells = <1>;
-		#size-cells = <0>;
+		#size-cells = <1>;
 	};
 
 };
diff --git a/arch/arm/dts/k2g.dtsi b/arch/arm/dts/k2g.dtsi
index bbc2cf9..a3ed444 100644
--- a/arch/arm/dts/k2g.dtsi
+++ b/arch/arm/dts/k2g.dtsi
@@ -81,5 +81,12 @@
 		};
 
 		#include "k2g-netcp.dtsi"
+
+		pmmc: pmmc@2900000 {
+			compatible = "ti,power-processor";
+			reg = <0x02900000 0x40000>;
+			ti,lpsc_module = <1>;
+		};
+
 	};
 };
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index e51c75c..3dab0fc 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/clock/rk3288-cru.h>
 #include <dt-bindings/power-domain/rk3288.h>
 #include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/video/rk3288.h>
 #include "skeleton.dtsi"
 
 / {
@@ -683,6 +684,10 @@
 				reg = <1>;
 				remote-endpoint = <&hdmi_in_vopb>;
 			};
+			vopb_out_lvds: endpoint@2 {
+				reg = <2>;
+				remote-endpoint = <&lvds_in_vopb>;
+			};
 		};
 	};
 
@@ -719,7 +724,10 @@
 				reg = <1>;
 				remote-endpoint = <&hdmi_in_vopl>;
 			};
-
+			vopl_out_lvds: endpoint@2 {
+				reg = <2>;
+				remote-endpoint = <&lvds_in_vopl>;
+			};
 		};
 	};
 
@@ -786,6 +794,34 @@
 		};
 	};
 
+	lvds: lvds@ff96c000 {
+		compatible = "rockchip,rk3288-lvds";
+		reg = <0xff96c000 0x4000>;
+		clocks = <&cru PCLK_LVDS_PHY>;
+		clock-names = "pclk_lvds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&lcdc0_ctl>;
+		rockchip,grf = <&grf>;
+		status = "disabled";
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			lvds_in: port@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				lvds_in_vopb: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_lvds>;
+				};
+				lvds_in_vopl: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_lvds>;
+				};
+			};
+		};
+	};
+
 	hdmi_audio: hdmi_audio {
 		compatible = "rockchip,rk3288-hdmi-audio";
 		i2s-controller = <&i2s>;
@@ -1109,6 +1145,15 @@
 			};
 		};
 
+		lcdc0 {
+			lcdc0_ctl: lcdc0-ctl {
+				rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
+						<1 25 RK_FUNC_1 &pcfg_pull_none>,
+						<1 26 RK_FUNC_1 &pcfg_pull_none>,
+						<1 27 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
 		sdmmc {
 			sdmmc_clk: sdmmc-clk {
 				rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
diff --git a/arch/arm/dts/s5pc110-pinctrl.dtsi b/arch/arm/dts/s5pc110-pinctrl.dtsi
index 2e9d552..07e76c0 100644
--- a/arch/arm/dts/s5pc110-pinctrl.dtsi
+++ b/arch/arm/dts/s5pc110-pinctrl.dtsi
@@ -9,7 +9,7 @@
 / {
 	pinctrl@e0200000 {
 		#address-cells = <1>;
-		#size-cells = <0>;
+		#size-cells = <1>;
 		gpa0: gpa0 {
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -251,7 +251,7 @@
 		};
 
 		gph0: gph0 {
-			reg = <0xc00>;
+			reg = <0xc00 0x20>;
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 15ade84..93bbda3 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -117,48 +117,48 @@
 #ifdef CONFIG_FSL_LSCH3
 	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 	  CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
 	/* For IFC Region #1, only the first 4MB is cache-enabled */
 	{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
-	  CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE },
+	  CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE },
 	{ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 	  CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 	  CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
-	  MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	  MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
 	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
-	  CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	  CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
-	  PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
+	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
 	/* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
 	{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 	  CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
-	  MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	  MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 	  CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
-	  PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
+	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
 #elif defined(CONFIG_FSL_LSCH2)
 	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 	  CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 	  CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
-	  CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	  CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
 	{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
-	  CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	  CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
 	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
 #endif
 };
 
@@ -166,96 +166,96 @@
 #ifdef CONFIG_FSL_LSCH3
 	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 	  CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
-	  PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
+	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
 	{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
 	  CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
-	  CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	  CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 	  CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
 	  CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
 	  CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	/* For QBMAN portal, only the first 64MB is cache-enabled */
 	{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 	  CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN | PMD_SECT_NS },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS },
 	{ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 	  CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 	  CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
-	  MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 	  CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 	  CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 	  CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
 	{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
 	  CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 #endif
 	{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
 	  CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
 	  CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
 	  CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
-	  PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
+	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
 #elif defined(CONFIG_FSL_LSCH2)
 	{ CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
 	  CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 	  CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 	  CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 	  CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
-	  CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+	  CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
-	  PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
+	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
 	{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 	  CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
 	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 	  CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 	  CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 	  CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
-	  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
-	  CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+	  CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
 #endif
 };
 #endif
diff --git a/arch/arm/include/asm/arch-omap3/omap.h b/arch/arm/include/asm/arch-omap3/omap.h
index 2c94a81..bc0e02a 100644
--- a/arch/arm/include/asm/arch-omap3/omap.h
+++ b/arch/arm/include/asm/arch-omap3/omap.h
@@ -249,6 +249,8 @@
 /* ABB tranxdone mask */
 #define OMAP_ABB_MPU_TXDONE_MASK	(0x1 << 26)
 
+#define OMAP_REBOOT_REASON_OFFSET	0x04
+
 /* Boot parameters */
 #ifndef __ASSEMBLY__
 struct omap_boot_parameters {
@@ -260,9 +262,9 @@
 	unsigned int boot_device_descriptor;
 };
 
-char omap_reboot_mode(void);
+int omap_reboot_mode(char *mode, unsigned int length);
 int omap_reboot_mode_clear(void);
-int omap_reboot_mode_store(char c);
+int omap_reboot_mode_store(char *mode);
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h
index f3a682a..a408c0c 100644
--- a/arch/arm/include/asm/arch-omap4/clock.h
+++ b/arch/arm/include/asm/arch-omap4/clock.h
@@ -134,8 +134,11 @@
 /* CM_DSS_DSS_CLKCTRL */
 #define DSS_CLKCTRL_OPTFCLKEN_MASK		0xF00
 
+/* CM_COREAON_USB_PHY_CORE_CLKCTRL */
+#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K	(1 << 8)
+
 /* CM_L3INIT_USBPHY_CLKCTRL */
-#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK	8
+#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK	(1 << 8)
 
 /* CM_MPU_MPU_CLKCTRL */
 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT	24
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index 4712722..5ccda6e 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -120,6 +120,10 @@
 /* ABB tranxdone mask */
 #define OMAP_ABB_MPU_TXDONE_MASK	(0x1 << 7)
 
+#define OMAP44XX_SAR_RAM_BASE		0x4a326000
+#define OMAP_REBOOT_REASON_OFFSET	0xA0C
+#define OMAP_REBOOT_REASON_SIZE		0x0F
+
 /* Boot parameters */
 #ifndef __ASSEMBLY__
 struct omap_boot_parameters {
@@ -129,6 +133,10 @@
 	unsigned char reset_reason;
 	unsigned char ch_flags;
 };
+
+int omap_reboot_mode(char *mode, unsigned int length);
+int omap_reboot_mode_clear(void);
+int omap_reboot_mode_store(char *mode);
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index f30f865..c9f0b3a 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -18,6 +18,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 extern const struct emif_regs emif_regs_elpida_200_mhz_2cs;
 extern const struct emif_regs emif_regs_elpida_380_mhz_1cs;
 extern const struct emif_regs emif_regs_elpida_400_mhz_1cs;
@@ -25,6 +26,17 @@
 extern const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2;
 extern const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2;
 extern const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2;
+#else
+extern const struct lpddr2_device_details elpida_2G_S4_details;
+extern const struct lpddr2_device_details elpida_4G_S4_details;
+#endif
+
+#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+extern const struct lpddr2_device_timings jedec_default_timings;
+#else
+extern const struct lpddr2_device_timings elpida_2G_S4_timings;
+#endif
+
 struct omap_sysinfo {
 	char *board_string;
 };
@@ -34,11 +46,12 @@
 void watchdog_init(void);
 u32 get_device_type(void);
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
-void set_muxconf_regs_essential(void);
+void set_muxconf_regs(void);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
-void setup_clocks_for_console(void);
+void setup_early_clocks(void);
 void prcm_init(void);
+void do_board_detect(void);
 void bypass_dpll(u32 const base);
 void freq_update_core(void);
 u32 get_sys_clk_freq(void);
@@ -51,7 +64,6 @@
 void init_omap_revision(void);
 void do_io_settings(void);
 void sri2c_init(void);
-void gpi2c_init(void);
 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
 u32 warm_reset(void);
 void force_emif_self_refresh(void);
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 7fcb783..804266a 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -45,11 +45,12 @@
 u32 get_device_type(void);
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
 void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size);
-void set_muxconf_regs_essential(void);
+void set_muxconf_regs(void);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
-void setup_clocks_for_console(void);
+void setup_early_clocks(void);
 void prcm_init(void);
+void do_board_detect(void);
 void bypass_dpll(u32 const base);
 void freq_update_core(void);
 u32 get_sys_clk_freq(void);
@@ -62,7 +63,6 @@
 void init_omap_revision(void);
 void do_io_settings(void);
 void sri2c_init(void);
-void gpi2c_init(void);
 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
 u32 warm_reset(void);
 void force_emif_self_refresh(void);
diff --git a/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h b/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h
new file mode 100644
index 0000000..121a898
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2016 Rockchip Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_LVDS_RK3288_H
+#define _ASM_ARCH_LVDS_RK3288_H
+
+#define RK3288_LVDS_CH0_REG0			0x00
+#define RK3288_LVDS_CH0_REG0_LVDS_EN		BIT(7)
+#define RK3288_LVDS_CH0_REG0_TTL_EN		BIT(6)
+#define RK3288_LVDS_CH0_REG0_LANECK_EN		BIT(5)
+#define RK3288_LVDS_CH0_REG0_LANE4_EN		BIT(4)
+#define RK3288_LVDS_CH0_REG0_LANE3_EN		BIT(3)
+#define RK3288_LVDS_CH0_REG0_LANE2_EN		BIT(2)
+#define RK3288_LVDS_CH0_REG0_LANE1_EN		BIT(1)
+#define RK3288_LVDS_CH0_REG0_LANE0_EN		BIT(0)
+
+#define RK3288_LVDS_CH0_REG1			0x04
+#define RK3288_LVDS_CH0_REG1_LANECK_BIAS	BIT(5)
+#define RK3288_LVDS_CH0_REG1_LANE4_BIAS		BIT(4)
+#define RK3288_LVDS_CH0_REG1_LANE3_BIAS		BIT(3)
+#define RK3288_LVDS_CH0_REG1_LANE2_BIAS		BIT(2)
+#define RK3288_LVDS_CH0_REG1_LANE1_BIAS		BIT(1)
+#define RK3288_LVDS_CH0_REG1_LANE0_BIAS		BIT(0)
+
+#define RK3288_LVDS_CH0_REG2			0x08
+#define RK3288_LVDS_CH0_REG2_RESERVE_ON		BIT(7)
+#define RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE	BIT(6)
+#define RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE	BIT(5)
+#define RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE	BIT(4)
+#define RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE	BIT(3)
+#define RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE	BIT(2)
+#define RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE	BIT(1)
+#define RK3288_LVDS_CH0_REG2_PLL_FBDIV8		BIT(0)
+
+#define RK3288_LVDS_CH0_REG3			0x0c
+#define RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK	0xff
+
+#define RK3288_LVDS_CH0_REG4			0x10
+#define RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE	BIT(5)
+#define RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE	BIT(4)
+#define RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE	BIT(3)
+#define RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE	BIT(2)
+#define RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE	BIT(1)
+#define RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE	BIT(0)
+
+#define RK3288_LVDS_CH0_REG5			0x14
+#define RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA	BIT(5)
+#define RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA	BIT(4)
+#define RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA	BIT(3)
+#define RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA	BIT(2)
+#define RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA	BIT(1)
+#define RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA	BIT(0)
+
+#define RK3288_LVDS_CFG_REGC			0x30
+#define RK3288_LVDS_CFG_REGC_PLL_ENABLE		0x00
+#define RK3288_LVDS_CFG_REGC_PLL_DISABLE	0xff
+
+#define RK3288_LVDS_CH0_REGD			0x34
+#define RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK	0x1f
+
+#define RK3288_LVDS_CH0_REG20			0x80
+#define RK3288_LVDS_CH0_REG20_MSB		0x45
+#define RK3288_LVDS_CH0_REG20_LSB		0x44
+
+#define RK3288_LVDS_CFG_REG21			0x84
+#define RK3288_LVDS_CFG_REG21_TX_ENABLE		0x92
+#define RK3288_LVDS_CFG_REG21_TX_DISABLE	0x00
+
+/* fbdiv value is split over 2 registers, with bit8 in reg2 */
+#define RK3288_LVDS_PLL_FBDIV_REG2(_fbd) \
+		(_fbd & BIT(8) ? RK3288_LVDS_CH0_REG2_PLL_FBDIV8 : 0)
+#define RK3288_LVDS_PLL_FBDIV_REG3(_fbd) \
+		(_fbd & RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK)
+#define RK3288_LVDS_PLL_PREDIV_REGD(_pd) \
+		(_pd & RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK)
+
+#define RK3288_LVDS_SOC_CON6_SEL_VOP_LIT	BIT(3)
+
+#define LVDS_FMT_MASK			(7 << 16)
+#define LVDS_MSB			(1 << 3)
+#define LVDS_DUAL			(1 << 4)
+#define LVDS_FMT_1			(1 << 5)
+#define LVDS_TTL_EN			(1 << 6)
+#define LVDS_START_PHASE_RST_1		(1 << 7)
+#define LVDS_DCLK_INV			(1 << 8)
+#define LVDS_CH0_EN			(1 << 11)
+#define LVDS_CH1_EN			(1 << 12)
+#define LVDS_PWRDN			(1 << 15)
+
+#define LVDS_24BIT		(0 << 1)
+#define LVDS_18BIT		(1 << 1)
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
index 0104ba3..0ce3d67 100644
--- a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
@@ -89,6 +89,7 @@
 enum vop_modes {
 	VOP_MODE_EDP = 0,
 	VOP_MODE_HDMI,
+	VOP_MODE_LVDS,
 	VOP_MODE_NONE,
 	VOP_MODE_AUTO_DETECT,
 	VOP_MODE_UNKNOWN,
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 897f010..0d08ed3 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -22,32 +22,19 @@
  * calculated specifically.
  */
 
-#ifndef CONFIG_SYS_FULL_VA
-#define VA_BITS			(42)	/* 42 bits virtual address */
-#else
 #define VA_BITS			CONFIG_SYS_VA_BITS
-#define PTL2_BITS		CONFIG_SYS_PTL2_BITS
-#endif
+#define PTE_BLOCK_BITS		CONFIG_SYS_PTL2_BITS
+
+/*
+ * block/section address mask and size definitions.
+ */
 
 /* PAGE_SHIFT determines the page size */
 #undef  PAGE_SIZE
-#define PAGE_SHIFT		16
+#define PAGE_SHIFT		12
 #define PAGE_SIZE		(1 << PAGE_SHIFT)
 #define PAGE_MASK		(~(PAGE_SIZE-1))
 
-/*
- * block/section address mask and size definitions.
- */
-#ifndef CONFIG_SYS_FULL_VA
-#define SECTION_SHIFT		29
-#define SECTION_SIZE		(UL(1) << SECTION_SHIFT)
-#define SECTION_MASK		(~(SECTION_SIZE-1))
-#else
-#define BLOCK_SHIFT		CONFIG_SYS_BLOCK_SHIFT
-#define BLOCK_SIZE		(UL(1) << BLOCK_SHIFT)
-#define BLOCK_MASK		(~(BLOCK_SIZE-1))
-#endif
-
 /***************************************************************/
 
 /*
@@ -70,63 +57,28 @@
  *
  */
 
-#ifdef CONFIG_SYS_FULL_VA
-/*
- * Level 1 descriptor (PGD).
- */
-
-#define PTL1_TYPE_MASK		(3 << 0)
-#define PTL1_TYPE_TABLE		(3 << 0)
-
-#define PTL1_TABLE_PXN		(1UL << 59)
-#define PTL1_TABLE_XN		(1UL << 60)
-#define PTL1_TABLE_AP		(1UL << 61)
-#define PTL1_TABLE_NS		(1UL << 63)
-
-
-/*
- * Level 2 descriptor (PMD).
- */
+#define PTE_TYPE_MASK		(3 << 0)
+#define PTE_TYPE_FAULT		(0 << 0)
+#define PTE_TYPE_TABLE		(3 << 0)
+#define PTE_TYPE_BLOCK		(1 << 0)
 
-#define PTL2_TYPE_MASK		(3 << 0)
-#define PTL2_TYPE_FAULT		(0 << 0)
-#define PTL2_TYPE_TABLE		(3 << 0)
-#define PTL2_TYPE_BLOCK		(1 << 0)
+#define PTE_TABLE_PXN		(1UL << 59)
+#define PTE_TABLE_XN		(1UL << 60)
+#define PTE_TABLE_AP		(1UL << 61)
+#define PTE_TABLE_NS		(1UL << 63)
 
 /*
  * Block
  */
-#define PTL2_MEMTYPE(x)		((x) << 2)
-#define PTL2_BLOCK_NON_SHARE	(0 << 8)
-#define PTL2_BLOCK_OUTER_SHARE	(2 << 8)
-#define PTL2_BLOCK_INNER_SHARE	(3 << 8)
-#define PTL2_BLOCK_AF		(1 << 10)
-#define PTL2_BLOCK_NG		(1 << 11)
-#define PTL2_BLOCK_PXN		(UL(1) << 53)
-#define PTL2_BLOCK_UXN		(UL(1) << 54)
-
-#else
-/*
- * Level 2 descriptor (PMD).
- */
-#define PMD_TYPE_MASK		(3 << 0)
-#define PMD_TYPE_FAULT		(0 << 0)
-#define PMD_TYPE_TABLE		(3 << 0)
-#define PMD_TYPE_SECT		(1 << 0)
-
-/*
- * Section
- */
-#define PMD_SECT_NS		(1 << 5)
-#define PMD_SECT_NON_SHARE	(0 << 8)
-#define PMD_SECT_OUTER_SHARE	(2 << 8)
-#define PMD_SECT_INNER_SHARE	(3 << 8)
-#define PMD_SECT_AF		(1 << 10)
-#define PMD_SECT_NG		(1 << 11)
-#define PMD_SECT_PXN		(UL(1) << 53)
-#define PMD_SECT_UXN		(UL(1) << 54)
-
-#endif
+#define PTE_BLOCK_MEMTYPE(x)	((x) << 2)
+#define PTE_BLOCK_NS            (1 << 5)
+#define PTE_BLOCK_NON_SHARE	(0 << 8)
+#define PTE_BLOCK_OUTER_SHARE	(2 << 8)
+#define PTE_BLOCK_INNER_SHARE	(3 << 8)
+#define PTE_BLOCK_AF		(1 << 10)
+#define PTE_BLOCK_NG		(1 << 11)
+#define PTE_BLOCK_PXN		(UL(1) << 53)
+#define PTE_BLOCK_UXN		(UL(1) << 54)
 
 /*
  * AttrIndx[2:0]
@@ -154,38 +106,13 @@
 #define TCR_TG0_4K		(0 << 14)
 #define TCR_TG0_64K		(1 << 14)
 #define TCR_TG0_16K		(2 << 14)
-
-#ifndef CONFIG_SYS_FULL_VA
-#define TCR_EL1_IPS_BITS	(UL(3) << 32)	/* 42 bits physical address */
-#define TCR_EL2_IPS_BITS	(3 << 16)	/* 42 bits physical address */
-#define TCR_EL3_IPS_BITS	(3 << 16)	/* 42 bits physical address */
-#else
-#define TCR_EL1_IPS_BITS	CONFIG_SYS_TCR_EL1_IPS_BITS
-#define TCR_EL2_IPS_BITS	CONFIG_SYS_TCR_EL2_IPS_BITS
-#define TCR_EL3_IPS_BITS	CONFIG_SYS_TCR_EL3_IPS_BITS
-#endif
-
-/* PTWs cacheable, inner/outer WBWA and inner shareable */
-#define TCR_FLAGS		(TCR_TG0_64K |		\
-				TCR_SHARED_INNER |	\
-				TCR_ORGN_WBWA |		\
-				TCR_IRGN_WBWA |		\
-				TCR_T0SZ(VA_BITS))
+#define TCR_EPD1_DISABLE	(1 << 23)
 
 #define TCR_EL1_RSVD		(1 << 31)
 #define TCR_EL2_RSVD		(1 << 31 | 1 << 23)
 #define TCR_EL3_RSVD		(1 << 31 | 1 << 23)
 
 #ifndef __ASSEMBLY__
-#ifndef CONFIG_SYS_FULL_VA
-
-void set_pgtable_section(u64 *page_table, u64 index,
-			 u64 section, u64 memory_type,
-			 u64 attribute);
-void set_pgtable_table(u64 *page_table, u64 index,
-		       u64 *table_addr);
-
-#endif
 static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
 {
 	asm volatile("dsb sy");
@@ -212,6 +139,8 @@
 	u64 size;
 	u64 attrs;
 };
+
+extern struct mm_region *mem_map;
 #endif
 
 #endif /* _ASM_ARMV8_MMU_H_ */
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 7986e6e..b00dece 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -478,6 +478,12 @@
 #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK	(0xFF << 4)
 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12
 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK	(0xFFFFF << 12)
+#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_SHIFT		25
+#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK		(1 << 25)
+#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_SHIFT	26
+#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK		(1 << 26)
+#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_SHIFT		27
+#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK		(1 << 27)
 
 /* DDR_PHY_CTRL_2 */
 #define EMIF_REG_DDR_PHY_CTRL_2_SHIFT		0
@@ -539,6 +545,9 @@
 
 /* Memory Adapter */
 #define MA_BASE				0x482AF040
+#define MA_PRIORITY			0x482A2000
+#define MA_HIMEM_INTERLEAVE_UN_SHIFT	8
+#define MA_HIMEM_INTERLEAVE_UN_MASK	(1 << 8)
 
 /* DMM_LISA_MAP */
 #define EMIF_SYS_ADDR_SHIFT		24
@@ -905,8 +914,8 @@
 
 /* Maximum delay before Low Power Modes */
 #define REG_CS_TIM		0x0
-#define REG_SR_TIM		0x0
-#define REG_PD_TIM		0x0
+#define REG_SR_TIM		0xF
+#define REG_PD_TIM		0xF
 
 
 /* EMIF_PWR_MGMT_CTRL register */
@@ -914,7 +923,7 @@
 	((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\
 	((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\
 	((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
-	((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\
+	((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)\
 			& EMIF_REG_LP_MODE_MASK) |\
 	((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\
 			& EMIF_REG_DPD_EN_MASK))\
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
index 0da0599..a32a1d7 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -20,17 +20,12 @@
 #define CONFIG_CMD_BLOB
 #define CONFIG_FSL_SEC_MON
 #define CONFIG_SHA_PROG_HW_ACCEL
-#define CONFIG_RSA
 #define CONFIG_RSA_FREESCALE_EXP
 
 #ifndef CONFIG_FSL_CAAM
 #define CONFIG_FSL_CAAM
 #endif
 
-#ifndef CONFIG_DM
-#define CONFIG_DM
-#endif
-
 #define CONFIG_KEY_REVOCATION
 #ifndef CONFIG_SYS_RAMBOOT
 /* The key used for verification of next level images
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index dcfa098..77d2653 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -38,10 +38,11 @@
 	unsigned long long timer_reset_value;
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 	unsigned long tlb_addr;
-#if defined(CONFIG_SYS_FULL_VA)
-	unsigned long pmd_addr[CONFIG_SYS_PTL1_ENTRIES];
-#endif
 	unsigned long tlb_size;
+#if defined(CONFIG_ARM64)
+	unsigned long tlb_fillptr;
+	unsigned long tlb_emerg;
+#endif
 #endif
 
 #ifdef CONFIG_OMAP_COMMON
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index d7b81c1..aef3126 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -617,6 +617,9 @@
 
 void omap_die_id(unsigned int *die_id);
 
+/* Initialize general purpose I2C(0) on the SoC */
+void gpi2c_init(void);
+
 /* ABB */
 #define OMAP_ABB_NOMINAL_OPP		0
 #define OMAP_ABB_FAST_OPP		1
@@ -710,7 +713,9 @@
 #define OMAP_SRAM_SCRATCH_VCORES_PTR    (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
 #define OMAP_SRAM_SCRATCH_SYS_CTRL	(SRAM_SCRATCH_SPACE_ADDR + 0x20)
 #define OMAP_SRAM_SCRATCH_BOOT_PARAMS	(SRAM_SCRATCH_SPACE_ADDR + 0x24)
-#define OMAP5_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x28)
+#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28)
+#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
+#define OMAP_SRAM_SCRATCH_SPACE_END	(OMAP_SRAM_SCRATCH_BOARD_EEPROM_END)
 
 /* Boot parameters */
 #define DEVICE_DATA_OFFSET	0x18
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 026e7ef..ac1173d 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -17,18 +17,15 @@
 #define CR_WXN		(1 << 19)	/* Write Permision Imply XN	*/
 #define CR_EE		(1 << 25)	/* Exception (Big) Endian	*/
 
-#ifndef CONFIG_SYS_FULL_VA
-#define PGTABLE_SIZE	(0x10000)
-#else
-#define PGTABLE_SIZE	CONFIG_SYS_PGTABLE_SIZE
-#endif
+#ifndef __ASSEMBLY__
+
+u64 get_page_table_size(void);
+#define PGTABLE_SIZE	get_page_table_size()
 
 /* 2MB granularity */
 #define MMU_SECTION_SHIFT	21
 #define MMU_SECTION_SIZE	(1 << MMU_SECTION_SHIFT)
 
-#ifndef __ASSEMBLY__
-
 enum dcache_option {
 	DCACHE_OFF = 0x3,
 };
@@ -97,6 +94,7 @@
 void __asm_invalidate_tlb_all(void);
 void __asm_invalidate_icache_all(void);
 int __asm_flush_l3_cache(void);
+void __asm_switch_ttbr(u64 new_ttbr);
 
 void armv8_switch_to_el2(void);
 void armv8_switch_to_el1(void);
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index f3db7b5..7a0fb58 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -6,7 +6,8 @@
 #
 
 lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \
-			_lshrdi3.o _modsi3.o _udivsi3.o _umodsi3.o div0.o
+			_lshrdi3.o _modsi3.o _udivsi3.o _umodsi3.o div0.o \
+			_uldivmod.o
 
 ifdef CONFIG_CPU_V7M
 obj-y	+= vectors_m.o crt0.o
diff --git a/arch/arm/lib/_uldivmod.S b/arch/arm/lib/_uldivmod.S
new file mode 100644
index 0000000..426c2f2
--- /dev/null
+++ b/arch/arm/lib/_uldivmod.S
@@ -0,0 +1,245 @@
+/*
+ * Copyright 2010, Google Inc.
+ *
+ * Brought in from coreboot uldivmod.S
+ *
+ * SPDX-License-Identifier:     GPL-2.0
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/* We don't use Thumb instructions for now */
+#define ARM(x...)	x
+#define THUMB(x...)
+
+/*
+ * A, Q = r0 + (r1 << 32)
+ * B, R = r2 + (r3 << 32)
+ * A / B = Q ... R
+ */
+
+A_0	.req	r0
+A_1	.req	r1
+B_0	.req	r2
+B_1	.req	r3
+C_0	.req	r4
+C_1	.req	r5
+D_0	.req	r6
+D_1	.req	r7
+
+Q_0	.req	r0
+Q_1	.req	r1
+R_0	.req	r2
+R_1	.req	r3
+
+THUMB(
+TMP	.req	r8
+)
+
+ENTRY(__aeabi_uldivmod)
+	stmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) lr}
+	@ Test if B == 0
+	orrs	ip, B_0, B_1		@ Z set -> B == 0
+	beq	L_div_by_0
+	@ Test if B is power of 2: (B & (B - 1)) == 0
+	subs	C_0, B_0, #1
+	sbc	C_1, B_1, #0
+	tst	C_0, B_0
+	tsteq	B_1, C_1
+	beq	L_pow2
+	@ Test if A_1 == B_1 == 0
+	orrs	ip, A_1, B_1
+	beq	L_div_32_32
+
+L_div_64_64:
+/* CLZ only exists in ARM architecture version 5 and above. */
+#ifdef HAVE_CLZ
+	mov	C_0, #1
+	mov	C_1, #0
+	@ D_0 = clz A
+	teq	A_1, #0
+	clz	D_0, A_1
+	clzeq	ip, A_0
+	addeq	D_0, D_0, ip
+	@ D_1 = clz B
+	teq	B_1, #0
+	clz	D_1, B_1
+	clzeq	ip, B_0
+	addeq	D_1, D_1, ip
+	@ if clz B - clz A > 0
+	subs	D_0, D_1, D_0
+	bls	L_done_shift
+	@ B <<= (clz B - clz A)
+	subs	D_1, D_0, #32
+	rsb	ip, D_0, #32
+	movmi	B_1, B_1, lsl D_0
+ARM(	orrmi	B_1, B_1, B_0, lsr ip	)
+THUMB(	lsrmi	TMP, B_0, ip		)
+THUMB(	orrmi	B_1, B_1, TMP		)
+	movpl	B_1, B_0, lsl D_1
+	mov	B_0, B_0, lsl D_0
+	@ C = 1 << (clz B - clz A)
+	movmi	C_1, C_1, lsl D_0
+ARM(	orrmi	C_1, C_1, C_0, lsr ip	)
+THUMB(	lsrmi	TMP, C_0, ip		)
+THUMB(	orrmi	C_1, C_1, TMP		)
+	movpl	C_1, C_0, lsl D_1
+	mov	C_0, C_0, lsl D_0
+L_done_shift:
+	mov	D_0, #0
+	mov	D_1, #0
+	@ C: current bit; D: result
+#else
+	@ C: current bit; D: result
+	mov	C_0, #1
+	mov	C_1, #0
+	mov	D_0, #0
+	mov	D_1, #0
+L_lsl_4:
+	cmp	B_1, #0x10000000
+	cmpcc	B_1, A_1
+	cmpeq	B_0, A_0
+	bcs	L_lsl_1
+	@ B <<= 4
+	mov	B_1, B_1, lsl #4
+	orr	B_1, B_1, B_0, lsr #28
+	mov	B_0, B_0, lsl #4
+	@ C <<= 4
+	mov	C_1, C_1, lsl #4
+	orr	C_1, C_1, C_0, lsr #28
+	mov	C_0, C_0, lsl #4
+	b	L_lsl_4
+L_lsl_1:
+	cmp	B_1, #0x80000000
+	cmpcc	B_1, A_1
+	cmpeq	B_0, A_0
+	bcs	L_subtract
+	@ B <<= 1
+	mov	B_1, B_1, lsl #1
+	orr	B_1, B_1, B_0, lsr #31
+	mov	B_0, B_0, lsl #1
+	@ C <<= 1
+	mov	C_1, C_1, lsl #1
+	orr	C_1, C_1, C_0, lsr #31
+	mov	C_0, C_0, lsl #1
+	b	L_lsl_1
+#endif
+L_subtract:
+	@ if A >= B
+	cmp	A_1, B_1
+	cmpeq	A_0, B_0
+	bcc	L_update
+	@ A -= B
+	subs	A_0, A_0, B_0
+	sbc	A_1, A_1, B_1
+	@ D |= C
+	orr	D_0, D_0, C_0
+	orr	D_1, D_1, C_1
+L_update:
+	@ if A == 0: break
+	orrs	ip, A_1, A_0
+	beq	L_exit
+	@ C >>= 1
+	movs	C_1, C_1, lsr #1
+	movs	C_0, C_0, rrx
+	@ if C == 0: break
+	orrs	ip, C_1, C_0
+	beq	L_exit
+	@ B >>= 1
+	movs	B_1, B_1, lsr #1
+	mov	B_0, B_0, rrx
+	b	L_subtract
+L_exit:
+	@ Note: A, B & Q, R are aliases
+	mov	R_0, A_0
+	mov	R_1, A_1
+	mov	Q_0, D_0
+	mov	Q_1, D_1
+	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+
+L_div_32_32:
+	@ Note:	A_0 &	r0 are aliases
+	@	Q_1	r1
+	mov	r1, B_0
+	bl	__aeabi_uidivmod
+	mov	R_0, r1
+	mov	R_1, #0
+	mov	Q_1, #0
+	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+
+L_pow2:
+#ifdef HAVE_CLZ
+	@ Note: A, B and Q, R are aliases
+	@ R = A & (B - 1)
+	and	C_0, A_0, C_0
+	and	C_1, A_1, C_1
+	@ Q = A >> log2(B)
+	@ Note: B must not be 0 here!
+	clz	D_0, B_0
+	add	D_1, D_0, #1
+	rsbs	D_0, D_0, #31
+	bpl	L_1
+	clz	D_0, B_1
+	rsb	D_0, D_0, #31
+	mov	A_0, A_1, lsr D_0
+	add	D_0, D_0, #32
+L_1:
+	movpl	A_0, A_0, lsr D_0
+ARM(	orrpl	A_0, A_0, A_1, lsl D_1	)
+THUMB(	lslpl	TMP, A_1, D_1		)
+THUMB(	orrpl	A_0, A_0, TMP		)
+	mov	A_1, A_1, lsr D_0
+	@ Mov back C to R
+	mov	R_0, C_0
+	mov	R_1, C_1
+	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+#else
+	@ Note: A, B and Q, R are aliases
+	@ R = A & (B - 1)
+	and	C_0, A_0, C_0
+	and	C_1, A_1, C_1
+	@ Q = A >> log2(B)
+	@ Note: B must not be 0 here!
+	@ Count the leading zeroes in B.
+	mov	D_0, #0
+	orrs	B_0, B_0, B_0
+	@ If B is greater than 1 << 31, divide A and B by 1 << 32.
+	moveq	A_0, A_1
+	moveq	A_1, #0
+	moveq	B_0, B_1
+	@ Count the remaining leading zeroes in B.
+	movs	B_1, B_0, lsl #16
+	addeq	D_0, #16
+	moveq	B_0, B_0, lsr #16
+	tst	B_0, #0xff
+	addeq	D_0, #8
+	moveq	B_0, B_0, lsr #8
+	tst	B_0, #0xf
+	addeq	D_0, #4
+	moveq	B_0, B_0, lsr #4
+	tst	B_0, #0x3
+	addeq	D_0, #2
+	moveq	B_0, B_0, lsr #2
+	tst	B_0, #0x1
+	addeq	D_0, #1
+	@ Shift A to the right by the appropriate amount.
+	rsb	D_1, D_0, #32
+	mov	Q_0, A_0, lsr D_0
+	orr	Q_0, A_1, lsl D_1
+	mov	Q_1, A_1, lsr D_0
+	@ Move C to R
+	mov	R_0, C_0
+	mov	R_1, C_1
+	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+#endif
+
+L_div_by_0:
+	bl	__div0
+	@ As wrong as it could be
+	mov	Q_0, #0
+	mov	Q_1, #0
+	mov	R_0, #0
+	mov	R_1, #0
+	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+ENDPROC(__aeabi_uldivmod)
diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c
index ec3fb77..ed83043 100644
--- a/arch/arm/lib/interrupts.c
+++ b/arch/arm/lib/interrupts.c
@@ -22,6 +22,7 @@
 #include <common.h>
 #include <asm/proc-armv/ptrace.h>
 #include <asm/u-boot-arm.h>
+#include <efi_loader.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -165,6 +166,7 @@
 
 void do_undefined_instruction (struct pt_regs *pt_regs)
 {
+	efi_restore_gd();
 	printf ("undefined instruction\n");
 	show_regs (pt_regs);
 	bad_mode ();
@@ -172,6 +174,7 @@
 
 void do_software_interrupt (struct pt_regs *pt_regs)
 {
+	efi_restore_gd();
 	printf ("software interrupt\n");
 	show_regs (pt_regs);
 	bad_mode ();
@@ -179,6 +182,7 @@
 
 void do_prefetch_abort (struct pt_regs *pt_regs)
 {
+	efi_restore_gd();
 	printf ("prefetch abort\n");
 	show_regs (pt_regs);
 	bad_mode ();
@@ -186,6 +190,7 @@
 
 void do_data_abort (struct pt_regs *pt_regs)
 {
+	efi_restore_gd();
 	printf ("data abort\n");
 	show_regs (pt_regs);
 	bad_mode ();
@@ -193,6 +198,7 @@
 
 void do_not_used (struct pt_regs *pt_regs)
 {
+	efi_restore_gd();
 	printf ("not used\n");
 	show_regs (pt_regs);
 	bad_mode ();
@@ -200,6 +206,7 @@
 
 void do_fiq (struct pt_regs *pt_regs)
 {
+	efi_restore_gd();
 	printf ("fast interrupt request\n");
 	show_regs (pt_regs);
 	bad_mode ();
@@ -208,6 +215,7 @@
 #ifndef CONFIG_USE_IRQ
 void do_irq (struct pt_regs *pt_regs)
 {
+	efi_restore_gd();
 	printf ("interrupt request\n");
 	show_regs (pt_regs);
 	bad_mode ();
diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c
index b476722..7c9cfce 100644
--- a/arch/arm/lib/interrupts_64.c
+++ b/arch/arm/lib/interrupts_64.c
@@ -7,6 +7,7 @@
 
 #include <common.h>
 #include <linux/compiler.h>
+#include <efi_loader.h>
 
 
 int interrupt_init(void)
@@ -41,6 +42,7 @@
  */
 void do_bad_sync(struct pt_regs *pt_regs, unsigned int esr)
 {
+	efi_restore_gd();
 	printf("Bad mode in \"Synchronous Abort\" handler, esr 0x%08x\n", esr);
 	show_regs(pt_regs);
 	panic("Resetting CPU ...\n");
@@ -51,6 +53,7 @@
  */
 void do_bad_irq(struct pt_regs *pt_regs, unsigned int esr)
 {
+	efi_restore_gd();
 	printf("Bad mode in \"Irq\" handler, esr 0x%08x\n", esr);
 	show_regs(pt_regs);
 	panic("Resetting CPU ...\n");
@@ -61,6 +64,7 @@
  */
 void do_bad_fiq(struct pt_regs *pt_regs, unsigned int esr)
 {
+	efi_restore_gd();
 	printf("Bad mode in \"Fiq\" handler, esr 0x%08x\n", esr);
 	show_regs(pt_regs);
 	panic("Resetting CPU ...\n");
@@ -71,6 +75,7 @@
  */
 void do_bad_error(struct pt_regs *pt_regs, unsigned int esr)
 {
+	efi_restore_gd();
 	printf("Bad mode in \"Error\" handler, esr 0x%08x\n", esr);
 	show_regs(pt_regs);
 	panic("Resetting CPU ...\n");
@@ -81,6 +86,7 @@
  */
 void do_sync(struct pt_regs *pt_regs, unsigned int esr)
 {
+	efi_restore_gd();
 	printf("\"Synchronous Abort\" handler, esr 0x%08x\n", esr);
 	show_regs(pt_regs);
 	panic("Resetting CPU ...\n");
@@ -91,6 +97,7 @@
  */
 void do_irq(struct pt_regs *pt_regs, unsigned int esr)
 {
+	efi_restore_gd();
 	printf("\"Irq\" handler, esr 0x%08x\n", esr);
 	show_regs(pt_regs);
 	panic("Resetting CPU ...\n");
@@ -101,6 +108,7 @@
  */
 void do_fiq(struct pt_regs *pt_regs, unsigned int esr)
 {
+	efi_restore_gd();
 	printf("\"Fiq\" handler, esr 0x%08x\n", esr);
 	show_regs(pt_regs);
 	panic("Resetting CPU ...\n");
@@ -114,6 +122,7 @@
  */
 void __weak do_error(struct pt_regs *pt_regs, unsigned int esr)
 {
+	efi_restore_gd();
 	printf("\"Error\" handler, esr 0x%08x\n", esr);
 	show_regs(pt_regs);
 	panic("Resetting CPU ...\n");
diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c
index a1205c3..6a94522 100644
--- a/arch/arm/lib/sections.c
+++ b/arch/arm/lib/sections.c
@@ -27,4 +27,8 @@
 char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
 char __secure_start[0] __attribute__((section(".__secure_start")));
 char __secure_end[0] __attribute__((section(".__secure_end")));
+char __efi_runtime_start[0] __attribute__((section(".__efi_runtime_start")));
+char __efi_runtime_stop[0] __attribute__((section(".__efi_runtime_stop")));
+char __efi_runtime_rel_start[0] __attribute__((section(".__efi_runtime_rel_start")));
+char __efi_runtime_rel_stop[0] __attribute__((section(".__efi_runtime_rel_stop")));
 char _end[0] __attribute__((section(".__end")));
diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
index acadd1d..1b04206 100644
--- a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
+++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
@@ -30,6 +30,9 @@
 	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
 
 	. = ALIGN(4);
+	.u_boot_list : { KEEP(*(SORT(.u_boot_list*))) } > .sram
+
+	. = ALIGN(4);
 	__image_copy_end = .;
 
 	.end :
diff --git a/arch/arm/mach-at91/armv7/u-boot-spl.lds b/arch/arm/mach-at91/armv7/u-boot-spl.lds
index eccca43..c667c55 100644
--- a/arch/arm/mach-at91/armv7/u-boot-spl.lds
+++ b/arch/arm/mach-at91/armv7/u-boot-spl.lds
@@ -37,6 +37,9 @@
 	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
 
 	. = ALIGN(4);
+	.u_boot_list : { KEEP(*(SORT(.u_boot_list*))) } > .sram
+
+	. = ALIGN(4);
 	__image_copy_end = .;
 
 	.end :
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index a8d3e2f..5d1c5c5 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -22,6 +22,9 @@
 config TARGET_CALIMAIN
 	bool "Calimain board"
 
+config TARGET_LEGOEV3
+	bool "LEGO MINDSTORMS EV3"
+
 endchoice
 
 config SYS_SOC
@@ -31,5 +34,6 @@
 source "board/davinci/da8xxevm/Kconfig"
 source "board/davinci/ea20/Kconfig"
 source "board/omicron/calimain/Kconfig"
+source "board/lego/ev3/Kconfig"
 
 endif
diff --git a/arch/arm/mach-davinci/da850_pinmux.c b/arch/arm/mach-davinci/da850_pinmux.c
index 6105f63..758109e 100644
--- a/arch/arm/mach-davinci/da850_pinmux.c
+++ b/arch/arm/mach-davinci/da850_pinmux.c
@@ -12,6 +12,16 @@
 #include <asm/arch/pinmux_defs.h>
 
 /* SPI pin muxer settings */
+const struct pinmux_config spi0_pins_base[] = {
+	{ pinmux(3), 1, 0 }, /* SPI0_CLK */
+	{ pinmux(3), 1, 2 }, /* SPI0_SOMI */
+	{ pinmux(3), 1, 3 }, /* SPI0_SIMO */
+};
+
+const struct pinmux_config spi0_pins_scs0[] = {
+	{ pinmux(4), 1, 1 }, /* SPI0_SCS[0] */
+};
+
 const struct pinmux_config spi1_pins_base[] = {
 	{ pinmux(5), 1, 2 }, /* SPI1_CLK */
 	{ pinmux(5), 1, 4 }, /* SPI1_SOMI */
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index a4eb0bd..2a0360a 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -503,6 +503,7 @@
 #define DAVINCI_SYSCFG_SUSPSRC_SPI0		(1 << 21)
 #define DAVINCI_SYSCFG_SUSPSRC_SPI1		(1 << 22)
 #define DAVINCI_SYSCFG_SUSPSRC_UART0		(1 << 18)
+#define DAVINCI_SYSCFG_SUSPSRC_UART1		(1 << 19)
 #define DAVINCI_SYSCFG_SUSPSRC_UART2		(1 << 20)
 #define DAVINCI_SYSCFG_SUSPSRC_TIMER0		(1 << 27)
 
diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile
index ffd9ead..b2ffe5b 100644
--- a/arch/arm/mach-keystone/Makefile
+++ b/arch/arm/mach-keystone/Makefile
@@ -8,8 +8,15 @@
 obj-y	+= init.o
 obj-y	+= psc.o
 obj-y	+= clock.o
+obj-y	+= mon.o
+ifndef CONFIG_SPL_BUILD
 obj-y	+= cmd_clock.o
 obj-y	+= cmd_mon.o
+obj-y	+= cmd_poweroff.o
+obj-y	+= cmd_ddr3.o
+endif
 obj-y	+= msmc.o
-obj-y	+= ddr3.o cmd_ddr3.o
+obj-y	+= ddr3.o
 obj-y	+= keystone.o
+obj-$(CONFIG_K2E_EVM) += ddr3_spd.o
+obj-$(CONFIG_K2HK_EVM) += ddr3_spd.o
diff --git a/arch/arm/mach-keystone/clock-k2e.c b/arch/arm/mach-keystone/clock-k2e.c
deleted file mode 100644
index 7d163a4..0000000
--- a/arch/arm/mach-keystone/clock-k2e.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Keystone2: get clk rate for K2E
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clock_defs.h>
-
-/**
- * pll_freq_get - get pll frequency
- * Fout = Fref * NF(mult) / NR(prediv) / OD
- * @pll:	pll identifier
- */
-static unsigned long pll_freq_get(int pll)
-{
-	unsigned long mult = 1, prediv = 1, output_div = 2;
-	unsigned long ret;
-	u32 tmp, reg;
-
-	if (pll == CORE_PLL) {
-		ret = external_clk[sys_clk];
-		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
-			/* PLL mode */
-			tmp = __raw_readl(KS2_MAINPLLCTL0);
-			prediv = (tmp & PLL_DIV_MASK) + 1;
-			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
-				(pllctl_reg_read(pll, mult) &
-				PLLM_MULT_LO_MASK)) + 1;
-			output_div = ((pllctl_reg_read(pll, secctl) >>
-				       PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
-
-			ret = ret / prediv / output_div * mult;
-		}
-	} else {
-		switch (pll) {
-		case PASS_PLL:
-			ret = external_clk[pa_clk];
-			reg = KS2_PASSPLLCTL0;
-			break;
-		case DDR3_PLL:
-			ret = external_clk[ddr3a_clk];
-			reg = KS2_DDR3APLLCTL0;
-			break;
-		default:
-			return 0;
-		}
-
-		tmp = __raw_readl(reg);
-
-		if (!(tmp & PLLCTL_BYPASS)) {
-			/* Bypass disabled */
-			prediv = (tmp & PLL_DIV_MASK) + 1;
-			mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
-			output_div = ((tmp >> PLL_CLKOD_SHIFT) &
-				      PLL_CLKOD_MASK) + 1;
-			ret = ((ret / prediv) * mult) / output_div;
-		}
-	}
-
-	return ret;
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
-	switch (clk) {
-	case core_pll_clk:      return pll_freq_get(CORE_PLL);
-	case pass_pll_clk:      return pll_freq_get(PASS_PLL);
-	case ddr3_pll_clk:      return pll_freq_get(DDR3_PLL);
-	case sys_clk0_1_clk:
-	case sys_clk0_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(1);
-	case sys_clk1_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(2);
-	case sys_clk2_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(3);
-	case sys_clk3_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(4);
-	case sys_clk0_2_clk:    return clk_get_rate(sys_clk0_clk) / 2;
-	case sys_clk0_3_clk:    return clk_get_rate(sys_clk0_clk) / 3;
-	case sys_clk0_4_clk:    return clk_get_rate(sys_clk0_clk) / 4;
-	case sys_clk0_6_clk:    return clk_get_rate(sys_clk0_clk) / 6;
-	case sys_clk0_8_clk:    return clk_get_rate(sys_clk0_clk) / 8;
-	case sys_clk0_12_clk:   return clk_get_rate(sys_clk0_clk) / 12;
-	case sys_clk0_24_clk:   return clk_get_rate(sys_clk0_clk) / 24;
-	case sys_clk1_3_clk:    return clk_get_rate(sys_clk1_clk) / 3;
-	case sys_clk1_4_clk:    return clk_get_rate(sys_clk1_clk) / 4;
-	case sys_clk1_6_clk:    return clk_get_rate(sys_clk1_clk) / 6;
-	case sys_clk1_12_clk:   return clk_get_rate(sys_clk1_clk) / 12;
-	default:
-		break;
-	}
-
-	return 0;
-}
diff --git a/arch/arm/mach-keystone/clock-k2hk.c b/arch/arm/mach-keystone/clock-k2hk.c
deleted file mode 100644
index 2e36891..0000000
--- a/arch/arm/mach-keystone/clock-k2hk.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Keystone2: get clk rate for K2HK
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clock_defs.h>
-
-/**
- * pll_freq_get - get pll frequency
- * Fout = Fref * NF(mult) / NR(prediv) / OD
- * @pll:	pll identifier
- */
-static unsigned long pll_freq_get(int pll)
-{
-	unsigned long mult = 1, prediv = 1, output_div = 2;
-	unsigned long ret;
-	u32 tmp, reg;
-
-	if (pll == CORE_PLL) {
-		ret = external_clk[sys_clk];
-		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
-			/* PLL mode */
-			tmp = __raw_readl(KS2_MAINPLLCTL0);
-			prediv = (tmp & PLL_DIV_MASK) + 1;
-			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
-				(pllctl_reg_read(pll, mult) &
-				 PLLM_MULT_LO_MASK)) + 1;
-			output_div = ((pllctl_reg_read(pll, secctl) >>
-				       PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
-
-			ret = ret / prediv / output_div * mult;
-		}
-	} else {
-		switch (pll) {
-		case PASS_PLL:
-			ret = external_clk[pa_clk];
-			reg = KS2_PASSPLLCTL0;
-			break;
-		case TETRIS_PLL:
-			ret = external_clk[tetris_clk];
-			reg = KS2_ARMPLLCTL0;
-			break;
-		case DDR3A_PLL:
-			ret = external_clk[ddr3a_clk];
-			reg = KS2_DDR3APLLCTL0;
-			break;
-		case DDR3B_PLL:
-			ret = external_clk[ddr3b_clk];
-			reg = KS2_DDR3BPLLCTL0;
-			break;
-		default:
-			return 0;
-		}
-
-		tmp = __raw_readl(reg);
-
-		if (!(tmp & PLLCTL_BYPASS)) {
-			/* Bypass disabled */
-			prediv = (tmp & PLL_DIV_MASK) + 1;
-			mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
-			output_div = ((tmp >> PLL_CLKOD_SHIFT) &
-				      PLL_CLKOD_MASK) + 1;
-			ret = ((ret / prediv) * mult) / output_div;
-		}
-	}
-
-	return ret;
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
-	switch (clk) {
-	case core_pll_clk:	return pll_freq_get(CORE_PLL);
-	case pass_pll_clk:	return pll_freq_get(PASS_PLL);
-	case tetris_pll_clk:	return pll_freq_get(TETRIS_PLL);
-	case ddr3a_pll_clk:	return pll_freq_get(DDR3A_PLL);
-	case ddr3b_pll_clk:	return pll_freq_get(DDR3B_PLL);
-	case sys_clk0_1_clk:
-	case sys_clk0_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(1);
-	case sys_clk1_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(2);
-	case sys_clk2_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(3);
-	case sys_clk3_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(4);
-	case sys_clk0_2_clk:	return clk_get_rate(sys_clk0_clk) / 2;
-	case sys_clk0_3_clk:	return clk_get_rate(sys_clk0_clk) / 3;
-	case sys_clk0_4_clk:	return clk_get_rate(sys_clk0_clk) / 4;
-	case sys_clk0_6_clk:	return clk_get_rate(sys_clk0_clk) / 6;
-	case sys_clk0_8_clk:	return clk_get_rate(sys_clk0_clk) / 8;
-	case sys_clk0_12_clk:	return clk_get_rate(sys_clk0_clk) / 12;
-	case sys_clk0_24_clk:	return clk_get_rate(sys_clk0_clk) / 24;
-	case sys_clk1_3_clk:	return clk_get_rate(sys_clk1_clk) / 3;
-	case sys_clk1_4_clk:	return clk_get_rate(sys_clk1_clk) / 4;
-	case sys_clk1_6_clk:	return clk_get_rate(sys_clk1_clk) / 6;
-	case sys_clk1_12_clk:	return clk_get_rate(sys_clk1_clk) / 12;
-	default:
-		break;
-	}
-
-	return 0;
-}
diff --git a/arch/arm/mach-keystone/clock-k2l.c b/arch/arm/mach-keystone/clock-k2l.c
deleted file mode 100644
index 0004059..0000000
--- a/arch/arm/mach-keystone/clock-k2l.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Keystone2: get clk rate for K2L
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clock_defs.h>
-
-/**
- * pll_freq_get - get pll frequency
- * Fout = Fref * NF(mult) / NR(prediv) / OD
- * @pll:	pll identifier
- */
-static unsigned long pll_freq_get(int pll)
-{
-	unsigned long mult = 1, prediv = 1, output_div = 2;
-	unsigned long ret;
-	u32 tmp, reg;
-
-	if (pll == CORE_PLL) {
-		ret = external_clk[sys_clk];
-		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
-			/* PLL mode */
-			tmp = __raw_readl(KS2_MAINPLLCTL0);
-			prediv = (tmp & PLL_DIV_MASK) + 1;
-			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
-				(pllctl_reg_read(pll, mult) &
-				PLLM_MULT_LO_MASK)) + 1;
-			output_div = ((pllctl_reg_read(pll, secctl) >>
-					PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
-
-			ret = ret / prediv / output_div * mult;
-		}
-	} else {
-		switch (pll) {
-		case PASS_PLL:
-			ret = external_clk[pa_clk];
-			reg = KS2_PASSPLLCTL0;
-			break;
-		case TETRIS_PLL:
-			ret = external_clk[tetris_clk];
-			reg = KS2_ARMPLLCTL0;
-			break;
-		case DDR3_PLL:
-			ret = external_clk[ddr3a_clk];
-			reg = KS2_DDR3APLLCTL0;
-			break;
-		default:
-			return 0;
-		}
-
-		tmp = __raw_readl(reg);
-		if (!(tmp & PLLCTL_BYPASS)) {
-			/* Bypass disabled */
-			prediv = (tmp & PLL_DIV_MASK) + 1;
-			mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
-			output_div = ((tmp >> PLL_CLKOD_SHIFT) &
-				      PLL_CLKOD_MASK) + 1;
-			ret = ((ret / prediv) * mult) / output_div;
-		}
-	}
-
-	return ret;
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
-	switch (clk) {
-	case core_pll_clk:      return pll_freq_get(CORE_PLL);
-	case pass_pll_clk:      return pll_freq_get(PASS_PLL);
-	case tetris_pll_clk:    return pll_freq_get(TETRIS_PLL);
-	case ddr3_pll_clk:      return pll_freq_get(DDR3_PLL);
-	case sys_clk0_1_clk:
-	case sys_clk0_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(1);
-	case sys_clk1_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(2);
-	case sys_clk2_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(3);
-	case sys_clk3_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(4);
-	case sys_clk0_2_clk:    return clk_get_rate(sys_clk0_clk) / 2;
-	case sys_clk0_3_clk:    return clk_get_rate(sys_clk0_clk) / 3;
-	case sys_clk0_4_clk:    return clk_get_rate(sys_clk0_clk) / 4;
-	case sys_clk0_6_clk:    return clk_get_rate(sys_clk0_clk) / 6;
-	case sys_clk0_8_clk:    return clk_get_rate(sys_clk0_clk) / 8;
-	case sys_clk0_12_clk:   return clk_get_rate(sys_clk0_clk) / 12;
-	case sys_clk0_24_clk:   return clk_get_rate(sys_clk0_clk) / 24;
-	case sys_clk1_3_clk:    return clk_get_rate(sys_clk1_clk) / 3;
-	case sys_clk1_4_clk:    return clk_get_rate(sys_clk1_clk) / 4;
-	case sys_clk1_6_clk:    return clk_get_rate(sys_clk1_clk) / 6;
-	case sys_clk1_12_clk:   return clk_get_rate(sys_clk1_clk) / 12;
-	default:
-		break;
-	}
-
-	return 0;
-}
diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c
index 5c6051e..b25db1e 100644
--- a/arch/arm/mach-keystone/clock.c
+++ b/arch/arm/mach-keystone/clock.c
@@ -228,18 +228,21 @@
 	}
 }
 
-static int get_max_speed(u32 val, u32 speed_supported)
+static int get_max_speed(u32 val, u32 speed_supported, int *spds)
 {
 	int speed;
 
 	/* Left most setbit gives the speed */
 	for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) {
 		if ((val & BIT(speed)) & speed_supported)
-			return speeds[speed];
+			return spds[speed];
 	}
 
-	/* If no bit is set, use SPD800 */
-	return SPD800;
+	/* If no bit is set, return minimum speed */
+	if (cpu_is_k2g())
+		return SPD200;
+	else
+		return SPD800;
 }
 
 static inline u32 read_efuse_bootrom(void)
@@ -250,24 +253,24 @@
 		return __raw_readl(KS2_EFUSE_BOOTROM);
 }
 
-int get_max_arm_speed(void)
+int get_max_arm_speed(int *spds)
 {
 	u32 armspeed = read_efuse_bootrom();
 
 	armspeed = (armspeed & DEVSPEED_ARMSPEED_MASK) >>
 		    DEVSPEED_ARMSPEED_SHIFT;
 
-	return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS);
+	return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS, spds);
 }
 
-int get_max_dev_speed(void)
+int get_max_dev_speed(int *spds)
 {
 	u32 devspeed = read_efuse_bootrom();
 
 	devspeed = (devspeed & DEVSPEED_DEVSPEED_MASK) >>
 		    DEVSPEED_DEVSPEED_SHIFT;
 
-	return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS);
+	return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS, spds);
 }
 
 /**
diff --git a/arch/arm/mach-keystone/cmd_mon.c b/arch/arm/mach-keystone/cmd_mon.c
index a539d5d..6a9bdc9 100644
--- a/arch/arm/mach-keystone/cmd_mon.c
+++ b/arch/arm/mach-keystone/cmd_mon.c
@@ -9,25 +9,9 @@
 
 #include <common.h>
 #include <command.h>
+#include <mach/mon.h>
 asm(".arch_extension sec\n\t");
 
-static int mon_install(u32 addr, u32 dpsc, u32 freq)
-{
-	int result;
-
-	__asm__ __volatile__ (
-		"stmfd r13!, {lr}\n"
-		"mov r0, %1\n"
-		"mov r1, %2\n"
-		"mov r2, %3\n"
-		"blx r0\n"
-		"ldmfd r13!, {lr}\n"
-		: "=&r" (result)
-		: "r" (addr), "r" (dpsc), "r" (freq)
-		: "cc", "r0", "r1", "r2", "memory");
-	return result;
-}
-
 static int do_mon_install(cmd_tbl_t *cmdtp, int flag, int argc,
 			  char * const argv[])
 {
@@ -64,39 +48,6 @@
 	}
 }
 
-int mon_power_on(int core_id, void *ep)
-{
-	int result;
-
-	asm volatile (
-		"stmfd  r13!, {lr}\n"
-		"mov r1, %1\n"
-		"mov r2, %2\n"
-		"mov r0, #0\n"
-		"smc	#0\n"
-		"ldmfd  r13!, {lr}\n"
-		: "=&r" (result)
-		: "r" (core_id), "r" (ep)
-		: "cc", "r0", "r1", "r2", "memory");
-	return  result;
-}
-
-int mon_power_off(int core_id)
-{
-	int result;
-
-	asm volatile (
-		"stmfd  r13!, {lr}\n"
-		"mov r1, %1\n"
-		"mov r0, #1\n"
-		"smc	#1\n"
-		"ldmfd  r13!, {lr}\n"
-		: "=&r" (result)
-		: "r" (core_id)
-		: "cc", "r0", "r1", "memory");
-	return  result;
-}
-
 int do_mon_power(cmd_tbl_t *cmdtp, int flag, int argc,
 			char * const argv[])
 {
diff --git a/arch/arm/mach-keystone/cmd_poweroff.c b/arch/arm/mach-keystone/cmd_poweroff.c
new file mode 100644
index 0000000..1b127a8
--- /dev/null
+++ b/arch/arm/mach-keystone/cmd_poweroff.c
@@ -0,0 +1,28 @@
+/*
+ * Keystone EVM : Power off
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/mon.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/arch/hardware.h>
+
+int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	mon_power_off(0);
+
+	psc_disable_module(KS2_LPSC_TETRIS);
+	psc_disable_domain(KS2_TETRIS_PWR_DOMAIN);
+
+	asm volatile ("isb\n"
+		      "dsb\n"
+		      "wfi\n");
+
+	return 0;
+}
diff --git a/arch/arm/mach-keystone/ddr3_spd.c b/arch/arm/mach-keystone/ddr3_spd.c
new file mode 100644
index 0000000..c541886
--- /dev/null
+++ b/arch/arm/mach-keystone/ddr3_spd.c
@@ -0,0 +1,463 @@
+/*
+ * Keystone2: DDR3 SPD configuration
+ *
+ * (C) Copyright 2015-2016 Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <i2c.h>
+#include <ddr_spd.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+
+#define DUMP_DDR_CONFIG			0	/* set to 1 to debug */
+#define debug_ddr_cfg(fmt, args...)					\
+		   debug_cond(DUMP_DDR_CONFIG, fmt, ##args)
+
+static void dump_phy_config(struct ddr3_phy_config *ptr)
+{
+	debug_ddr_cfg("\npllcr		0x%08X\n", ptr->pllcr);
+	debug_ddr_cfg("pgcr1_mask	0x%08X\n", ptr->pgcr1_mask);
+	debug_ddr_cfg("pgcr1_val	0x%08X\n", ptr->pgcr1_val);
+	debug_ddr_cfg("ptr0		0x%08X\n", ptr->ptr0);
+	debug_ddr_cfg("ptr1		0x%08X\n", ptr->ptr1);
+	debug_ddr_cfg("ptr2		0x%08X\n", ptr->ptr2);
+	debug_ddr_cfg("ptr3		0x%08X\n", ptr->ptr3);
+	debug_ddr_cfg("ptr4		0x%08X\n", ptr->ptr4);
+	debug_ddr_cfg("dcr_mask		0x%08X\n", ptr->dcr_mask);
+	debug_ddr_cfg("dcr_val		0x%08X\n", ptr->dcr_val);
+	debug_ddr_cfg("dtpr0		0x%08X\n", ptr->dtpr0);
+	debug_ddr_cfg("dtpr1		0x%08X\n", ptr->dtpr1);
+	debug_ddr_cfg("dtpr2		0x%08X\n", ptr->dtpr2);
+	debug_ddr_cfg("mr0		0x%08X\n", ptr->mr0);
+	debug_ddr_cfg("mr1		0x%08X\n", ptr->mr1);
+	debug_ddr_cfg("mr2		0x%08X\n", ptr->mr2);
+	debug_ddr_cfg("dtcr		0x%08X\n", ptr->dtcr);
+	debug_ddr_cfg("pgcr2		0x%08X\n", ptr->pgcr2);
+	debug_ddr_cfg("zq0cr1		0x%08X\n", ptr->zq0cr1);
+	debug_ddr_cfg("zq1cr1		0x%08X\n", ptr->zq1cr1);
+	debug_ddr_cfg("zq2cr1		0x%08X\n", ptr->zq2cr1);
+	debug_ddr_cfg("pir_v1		0x%08X\n", ptr->pir_v1);
+	debug_ddr_cfg("pir_v2		0x%08X\n\n", ptr->pir_v2);
+};
+
+static void dump_emif_config(struct ddr3_emif_config *ptr)
+{
+	debug_ddr_cfg("\nsdcfg		0x%08X\n", ptr->sdcfg);
+	debug_ddr_cfg("sdtim1		0x%08X\n", ptr->sdtim1);
+	debug_ddr_cfg("sdtim2		0x%08X\n", ptr->sdtim2);
+	debug_ddr_cfg("sdtim3		0x%08X\n", ptr->sdtim3);
+	debug_ddr_cfg("sdtim4		0x%08X\n", ptr->sdtim4);
+	debug_ddr_cfg("zqcfg		0x%08X\n", ptr->zqcfg);
+	debug_ddr_cfg("sdrfc		0x%08X\n\n", ptr->sdrfc);
+};
+
+#define TEMP NORMAL_TEMP
+#define VBUS_CLKPERIOD 1.875 /* Corresponds to vbus=533MHz, */
+#define PLLGS_VAL	(4000.0 / VBUS_CLKPERIOD) /* 4 us */
+#define PLLPD_VAL	(1000.0 / VBUS_CLKPERIOD) /* 1 us */
+#define PLLLOCK_VAL	(100000.0 / VBUS_CLKPERIOD) /* 100 us */
+#define PLLRST_VAL	(9000.0 / VBUS_CLKPERIOD) /* 9 us */
+#define PHYRST_VAL	0x10
+#define DDR_TERM RZQ_4_TERM
+#define SDRAM_DRIVE RZQ_7_IMP
+#define DYN_ODT ODT_DISABLE
+
+enum srt {
+	NORMAL_TEMP,
+	EXTENDED_TEMP
+};
+
+enum out_impedance {
+	RZQ_6_IMP = 0,
+	RZQ_7_IMP
+};
+
+enum die_term {
+	ODT_DISABLE = 0,
+	RZQ_4_TERM,
+	RZQ_2_TERM,
+	RZQ_6_TERM,
+	RZQ_12_TERM,
+	RZQ_8_TERM
+};
+
+struct ddr3_sodimm {
+	u32 t_ck;
+	u32 freqsel;
+	u32 t_xp;
+	u32 t_cke;
+	u32 t_pllpd;
+	u32 t_pllgs;
+	u32 t_phyrst;
+	u32 t_plllock;
+	u32 t_pllrst;
+	u32 t_rfc;
+	u32 t_xs;
+	u32 t_dinit0;
+	u32 t_dinit1;
+	u32 t_dinit2;
+	u32 t_dinit3;
+	u32 t_rtp;
+	u32 t_wtr;
+	u32 t_rp;
+	u32 t_rcd;
+	u32 t_ras;
+	u32 t_rrd;
+	u32 t_rc;
+	u32 t_faw;
+	u32 t_mrd;
+	u32 t_mod;
+	u32 t_wlo;
+	u32 t_wlmrd;
+	u32 t_xsdll;
+	u32 t_xpdll;
+	u32 t_ckesr;
+	u32 t_dllk;
+	u32 t_wr;
+	u32 t_wr_bin;
+	u32 cas;
+	u32 cwl;
+	u32 asr;
+	u32 pasr;
+	u32 t_refprd;
+	u8 sdram_type;
+	u8 ibank;
+	u8 pagesize;
+	u8 t_rrd2;
+	u8 t_ras_max;
+	u8 t_zqcs;
+	u32 refresh_rate;
+	u8 t_csta;
+
+	u8 rank;
+	u8 mirrored;
+	u8 buswidth;
+};
+
+static u8 cas_latancy(u16 temp)
+{
+	int loop;
+	u8 cas_bin = 0;
+
+	for (loop = 0; loop < 32; loop += 2, temp >>= 1) {
+		if (temp & 0x0001)
+			cas_bin = (loop > 15) ? loop - 15 : loop;
+	}
+
+	return cas_bin;
+}
+
+static int ddr3_get_size_in_mb(ddr3_spd_eeprom_t *buf)
+{
+	return (((buf->organization & 0x38) >> 3) + 1) *
+		(256 << (buf->density_banks & 0xf));
+}
+
+static int ddrtimingcalculation(ddr3_spd_eeprom_t *buf, struct ddr3_sodimm *spd,
+				struct ddr3_spd_cb *spd_cb)
+{
+	u32 mtb, clk_freq;
+
+	if ((buf->mem_type != 0x0b) ||
+	    ((buf->density_banks & 0x70) != 0x00))
+		return 1;
+
+	spd->sdram_type = 0x03;
+	spd->ibank = 0x03;
+
+	mtb = buf->mtb_dividend * 1000 / buf->mtb_divisor;
+
+	spd->t_ck = buf->tck_min * mtb;
+
+	spd_cb->ddrspdclock = 2000000 / spd->t_ck;
+	clk_freq = spd_cb->ddrspdclock / 2;
+
+	spd->rank = ((buf->organization & 0x38) >> 3) + 1;
+	if (spd->rank > 2)
+		return 1;
+
+	spd->pagesize = (buf->addressing & 0x07) + 1;
+	if (spd->pagesize > 3)
+		return 1;
+
+	spd->buswidth = 8 << (buf->bus_width & 0x7);
+	if ((spd->buswidth < 16) || (spd->buswidth > 64))
+		return 1;
+
+	spd->mirrored = buf->mod_section.unbuffered.addr_mapping & 1;
+
+	printf("DDR3A Speed will be configured for %d Operation.\n",
+	       spd_cb->ddrspdclock);
+	if (spd_cb->ddrspdclock == 1333) {
+		spd->t_xp = ((3 * spd->t_ck) > 6000) ?
+			3 : ((5999 / spd->t_ck) + 1);
+		spd->t_cke = ((3 * spd->t_ck) > 5625) ?
+			3 : ((5624 / spd->t_ck) + 1);
+	} else if (spd_cb->ddrspdclock == 1600) {
+		spd->t_xp = ((3 * spd->t_ck) > 6000) ?
+			3 : ((5999 / spd->t_ck) + 1);
+		spd->t_cke = ((3 * spd->t_ck) > 5000) ?
+			3 : ((4999 / spd->t_ck) + 1);
+	} else {
+		printf("Unsupported DDR3 speed %d\n", spd_cb->ddrspdclock);
+		return 1;
+	}
+
+	spd->t_xpdll = (spd->t_ck > 2400) ? 10 : 24000 / spd->t_ck;
+	spd->t_ckesr = spd->t_cke + 1;
+
+	/* SPD Calculated Values */
+	spd->cas = cas_latancy((buf->caslat_msb << 8) |
+			       buf->caslat_lsb);
+
+	spd->t_wr = (buf->twr_min * mtb) / spd->t_ck;
+	spd->t_wr_bin = (spd->t_wr / 2) & 0x07;
+
+	spd->t_rcd = ((buf->trcd_min * mtb) - 1) / spd->t_ck + 1;
+	spd->t_rrd = ((buf->trrd_min * mtb) - 1) / spd->t_ck + 1;
+	spd->t_rp  = (((buf->trp_min * mtb) - 1) / spd->t_ck) + 1;
+
+	spd->t_ras = (((buf->tras_trc_ext & 0x0f) << 8 | buf->tras_min_lsb) *
+		      mtb) / spd->t_ck;
+
+	spd->t_rc = (((((buf->tras_trc_ext & 0xf0) << 4) | buf->trc_min_lsb) *
+		      mtb) - 1) / spd->t_ck + 1;
+
+	spd->t_rfc = (buf->trfc_min_lsb | (buf->trfc_min_msb << 8)) * mtb /
+		1000;
+	spd->t_wtr = (buf->twtr_min * mtb) / spd->t_ck;
+	spd->t_rtp = (buf->trtp_min * mtb) / spd->t_ck;
+
+	spd->t_xs  = (((spd->t_rfc + 10) * 1000) / spd->t_ck);
+	spd->t_rfc = ((spd->t_rfc * 1000) - 1) / spd->t_ck + 1;
+
+	spd->t_faw = (((buf->tfaw_msb << 8) | buf->tfaw_min) * mtb) / spd->t_ck;
+	spd->t_rrd2 = ((((buf->tfaw_msb << 8) |
+			 buf->tfaw_min) * mtb) / (4 * spd->t_ck)) - 1;
+
+	/* Hard-coded values */
+	spd->t_mrd = 0x00;
+	spd->t_mod = 0x00;
+	spd->t_wlo = 0x0C;
+	spd->t_wlmrd = 0x28;
+	spd->t_xsdll = 0x200;
+	spd->t_ras_max = 0x0F;
+	spd->t_csta = 0x05;
+	spd->t_dllk = 0x200;
+
+	/* CAS Write Latency */
+	if (spd->t_ck >= 2500)
+		spd->cwl = 0;
+	else if (spd->t_ck >= 1875)
+		spd->cwl = 1;
+	else if (spd->t_ck >= 1500)
+		spd->cwl = 2;
+	else if (spd->t_ck >= 1250)
+		spd->cwl = 3;
+	else if (spd->t_ck >= 1071)
+		spd->cwl = 4;
+	else
+		spd->cwl = 5;
+
+	/* SD:RAM Thermal and Refresh Options */
+	spd->asr = (buf->therm_ref_opt & 0x04) >> 2;
+	spd->pasr = (buf->therm_ref_opt & 0x80) >> 7;
+	spd->t_zqcs = 64;
+
+	spd->t_refprd = (TEMP == NORMAL_TEMP) ? 7812500 : 3906250;
+	spd->t_refprd = spd->t_refprd / spd->t_ck;
+
+	spd->refresh_rate = spd->t_refprd;
+	spd->t_refprd = spd->t_refprd * 5;
+
+	/* Set MISC PHY space registers fields */
+	if ((clk_freq / 2) >= 166 && (clk_freq / 2 < 275))
+		spd->freqsel = 0x03;
+	else if ((clk_freq / 2) > 225 && (clk_freq / 2 < 385))
+		spd->freqsel = 0x01;
+	else if ((clk_freq / 2) > 335 && (clk_freq / 2 < 534))
+		spd->freqsel = 0x00;
+
+	spd->t_dinit0 = 500000000 / spd->t_ck; /* CKE low time 500 us */
+	spd->t_dinit1 = spd->t_xs;
+	spd->t_dinit2 = 200000000 / spd->t_ck; /* Reset low time 200 us */
+	/* Time from ZQ initialization command to first command (1 us) */
+	spd->t_dinit3 =  1000000 / spd->t_ck;
+
+	spd->t_pllgs = PLLGS_VAL + 1;
+	spd->t_pllpd = PLLPD_VAL + 1;
+	spd->t_plllock = PLLLOCK_VAL + 1;
+	spd->t_pllrst = PLLRST_VAL;
+	spd->t_phyrst = PHYRST_VAL;
+
+	spd_cb->ddr_size_gbyte = ddr3_get_size_in_mb(buf) / 1024;
+
+	return 0;
+}
+
+static void init_ddr3param(struct ddr3_spd_cb *spd_cb,
+			   struct ddr3_sodimm *spd)
+{
+	spd_cb->phy_cfg.pllcr = (spd->freqsel & 3) << 18 | 0xE << 13;
+	spd_cb->phy_cfg.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK);
+	spd_cb->phy_cfg.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23));
+	spd_cb->phy_cfg.ptr0 = ((spd->t_pllpd & 0x7ff) << 21) |
+		((spd->t_pllgs & 0x7fff) << 6) | (spd->t_phyrst & 0x3f);
+	spd_cb->phy_cfg.ptr1 = ((spd->t_plllock & 0xffff) << 16) |
+		(spd->t_pllrst & 0x1fff);
+	spd_cb->phy_cfg.ptr2 = 0;
+	spd_cb->phy_cfg.ptr3 = ((spd->t_dinit1 & 0x1ff) << 20) |
+		(spd->t_dinit0 & 0xfffff);
+	spd_cb->phy_cfg.ptr4 = ((spd->t_dinit3 & 0x3ff) << 18) |
+		(spd->t_dinit2 & 0x3ffff);
+
+	spd_cb->phy_cfg.dcr_mask = PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK;
+	spd_cb->phy_cfg.dcr_val = 1 << 10;
+
+	if (spd->mirrored) {
+		spd_cb->phy_cfg.dcr_mask |= NOSRA_MASK | UDIMM_MASK;
+		spd_cb->phy_cfg.dcr_val |= (1 << 27) | (1 << 29);
+	}
+
+	spd_cb->phy_cfg.dtpr0 = (spd->t_rc & 0x3f) << 26 |
+		(spd->t_rrd & 0xf) << 22 |
+		(spd->t_ras & 0x3f) << 16 | (spd->t_rcd & 0xf) << 12 |
+		(spd->t_rp & 0xf) << 8 | (spd->t_wtr & 0xf) << 4 |
+		(spd->t_rtp & 0xf);
+	spd_cb->phy_cfg.dtpr1 = (spd->t_wlo & 0xf) << 26 |
+		(spd->t_wlmrd & 0x3f) << 20 | (spd->t_rfc & 0x1ff) << 11 |
+		(spd->t_faw & 0x3f) << 5 | (spd->t_mod & 0x7) << 2 |
+		(spd->t_mrd & 0x3);
+
+	spd_cb->phy_cfg.dtpr2 = 0 << 31 | 1 << 30 | 0 << 29 |
+		(spd->t_dllk & 0x3ff) << 19 | (spd->t_ckesr & 0xf) << 15;
+
+	spd_cb->phy_cfg.dtpr2 |= (((spd->t_xp > spd->t_xpdll) ?
+				   spd->t_xp : spd->t_xpdll) &
+				  0x1f) << 10;
+
+	spd_cb->phy_cfg.dtpr2 |= (((spd->t_xs > spd->t_xsdll) ?
+			      spd->t_xs : spd->t_xsdll) &
+			     0x3ff);
+
+	spd_cb->phy_cfg.mr0 = 1 << 12 | (spd->t_wr_bin & 0x7) << 9 | 0 << 8 |
+		0 << 7 | ((spd->cas & 0x0E) >> 1) << 4 | 0 << 3 |
+		(spd->cas & 0x01) << 2;
+
+	spd_cb->phy_cfg.mr1 = 0 << 12 | 0 << 11 | 0 << 7 | 0 << 3 |
+		((DDR_TERM >> 2) & 1) << 9 | ((DDR_TERM >> 1) & 1) << 6 |
+		(DDR_TERM & 0x1) << 2 | ((SDRAM_DRIVE >> 1) & 1) << 5 |
+		(SDRAM_DRIVE & 1) << 1 | 0 << 0;
+
+	spd_cb->phy_cfg.mr2 = DYN_ODT << 9 | TEMP << 7 | (spd->asr & 1) << 6 |
+		(spd->cwl & 7) << 3 | (spd->pasr & 7);
+
+	spd_cb->phy_cfg.dtcr = (spd->rank == 2) ? 0x730035C7 : 0x710035C7;
+	spd_cb->phy_cfg.pgcr2 = (0xF << 20) | ((int)spd->t_refprd & 0x3ffff);
+
+	spd_cb->phy_cfg.zq0cr1 = 0x0000005D;
+	spd_cb->phy_cfg.zq1cr1 = 0x0000005B;
+	spd_cb->phy_cfg.zq2cr1 = 0x0000005B;
+
+	spd_cb->phy_cfg.pir_v1 = 0x00000033;
+	spd_cb->phy_cfg.pir_v2 = 0x0000FF81;
+
+	/* EMIF Registers */
+	spd_cb->emif_cfg.sdcfg = spd->sdram_type << 29 | (DDR_TERM & 7) << 25 |
+		(DYN_ODT & 3) << 22 | (spd->cwl & 0x7) << 14 |
+		(spd->cas & 0xf) << 8 | (spd->ibank & 3) << 5 |
+		(spd->buswidth & 3) << 12 | (spd->pagesize & 3);
+
+	if (spd->rank == 2)
+		spd_cb->emif_cfg.sdcfg |= 1 << 3;
+
+	spd_cb->emif_cfg.sdtim1 = ((spd->t_wr - 1) & 0x1f) << 25 |
+		((spd->t_ras - 1) & 0x7f) << 18 |
+		((spd->t_rc - 1) & 0xff) << 10 |
+		(spd->t_rrd2 & 0x3f) << 4  |
+		((spd->t_wtr - 1) & 0xf);
+
+	spd_cb->emif_cfg.sdtim2 = 0x07 << 10 | ((spd->t_rp - 1) & 0x1f) << 5 |
+		((spd->t_rcd - 1) & 0x1f);
+
+	spd_cb->emif_cfg.sdtim3 = ((spd->t_xp - 2) & 0xf) << 28 |
+		((spd->t_xs - 1) & 0x3ff) << 18 |
+		((spd->t_xsdll - 1) & 0x3ff) << 8 |
+		((spd->t_rtp - 1) & 0xf) << 4 | ((spd->t_cke) & 0xf);
+
+	spd_cb->emif_cfg.sdtim4 = (spd->t_csta & 0xf) << 28 |
+		((spd->t_ckesr - 1) & 0xf) << 24 |
+		((spd->t_zqcs - 1) & 0xff) << 16 |
+		((spd->t_rfc - 1) & 0x3ff) << 4 |
+		(spd->t_ras_max & 0xf);
+
+	spd_cb->emif_cfg.sdrfc = (spd->refresh_rate - 1) & 0xffff;
+
+	/* TODO zqcfg value fixed ,May be required correction for K2E evm. */
+	spd_cb->emif_cfg.zqcfg = (spd->rank == 2) ? 0xF0073200 : 0x70073200;
+}
+
+static int ddr3_read_spd(ddr3_spd_eeprom_t *spd_params)
+{
+	int ret;
+	int old_bus;
+
+	i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
+
+	old_bus = i2c_get_bus_num();
+	i2c_set_bus_num(1);
+
+	ret = i2c_read(0x53, 0, 1, (unsigned char *)spd_params, 256);
+
+	i2c_set_bus_num(old_bus);
+
+	if (ret) {
+		printf("Cannot read DIMM params\n");
+		return 1;
+	}
+
+	if (ddr3_spd_check(spd_params))
+		return 1;
+
+	return 0;
+}
+
+int ddr3_get_size(void)
+{
+	ddr3_spd_eeprom_t spd_params;
+
+	if (ddr3_read_spd(&spd_params))
+		return 0;
+
+	return ddr3_get_size_in_mb(&spd_params) / 1024;
+}
+
+int ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb *spd_cb)
+{
+	struct ddr3_sodimm spd;
+	ddr3_spd_eeprom_t spd_params;
+
+	memset(&spd, 0, sizeof(spd));
+
+	if (ddr3_read_spd(&spd_params))
+		return 1;
+
+	if (ddrtimingcalculation(&spd_params, &spd, spd_cb)) {
+		printf("Timing caclulation error\n");
+		return 1;
+	}
+
+	strncpy(spd_cb->dimm_name, (char *)spd_params.mpart, 18);
+	spd_cb->dimm_name[18] = '\0';
+
+	init_ddr3param(spd_cb, &spd);
+
+	dump_emif_config(&spd_cb->emif_cfg);
+	dump_phy_config(&spd_cb->phy_cfg);
+
+	return 0;
+}
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2g.h b/arch/arm/mach-keystone/include/mach/clock-k2g.h
index 214c1d3..74de620 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2g.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2g.h
@@ -12,8 +12,8 @@
 
 #define PLLSET_CMD_LIST		"<pa|arm|ddr3>"
 
-#define DEV_SUPPORTED_SPEEDS	0xfff
-#define ARM_SUPPORTED_SPEEDS	0xfff
+#define DEV_SUPPORTED_SPEEDS	0x1ff
+#define ARM_SUPPORTED_SPEEDS	0xff
 
 #define KS2_CLK1_6 sys_clk0_6_clk
 
diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h
index cdcff3b..72724aa 100644
--- a/arch/arm/mach-keystone/include/mach/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
@@ -63,8 +63,12 @@
 #define CLOCK_INDEXES_LIST	CLK_LIST(GENERATE_INDX_STR)
 
 enum {
+	SPD200,
+	SPD400,
+	SPD600,
 	SPD800,
 	SPD850,
+	SPD900,
 	SPD1000,
 	SPD1200,
 	SPD1250,
@@ -124,8 +128,8 @@
 unsigned long clk_get_rate(unsigned int clk);
 unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
 int clk_set_rate(unsigned int clk, unsigned long hz);
-int get_max_dev_speed(void);
-int get_max_arm_speed(void);
+int get_max_dev_speed(int *spds);
+int get_max_arm_speed(int *spds);
 void pll_pa_clk_sel(void);
 
 #endif
diff --git a/arch/arm/mach-keystone/include/mach/ddr3.h b/arch/arm/mach-keystone/include/mach/ddr3.h
index a22c237..5feffe8 100644
--- a/arch/arm/mach-keystone/include/mach/ddr3.h
+++ b/arch/arm/mach-keystone/include/mach/ddr3.h
@@ -48,6 +48,14 @@
 	unsigned int sdrfc;
 };
 
+struct ddr3_spd_cb {
+	char   dimm_name[32];
+	struct ddr3_phy_config phy_cfg;
+	struct ddr3_emif_config emif_cfg;
+	unsigned int ddrspdclock;
+	int    ddr_size_gbyte;
+};
+
 u32 ddr3_init(void);
 void ddr3_reset_ddrphy(void);
 void ddr3_init_ecc(u32 base, u32 ddr3_size);
@@ -58,5 +66,6 @@
 void ddr3_enable_ecc(u32 base, int test);
 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
+int ddr3_get_size(void);
 
 #endif
diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
index fa4162f..ca2a119 100644
--- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
@@ -10,7 +10,7 @@
 #ifndef __ASM_ARCH_HARDWARE_K2G_H
 #define __ASM_ARCH_HARDWARE_K2G_H
 
-#define KS2_NUM_DSPS	0
+#define KS2_NUM_DSPS			1
 
 /* Power and Sleep Controller (PSC) Domains */
 #define KS2_LPSC_ALWAYSON		0
@@ -30,7 +30,10 @@
 #define KS2_LPSC_MCASP			15
 #define KS2_LPSC_SR			16
 #define KS2_LPSC_MSMC			17
-#define KS2_LPSC_GEM			18
+#ifdef KS2_LPSC_GEM_0
+#undef KS2_LPSC_GEM_0
+#endif
+#define KS2_LPSC_GEM_0			18
 #define KS2_LPSC_ARM			19
 #define KS2_LPSC_ASRC			20
 #define KS2_LPSC_ICSS			21
diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2l.h b/arch/arm/mach-keystone/include/mach/hardware-k2l.h
index 4f1197e..a59e071 100644
--- a/arch/arm/mach-keystone/include/mach/hardware-k2l.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2l.h
@@ -105,4 +105,11 @@
 /* NETCP */
 #define KS2_NETCP_BASE			0x26000000
 
+#ifndef __ASSEMBLY__
+static inline int ddr3_get_size(void)
+{
+	return 2;
+}
+#endif
+
 #endif /* __ASM_ARCH_HARDWARE_K2L_H */
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index edebcd7..8ca19bb 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -160,6 +160,7 @@
 #define KS2_LPSC_GEM_0			15
 #define KS2_LPSC_TETRIS			52
 #define KS2_TETRIS_PWR_DOMAIN		31
+#define KS2_GEM_0_PWR_DOMAIN		8
 
 /* Chip configuration unlock codes and registers */
 #define KS2_KICK0			(KS2_DEVICE_STATE_CTRL_BASE + 0x38)
diff --git a/arch/arm/mach-keystone/include/mach/mon.h b/arch/arm/mach-keystone/include/mach/mon.h
index 33a2876..eb7aa93 100644
--- a/arch/arm/mach-keystone/include/mach/mon.h
+++ b/arch/arm/mach-keystone/include/mach/mon.h
@@ -7,9 +7,11 @@
  * SPDX-License-Identifier:     GPL-2.0+
  */
 
-#ifndef _MON_H_
-#define _MON_H_
+#ifndef _MACH_MON_H_
+#define _MACH_MON_H_
 
+int mon_install(u32 addr, u32 dpsc, u32 freq);
+int mon_power_on(int core_id, void *ep);
 int mon_power_off(int core_id);
 
 #endif
diff --git a/arch/arm/mach-keystone/include/mach/psc_defs.h b/arch/arm/mach-keystone/include/mach/psc_defs.h
index 70d22cf..6e6e7fd 100644
--- a/arch/arm/mach-keystone/include/mach/psc_defs.h
+++ b/arch/arm/mach-keystone/include/mach/psc_defs.h
@@ -30,9 +30,9 @@
 #define BOOTBITMASK(x, y)     ((((((u32)1 << (((u32)x) - ((u32)y) + (u32)1)) - \
 				  (u32)1)) << ((u32)y)))
 
-#define BOOT_READ_BITFIELD(z, x, y)    (((u32)z) & BOOTBITMASK(x, y)) >> (y)
-#define BOOT_SET_BITFIELD(z, f, x, y)  (((u32)z) & ~BOOTBITMASK(x, y)) | \
-					 ((((u32)f) << (y)) & BOOTBITMASK(x, y))
+#define BOOT_READ_BITFIELD(z, x, y)    ((((u32)z) & BOOTBITMASK(x, y)) >> (y))
+#define BOOT_SET_BITFIELD(z, f, x, y)  ((((u32)z) & ~BOOTBITMASK(x, y)) | \
+					((((u32)f) << (y)) & BOOTBITMASK(x, y)))
 
 /* PDCTL */
 #define PSC_REG_PDCTL_SET_NEXT(x, y)        BOOT_SET_BITFIELD((x), (y), 0, 0)
@@ -56,6 +56,8 @@
 #define PSC_REG_MDSTAT_GET_STATUS(x)        BOOT_READ_BITFIELD((x), 5, 0)
 #define PSC_REG_MDSTAT_GET_LRSTZ(x)         BOOT_READ_BITFIELD((x), 8, 8)
 #define PSC_REG_MDSTAT_GET_LRSTDONE(x)      BOOT_READ_BITFIELD((x), 9, 9)
+#define PSC_REG_MDSTAT_GET_MRSTZ(x)         BOOT_READ_BITFIELD((x), 10, 10)
+#define PSC_REG_MDSTAT_GET_MRSTDONE(x)      BOOT_READ_BITFIELD((x), 11, 11)
 
 /* PDCTL states */
 #define PSC_REG_VAL_PDCTL_NEXT_ON           1
@@ -86,5 +88,7 @@
 int psc_enable_module(u32 mod_num);
 int psc_disable_module(u32 mod_num);
 int psc_disable_domain(u32 domain_num);
+int psc_module_keep_in_reset_enabled(u32 mod_num, bool gate_clocks);
+int psc_module_release_from_reset(u32 mod_num);
 
 #endif /* _PSC_DEFS_H_ */
diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c
index 11a9357..beb8a76 100644
--- a/arch/arm/mach-keystone/keystone.c
+++ b/arch/arm/mach-keystone/keystone.c
@@ -9,10 +9,8 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/mon.h>
 #include <asm/arch/psc_defs.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/hardware.h>
 
 /**
  * cpu_to_bus - swap bytes of the 32-bit data if the device is BE
@@ -27,22 +25,6 @@
 		for (i = 0; i < length; i++, ptr++)
 			*ptr = cpu_to_be32(*ptr);
 
-	return 0;
-}
-
-static int turn_off_myself(void)
-{
-	printf("Turning off ourselves\r\n");
-	mon_power_off(0);
-
-	psc_disable_module(KS2_LPSC_TETRIS);
-	psc_disable_domain(KS2_TETRIS_PWR_DOMAIN);
-
-	asm volatile ("isb\n"
-		      "dsb\n"
-		      "wfi\n");
-
-	printf("What! Should not see that\n");
 	return 0;
 }
 
@@ -54,22 +36,11 @@
 		if (psc_disable_module(i + KS2_LPSC_GEM_0))
 			printf("Cannot disable module for #%d DSP", i);
 
-		if (psc_disable_domain(i + 8))
+		if (psc_disable_domain(i + KS2_GEM_0_PWR_DOMAIN))
 			printf("Cannot disable domain for #%d DSP", i);
 	}
 }
 
-int do_killme_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	return turn_off_myself();
-}
-
-U_BOOT_CMD(
-	killme, 1,      0,      do_killme_cmd,
-	"turn off main ARM core",
-	"turn off main ARM core. Should not live after that :(\n"
-);
-
 int misc_init_r(void)
 {
 	char *env;
diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c
new file mode 100644
index 0000000..256f630
--- /dev/null
+++ b/arch/arm/mach-keystone/mon.c
@@ -0,0 +1,63 @@
+/*
+ * K2HK: secure kernel command file
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <mach/mon.h>
+asm(".arch_extension sec\n\t");
+
+int mon_install(u32 addr, u32 dpsc, u32 freq)
+{
+	int result;
+
+	__asm__ __volatile__ (
+		"stmfd r13!, {lr}\n"
+		"mov r0, %1\n"
+		"mov r1, %2\n"
+		"mov r2, %3\n"
+		"blx r0\n"
+		"ldmfd r13!, {lr}\n"
+		: "=&r" (result)
+		: "r" (addr), "r" (dpsc), "r" (freq)
+		: "cc", "r0", "r1", "r2", "memory");
+	return result;
+}
+
+int mon_power_on(int core_id, void *ep)
+{
+	int result;
+
+	asm volatile (
+		"stmfd  r13!, {lr}\n"
+		"mov r1, %1\n"
+		"mov r2, %2\n"
+		"mov r0, #0\n"
+		"smc	#0\n"
+		"ldmfd  r13!, {lr}\n"
+		: "=&r" (result)
+		: "r" (core_id), "r" (ep)
+		: "cc", "r0", "r1", "r2", "memory");
+	return  result;
+}
+
+int mon_power_off(int core_id)
+{
+	int result;
+
+	asm volatile (
+		"stmfd  r13!, {lr}\n"
+		"mov r1, %1\n"
+		"mov r0, #1\n"
+		"smc	#1\n"
+		"ldmfd  r13!, {lr}\n"
+		: "=&r" (result)
+		: "r" (core_id)
+		: "cc", "r0", "r1", "memory");
+	return  result;
+}
diff --git a/arch/arm/mach-keystone/psc.c b/arch/arm/mach-keystone/psc.c
index 237e776..ff042a6 100644
--- a/arch/arm/mach-keystone/psc.c
+++ b/arch/arm/mach-keystone/psc.c
@@ -13,24 +13,27 @@
 #include <asm/processor.h>
 #include <asm/arch/psc_defs.h>
 
+/**
+ * psc_delay() - delay for psc
+ *
+ * Return: 10
+ */
 int psc_delay(void)
 {
 	udelay(10);
 	return 10;
 }
 
-/*
- * FUNCTION PURPOSE: Wait for end of transitional state
- *
- * DESCRIPTION: Polls pstat for the selected domain and waits for transitions
- *              to be complete.
+/**
+ * psc_wait() - Wait for end of transitional state
+ * @domain_num: GPSC domain number
  *
- *              Since this is boot loader code it is *ASSUMED* that interrupts
- *              are disabled and no other core is mucking around with the psc
- *              at the same time.
+ * Polls pstat for the selected domain and waits for transitions to be complete.
+ * Since this is boot loader code it is *ASSUMED* that interrupts are disabled
+ * and no other core is mucking around with the psc at the same time.
  *
- *              Returns 0 when the domain is free. Returns -1 if a timeout
- *              occurred waiting for the completion.
+ * Return: 0 when the domain is free. Returns -1 if a timeout occurred waiting
+ * for the completion.
  */
 int psc_wait(u32 domain_num)
 {
@@ -59,6 +62,10 @@
 	return 0;
 }
 
+/**
+ * psc_get_domain_num() - Get the domain number
+ * @mod_num:	LPSC module number
+ */
 u32 psc_get_domain_num(u32 mod_num)
 {
 	u32 domain_num;
@@ -70,20 +77,19 @@
 	return domain_num;
 }
 
-/*
- * FUNCTION PURPOSE: Power up/down a module
+/**
+ * psc_set_state() - powers up/down a module
+ * @mod_num:	LPSC module number
+ * @state:	1 to enable, 0 to disable.
  *
- * DESCRIPTION: Powers up/down the requested module and the associated power
- *		domain if required. No action is taken it the module is
- *		already powered up/down.
+ * Powers up/down the requested module and the associated power domain if
+ * required. No action is taken it the module is already powered up/down.
+ * This only controls modules. The domain in which the module resides will
+ * be left in the power on state. Multiple modules can exist in a power
+ * domain, so powering down the domain based on a single module is not done.
  *
- *              This only controls modules. The domain in which the module
- *              resides will be left in the power on state. Multiple modules
- *              can exist in a power domain, so powering down the domain based
- *              on a single module is not done.
- *
- *              Returns 0 on success, -1 if the module can't be powered up, or
- *              if there is a timeout waiting for the transition.
+ * Return: 0 on success, -1 if the module can't be powered up, or if there is a
+ * timeout waiting for the transition.
  */
 int psc_set_state(u32 mod_num, u32 state)
 {
@@ -136,15 +142,16 @@
 	return psc_wait(domain_num);
 }
 
-/*
- * FUNCTION PURPOSE: Power up a module
+/**
+ * psc_enable_module() - power up a module
+ * @mod_num:	LPSC module number
  *
- * DESCRIPTION: Powers up the requested module and the associated power domain
- *              if required. No action is taken it the module is already
- *              powered up.
+ * Powers up the requested module and the associated power domain
+ * if required. No action is taken it the module is already powered up.
  *
- *              Returns 0 on success, -1 if the module can't be powered up, or
- *              if there is a timeout waiting for the transition.
+ * Return: 0 on success, -1 if the module can't be powered up, or
+ * if there is a timeout waiting for the transition.
+ *
  */
 int psc_enable_module(u32 mod_num)
 {
@@ -158,12 +165,11 @@
 	return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_ON);
 }
 
-/*
- * FUNCTION PURPOSE: Power down a module
+/**
+ * psc_disable_module() - Power down a module
+ * @mod_num:	LPSC module number
  *
- * DESCRIPTION: Powers down the requested module.
- *
- *              Returns 0 on success, -1 on failure or timeout.
+ * Return: 0 on success, -1 on failure or timeout.
  */
 int psc_disable_module(u32 mod_num)
 {
@@ -179,13 +185,16 @@
 	return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
 }
 
-/*
- * FUNCTION PURPOSE: Set the reset isolation bit in mdctl
+/**
+ * psc_set_reset_iso() - Set the reset isolation bit in mdctl
+ * @mod_num:	LPSC module number
  *
- * DESCRIPTION: The reset isolation enable bit is set. The state of the module
- *              is not changed. Returns 0 if the module config showed that
- *              reset isolation is supported. Returns 1 otherwise. This is not
- *              an error, but setting the bit in mdctl has no effect.
+ * The reset isolation enable bit is set. The state of the module is not
+ * changed.
+ *
+ * Return: 0 if the module config showed that reset isolation is supported.
+ * Returns 1 otherwise. This is not an error, but setting the bit in mdctl
+ * has no effect.
  */
 int psc_set_reset_iso(u32 mod_num)
 {
@@ -204,10 +213,9 @@
 	return 1;
 }
 
-/*
- * FUNCTION PURPOSE: Disable a power domain
- *
- * DESCRIPTION: The power domain is disabled
+/**
+ * psc_disable_domain() - Disable a power domain
+ * @domain_num: GPSC domain number
  */
 int psc_disable_domain(u32 domain_num)
 {
@@ -225,3 +233,107 @@
 
 	return psc_wait(domain_num);
 }
+
+/**
+ * psc_module_keep_in_reset_enabled() - Keep module in enabled,in-reset state
+ * @mod_num:	LPSC module number
+ * @gate_clocks: Can the clocks be gated on this module?
+ *
+ * Enable the module, but do not release the module from local reset. This is
+ * necessary for many processor systems on keystone SoCs to allow for system
+ * initialization from a master processor prior to releasing the processor
+ * from reset.
+ */
+int psc_module_keep_in_reset_enabled(u32 mod_num, bool gate_clocks)
+{
+	u32 mdctl, ptcmd, mdstat;
+	u32 next_state;
+	int domain_num = psc_get_domain_num(mod_num);
+	int timeout = 100000;
+
+	/* Wait for any previous transitions to complete */
+	psc_wait(domain_num);
+	mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
+	/* Should be set 0 to assert Local reset */
+	if ((mdctl & PSC_REG_MDCTL_SET_LRSTZ(mdctl, 1))) {
+		mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
+		__raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
+		/* Wait for transition to take place */
+		psc_wait(domain_num);
+	}
+
+	/* Clear Module reset */
+	mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
+	next_state = gate_clocks ? PSC_REG_VAL_MDCTL_NEXT_OFF :
+			PSC_REG_VAL_MDCTL_NEXT_ON;
+	mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, next_state);
+	__raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
+	/* Trigger PD transition */
+	ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD);
+	ptcmd |= (u32)(1 << domain_num);
+	__raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD);
+	psc_wait(domain_num);
+
+	mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num));
+	while (timeout) {
+		mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num));
+
+		if (!(PSC_REG_MDSTAT_GET_STATUS(mdstat) & 0x30) &&
+		    PSC_REG_MDSTAT_GET_MRSTDONE(mdstat) &&
+		    PSC_REG_MDSTAT_GET_LRSTDONE(mdstat))
+			break;
+		timeout--;
+	}
+
+	if (!timeout) {
+		printf("%s: Timedout waiting for mdstat(0x%08x) to change\n",
+		       __func__, mdstat);
+		return -ETIMEDOUT;
+	}
+	return 0;
+}
+
+/**
+ * psc_module_release_from_reset() - Release the module from reset
+ * @mod_num:	LPSC module number
+ *
+ * This is the follow through for the command 'psc_module_keep_in_reset_enabled'
+ * Allowing the module to be released from reset once all required inits are
+ * complete for the module. Typically, this allows the processor module to start
+ * execution.
+ */
+int psc_module_release_from_reset(u32 mod_num)
+{
+	u32 mdctl, mdstat;
+	int domain_num = psc_get_domain_num(mod_num);
+	int timeout = 100000;
+
+	/* Wait for any previous transitions to complete */
+	psc_wait(domain_num);
+	mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
+	/* Should be set to 1 to de-assert Local reset */
+	if ((mdctl & PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0))) {
+		mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 1);
+		__raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
+		/* Wait for transition to take place */
+		psc_wait(domain_num);
+	}
+	mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num));
+	while (timeout) {
+		mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num));
+
+		if (!(PSC_REG_MDSTAT_GET_STATUS(mdstat) & 0x30) &&
+		    PSC_REG_MDSTAT_GET_MRSTDONE(mdstat) &&
+		    PSC_REG_MDSTAT_GET_LRSTDONE(mdstat))
+			break;
+		timeout--;
+	}
+
+	if (!timeout) {
+		printf("%s: Timedout waiting for mdstat(0x%08x) to change\n",
+		       __func__, mdstat);
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index e3ca870..ec8305c 100644
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -37,7 +37,7 @@
 /* use integer mode, 396MHz dpll setting
  * refdiv, fbdiv, postdiv1, postdiv2
  */
-const struct pll_div dpll_init_cfg = {1, 66, 4, 1};
+const struct pll_div dpll_init_cfg = {1, 50, 3, 1};
 
 /* 396Mhz ddr timing */
 const struct rk3036_ddr_timing ddr_timing = {0x18c,
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
index 6a54368..e133cca 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -114,7 +114,7 @@
 #ifdef CONFIG_SPL_MMC_SUPPORT
 static int configure_emmc(struct udevice *pinctrl)
 {
-#ifndef CONFIG_TARGET_ROCK2
+#if !defined(CONFIG_TARGET_ROCK2) && !defined(CONFIG_TARGET_FIREFLY_RK3288)
 	struct gpio_desc desc;
 	int ret;
 
diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index e9e2211..71330cb 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -561,14 +561,14 @@
 			&sdram_params->ch[chan];
 
 		sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
-		sys_reg |= chan << SYS_REG_CHINFO_SHIFT(chan);
+		sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
 		sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
 		sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
-		sys_reg |= info->bk == 3 ? 1 << SYS_REG_BK_SHIFT(chan) : 0;
+		sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
 		sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
 		sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
-		sys_reg |= info->bw << SYS_REG_BW_SHIFT(chan);
-		sys_reg |= info->dbw << SYS_REG_DBW_SHIFT(chan);
+		sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
+		sys_reg |= (2 >>info->dbw) << SYS_REG_DBW_SHIFT(chan);
 
 		dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
 	}
@@ -720,13 +720,13 @@
 		rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
 			SYS_REG_RANK_MASK);
 		col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
-		bk = sys_reg & (1 << SYS_REG_BK_SHIFT(ch)) ? 3 : 0;
+		bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK) ;
 		cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
 				SYS_REG_CS0_ROW_MASK);
 		cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
 				SYS_REG_CS1_ROW_MASK);
-		bw = (sys_reg >> SYS_REG_BW_SHIFT(ch)) &
-			SYS_REG_BW_MASK;
+		bw = (2 >> (sys_reg >> SYS_REG_BW_SHIFT(ch)) &
+			SYS_REG_BW_MASK);
 		row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
 			SYS_REG_ROW_3_4_MASK;
 
@@ -756,7 +756,7 @@
 	struct udevice *pmic;
 	int ret;
 
-	ret = uclass_first_device(UCLASS_PMIC, &pmic);
+	ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
 	if (ret)
 		return ret;
 
diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c
index c227652..501c4f0 100644
--- a/arch/arm/mach-tegra/arm64-mmu.c
+++ b/arch/arm/mach-tegra/arm64-mmu.c
@@ -12,120 +12,22 @@
 #include <asm/system.h>
 #include <asm/armv8/mmu.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
-#define SECTION_SHIFT_L1	30UL
-#define SECTION_SHIFT_L2	21UL
-#define BLOCK_SIZE_L0		0x8000000000UL
-#define BLOCK_SIZE_L1		(1 << SECTION_SHIFT_L1)
-#define BLOCK_SIZE_L2		(1 << SECTION_SHIFT_L2)
-
-#define TCR_TG1_4K		(1 << 31)
-#define TCR_EPD1_DISABLE	(1 << 23)
-#define TEGRA_VA_BITS		40
-#define TEGRA_TCR		TCR_TG1_4K | \
-				TCR_EPD1_DISABLE | \
-				TCR_SHARED_OUTER | \
-				TCR_SHARED_INNER | \
-				TCR_IRGN_WBWA | \
-				TCR_ORGN_WBWA | \
-				TCR_T0SZ(TEGRA_VA_BITS)
-
-#define MEMORY_ATTR	PMD_SECT_AF | PMD_SECT_INNER_SHARE |	\
-			PMD_ATTRINDX(MT_NORMAL) |	\
-			PMD_TYPE_SECT
-#define DEVICE_ATTR	PMD_SECT_AF | PMD_SECT_PXN |	\
-			PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) |	\
-			PMD_TYPE_SECT
-
-/* 4K size is required to place 512 entries in each level */
-#define TLB_TABLE_SIZE	0x1000
-
-/*
- * This mmu table looks as below
- * Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0
- * and other Level1 Table1.
- * Level1 Table0 contains entries for each 1GB from 0 to 511GB.
- * Level1 Table1 contains entries for each 1GB from 512GB to 1TB.
- * Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains
- * entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively.
- */
-void mmu_setup(void)
-{
-	int el;
-	u64 i, section_l1t0, section_l1t1;
-	u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3;
-	u64 *level0_table = (u64 *)gd->arch.tlb_addr;
-	u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE);
-	u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE));
-	u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE));
-	u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE));
-	u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE));
-	u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE));
-
-	/* Invalidate all table entries */
-	memset(level0_table, 0, PGTABLE_SIZE);
-
-	level0_table[0] =
-		(u64)level1_table_0 | PMD_TYPE_TABLE;
-	level0_table[1] =
-		(u64)level1_table_1 | PMD_TYPE_TABLE;
-
-	/*
-	 * set level 1 table 0, covering 0 to 512GB
-	 * set level 1 table 1, covering 512GB to 1TB
-	 */
-	section_l1t0 = 0;
-	section_l1t1 = BLOCK_SIZE_L0;
-
-	for (i = 0; i < 512; i++) {
-		level1_table_0[i] = section_l1t0;
-		if (i >= 4)
-			level1_table_0[i] |= MEMORY_ATTR;
-		level1_table_1[i] = section_l1t1;
-		level1_table_1[i] |= MEMORY_ATTR;
-		section_l1t0 += BLOCK_SIZE_L1;
-		section_l1t1 += BLOCK_SIZE_L1;
-	}
-
-	level1_table_0[0] =
-		(u64)level2_table_0 | PMD_TYPE_TABLE;
-	level1_table_0[1] =
-		(u64)level2_table_1 | PMD_TYPE_TABLE;
-	level1_table_0[2] =
-		(u64)level2_table_2 | PMD_TYPE_TABLE;
-	level1_table_0[3] =
-		(u64)level2_table_3 | PMD_TYPE_TABLE;
-
-	section_l2t0 = 0;
-	section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */
-	section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */
-	section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */
-
-	for (i = 0; i < 512; i++) {
-		level2_table_0[i] = section_l2t0 | DEVICE_ATTR;
-		level2_table_1[i] = section_l2t1 | DEVICE_ATTR;
-		level2_table_2[i] = section_l2t2 | MEMORY_ATTR;
-		level2_table_3[i] = section_l2t3 | MEMORY_ATTR;
-		section_l2t0 += BLOCK_SIZE_L2;
-		section_l2t1 += BLOCK_SIZE_L2;
-		section_l2t2 += BLOCK_SIZE_L2;
-		section_l2t3 += BLOCK_SIZE_L2;
+static struct mm_region tegra_mem_map[] = {
+	{
+		.base = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.base = 0x80000000UL,
+		.size = 0xff80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* List terminator */
+		0,
 	}
-
-	/* flush new MMU table */
-	flush_dcache_range(gd->arch.tlb_addr,
-			   gd->arch.tlb_addr + gd->arch.tlb_size);
-
-	/* point TTBR to the new table */
-	el = current_el();
-	set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
-			  TEGRA_TCR, MEMORY_ATTRIBUTES);
-
-	set_sctlr(get_sctlr() | CR_M);
-}
+};
 
-u64 *arch_get_page_table(void)
-{
-	return (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE));
-}
+struct mm_region *mem_map = tegra_mem_map;
diff --git a/arch/arm/mach-zynq/u-boot-spl.lds b/arch/arm/mach-zynq/u-boot-spl.lds
index ecdf6a0..9a59164 100644
--- a/arch/arm/mach-zynq/u-boot-spl.lds
+++ b/arch/arm/mach-zynq/u-boot-spl.lds
@@ -38,16 +38,11 @@
 	} > .sram
 
 	. = ALIGN(4);
-#ifdef CONFIG_SPL_DM
 	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list_*_driver_*)));
-		KEEP(*(SORT(.u_boot_list_*_uclass_*)));
+		KEEP(*(SORT(.u_boot_list*)));
 	} > .sram
 
 	. = ALIGN(4);
-#endif
-
-	. = .;
 
 	_image_binary_end = .;
 
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index 6977dd6..3eb3440 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -10,6 +10,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <fdt_support.h>
 #include <image.h>
 #include <u-boot/zlib.h>
 #include <asm/byteorder.h>
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index a3b07c6..002b839 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -16,7 +16,7 @@
 #ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE
 	__builtin_mips_cache(op, addr);
 #else
-	__asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr));
+	__asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(addr));
 #endif
 }
 
diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c
index be7f99c..4f0f8fc 100644
--- a/arch/nios2/cpu/cpu.c
+++ b/arch/nios2/cpu/cpu.c
@@ -63,11 +63,9 @@
 	struct udevice *dev;
 	int ret;
 
-	ret = uclass_first_device(UCLASS_CPU, &dev);
+	ret = uclass_first_device_err(UCLASS_CPU, &dev);
 	if (ret)
 		return ret;
-	if (!dev)
-		return -ENODEV;
 
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 #ifndef CONFIG_ROM_STUBS
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index c45cace..826f9c9 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -76,13 +76,8 @@
 #define CONFIG_CMD_BLOB
 #define CONFIG_FSL_SEC_MON
 #define CONFIG_SHA_PROG_HW_ACCEL
-#define CONFIG_RSA
 #define CONFIG_RSA_FREESCALE_EXP
 
-#ifndef CONFIG_DM
-#define CONFIG_DM
-#endif
-
 #ifndef CONFIG_FSL_CAAM
 #define CONFIG_FSL_CAAM
 #endif
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index a0bd344..4ef27dc 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -8,6 +8,9 @@
 	prompt "Mainboard vendor"
 	default VENDOR_EMULATION
 
+config VENDOR_CONGATEC
+	bool "congatec"
+
 config VENDOR_COREBOOT
 	bool "coreboot"
 
@@ -26,6 +29,7 @@
 endchoice
 
 # board-specific options below
+source "board/congatec/Kconfig"
 source "board/coreboot/Kconfig"
 source "board/efi/Kconfig"
 source "board/emulation/Kconfig"
@@ -34,6 +38,7 @@
 
 # platform-specific options below
 source "arch/x86/cpu/baytrail/Kconfig"
+source "arch/x86/cpu/broadwell/Kconfig"
 source "arch/x86/cpu/coreboot/Kconfig"
 source "arch/x86/cpu/ivybridge/Kconfig"
 source "arch/x86/cpu/qemu/Kconfig"
@@ -266,6 +271,78 @@
 	  to be used for speeding up boot time on future reboots and/or
 	  power cycles.
 
+config HAVE_MRC
+	bool "Add a System Agent binary"
+	depends on !HAVE_FSP
+	help
+	  Select this option to add a System Agent binary to
+	  the resulting U-Boot image. MRC stands for Memory Reference Code.
+	  It is a binary blob which U-Boot uses to set up SDRAM.
+
+	  Note: Without this binary U-Boot will not be able to set up its
+	  SDRAM so will not boot.
+
+config CACHE_MRC_BIN
+	bool
+	depends on HAVE_MRC
+	default n
+	help
+	  Enable caching for the memory reference code binary. This uses an
+	  MTRR (memory type range register) to turn on caching for the section
+	  of SPI flash that contains the memory reference code. This makes
+	  SDRAM init run faster.
+
+config CACHE_MRC_SIZE_KB
+	int
+	depends on HAVE_MRC
+	default 512
+	help
+	  Sets the size of the cached area for the memory reference code.
+	  This ends at the end of SPI flash (address 0xffffffff) and is
+	  measured in KB. Typically this is set to 512, providing for 0.5MB
+	  of cached space.
+
+config DCACHE_RAM_BASE
+	hex
+	depends on HAVE_MRC
+	help
+	  Sets the base of the data cache area in memory space. This is the
+	  start address of the cache-as-RAM (CAR) area and the address varies
+	  depending on the CPU. Once CAR is set up, read/write memory becomes
+	  available at this address and can be used temporarily until SDRAM
+	  is working.
+
+config DCACHE_RAM_SIZE
+	hex
+	depends on HAVE_MRC
+	default 0x40000
+	help
+	  Sets the total size of the data cache area in memory space. This
+	  sets the size of the cache-as-RAM (CAR) area. Note that much of the
+	  CAR space is required by the MRC. The CAR space available to U-Boot
+	  is normally at the start and typically extends to 1/4 or 1/2 of the
+	  available size.
+
+config DCACHE_RAM_MRC_VAR_SIZE
+	hex
+	depends on HAVE_MRC
+	help
+	  This is the amount of CAR (Cache as RAM) reserved for use by the
+	  memory reference code. This depends on the implementation of the
+	  memory reference code and must be set correctly or the board will
+	  not boot.
+
+config HAVE_REFCODE
+        bool "Add a Reference Code binary"
+        help
+          Select this option to add a Reference Code binary to the resulting
+          U-Boot image. This is an Intel binary blob that handles system
+          initialisation, in this case the PCH and System Agent.
+
+          Note: Without this binary (on platforms that need it such as
+          broadwell) U-Boot will be missing some critical setup steps.
+          Various peripherals may fail to work.
+
 config SMP
 	bool "Enable Symmetric Multiprocessing"
 	default n
@@ -449,6 +526,16 @@
 config DM_KEYBOARD
 	default y
 
+config SEABIOS
+	bool "Support booting SeaBIOS"
+	help
+	  SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
+	  It can run in an emulator or natively on X86 hardware with the use
+	  of coreboot/U-Boot. By turning on this option, U-Boot prepares
+	  all the configuration tables that are necessary to boot SeaBIOS.
+
+	  Check http://www.seabios.org/SeaBIOS for details.
+
 source "arch/x86/lib/efi/Kconfig"
 
 endmenu
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 2ff2377..2667e0b 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -18,7 +18,9 @@
 
 extra-y += call32.o
 
+obj-y += intel_common/
 obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
+obj-$(CONFIG_INTEL_BROADWELL) += broadwell/
 obj-$(CONFIG_SYS_COREBOOT) += coreboot/
 obj-$(CONFIG_EFI_APP) += efi/
 obj-$(CONFIG_QEMU) += qemu/
diff --git a/arch/x86/cpu/broadwell/Kconfig b/arch/x86/cpu/broadwell/Kconfig
new file mode 100644
index 0000000..1ce3848
--- /dev/null
+++ b/arch/x86/cpu/broadwell/Kconfig
@@ -0,0 +1,30 @@
+#
+# Copyright (C) 2016 Google Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0
+
+config INTEL_BROADWELL
+	bool
+	select CACHE_MRC_BIN
+
+if INTEL_BROADWELL
+
+config DCACHE_RAM_BASE
+	default 0xff7c0000
+
+config DCACHE_RAM_SIZE
+	default 0x40000
+
+config DCACHE_RAM_MRC_VAR_SIZE
+	default 0x30000
+
+config CPU_SPECIFIC_OPTIONS
+	def_bool y
+	select SMM_TSEG
+	select X86_RAMTEST
+
+config SMM_TSEG_SIZE
+	hex
+	default 0x800000
+
+endif
diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
new file mode 100644
index 0000000..7edb6f6
--- /dev/null
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += iobp.o
+obj-y += lpc.o
+obj-y += me.o
+obj-y += northbridge.o
+obj-y += pch.o
+obj-y += pinctrl_broadwell.o
+obj-y += power_state.o
+obj-y += refcode.o
+obj-y += sata.o
+obj-y += sdram.o
diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c
new file mode 100644
index 0000000..3ba21aa
--- /dev/null
+++ b/arch/x86/cpu/broadwell/cpu.c
@@ -0,0 +1,761 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ *
+ * Based on code from coreboot src/soc/intel/broadwell/cpu.c
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <cpu.h>
+#include <asm/cpu.h>
+#include <asm/cpu_x86.h>
+#include <asm/cpu_common.h>
+#include <asm/intel_regs.h>
+#include <asm/msr.h>
+#include <asm/post.h>
+#include <asm/turbo.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/rcb.h>
+
+struct cpu_broadwell_priv {
+	bool ht_disabled;
+};
+
+/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
+static const u8 power_limit_time_sec_to_msr[] = {
+	[0]   = 0x00,
+	[1]   = 0x0a,
+	[2]   = 0x0b,
+	[3]   = 0x4b,
+	[4]   = 0x0c,
+	[5]   = 0x2c,
+	[6]   = 0x4c,
+	[7]   = 0x6c,
+	[8]   = 0x0d,
+	[10]  = 0x2d,
+	[12]  = 0x4d,
+	[14]  = 0x6d,
+	[16]  = 0x0e,
+	[20]  = 0x2e,
+	[24]  = 0x4e,
+	[28]  = 0x6e,
+	[32]  = 0x0f,
+	[40]  = 0x2f,
+	[48]  = 0x4f,
+	[56]  = 0x6f,
+	[64]  = 0x10,
+	[80]  = 0x30,
+	[96]  = 0x50,
+	[112] = 0x70,
+	[128] = 0x11,
+};
+
+/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
+static const u8 power_limit_time_msr_to_sec[] = {
+	[0x00] = 0,
+	[0x0a] = 1,
+	[0x0b] = 2,
+	[0x4b] = 3,
+	[0x0c] = 4,
+	[0x2c] = 5,
+	[0x4c] = 6,
+	[0x6c] = 7,
+	[0x0d] = 8,
+	[0x2d] = 10,
+	[0x4d] = 12,
+	[0x6d] = 14,
+	[0x0e] = 16,
+	[0x2e] = 20,
+	[0x4e] = 24,
+	[0x6e] = 28,
+	[0x0f] = 32,
+	[0x2f] = 40,
+	[0x4f] = 48,
+	[0x6f] = 56,
+	[0x10] = 64,
+	[0x30] = 80,
+	[0x50] = 96,
+	[0x70] = 112,
+	[0x11] = 128,
+};
+
+int arch_cpu_init_dm(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	/* Start up the LPC so we have serial */
+	ret = uclass_first_device(UCLASS_LPC, &dev);
+	if (ret)
+		return ret;
+	if (!dev)
+		return -ENODEV;
+	ret = cpu_set_flex_ratio_to_tdp_nominal();
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+void set_max_freq(void)
+{
+	msr_t msr, perf_ctl, platform_info;
+
+	/* Check for configurable TDP option */
+	platform_info = msr_read(MSR_PLATFORM_INFO);
+
+	if ((platform_info.hi >> 1) & 3) {
+		/* Set to nominal TDP ratio */
+		msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+		perf_ctl.lo = (msr.lo & 0xff) << 8;
+	} else {
+		/* Platform Info bits 15:8 give max ratio */
+		msr = msr_read(MSR_PLATFORM_INFO);
+		perf_ctl.lo = msr.lo & 0xff00;
+	}
+
+	perf_ctl.hi = 0;
+	msr_write(IA32_PERF_CTL, perf_ctl);
+
+	debug("CPU: frequency set to %d MHz\n",
+	      ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
+}
+
+int arch_cpu_init(void)
+{
+	post_code(POST_CPU_INIT);
+
+	return x86_cpu_init_f();
+}
+
+int print_cpuinfo(void)
+{
+	char processor_name[CPU_MAX_NAME_LEN];
+	const char *name;
+	int ret;
+
+	set_max_freq();
+
+	ret = cpu_common_init();
+	if (ret)
+		return ret;
+	gd->arch.pei_boot_mode = PEI_BOOT_NONE;
+
+	/* Print processor name */
+	name = cpu_get_name(processor_name);
+	printf("CPU:   %s\n", name);
+
+	return 0;
+}
+
+/*
+ * The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
+ * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
+ * when a core is woken up
+ */
+static int pcode_ready(void)
+{
+	int wait_count;
+	const int delay_step = 10;
+
+	wait_count = 0;
+	do {
+		if (!(readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) &
+				MAILBOX_RUN_BUSY))
+			return 0;
+		wait_count += delay_step;
+		udelay(delay_step);
+	} while (wait_count < 1000);
+
+	return -ETIMEDOUT;
+}
+
+static u32 pcode_mailbox_read(u32 command)
+{
+	int ret;
+
+	ret = pcode_ready();
+	if (ret) {
+		debug("PCODE: mailbox timeout on wait ready\n");
+		return ret;
+	}
+
+	/* Send command and start transaction */
+	writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
+
+	ret = pcode_ready();
+	if (ret) {
+		debug("PCODE: mailbox timeout on completion\n");
+		return ret;
+	}
+
+	/* Read mailbox */
+	return readl(MCHBAR_REG(BIOS_MAILBOX_DATA));
+}
+
+static int pcode_mailbox_write(u32 command, u32 data)
+{
+	int ret;
+
+	ret = pcode_ready();
+	if (ret) {
+		debug("PCODE: mailbox timeout on wait ready\n");
+		return ret;
+	}
+
+	writel(data, MCHBAR_REG(BIOS_MAILBOX_DATA));
+
+	/* Send command and start transaction */
+	writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
+
+	ret = pcode_ready();
+	if (ret) {
+		debug("PCODE: mailbox timeout on completion\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+/* @dev is the CPU device */
+static void initialize_vr_config(struct udevice *dev)
+{
+	int ramp, min_vid;
+	msr_t msr;
+
+	debug("Initializing VR config\n");
+
+	/* Configure VR_CURRENT_CONFIG */
+	msr = msr_read(MSR_VR_CURRENT_CONFIG);
+	/*
+	 * Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid
+	 * on ULT systems
+	 */
+	msr.hi &= 0xc0000000;
+	msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold -  1A */
+	msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold -  5A */
+	msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A */
+	msr.hi |= (1 <<  (62 - 32)); /* Enable PSI4 */
+	/* Leave the max instantaneous current limit (12:0) to default */
+	msr_write(MSR_VR_CURRENT_CONFIG, msr);
+
+	/* Configure VR_MISC_CONFIG MSR */
+	msr = msr_read(MSR_VR_MISC_CONFIG);
+	/* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format */
+	msr.hi &= ~(0x3ff << (40 - 32));
+	msr.hi |= (0x200 << (40 - 32)); /* 1.0 */
+	/* Set IOUT_OFFSET to 0 */
+	msr.hi &= ~0xff;
+	/* Set entry ramp rate to slow */
+	msr.hi &= ~(1 << (51 - 32));
+	/* Enable decay mode on C-state entry */
+	msr.hi |= (1 << (52 - 32));
+	/* Set the slow ramp rate */
+	msr.hi &= ~(0x3 << (53 - 32));
+	/* Configure the C-state exit ramp rate */
+	ramp = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "intel,slow-ramp",
+			      -1);
+	if (ramp != -1) {
+		/* Configured slow ramp rate */
+		msr.hi |= ((ramp & 0x3) << (53 - 32));
+		/* Set exit ramp rate to slow */
+		msr.hi &= ~(1 << (50 - 32));
+	} else {
+		/* Fast ramp rate / 4 */
+		msr.hi |= (0x01 << (53 - 32));
+		/* Set exit ramp rate to fast */
+		msr.hi |= (1 << (50 - 32));
+	}
+	/* Set MIN_VID (31:24) to allow CPU to have full control */
+	msr.lo &= ~0xff000000;
+	min_vid = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "intel,min-vid",
+				 0);
+	msr.lo |= (min_vid & 0xff) << 24;
+	msr_write(MSR_VR_MISC_CONFIG, msr);
+
+	/*  Configure VR_MISC_CONFIG2 MSR */
+	msr = msr_read(MSR_VR_MISC_CONFIG2);
+	msr.lo &= ~0xffff;
+	/*
+	 * Allow CPU to control minimum voltage completely (15:8) and
+	 * set the fast ramp voltage in 10mV steps
+	 */
+	if (cpu_get_family_model() == BROADWELL_FAMILY_ULT)
+		msr.lo |= 0x006a; /* 1.56V */
+	else
+		msr.lo |= 0x006f; /* 1.60V */
+	msr_write(MSR_VR_MISC_CONFIG2, msr);
+
+	/* Set C9/C10 VCC Min */
+	pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f);
+}
+
+static int calibrate_24mhz_bclk(void)
+{
+	int err_code;
+	int ret;
+
+	ret = pcode_ready();
+	if (ret)
+		return ret;
+
+	/* A non-zero value initiates the PCODE calibration */
+	writel(~0, MCHBAR_REG(BIOS_MAILBOX_DATA));
+	writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL,
+	       MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
+
+	ret = pcode_ready();
+	if (ret)
+		return ret;
+
+	err_code = readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) & 0xff;
+
+	debug("PCODE: 24MHz BLCK calibration response: %d\n", err_code);
+
+	/* Read the calibrated value */
+	writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION,
+	       MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
+
+	ret = pcode_ready();
+	if (ret)
+		return ret;
+
+	debug("PCODE: 24MHz BLCK calibration value: 0x%08x\n",
+	      readl(MCHBAR_REG(BIOS_MAILBOX_DATA)));
+
+	return 0;
+}
+
+static void configure_pch_power_sharing(void)
+{
+	u32 pch_power, pch_power_ext, pmsync, pmsync2;
+	int i;
+
+	/* Read PCH Power levels from PCODE */
+	pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER);
+	pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
+
+	debug("PCH Power: PCODE Levels 0x%08x 0x%08x\n", pch_power,
+	      pch_power_ext);
+
+	pmsync = readl(RCB_REG(PMSYNC_CONFIG));
+	pmsync2 = readl(RCB_REG(PMSYNC_CONFIG2));
+
+	/*
+	 * Program PMSYNC_TPR_CONFIG PCH power limit values
+	 *  pmsync[0:4]   = mailbox[0:5]
+	 *  pmsync[8:12]  = mailbox[6:11]
+	 *  pmsync[16:20] = mailbox[12:17]
+	 */
+	for (i = 0; i < 3; i++) {
+		u32 level = pch_power & 0x3f;
+		pch_power >>= 6;
+		pmsync &= ~(0x1f << (i * 8));
+		pmsync |= (level & 0x1f) << (i * 8);
+	}
+	writel(pmsync, RCB_REG(PMSYNC_CONFIG));
+
+	/*
+	 * Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values
+	 *  pmsync2[0:4]   = mailbox[23:18]
+	 *  pmsync2[8:12]  = mailbox_ext[6:11]
+	 *  pmsync2[16:20] = mailbox_ext[12:17]
+	 *  pmsync2[24:28] = mailbox_ext[18:22]
+	 */
+	pmsync2 &= ~0x1f;
+	pmsync2 |= pch_power & 0x1f;
+
+	for (i = 1; i < 4; i++) {
+		u32 level = pch_power_ext & 0x3f;
+		pch_power_ext >>= 6;
+		pmsync2 &= ~(0x1f << (i * 8));
+		pmsync2 |= (level & 0x1f) << (i * 8);
+	}
+	writel(pmsync2, RCB_REG(PMSYNC_CONFIG2));
+}
+
+static int bsp_init_before_ap_bringup(struct udevice *dev)
+{
+	int ret;
+
+	initialize_vr_config(dev);
+	ret = calibrate_24mhz_bclk();
+	if (ret)
+		return ret;
+	configure_pch_power_sharing();
+
+	return 0;
+}
+
+int cpu_config_tdp_levels(void)
+{
+	msr_t platform_info;
+
+	/* Bits 34:33 indicate how many levels supported */
+	platform_info = msr_read(MSR_PLATFORM_INFO);
+	return (platform_info.hi >> 1) & 3;
+}
+
+static void set_max_ratio(void)
+{
+	msr_t msr, perf_ctl;
+
+	perf_ctl.hi = 0;
+
+	/* Check for configurable TDP option */
+	if (turbo_get_state() == TURBO_ENABLED) {
+		msr = msr_read(MSR_NHM_TURBO_RATIO_LIMIT);
+		perf_ctl.lo = (msr.lo & 0xff) << 8;
+	} else if (cpu_config_tdp_levels()) {
+		/* Set to nominal TDP ratio */
+		msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+		perf_ctl.lo = (msr.lo & 0xff) << 8;
+	} else {
+		/* Platform Info bits 15:8 give max ratio */
+		msr = msr_read(MSR_PLATFORM_INFO);
+		perf_ctl.lo = msr.lo & 0xff00;
+	}
+	msr_write(IA32_PERF_CTL, perf_ctl);
+
+	debug("cpu: frequency set to %d\n",
+	      ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
+}
+
+int broadwell_init(struct udevice *dev)
+{
+	struct cpu_broadwell_priv *priv = dev_get_priv(dev);
+	int num_threads;
+	int num_cores;
+	msr_t msr;
+	int ret;
+
+	msr = msr_read(CORE_THREAD_COUNT_MSR);
+	num_threads = (msr.lo >> 0) & 0xffff;
+	num_cores = (msr.lo >> 16) & 0xffff;
+	debug("CPU has %u cores, %u threads enabled\n", num_cores,
+	      num_threads);
+
+	priv->ht_disabled = num_threads == num_cores;
+
+	ret = bsp_init_before_ap_bringup(dev);
+	if (ret)
+		return ret;
+
+	set_max_ratio();
+
+	return ret;
+}
+
+static void configure_mca(void)
+{
+	msr_t msr;
+	const unsigned int mcg_cap_msr = 0x179;
+	int i;
+	int num_banks;
+
+	msr = msr_read(mcg_cap_msr);
+	num_banks = msr.lo & 0xff;
+	msr.lo = 0;
+	msr.hi = 0;
+	/*
+	 * TODO(adurbin): This should only be done on a cold boot. Also, some
+	 * of these banks are core vs package scope. For now every CPU clears
+	 * every bank
+	 */
+	for (i = 0; i < num_banks; i++)
+		msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr);
+}
+
+static void enable_lapic_tpr(void)
+{
+	msr_t msr;
+
+	msr = msr_read(MSR_PIC_MSG_CONTROL);
+	msr.lo &= ~(1 << 10);	/* Enable APIC TPR updates */
+	msr_write(MSR_PIC_MSG_CONTROL, msr);
+}
+
+
+static void configure_c_states(void)
+{
+	msr_t msr;
+
+	msr = msr_read(MSR_PMG_CST_CONFIG_CONTROL);
+	msr.lo |= (1 << 31);	/* Timed MWAIT Enable */
+	msr.lo |= (1 << 30);	/* Package c-state Undemotion Enable */
+	msr.lo |= (1 << 29);	/* Package c-state Demotion Enable */
+	msr.lo |= (1 << 28);	/* C1 Auto Undemotion Enable */
+	msr.lo |= (1 << 27);	/* C3 Auto Undemotion Enable */
+	msr.lo |= (1 << 26);	/* C1 Auto Demotion Enable */
+	msr.lo |= (1 << 25);	/* C3 Auto Demotion Enable */
+	msr.lo &= ~(1 << 10);	/* Disable IO MWAIT redirection */
+	/* The deepest package c-state defaults to factory-configured value */
+	msr_write(MSR_PMG_CST_CONFIG_CONTROL, msr);
+
+	msr = msr_read(MSR_MISC_PWR_MGMT);
+	msr.lo &= ~(1 << 0);	/* Enable P-state HW_ALL coordination */
+	msr_write(MSR_MISC_PWR_MGMT, msr);
+
+	msr = msr_read(MSR_POWER_CTL);
+	msr.lo |= (1 << 18);	/* Enable Energy Perf Bias MSR 0x1b0 */
+	msr.lo |= (1 << 1);	/* C1E Enable */
+	msr.lo |= (1 << 0);	/* Bi-directional PROCHOT# */
+	msr_write(MSR_POWER_CTL, msr);
+
+	/* C-state Interrupt Response Latency Control 0 - package C3 latency */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
+	msr_write(MSR_C_STATE_LATENCY_CONTROL_0, msr);
+
+	/* C-state Interrupt Response Latency Control 1 */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
+	msr_write(MSR_C_STATE_LATENCY_CONTROL_1, msr);
+
+	/* C-state Interrupt Response Latency Control 2 - package C6/C7 short */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
+	msr_write(MSR_C_STATE_LATENCY_CONTROL_2, msr);
+
+	/* C-state Interrupt Response Latency Control 3 - package C8 */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT;
+	msr_write(MSR_C_STATE_LATENCY_CONTROL_3, msr);
+
+	/* C-state Interrupt Response Latency Control 4 - package C9 */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT;
+	msr_write(MSR_C_STATE_LATENCY_CONTROL_4, msr);
+
+	/* C-state Interrupt Response Latency Control 5 - package C10 */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT;
+	msr_write(MSR_C_STATE_LATENCY_CONTROL_5, msr);
+}
+
+static void configure_misc(void)
+{
+	msr_t msr;
+
+	msr = msr_read(MSR_IA32_MISC_ENABLE);
+	msr.lo |= (1 << 0);	  /* Fast String enable */
+	msr.lo |= (1 << 3);	  /* TM1/TM2/EMTTM enable */
+	msr.lo |= (1 << 16);	  /* Enhanced SpeedStep Enable */
+	msr_write(MSR_IA32_MISC_ENABLE, msr);
+
+	/* Disable thermal interrupts */
+	msr.lo = 0;
+	msr.hi = 0;
+	msr_write(MSR_IA32_THERM_INTERRUPT, msr);
+
+	/* Enable package critical interrupt only */
+	msr.lo = 1 << 4;
+	msr.hi = 0;
+	msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr);
+}
+
+static void configure_thermal_target(struct udevice *dev)
+{
+	int tcc_offset;
+	msr_t msr;
+
+	tcc_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+				    "intel,tcc-offset", 0);
+
+	/* Set TCC activaiton offset if supported */
+	msr = msr_read(MSR_PLATFORM_INFO);
+	if ((msr.lo & (1 << 30)) && tcc_offset) {
+		msr = msr_read(MSR_TEMPERATURE_TARGET);
+		msr.lo &= ~(0xf << 24); /* Bits 27:24 */
+		msr.lo |= (tcc_offset & 0xf) << 24;
+		msr_write(MSR_TEMPERATURE_TARGET, msr);
+	}
+}
+
+static void configure_dca_cap(void)
+{
+	struct cpuid_result cpuid_regs;
+	msr_t msr;
+
+	/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
+	cpuid_regs = cpuid(1);
+	if (cpuid_regs.ecx & (1 << 18)) {
+		msr = msr_read(MSR_IA32_PLATFORM_DCA_CAP);
+		msr.lo |= 1;
+		msr_write(MSR_IA32_PLATFORM_DCA_CAP, msr);
+	}
+}
+
+static void set_energy_perf_bias(u8 policy)
+{
+	msr_t msr;
+	int ecx;
+
+	/* Determine if energy efficient policy is supported */
+	ecx = cpuid_ecx(0x6);
+	if (!(ecx & (1 << 3)))
+		return;
+
+	/* Energy Policy is bits 3:0 */
+	msr = msr_read(MSR_IA32_ENERGY_PERFORMANCE_BIAS);
+	msr.lo &= ~0xf;
+	msr.lo |= policy & 0xf;
+	msr_write(MSR_IA32_ENERGY_PERFORMANCE_BIAS, msr);
+
+	debug("cpu: energy policy set to %u\n", policy);
+}
+
+/* All CPUs including BSP will run the following function */
+static void cpu_core_init(struct udevice *dev)
+{
+	/* Clear out pending MCEs */
+	configure_mca();
+
+	/* Enable the local cpu apics */
+	enable_lapic_tpr();
+
+	/* Configure C States */
+	configure_c_states();
+
+	/* Configure Enhanced SpeedStep and Thermal Sensors */
+	configure_misc();
+
+	/* Thermal throttle activation offset */
+	configure_thermal_target(dev);
+
+	/* Enable Direct Cache Access */
+	configure_dca_cap();
+
+	/* Set energy policy */
+	set_energy_perf_bias(ENERGY_POLICY_NORMAL);
+
+	/* Enable Turbo */
+	turbo_enable();
+}
+
+/*
+ * Configure processor power limits if possible
+ * This must be done AFTER set of BIOS_RESET_CPL
+ */
+void cpu_set_power_limits(int power_limit_1_time)
+{
+	msr_t msr;
+	msr_t limit;
+	unsigned power_unit;
+	unsigned tdp, min_power, max_power, max_time;
+	u8 power_limit_1_val;
+
+	msr = msr_read(MSR_PLATFORM_INFO);
+	if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
+		power_limit_1_time = 28;
+
+	if (!(msr.lo & PLATFORM_INFO_SET_TDP))
+		return;
+
+	/* Get units */
+	msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
+	power_unit = 2 << ((msr.lo & 0xf) - 1);
+
+	/* Get power defaults for this SKU */
+	msr = msr_read(MSR_PKG_POWER_SKU);
+	tdp = msr.lo & 0x7fff;
+	min_power = (msr.lo >> 16) & 0x7fff;
+	max_power = msr.hi & 0x7fff;
+	max_time = (msr.hi >> 16) & 0x7f;
+
+	debug("CPU TDP: %u Watts\n", tdp / power_unit);
+
+	if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
+		power_limit_1_time = power_limit_time_msr_to_sec[max_time];
+
+	if (min_power > 0 && tdp < min_power)
+		tdp = min_power;
+
+	if (max_power > 0 && tdp > max_power)
+		tdp = max_power;
+
+	power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
+
+	/* Set long term power limit to TDP */
+	limit.lo = 0;
+	limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
+	limit.lo |= PKG_POWER_LIMIT_EN;
+	limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
+		PKG_POWER_LIMIT_TIME_SHIFT;
+
+	/* Set short term power limit to 1.25 * TDP */
+	limit.hi = 0;
+	limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
+	limit.hi |= PKG_POWER_LIMIT_EN;
+	/* Power limit 2 time is only programmable on server SKU */
+
+	msr_write(MSR_PKG_POWER_LIMIT, limit);
+
+	/* Set power limit values in MCHBAR as well */
+	writel(limit.lo, MCHBAR_REG(MCH_PKG_POWER_LIMIT_LO));
+	writel(limit.hi, MCHBAR_REG(MCH_PKG_POWER_LIMIT_HI));
+
+	/* Set DDR RAPL power limit by copying from MMIO to MSR */
+	msr.lo = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_LO));
+	msr.hi = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_HI));
+	msr_write(MSR_DDR_RAPL_LIMIT, msr);
+
+	/* Use nominal TDP values for CPUs with configurable TDP */
+	if (cpu_config_tdp_levels()) {
+		msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+		limit.hi = 0;
+		limit.lo = msr.lo & 0xff;
+		msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
+	}
+}
+
+static int broadwell_get_info(struct udevice *dev, struct cpu_info *info)
+{
+	msr_t msr;
+
+	msr = msr_read(IA32_PERF_CTL);
+	info->cpu_freq = ((msr.lo >> 8) & 0xff) * BROADWELL_BCLK * 1000000;
+	info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
+		1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID;
+
+	return 0;
+}
+
+static int broadwell_get_count(struct udevice *dev)
+{
+	return 4;
+}
+
+static int cpu_x86_broadwell_probe(struct udevice *dev)
+{
+	if (dev->seq == 0) {
+		cpu_core_init(dev);
+		return broadwell_init(dev);
+	}
+
+	return 0;
+}
+
+static const struct cpu_ops cpu_x86_broadwell_ops = {
+	.get_desc	= cpu_x86_get_desc,
+	.get_info	= broadwell_get_info,
+	.get_count	= broadwell_get_count,
+};
+
+static const struct udevice_id cpu_x86_broadwell_ids[] = {
+	{ .compatible = "intel,core-i3-gen5" },
+	{ }
+};
+
+U_BOOT_DRIVER(cpu_x86_broadwell_drv) = {
+	.name		= "cpu_x86_broadwell",
+	.id		= UCLASS_CPU,
+	.of_match	= cpu_x86_broadwell_ids,
+	.bind		= cpu_x86_bind,
+	.probe		= cpu_x86_broadwell_probe,
+	.ops		= &cpu_x86_broadwell_ops,
+	.priv_auto_alloc_size	= sizeof(struct cpu_broadwell_priv),
+};
diff --git a/arch/x86/cpu/broadwell/iobp.c b/arch/x86/cpu/broadwell/iobp.c
new file mode 100644
index 0000000..5eed849
--- /dev/null
+++ b/arch/x86/cpu/broadwell/iobp.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * Modified from coreboot
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/intel_regs.h>
+#include <asm/io.h>
+#include <asm/arch/pch.h>
+
+#define IOBP_RETRY 1000
+
+/* IO Buffer Programming */
+#define IOBPIRI		0x2330
+#define IOBPD		0x2334
+#define IOBPS		0x2338
+#define  IOBPS_READY	0x0001
+#define  IOBPS_TX_MASK	0x0006
+#define  IOBPS_MASK     0xff00
+#define  IOBPS_READ     0x0600
+#define  IOBPS_WRITE	0x0700
+#define IOBPU		0x233a
+#define  IOBPU_MAGIC	0xf000
+#define  IOBP_PCICFG_READ	0x0400
+#define  IOBP_PCICFG_WRITE	0x0500
+
+static inline int iobp_poll(void)
+{
+	unsigned try;
+
+	for (try = IOBP_RETRY; try > 0; try--) {
+		u16 status = readw(RCB_REG(IOBPS));
+		if ((status & IOBPS_READY) == 0)
+			return 1;
+		udelay(10);
+	}
+
+	printf("IOBP: timeout waiting for transaction to complete\n");
+	return 0;
+}
+
+int pch_iobp_trans_start(u32 address, int op)
+{
+	if (!iobp_poll())
+		return 0;
+
+	/* Set the address */
+	writel(address, RCB_REG(IOBPIRI));
+
+	/* READ OPCODE */
+	clrsetbits_le16(RCB_REG(IOBPS), IOBPS_MASK, op);
+
+	return 1;
+}
+
+int pch_iobp_trans_finish(void)
+{
+	u16 status;
+
+	/* Undocumented magic */
+	writew(IOBPU_MAGIC, RCB_REG(IOBPU));
+
+	/* Set ready bit */
+	setbits_le16(RCB_REG(IOBPS), IOBPS_READY);
+
+	if (!iobp_poll())
+		return 1;
+
+	/* Check for successful transaction */
+	status = readw(RCB_REG(IOBPS));
+	if (status & IOBPS_TX_MASK)
+		return 1;
+
+	return 0;
+}
+
+u32 pch_iobp_read(u32 address)
+{
+	if (!pch_iobp_trans_start(address, IOBPS_READ))
+		return 0;
+	if (pch_iobp_trans_finish()) {
+		printf("IOBP: read 0x%08x failed\n", address);
+		return 0;
+	}
+
+	/* Read IOBP data */
+	return readl(RCB_REG(IOBPD));
+}
+
+int pch_iobp_write(u32 address, u32 data)
+{
+	if (!pch_iobp_trans_start(address, IOBPS_WRITE))
+		return -EIO;
+
+	writel(data, RCB_REG(IOBPD));
+
+	if (pch_iobp_trans_finish()) {
+		printf("IOBP: write 0x%08x failed\n", address);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+int pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
+{
+	u32 data = pch_iobp_read(address);
+
+	/* Update the data */
+	data &= andvalue;
+	data |= orvalue;
+
+	return pch_iobp_write(address, data);
+}
+
+int pch_iobp_exec(u32 addr, u16 op_code, u8 route_id, u32 *data, u8 *resp)
+{
+	if (!data || !resp)
+		return 0;
+
+	*resp = -1;
+	if (!iobp_poll())
+		return -EIO;
+
+	writel(addr, RCB_REG(IOBPIRI));
+	clrsetbits_le16(RCB_REG(IOBPS), 0xff00, op_code);
+	writew(IOBPU_MAGIC | route_id, RCB_REG(IOBPU));
+
+	writel(*data, RCB_REG(IOBPD));
+	/* Set IOBPS[0] to trigger IOBP transaction*/
+	setbits_le16(RCB_REG(IOBPS), 1);
+
+	if (!iobp_poll())
+		return -EIO;
+
+	*resp = (readw(RCB_REG(IOBPS)) & IOBPS_TX_MASK) >> 1;
+	*data = readl(RCB_REG(IOBPD));
+
+	return 0;
+}
diff --git a/arch/x86/cpu/broadwell/lpc.c b/arch/x86/cpu/broadwell/lpc.c
new file mode 100644
index 0000000..ee3ac18
--- /dev/null
+++ b/arch/x86/cpu/broadwell/lpc.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * From coreboot broadwell support
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pch.h>
+#include <asm/intel_regs.h>
+#include <asm/io.h>
+#include <asm/lpc_common.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/spi.h>
+
+static void set_spi_speed(void)
+{
+	u32 fdod;
+	u8 ssfc;
+
+	/* Observe SPI Descriptor Component Section 0 */
+	writel(0x1000, SPI_REG(SPIBAR_FDOC));
+
+	/* Extract the Write/Erase SPI Frequency from descriptor */
+	fdod = readl(SPI_REG(SPIBAR_FDOD));
+	fdod >>= 24;
+	fdod &= 7;
+
+	/* Set Software Sequence frequency to match */
+	ssfc = readb(SPI_REG(SPIBAR_SSFC + 2));
+	ssfc &= ~7;
+	ssfc |= fdod;
+	writeb(ssfc, SPI_REG(SPIBAR_SSFC + 2));
+}
+
+static int broadwell_lpc_early_init(struct udevice *dev)
+{
+	set_spi_speed();
+
+	return 0;
+}
+
+static int lpc_init_extra(struct udevice *dev)
+{
+	return 0;
+}
+
+static int broadwell_lpc_probe(struct udevice *dev)
+{
+	int ret;
+
+	if (!(gd->flags & GD_FLG_RELOC)) {
+		ret = lpc_common_early_init(dev);
+		if (ret) {
+			debug("%s: lpc_early_init() failed\n", __func__);
+			return ret;
+		}
+
+		return broadwell_lpc_early_init(dev);
+	}
+
+	return lpc_init_extra(dev);
+}
+
+static const struct udevice_id broadwell_lpc_ids[] = {
+	{ .compatible = "intel,broadwell-lpc" },
+	{ }
+};
+
+U_BOOT_DRIVER(broadwell_lpc_drv) = {
+	.name		= "lpc",
+	.id		= UCLASS_LPC,
+	.of_match	= broadwell_lpc_ids,
+	.probe		= broadwell_lpc_probe,
+};
diff --git a/arch/x86/cpu/broadwell/me.c b/arch/x86/cpu/broadwell/me.c
new file mode 100644
index 0000000..e03b87c
--- /dev/null
+++ b/arch/x86/cpu/broadwell/me.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ *
+ * Based on code from coreboot src/soc/intel/broadwell/me_status.c
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/me.h>
+
+static inline void me_read_dword_ptr(struct udevice *dev, void *ptr, int offset)
+{
+	u32 dword;
+
+	dm_pci_read_config32(dev, offset, &dword);
+	memcpy(ptr, &dword, sizeof(dword));
+}
+
+int intel_me_hsio_version(struct udevice *dev, uint16_t *versionp,
+			  uint16_t *checksump)
+{
+	int count;
+	u32 hsiover;
+	struct me_hfs hfs;
+
+	/* Query for HSIO version, overloads H_GS and HFS */
+	dm_pci_write_config32(dev, PCI_ME_H_GS,
+			      ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);
+
+	/* Must wait for ME acknowledgement */
+	for (count = ME_RETRY; count > 0; --count) {
+		me_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
+		if (hfs.bios_msg_ack)
+			break;
+		udelay(ME_DELAY);
+	}
+	if (!count) {
+		debug("ERROR: ME failed to respond\n");
+		return -ETIMEDOUT;
+	}
+
+	/* HSIO version should be in HFS_5 */
+	dm_pci_read_config32(dev, PCI_ME_HFS5, &hsiover);
+	*versionp = hsiover >> 16;
+	*checksump = hsiover & 0xffff;
+
+	debug("ME: HSIO Version            : %d (CRC 0x%04x)\n",
+	      *versionp, *checksump);
+
+	/* Reset registers to normal behavior */
+	dm_pci_write_config32(dev, PCI_ME_H_GS,
+			      ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);
+
+	return 0;
+}
diff --git a/arch/x86/cpu/broadwell/northbridge.c b/arch/x86/cpu/broadwell/northbridge.c
new file mode 100644
index 0000000..aa64808
--- /dev/null
+++ b/arch/x86/cpu/broadwell/northbridge.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2011 The Chromium Authors
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/iomap.h>
+#include <asm/arch/pch.h>
+
+static int broadwell_northbridge_early_init(struct udevice *dev)
+{
+	/* Move earlier? */
+	dm_pci_write_config32(dev, PCIEXBAR + 4, 0);
+	/* 64MiB - 0-63 buses */
+	dm_pci_write_config32(dev, PCIEXBAR, MCFG_BASE_ADDRESS | 4 | 1);
+
+	dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1);
+	dm_pci_write_config32(dev, DMIBAR, DMI_BASE_ADDRESS | 1);
+	dm_pci_write_config32(dev, EPBAR, EP_BASE_ADDRESS | 1);
+	writel(EDRAM_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + EDRAMBAR);
+	writel(GDXC_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + GDXCBAR);
+
+	/* Set C0000-FFFFF to access RAM on both reads and writes */
+	dm_pci_write_config8(dev, PAM0, 0x30);
+	dm_pci_write_config8(dev, PAM1, 0x33);
+	dm_pci_write_config8(dev, PAM2, 0x33);
+	dm_pci_write_config8(dev, PAM3, 0x33);
+	dm_pci_write_config8(dev, PAM4, 0x33);
+	dm_pci_write_config8(dev, PAM5, 0x33);
+	dm_pci_write_config8(dev, PAM6, 0x33);
+
+	/* Device enable: IGD and Mini-HD */
+	dm_pci_write_config32(dev, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
+
+	return 0;
+}
+
+static int broadwell_northbridge_probe(struct udevice *dev)
+{
+	if (!(gd->flags & GD_FLG_RELOC))
+		return broadwell_northbridge_early_init(dev);
+
+	return 0;
+}
+
+static const struct udevice_id broadwell_northbridge_ids[] = {
+	{ .compatible = "intel,broadwell-northbridge" },
+	{ }
+};
+
+U_BOOT_DRIVER(broadwell_northbridge_drv) = {
+	.name		= "broadwell_northbridge",
+	.id		= UCLASS_NORTHBRIDGE,
+	.of_match	= broadwell_northbridge_ids,
+	.probe		= broadwell_northbridge_probe,
+};
diff --git a/arch/x86/cpu/broadwell/pch.c b/arch/x86/cpu/broadwell/pch.c
new file mode 100644
index 0000000..f0798a7
--- /dev/null
+++ b/arch/x86/cpu/broadwell/pch.c
@@ -0,0 +1,540 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pch.h>
+#include <asm/cpu.h>
+#include <asm/gpio.h>
+#include <asm/i8259.h>
+#include <asm/intel_regs.h>
+#include <asm/io.h>
+#include <asm/ioapic.h>
+#include <asm/lpc_common.h>
+#include <asm/pch_common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/iomap.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/pm.h>
+#include <asm/arch/rcb.h>
+#include <asm/arch/spi.h>
+
+#define BIOS_CTRL	0xdc
+
+bool cpu_is_ult(void)
+{
+	u32 fm = cpu_get_family_model();
+
+	return fm == BROADWELL_FAMILY_ULT || fm == HASWELL_FAMILY_ULT;
+}
+
+static int broadwell_pch_early_init(struct udevice *dev)
+{
+	struct gpio_desc desc;
+	struct udevice *bus;
+	pci_dev_t bdf;
+	int ret;
+
+	dm_pci_write_config32(dev, PCH_RCBA, RCB_BASE_ADDRESS | 1);
+
+	dm_pci_write_config32(dev, PMBASE, ACPI_BASE_ADDRESS | 1);
+	dm_pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
+	dm_pci_write_config32(dev, GPIO_BASE, GPIO_BASE_ADDRESS | 1);
+	dm_pci_write_config8(dev, GPIO_CNTL, GPIO_EN);
+
+	/* Enable IOAPIC */
+	writew(0x1000, RCB_REG(OIC));
+	/* Read back for posted write */
+	readw(RCB_REG(OIC));
+
+	/* Set HPET address and enable it */
+	clrsetbits_le32(RCB_REG(HPTC), 3, 1 << 7);
+	/* Read back for posted write */
+	readl(RCB_REG(HPTC));
+	/* Enable HPET to start counter */
+	setbits_le32(HPET_BASE_ADDRESS + 0x10, 1 << 0);
+
+	setbits_le32(RCB_REG(GCS), 1 << 5);
+
+	/*
+	 * Enable PP3300_AUTOBAHN_EN after initial GPIO setup
+	 * to prevent possible brownout. This will cause the GPIOs to be set
+	 * up if it has not been done already.
+	 */
+	ret = gpio_request_by_name(dev, "power-enable-gpio", 0, &desc,
+				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+	if (ret)
+		return ret;
+
+	/* 8.14 Additional PCI Express Programming Steps, step #1 */
+	bdf = PCI_BDF(0, 0x1c, 0);
+	bus = pci_get_controller(dev);
+	pci_bus_clrset_config32(bus, bdf, 0xf4, 0x60, 0);
+	pci_bus_clrset_config32(bus, bdf, 0xf4, 0x80, 0x80);
+	pci_bus_clrset_config32(bus, bdf, 0xe2, 0x30, 0x30);
+
+	return 0;
+}
+
+static void pch_misc_init(struct udevice *dev)
+{
+	/* Setup SLP signal assertion, SLP_S4=4s, SLP_S3=50ms */
+	dm_pci_clrset_config8(dev, GEN_PMCON_3, 3 << 4 | 1 << 10,
+			      1 << 3 | 1 << 11 | 1 << 12);
+	/* Prepare sleep mode */
+	clrsetio_32(ACPI_BASE_ADDRESS + PM1_CNT, SLP_TYP, SCI_EN);
+
+	/* Setup NMI on errors, disable SERR */
+	clrsetio_8(0x61, 0xf0, 1 << 2);
+	/* Disable NMI sources */
+	setio_8(0x70, 1 << 7);
+	/* Indicate DRAM init done for MRC */
+	dm_pci_clrset_config8(dev, GEN_PMCON_2, 0, 1 << 7);
+
+	/* Clear status bits to prevent unexpected wake */
+	setbits_le32(RCB_REG(0x3310), 0x0000002f);
+	clrsetbits_le32(RCB_REG(0x3f02), 0x0000000f, 0);
+	/* Enable PCIe Relaxed Order */
+	setbits_le32(RCB_REG(0x2314), 1 << 31 | 1 << 7);
+	setbits_le32(RCB_REG(0x1114), 1 << 15 | 1 << 14);
+	/* Setup SERIRQ, enable continuous mode */
+	dm_pci_clrset_config8(dev, SERIRQ_CNTL, 0, 1 << 7 | 1 << 6);
+};
+
+static void pch_enable_ioapic(void)
+{
+	u32 reg32;
+
+	io_apic_set_id(0x02);
+
+	/* affirm full set of redirection table entries ("write once") */
+	reg32 = io_apic_read(0x01);
+
+	/* PCH-LP has 39 redirection entries */
+	reg32 &= ~0x00ff0000;
+	reg32 |= 0x00270000;
+
+	io_apic_write(0x01, reg32);
+
+	/*
+	 * Select Boot Configuration register (0x03) and
+	 * use Processor System Bus (0x01) to deliver interrupts.
+	 */
+	io_apic_write(0x03, 0x01);
+}
+
+/* Enable all requested GPE */
+void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4)
+{
+	outl(set1, ACPI_BASE_ADDRESS + GPE0_EN(GPE_31_0));
+	outl(set2, ACPI_BASE_ADDRESS + GPE0_EN(GPE_63_32));
+	outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_94_64));
+	outl(set4, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
+}
+
+/*
+ * Enable GPIO SMI events - it would be good to put this in the GPIO driver
+ * but it would need a new driver operation.
+ */
+int enable_alt_smi(struct udevice *pch, u32 mask)
+{
+	struct pch_lp_gpio_regs *regs;
+	u32 gpiobase;
+	int ret;
+
+	ret = pch_get_gpio_base(pch, &gpiobase);
+	if (ret) {
+		debug("%s: invalid GPIOBASE address (%08x)\n", __func__,
+		      gpiobase);
+		return -EINVAL;
+	}
+
+	regs = (struct pch_lp_gpio_regs *)gpiobase;
+	setio_32(regs->alt_gpi_smi_en, mask);
+
+	return 0;
+}
+
+static int pch_power_options(struct udevice *dev)
+{
+	int pwr_on_after_power_fail = MAINBOARD_POWER_OFF;
+	const char *state;
+	u32 enable[4];
+	u16 reg16;
+	int ret;
+
+	dm_pci_read_config16(dev, GEN_PMCON_3, &reg16);
+	reg16 &= 0xfffe;
+	switch (pwr_on_after_power_fail) {
+	case MAINBOARD_POWER_OFF:
+		reg16 |= 1;
+		state = "off";
+		break;
+	case MAINBOARD_POWER_ON:
+		reg16 &= ~1;
+		state = "on";
+		break;
+	case MAINBOARD_POWER_KEEP:
+		reg16 &= ~1;
+		state = "state keep";
+		break;
+	default:
+		state = "undefined";
+	}
+	dm_pci_write_config16(dev, GEN_PMCON_3, reg16);
+	debug("Set power %s after power failure.\n", state);
+
+	/* GPE setup based on device tree configuration */
+	ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+				   "intel,gpe0-en", enable, ARRAY_SIZE(enable));
+	if (ret)
+		return -EINVAL;
+	enable_all_gpe(enable[0], enable[1], enable[2], enable[3]);
+
+	/* SMI setup based on device tree configuration */
+	enable_alt_smi(dev, fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+					   "intel,alt-gp-smi-enable", 0));
+
+	return 0;
+}
+
+/* Magic register settings for power management */
+static void pch_pm_init_magic(struct udevice *dev)
+{
+	dm_pci_write_config8(dev, 0xa9, 0x46);
+	clrbits_le32(RCB_REG(0x232c), 1),
+	setbits_le32(RCB_REG(0x1100), 0x0000c13f);
+	clrsetbits_le32(RCB_REG(0x2320), 0x60, 0x10);
+	writel(0x00012fff, RCB_REG(0x3314));
+	clrsetbits_le32(RCB_REG(0x3318), 0x000f0330, 0x0dcf0400);
+	writel(0x04000000, RCB_REG(0x3324));
+	writel(0x00041400, RCB_REG(0x3368));
+	writel(0x3f8ddbff, RCB_REG(0x3388));
+	writel(0x00007001, RCB_REG(0x33ac));
+	writel(0x00181900, RCB_REG(0x33b0));
+	writel(0x00060A00, RCB_REG(0x33c0));
+	writel(0x06200840, RCB_REG(0x33d0));
+	writel(0x01010101, RCB_REG(0x3a28));
+	writel(0x040c0404, RCB_REG(0x3a2c));
+	writel(0x9000000a, RCB_REG(0x3a9c));
+	writel(0x03808033, RCB_REG(0x2b1c));
+	writel(0x80000009, RCB_REG(0x2b34));
+	writel(0x022ddfff, RCB_REG(0x3348));
+	writel(0x00000001, RCB_REG(0x334c));
+	writel(0x0001c000, RCB_REG(0x3358));
+	writel(0x3f8ddbff, RCB_REG(0x3380));
+	writel(0x0001c7e1, RCB_REG(0x3384));
+	writel(0x0001c7e1, RCB_REG(0x338c));
+	writel(0x0001c000, RCB_REG(0x3398));
+	writel(0x00181900, RCB_REG(0x33a8));
+	writel(0x00080000, RCB_REG(0x33dc));
+	writel(0x00000001, RCB_REG(0x33e0));
+	writel(0x0000040c, RCB_REG(0x3a20));
+	writel(0x01010101, RCB_REG(0x3a24));
+	writel(0x01010101, RCB_REG(0x3a30));
+	dm_pci_clrset_config32(dev, 0xac, 0x00200000, 0);
+	setbits_le32(RCB_REG(0x0410), 0x00000003);
+	setbits_le32(RCB_REG(0x2618), 0x08000000);
+	setbits_le32(RCB_REG(0x2300), 0x00000002);
+	setbits_le32(RCB_REG(0x2600), 0x00000008);
+	writel(0x00007001, RCB_REG(0x33b4));
+	writel(0x022ddfff, RCB_REG(0x3350));
+	writel(0x00000001, RCB_REG(0x3354));
+	/* Power Optimizer */
+	setbits_le32(RCB_REG(0x33d4), 0x08000000);
+	/*
+	 * This stops the LCD from turning on:
+	 * setbits_le32(RCB_REG(0x33c8), 0x08000080);
+	 */
+	writel(0x0000883c, RCB_REG(0x2b10));
+	writel(0x1e0a4616, RCB_REG(0x2b14));
+	writel(0x40000005, RCB_REG(0x2b24));
+	writel(0x0005db01, RCB_REG(0x2b20));
+	writel(0x05145005, RCB_REG(0x3a80));
+	writel(0x00001005, RCB_REG(0x3a84));
+	setbits_le32(RCB_REG(0x33d4), 0x2fff2fb1);
+	setbits_le32(RCB_REG(0x33c8), 0x00008000);
+};
+
+static int pch_type(struct udevice *dev)
+{
+	u16 type;
+
+	dm_pci_read_config16(dev, PCI_DEVICE_ID, &type);
+
+	return type;
+}
+
+/* Return 1 if PCH type is WildcatPoint */
+static int pch_is_wpt(struct udevice *dev)
+{
+	return ((pch_type(dev) & 0xfff0) == 0x9cc0) ? 1 : 0;
+}
+
+/* Return 1 if PCH type is WildcatPoint ULX */
+static int pch_is_wpt_ulx(struct udevice *dev)
+{
+	u16 lpcid = pch_type(dev);
+
+	switch (lpcid) {
+	case PCH_WPT_BDW_Y_SAMPLE:
+	case PCH_WPT_BDW_Y_PREMIUM:
+	case PCH_WPT_BDW_Y_BASE:
+		return 1;
+	}
+
+	return 0;
+}
+
+static u32 pch_read_soft_strap(int id)
+{
+	clrbits_le32(SPI_REG(SPIBAR_FDOC), 0x00007ffc);
+	setbits_le32(SPI_REG(SPIBAR_FDOC), 0x00004000 | id * 4);
+
+	return readl(SPI_REG(SPIBAR_FDOD));
+}
+
+static void pch_enable_mphy(struct udevice *dev)
+{
+	u32 data_and = 0xffffffff;
+	u32 data_or = (1 << 14) | (1 << 13) | (1 << 12);
+
+	data_or |= (1 << 0);
+	if (pch_is_wpt(dev)) {
+		data_and &= ~((1 << 7) | (1 << 6) | (1 << 3));
+		data_or |= (1 << 5) | (1 << 4);
+
+		if (pch_is_wpt_ulx(dev)) {
+			/* Check if SATA and USB3 MPHY are enabled */
+			u32 strap19 = pch_read_soft_strap(19);
+			strap19 &= ((1 << 31) | (1 << 30));
+			strap19 >>= 30;
+			if (strap19 == 3) {
+				data_or |= (1 << 3);
+				debug("Enable ULX MPHY PG control in single domain\n");
+			} else if (strap19 == 0) {
+				debug("Enable ULX MPHY PG control in split domains\n");
+			} else {
+				debug("Invalid PCH Soft Strap 19 configuration\n");
+			}
+		} else {
+			data_or |= (1 << 3);
+		}
+	}
+
+	pch_iobp_update(0xCF000000, data_and, data_or);
+}
+
+static void pch_init_deep_sx(bool deep_sx_enable_ac, bool deep_sx_enable_dc)
+{
+	if (deep_sx_enable_ac) {
+		setbits_le32(RCB_REG(DEEP_S3_POL), DEEP_S3_EN_AC);
+		setbits_le32(RCB_REG(DEEP_S5_POL), DEEP_S5_EN_AC);
+	}
+
+	if (deep_sx_enable_dc) {
+		setbits_le32(RCB_REG(DEEP_S3_POL), DEEP_S3_EN_DC);
+		setbits_le32(RCB_REG(DEEP_S5_POL), DEEP_S5_EN_DC);
+	}
+
+	if (deep_sx_enable_ac || deep_sx_enable_dc) {
+		setbits_le32(RCB_REG(DEEP_SX_CONFIG),
+			     DEEP_SX_WAKE_PIN_EN | DEEP_SX_GP27_PIN_EN);
+	}
+}
+
+/* Power Management init */
+static void pch_pm_init(struct udevice *dev)
+{
+	debug("PCH PM init\n");
+
+	pch_init_deep_sx(false, false);
+	pch_enable_mphy(dev);
+	pch_pm_init_magic(dev);
+
+	if (pch_is_wpt(dev)) {
+		setbits_le32(RCB_REG(0x33e0), 1 << 4 | 1 << 1);
+		setbits_le32(RCB_REG(0x2b1c), 1 << 22 | 1 << 14 | 1 << 13);
+		writel(0x16bf0002, RCB_REG(0x33e4));
+		setbits_le32(RCB_REG(0x33e4), 0x1);
+	}
+
+	pch_iobp_update(0xCA000000, ~0UL, 0x00000009);
+
+	/* Set RCBA 0x2b1c[29]=1 if DSP disabled */
+	if (readl(RCB_REG(FD)) & PCH_DISABLE_ADSPD)
+		setbits_le32(RCB_REG(0x2b1c), 1 << 29);
+}
+
+static void pch_cg_init(struct udevice *dev)
+{
+	struct udevice *bus = pci_get_controller(dev);
+	u32 reg32;
+	u16 reg16;
+	ulong val;
+
+	/* DMI */
+	setbits_le32(RCB_REG(0x2234), 0xf);
+
+	dm_pci_read_config16(dev, GEN_PMCON_1, &reg16);
+	reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */
+	if (pch_is_wpt(dev))
+		reg16 &= ~(1 << 11);
+	else
+		reg16 |= 1 << 11;
+	reg16 |= 1 << 5 | 1 << 6 | 1 << 7 | 1 << 12;
+	reg16 |= 1 << 2; /* PCI CLKRUN# Enable */
+	dm_pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+	/*
+	 * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1
+	 * RCBA + 0x2614[23:16] = 0x20
+	 * RCBA + 0x2614[30:28] = 0x0
+	 * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b)
+	 */
+	clrsetbits_le32(RCB_REG(0x2614), 0x64ff0000, 0x0a206500);
+
+	/* Check for 0:2.0@0x08 >= 0x0b */
+	pci_bus_read_config(bus, PCI_BDF(0, 0x2, 0), 0x8, &val, PCI_SIZE_8);
+	if (pch_is_wpt(dev) || val >= 0x0b)
+		setbits_le32(RCB_REG(0x2614), 1 << 26);
+
+	setbits_le32(RCB_REG(0x900), 0x0000031f);
+
+	reg32 = readl(RCB_REG(CG));
+	if (readl(RCB_REG(0x3454)) & (1 << 4))
+		reg32 &= ~(1 << 29); /* LPC Dynamic */
+	else
+		reg32 |= (1 << 29); /* LPC Dynamic */
+	reg32 |= 1 << 31; /* LP LPC */
+	reg32 |= 1 << 30; /* LP BLA */
+	if (readl(RCB_REG(0x3454)) & (1 << 4))
+		reg32 &= ~(1 << 29);
+	else
+		reg32 |= 1 << 29;
+	reg32 |= 1 << 28; /* GPIO Dynamic */
+	reg32 |= 1 << 27; /* HPET Dynamic */
+	reg32 |= 1 << 26; /* Generic Platform Event Clock */
+	if (readl(RCB_REG(BUC)) & PCH_DISABLE_GBE)
+		reg32 |= 1 << 23; /* GbE Static */
+	if (readl(RCB_REG(FD)) & PCH_DISABLE_HD_AUDIO)
+		reg32 |= 1 << 21; /* HDA Static */
+	reg32 |= 1 << 22; /* HDA Dynamic */
+	writel(reg32, RCB_REG(CG));
+
+	/* PCH-LP LPC */
+	if (pch_is_wpt(dev))
+		clrsetbits_le32(RCB_REG(0x3434), 0x1f, 0x17);
+	else
+		setbits_le32(RCB_REG(0x3434), 0x7);
+
+	/* SPI */
+	setbits_le32(RCB_REG(0x38c0), 0x3c07);
+
+	pch_iobp_update(0xCE00C000, ~1UL, 0x00000000);
+}
+
+static void systemagent_init(void)
+{
+	/* Enable Power Aware Interrupt Routing */
+	clrsetbits_8(MCHBAR_REG(MCH_PAIR), 0x7, 0x4); /* Fixed Priority */
+
+	/*
+	 * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
+	 * that BIOS has initialized memory and power management
+	 */
+	setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3);
+	debug("Set BIOS_RESET_CPL\n");
+
+	/* Configure turbo power limits 1ms after reset complete bit */
+	mdelay(1);
+
+	cpu_set_power_limits(28);
+}
+
+static int broadwell_pch_init(struct udevice *dev)
+{
+	int ret;
+
+	/* Enable upper 128 bytes of CMOS */
+	setbits_le32(RCB_REG(RC), 1 << 2);
+
+	/*
+	 * TODO: TCO timer halt - this hangs
+	 * setio_16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT);
+	 */
+
+	/* Disable unused device (always) */
+	setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS);
+
+	pch_misc_init(dev);
+
+	/* Interrupt configuration */
+	pch_enable_ioapic();
+
+	/* Initialize power management */
+	ret = pch_power_options(dev);
+	if (ret)
+		return ret;
+	pch_pm_init(dev);
+	pch_cg_init(dev);
+	systemagent_init();
+
+	return 0;
+}
+
+static int broadwell_pch_probe(struct udevice *dev)
+{
+	if (!(gd->flags & GD_FLG_RELOC))
+		return broadwell_pch_early_init(dev);
+	else
+		return broadwell_pch_init(dev);
+}
+
+static int broadwell_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
+{
+	u32 rcba;
+
+	dm_pci_read_config32(dev, PCH_RCBA, &rcba);
+	/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
+	rcba = rcba & 0xffffc000;
+	*sbasep = rcba + 0x3800;
+
+	return 0;
+}
+
+static int broadwell_set_spi_protect(struct udevice *dev, bool protect)
+{
+	return lpc_set_spi_protect(dev, BIOS_CTRL, protect);
+}
+
+static int broadwell_get_gpio_base(struct udevice *dev, u32 *gbasep)
+{
+	dm_pci_read_config32(dev, GPIO_BASE, gbasep);
+	*gbasep &= PCI_BASE_ADDRESS_IO_MASK;
+
+	return 0;
+}
+
+static const struct pch_ops broadwell_pch_ops = {
+	.get_spi_base	= broadwell_pch_get_spi_base,
+	.set_spi_protect = broadwell_set_spi_protect,
+	.get_gpio_base	= broadwell_get_gpio_base,
+};
+
+static const struct udevice_id broadwell_pch_ids[] = {
+	{ .compatible = "intel,broadwell-pch" },
+	{ }
+};
+
+U_BOOT_DRIVER(broadwell_pch) = {
+	.name		= "broadwell_pch",
+	.id		= UCLASS_PCH,
+	.of_match	= broadwell_pch_ids,
+	.probe		= broadwell_pch_probe,
+	.ops		= &broadwell_pch_ops,
+};
diff --git a/arch/x86/cpu/broadwell/pinctrl_broadwell.c b/arch/x86/cpu/broadwell/pinctrl_broadwell.c
new file mode 100644
index 0000000..2a3fced
--- /dev/null
+++ b/arch/x86/cpu/broadwell/pinctrl_broadwell.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <pch.h>
+#include <pci.h>
+#include <asm/cpu.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/gpio.h>
+#include <dt-bindings/gpio/x86-gpio.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	MAX_GPIOS	= 95,
+};
+
+#define PIRQ_SHIFT	16
+#define CONF_MASK	0xffff
+
+struct pin_info {
+	int node;
+	int phandle;
+	bool mode_gpio;
+	bool dir_input;
+	bool invert;
+	bool trigger_level;
+	bool output_high;
+	bool sense_disable;
+	bool owner_gpio;
+	bool route_smi;
+	bool irq_enable;
+	bool reset_rsmrst;
+	bool pirq_apic_route;
+};
+
+static int broadwell_pinctrl_read_configs(struct udevice *dev,
+					  struct pin_info *conf, int max_pins)
+{
+	const void *blob = gd->fdt_blob;
+	int count = 0;
+	int node;
+
+	debug("%s: starting\n", __func__);
+	for (node = fdt_first_subnode(blob, dev->of_offset);
+	     node > 0;
+	     node = fdt_next_subnode(blob, node)) {
+		int phandle = fdt_get_phandle(blob, node);
+
+		if (!phandle)
+			continue;
+		if (count == max_pins)
+			return -ENOSPC;
+
+		/* We've found a new configuration */
+		memset(conf, '\0', sizeof(*conf));
+		conf->node = node;
+		conf->phandle = phandle;
+		conf->mode_gpio = fdtdec_get_bool(blob, node, "mode-gpio");
+		if (fdtdec_get_int(blob, node, "direction", -1) == PIN_INPUT)
+			conf->dir_input = true;
+		conf->invert = fdtdec_get_bool(blob, node, "invert");
+		if (fdtdec_get_int(blob, node, "trigger", -1) == TRIGGER_LEVEL)
+			conf->trigger_level = true;
+		if (fdtdec_get_int(blob, node, "output-value", -1) == 1)
+			conf->output_high = true;
+		conf->sense_disable = fdtdec_get_bool(blob, node,
+						      "sense-disable");
+		if (fdtdec_get_int(blob, node, "owner", -1) == OWNER_GPIO)
+			conf->owner_gpio = true;
+		if (fdtdec_get_int(blob, node, "route", -1) == ROUTE_SMI)
+			conf->route_smi = true;
+		conf->irq_enable = fdtdec_get_bool(blob, node, "irq-enable");
+		conf->reset_rsmrst = fdtdec_get_bool(blob, node,
+						     "reset-rsmrst");
+		if (fdtdec_get_int(blob, node, "pirq-apic", -1) ==
+				PIRQ_APIC_ROUTE)
+			conf->pirq_apic_route = true;
+		debug("config: phandle=%d\n", phandle);
+		count++;
+		conf++;
+	}
+	debug("%s: Found %d configurations\n", __func__, count);
+
+	return count;
+}
+
+static int broadwell_pinctrl_lookup_phandle(struct pin_info *conf,
+					    int conf_count, int phandle)
+{
+	int i;
+
+	for (i = 0; i < conf_count; i++) {
+		if (conf[i].phandle == phandle)
+			return i;
+	}
+
+	return -ENOENT;
+}
+
+static int broadwell_pinctrl_read_pins(struct udevice *dev,
+		struct pin_info *conf, int conf_count, int gpio_conf[],
+		int num_gpios)
+{
+	const void *blob = gd->fdt_blob;
+	int count = 0;
+	int node;
+
+	for (node = fdt_first_subnode(blob, dev->of_offset);
+	     node > 0;
+	     node = fdt_next_subnode(blob, node)) {
+		int len, i;
+		const u32 *prop = fdt_getprop(blob, node, "config", &len);
+
+		if (!prop)
+			continue;
+
+		/* There are three cells per pin */
+		count = len / (sizeof(u32) * 3);
+		debug("Found %d GPIOs to configure\n", count);
+		for (i = 0; i < count; i++) {
+			uint gpio = fdt32_to_cpu(prop[i * 3]);
+			uint phandle = fdt32_to_cpu(prop[i * 3 + 1]);
+			int val;
+
+			if (gpio >= num_gpios) {
+				debug("%s: GPIO %d out of range\n", __func__,
+				      gpio);
+				return -EDOM;
+			}
+			val = broadwell_pinctrl_lookup_phandle(conf, conf_count,
+							       phandle);
+			if (val < 0) {
+				debug("%s: Cannot find phandle %d\n", __func__,
+				      phandle);
+				return -EINVAL;
+			}
+			gpio_conf[gpio] = val |
+				fdt32_to_cpu(prop[i * 3 + 2]) << PIRQ_SHIFT;
+		}
+	}
+
+	return 0;
+}
+
+static void broadwell_pinctrl_commit(struct pch_lp_gpio_regs *regs,
+				     struct pin_info *pin_info,
+				     int gpio_conf[], int count)
+{
+	u32 owner_gpio[GPIO_BANKS] = {0};
+	u32 route_smi[GPIO_BANKS] = {0};
+	u32 irq_enable[GPIO_BANKS] = {0};
+	u32 reset_rsmrst[GPIO_BANKS] = {0};
+	u32 pirq2apic = 0;
+	int set, bit, gpio = 0;
+
+	for (gpio = 0; gpio < MAX_GPIOS; gpio++) {
+		int confnum = gpio_conf[gpio] & CONF_MASK;
+		struct pin_info *pin = &pin_info[confnum];
+		u32 val;
+
+		val = pin->mode_gpio << CONFA_MODE_SHIFT |
+			pin->dir_input << CONFA_DIR_SHIFT |
+			pin->invert << CONFA_INVERT_SHIFT |
+			pin->trigger_level << CONFA_TRIGGER_SHIFT |
+			pin->output_high << CONFA_OUTPUT_SHIFT;
+		outl(val, &regs->config[gpio].conf_a);
+		outl(pin->sense_disable << CONFB_SENSE_SHIFT,
+		     &regs->config[gpio].conf_b);
+
+		/* Determine set and bit based on GPIO number */
+		set = gpio / GPIO_PER_BANK;
+		bit = gpio % GPIO_PER_BANK;
+
+		/* Apply settings to set specific bits */
+		owner_gpio[set] |= pin->owner_gpio << bit;
+		route_smi[set] |= pin->route_smi << bit;
+		irq_enable[set] |= pin->irq_enable << bit;
+		reset_rsmrst[set] |= pin->reset_rsmrst << bit;
+
+		/* PIRQ to IO-APIC map */
+		if (pin->pirq_apic_route)
+			pirq2apic |= gpio_conf[gpio] >> PIRQ_SHIFT;
+		debug("gpio %d: conf %d, mode_gpio %d, dir_input %d, output_high %d\n",
+		      gpio, confnum, pin->mode_gpio, pin->dir_input,
+		      pin->output_high);
+	}
+
+	for (set = 0; set < GPIO_BANKS; set++) {
+		outl(owner_gpio[set], &regs->own[set]);
+		outl(route_smi[set], &regs->gpi_route[set]);
+		outl(irq_enable[set], &regs->gpi_ie[set]);
+		outl(reset_rsmrst[set], &regs->rst_sel[set]);
+	}
+
+	outl(pirq2apic, &regs->pirq_to_ioxapic);
+}
+
+static int broadwell_pinctrl_probe(struct udevice *dev)
+{
+	struct pch_lp_gpio_regs *regs;
+	struct pin_info conf[12];
+	int gpio_conf[MAX_GPIOS];
+	struct udevice *pch;
+	int conf_count;
+	u32 gpiobase;
+	int ret;
+
+	ret = uclass_first_device(UCLASS_PCH, &pch);
+	if (ret)
+		return ret;
+	if (!pch)
+		return -ENODEV;
+	debug("%s: start\n", __func__);
+
+	/* Only init once, before relocation */
+	if (gd->flags & GD_FLG_RELOC)
+		return 0;
+
+	/*
+	 * Get the memory/io base address to configure every pins.
+	 * IOBASE is used to configure the mode/pads
+	 * GPIOBASE is used to configure the direction and default value
+	 */
+	ret = pch_get_gpio_base(pch, &gpiobase);
+	if (ret) {
+		debug("%s: invalid GPIOBASE address (%08x)\n", __func__,
+		      gpiobase);
+		return -EINVAL;
+	}
+
+	conf_count = broadwell_pinctrl_read_configs(dev, conf,
+						    ARRAY_SIZE(conf));
+	if (conf_count < 0) {
+		debug("%s: Cannot read configs: err=%d\n", __func__, ret);
+		return conf_count;
+	}
+
+	/*
+	 * Assume that pin settings are provided for every pin. Pins not
+	 * mentioned will get the first config mentioned in the list.
+	 */
+	ret = broadwell_pinctrl_read_pins(dev, conf, conf_count, gpio_conf,
+					  MAX_GPIOS);
+	if (ret) {
+		debug("%s: Cannot read pin settings: err=%d\n", __func__, ret);
+		return ret;
+	}
+
+	regs = (struct pch_lp_gpio_regs *)gpiobase;
+	broadwell_pinctrl_commit(regs, conf, gpio_conf, ARRAY_SIZE(conf));
+
+	debug("%s: done\n", __func__);
+
+	return 0;
+}
+
+static const struct udevice_id broadwell_pinctrl_match[] = {
+	{ .compatible = "intel,x86-broadwell-pinctrl",
+		.data = X86_SYSCON_PINCONF },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(broadwell_pinctrl) = {
+	.name = "broadwell_pinctrl",
+	.id = UCLASS_SYSCON,
+	.of_match = broadwell_pinctrl_match,
+	.probe = broadwell_pinctrl_probe,
+};
diff --git a/arch/x86/cpu/broadwell/power_state.c b/arch/x86/cpu/broadwell/power_state.c
new file mode 100644
index 0000000..2b9a6bf
--- /dev/null
+++ b/arch/x86/cpu/broadwell/power_state.c
@@ -0,0 +1,90 @@
+/*
+ * From coreboot src/soc/intel/broadwell/romstage/power_state.c
+ *
+ * Copyright (C) 2016 Google, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/intel_regs.h>
+#include <asm/arch/iomap.h>
+#include <asm/arch/lpc.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/pm.h>
+
+/* Return 0, 3, or 5 to indicate the previous sleep state. */
+static int prev_sleep_state(struct chipset_power_state *ps)
+{
+	/* Default to S0. */
+	int prev_sleep_state = SLEEP_STATE_S0;
+
+	if (ps->pm1_sts & WAK_STS) {
+		switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
+#if CONFIG_HAVE_ACPI_RESUME
+		case SLP_TYP_S3:
+			prev_sleep_state = SLEEP_STATE_S3;
+			break;
+#endif
+		case SLP_TYP_S5:
+			prev_sleep_state = SLEEP_STATE_S5;
+			break;
+		}
+		/* Clear SLP_TYP. */
+		outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
+	}
+
+	if (ps->gen_pmcon3 & (PWR_FLR | SUS_PWR_FLR))
+		prev_sleep_state = SLEEP_STATE_S5;
+
+	return prev_sleep_state;
+}
+
+static void dump_power_state(struct chipset_power_state *ps)
+{
+	debug("PM1_STS:   %04x\n", ps->pm1_sts);
+	debug("PM1_EN:    %04x\n", ps->pm1_en);
+	debug("PM1_CNT:   %08x\n", ps->pm1_cnt);
+	debug("TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
+
+	debug("GPE0_STS:  %08x %08x %08x %08x\n",
+	      ps->gpe0_sts[0], ps->gpe0_sts[1],
+	      ps->gpe0_sts[2], ps->gpe0_sts[3]);
+	debug("GPE0_EN:   %08x %08x %08x %08x\n",
+	      ps->gpe0_en[0], ps->gpe0_en[1],
+	      ps->gpe0_en[2], ps->gpe0_en[3]);
+
+	debug("GEN_PMCON: %04x %04x %04x\n",
+	      ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
+
+	debug("Previous Sleep State: S%d\n",
+	      ps->prev_sleep_state);
+}
+
+/* Fill power state structure from ACPI PM registers */
+void power_state_get(struct udevice *pch_dev, struct chipset_power_state *ps)
+{
+	ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
+	ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
+	ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
+	ps->tco1_sts = inw(ACPI_BASE_ADDRESS + TCO1_STS);
+	ps->tco2_sts = inw(ACPI_BASE_ADDRESS + TCO2_STS);
+	ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0));
+	ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1));
+	ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2));
+	ps->gpe0_sts[3] = inl(ACPI_BASE_ADDRESS + GPE0_STS(3));
+	ps->gpe0_en[0] = inl(ACPI_BASE_ADDRESS + GPE0_EN(0));
+	ps->gpe0_en[1] = inl(ACPI_BASE_ADDRESS + GPE0_EN(1));
+	ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2));
+	ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3));
+
+	dm_pci_read_config16(pch_dev, GEN_PMCON_1, &ps->gen_pmcon1);
+	dm_pci_read_config16(pch_dev, GEN_PMCON_2, &ps->gen_pmcon2);
+	dm_pci_read_config16(pch_dev, GEN_PMCON_3, &ps->gen_pmcon3);
+
+	ps->prev_sleep_state = prev_sleep_state(ps);
+
+	dump_power_state(ps);
+}
diff --git a/arch/x86/cpu/broadwell/refcode.c b/arch/x86/cpu/broadwell/refcode.c
new file mode 100644
index 0000000..436c6c4
--- /dev/null
+++ b/arch/x86/cpu/broadwell/refcode.c
@@ -0,0 +1,113 @@
+/*
+ * Read a coreboot rmodule and execute it.
+ * The rmodule_header struct is from coreboot.
+ *
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/pei_data.h>
+
+#define RMODULE_MAGIC		0xf8fe
+#define RMODULE_VERSION_1	1
+
+/*
+ * All fields with '_offset' in the name are byte offsets into the flat blob.
+ * The linker and the linker script takes are of assigning the values.
+ */
+struct rmodule_header {
+	uint16_t magic;
+	uint8_t version;
+	uint8_t type;
+	/* The payload represents the program's loadable code and data */
+	uint32_t payload_begin_offset;
+	uint32_t payload_end_offset;
+	/* Begin and of relocation information about the program module */
+	uint32_t relocations_begin_offset;
+	uint32_t relocations_end_offset;
+	/*
+	 * The starting address of the linked program. This address is vital
+	 * for determining relocation offsets as the relocation info and other
+	 * symbols (bss, entry point) need this value as a basis to calculate
+	 * the offsets.
+	 */
+	uint32_t module_link_start_address;
+	/*
+	 * The module_program_size is the size of memory used while running
+	 * the program. The program is assumed to consume a contiguous amount
+	 * of memory
+	 */
+	uint32_t module_program_size;
+	/* This is program's execution entry point */
+	uint32_t module_entry_point;
+	/*
+	 * Optional parameter structure that can be used to pass data into
+	 * the module
+	 */
+	uint32_t parameters_begin;
+	uint32_t parameters_end;
+	/* BSS section information so the loader can clear the bss */
+	uint32_t bss_begin;
+	uint32_t bss_end;
+	/* Add some room for growth */
+	uint32_t padding[4];
+} __packed;
+
+int cpu_run_reference_code(void)
+{
+	struct pei_data _pei_data __aligned(8);
+	struct pei_data *pei_data = &_pei_data;
+	asmlinkage int (*func)(void *);
+	struct rmodule_header *hdr;
+	char *src, *dest;
+	int ret, dummy;
+	int size;
+
+	hdr = (struct rmodule_header *)CONFIG_X86_REFCODE_ADDR;
+	debug("Extracting code from rmodule at %p\n", hdr);
+	if (hdr->magic != RMODULE_MAGIC) {
+		debug("Invalid rmodule magic\n");
+		return -EINVAL;
+	}
+	if (hdr->module_link_start_address != 0) {
+		debug("Link start address must be 0\n");
+		return -EPERM;
+	}
+	if (hdr->module_entry_point != 0) {
+		debug("Entry point must be 0\n");
+		return -EPERM;
+	}
+
+	memset(pei_data, '\0', sizeof(struct pei_data));
+	broadwell_fill_pei_data(pei_data);
+	mainboard_fill_pei_data(pei_data);
+	pei_data->saved_data = (void *)&dummy;
+
+	src = (char *)hdr + hdr->payload_begin_offset;
+	dest = (char *)CONFIG_X86_REFCODE_RUN_ADDR;
+
+	size = hdr->payload_end_offset - hdr->payload_begin_offset;
+	debug("Copying refcode from %p to %p, size %x\n", src, dest, size);
+	memcpy(dest, src, size);
+
+	size = hdr->bss_end - hdr->bss_begin;
+	debug("Zeroing BSS at %p, size %x\n", dest + hdr->bss_begin, size);
+	memset(dest + hdr->bss_begin, '\0', size);
+
+	func = (asmlinkage int (*)(void *))dest;
+	debug("Running reference code at %p\n", func);
+#ifdef DEBUG
+	print_buffer(CONFIG_X86_REFCODE_RUN_ADDR, (void *)func, 1, 0x40, 0);
+#endif
+	ret = func(pei_data);
+	if (ret != 0) {
+		debug("Reference code returned %d\n", ret);
+		return -EL2HLT;
+	}
+	debug("Refereence code completed\n");
+
+	return 0;
+}
diff --git a/arch/x86/cpu/broadwell/sata.c b/arch/x86/cpu/broadwell/sata.c
new file mode 100644
index 0000000..dfb8486
--- /dev/null
+++ b/arch/x86/cpu/broadwell/sata.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * From coreboot src/soc/intel/broadwell/sata.c
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/intel_regs.h>
+#include <asm/lpc_common.h>
+#include <asm/pch_common.h>
+#include <asm/pch_common.h>
+#include <asm/arch/pch.h>
+
+struct sata_platdata {
+	int port_map;
+	uint port0_gen3_tx;
+	uint port1_gen3_tx;
+	uint port0_gen3_dtle;
+	uint port1_gen3_dtle;
+
+	/*
+	 * SATA DEVSLP Mux
+	 * 0 = port 0 DEVSLP on DEVSLP0/GPIO33
+	 * 1 = port 3 DEVSLP on DEVSLP0/GPIO33
+	 */
+	int devslp_mux;
+
+	/*
+	 * DEVSLP Disable
+	 * 0: DEVSLP is enabled
+	 * 1: DEVSLP is disabled
+	 */
+	int devslp_disable;
+};
+
+static void broadwell_sata_init(struct udevice *dev)
+{
+	struct sata_platdata *plat = dev_get_platdata(dev);
+	u32 reg32;
+	u8 *abar;
+	u16 reg16;
+	int port;
+
+	debug("SATA: Initializing controller in AHCI mode.\n");
+
+	/* Set timings */
+	dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE);
+	dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
+
+	/* for AHCI, Port Enable is managed in memory mapped space */
+	dm_pci_read_config16(dev, 0x92, &reg16);
+	reg16 &= ~0xf;
+	reg16 |= 0x8000 | plat->port_map;
+	dm_pci_write_config16(dev, 0x92, reg16);
+	udelay(2);
+
+	/* Setup register 98h */
+	dm_pci_read_config32(dev, 0x98, &reg32);
+	reg32 &= ~((1 << 31) | (1 << 30));
+	reg32 |= 1 << 23;
+	reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */
+	dm_pci_write_config32(dev, 0x98, reg32);
+
+	/* Setup register 9Ch */
+	reg16 = 0;           /* Disable alternate ID */
+	reg16 = 1 << 5;      /* BWG step 12 */
+	dm_pci_write_config16(dev, 0x9c, reg16);
+
+	/* SATA Initialization register */
+	reg32 = 0x183;
+	reg32 |= (plat->port_map ^ 0xf) << 24;
+	reg32 |= (plat->devslp_mux & 1) << 15;
+	dm_pci_write_config32(dev, 0x94, reg32);
+
+	/* Initialize AHCI memory-mapped space */
+	dm_pci_read_config32(dev, PCI_BASE_ADDRESS_5, &reg32);
+	abar = (u8 *)reg32;
+	debug("ABAR: %p\n", abar);
+
+	/* CAP (HBA Capabilities) : enable power management */
+	clrsetbits_le32(abar + 0x00, 0x00020060 /* SXS+EMS+PMS */,
+			0x0c006000 /* PSC+SSC+SALP+SSS */ |
+			1 << 18); /* SAM: SATA AHCI MODE ONLY */
+
+	/* PI (Ports implemented) */
+	writel(plat->port_map, abar + 0x0c);
+	(void) readl(abar + 0x0c); /* Read back 1 */
+	(void) readl(abar + 0x0c); /* Read back 2 */
+
+	/* CAP2 (HBA Capabilities Extended)*/
+	if (plat->devslp_disable) {
+		clrbits_le32(abar + 0x24, 1 << 3);
+	} else {
+		/* Enable DEVSLP */
+		setbits_le32(abar + 0x24, 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2);
+
+		for (port = 0; port < 4; port++) {
+			if (!(plat->port_map & (1 << port)))
+				continue;
+			/* DEVSLP DSP */
+			setbits_le32(abar + 0x144 + (0x80 * port), 1 << 1);
+		}
+	}
+
+	/* Static Power Gating for unused ports */
+	reg32 = readl(RCB_REG(0x3a84));
+	/* Port 3 and 2 disabled */
+	if ((plat->port_map & ((1 << 3)|(1 << 2))) == 0)
+		reg32 |= (1 << 24) | (1 << 26);
+	/* Port 1 and 0 disabled */
+	if ((plat->port_map & ((1 << 1)|(1 << 0))) == 0)
+		reg32 |= (1 << 20) | (1 << 18);
+	writel(reg32, RCB_REG(0x3a84));
+
+	/* Set Gen3 Transmitter settings if needed */
+	if (plat->port0_gen3_tx)
+		pch_iobp_update(SATA_IOBP_SP0_SECRT88,
+				~(SATA_SECRT88_VADJ_MASK <<
+				  SATA_SECRT88_VADJ_SHIFT),
+				(plat->port0_gen3_tx &
+				 SATA_SECRT88_VADJ_MASK)
+				<< SATA_SECRT88_VADJ_SHIFT);
+
+	if (plat->port1_gen3_tx)
+		pch_iobp_update(SATA_IOBP_SP1_SECRT88,
+				~(SATA_SECRT88_VADJ_MASK <<
+				  SATA_SECRT88_VADJ_SHIFT),
+				(plat->port1_gen3_tx &
+				 SATA_SECRT88_VADJ_MASK)
+				<< SATA_SECRT88_VADJ_SHIFT);
+
+	/* Set Gen3 DTLE DATA / EDGE registers if needed */
+	if (plat->port0_gen3_dtle) {
+		pch_iobp_update(SATA_IOBP_SP0DTLE_DATA,
+				~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT),
+				(plat->port0_gen3_dtle & SATA_DTLE_MASK)
+				<< SATA_DTLE_DATA_SHIFT);
+
+		pch_iobp_update(SATA_IOBP_SP0DTLE_EDGE,
+				~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT),
+				(plat->port0_gen3_dtle & SATA_DTLE_MASK)
+				<< SATA_DTLE_EDGE_SHIFT);
+	}
+
+	if (plat->port1_gen3_dtle) {
+		pch_iobp_update(SATA_IOBP_SP1DTLE_DATA,
+				~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT),
+				(plat->port1_gen3_dtle & SATA_DTLE_MASK)
+				<< SATA_DTLE_DATA_SHIFT);
+
+		pch_iobp_update(SATA_IOBP_SP1DTLE_EDGE,
+				~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT),
+				(plat->port1_gen3_dtle & SATA_DTLE_MASK)
+				<< SATA_DTLE_EDGE_SHIFT);
+	}
+
+	/*
+	 * Additional Programming Requirements for Power Optimizer
+	 */
+
+	/* Step 1 */
+	pch_common_sir_write(dev, 0x64, 0x883c9003);
+
+	/* Step 2: SIR 68h[15:0] = 880Ah */
+	reg32 = pch_common_sir_read(dev, 0x68);
+	reg32 &= 0xffff0000;
+	reg32 |= 0x880a;
+	pch_common_sir_write(dev, 0x68, reg32);
+
+	/* Step 3: SIR 60h[3] = 1 */
+	reg32 = pch_common_sir_read(dev, 0x60);
+	reg32 |= (1 << 3);
+	pch_common_sir_write(dev, 0x60, reg32);
+
+	/* Step 4: SIR 60h[0] = 1 */
+	reg32 = pch_common_sir_read(dev, 0x60);
+	reg32 |= (1 << 0);
+	pch_common_sir_write(dev, 0x60, reg32);
+
+	/* Step 5: SIR 60h[1] = 1 */
+	reg32 = pch_common_sir_read(dev, 0x60);
+	reg32 |= (1 << 1);
+	pch_common_sir_write(dev, 0x60, reg32);
+
+	/* Clock Gating */
+	pch_common_sir_write(dev, 0x70, 0x3f00bf1f);
+	pch_common_sir_write(dev, 0x54, 0xcf000f0f);
+	pch_common_sir_write(dev, 0x58, 0x00190000);
+	clrsetbits_le32(RCB_REG(0x333c), 0x00300000, 0x00c00000);
+
+	dm_pci_read_config32(dev, 0x300, &reg32);
+	reg32 |= 1 << 17 | 1 << 16 | 1 << 19;
+	reg32 |= 1 << 31 | 1 << 30 | 1 << 29;
+	dm_pci_write_config32(dev, 0x300, reg32);
+
+	dm_pci_read_config32(dev, 0x98, &reg32);
+	reg32 |= 1 << 29;
+	dm_pci_write_config32(dev, 0x98, reg32);
+
+	/* Register Lock */
+	dm_pci_read_config32(dev, 0x9c, &reg32);
+	reg32 |= 1 << 31;
+	dm_pci_write_config32(dev, 0x9c, reg32);
+}
+
+static int broadwell_sata_enable(struct udevice *dev)
+{
+	struct sata_platdata *plat = dev_get_platdata(dev);
+	struct gpio_desc desc;
+	u16 map;
+	int ret;
+
+	/*
+	 * Set SATA controller mode early so the resource allocator can
+	 * properly assign IO/Memory resources for the controller.
+	 */
+	map = 0x0060;
+
+	map |= (plat->port_map ^ 0x3f) << 8;
+	dm_pci_write_config16(dev, 0x90, map);
+
+	ret = gpio_request_by_name(dev, "reset-gpio", 0, &desc, GPIOD_IS_OUT);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int broadwell_sata_ofdata_to_platdata(struct udevice *dev)
+{
+	struct sata_platdata *plat = dev_get_platdata(dev);
+	const void *blob = gd->fdt_blob;
+	int node = dev->of_offset;
+
+	plat->port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
+	plat->port0_gen3_tx = fdtdec_get_int(blob, node,
+					"intel,sata-port0-gen3-tx", 0);
+
+	return 0;
+}
+
+static int broadwell_sata_probe(struct udevice *dev)
+{
+	if (!(gd->flags & GD_FLG_RELOC))
+		return broadwell_sata_enable(dev);
+	else
+		broadwell_sata_init(dev);
+
+	return 0;
+}
+
+static const struct udevice_id broadwell_ahci_ids[] = {
+	{ .compatible = "intel,wildcatpoint-ahci" },
+	{ }
+};
+
+U_BOOT_DRIVER(ahci_broadwell_drv) = {
+	.name		= "ahci_broadwell",
+	.id		= UCLASS_DISK,
+	.of_match	= broadwell_ahci_ids,
+	.ofdata_to_platdata	= broadwell_sata_ofdata_to_platdata,
+	.probe		= broadwell_sata_probe,
+	.platdata_auto_alloc_size	 = sizeof(struct sata_platdata),
+};
diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c
new file mode 100644
index 0000000..4bf5d15
--- /dev/null
+++ b/arch/x86/cpu/broadwell/sdram.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * From coreboot src/soc/intel/broadwell/romstage/raminit.c
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pci.h>
+#include <syscon.h>
+#include <asm/cpu.h>
+#include <asm/io.h>
+#include <asm/lpc_common.h>
+#include <asm/mrccache.h>
+#include <asm/mrc_common.h>
+#include <asm/mtrr.h>
+#include <asm/pci.h>
+#include <asm/arch/iomap.h>
+#include <asm/arch/me.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/pei_data.h>
+#include <asm/arch/pm.h>
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+	return mrc_common_board_get_usable_ram_top(total_size);
+}
+
+void dram_init_banksize(void)
+{
+	mrc_common_dram_init_banksize();
+}
+
+void broadwell_fill_pei_data(struct pei_data *pei_data)
+{
+	pei_data->pei_version = PEI_VERSION;
+	pei_data->board_type = BOARD_TYPE_ULT;
+	pei_data->pciexbar = MCFG_BASE_ADDRESS;
+	pei_data->smbusbar = SMBUS_BASE_ADDRESS;
+	pei_data->ehcibar = EARLY_EHCI_BAR;
+	pei_data->xhcibar = EARLY_XHCI_BAR;
+	pei_data->gttbar = EARLY_GTT_BAR;
+	pei_data->pmbase = ACPI_BASE_ADDRESS;
+	pei_data->gpiobase = GPIO_BASE_ADDRESS;
+	pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE;
+	pei_data->temp_mmio_base = EARLY_TEMP_MMIO;
+	pei_data->tx_byte = sdram_console_tx_byte;
+	pei_data->ddr_refresh_2x = 1;
+}
+
+static inline void pei_data_usb2_port(struct pei_data *pei_data, int port,
+				      uint16_t length, uint8_t enable,
+				      uint8_t oc_pin, uint8_t location)
+{
+	pei_data->usb2_ports[port].length   = length;
+	pei_data->usb2_ports[port].enable   = enable;
+	pei_data->usb2_ports[port].oc_pin   = oc_pin;
+	pei_data->usb2_ports[port].location = location;
+}
+
+static inline void pei_data_usb3_port(struct pei_data *pei_data, int port,
+				      uint8_t enable, uint8_t oc_pin,
+				      uint8_t fixed_eq)
+{
+	pei_data->usb3_ports[port].enable   = enable;
+	pei_data->usb3_ports[port].oc_pin   = oc_pin;
+	pei_data->usb3_ports[port].fixed_eq = fixed_eq;
+}
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+	/* DQ byte map for Samus board */
+	const u8 dq_map[2][6][2] = {
+		{ { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
+		  { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
+		{ { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
+		  { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } };
+	/* DQS CPU<>DRAM map for Samus board */
+	const u8 dqs_map[2][8] = {
+		{ 2, 0, 1, 3, 6, 4, 7, 5 },
+		{ 2, 1, 0, 3, 6, 5, 4, 7 } };
+
+	pei_data->ec_present = 1;
+
+	/* One installed DIMM per channel */
+	pei_data->dimm_channel0_disabled = 2;
+	pei_data->dimm_channel1_disabled = 2;
+
+	memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
+	memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
+
+	/* P0: HOST PORT */
+	pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0,
+			   USB_PORT_BACK_PANEL);
+	/* P1: HOST PORT */
+	pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1,
+			   USB_PORT_BACK_PANEL);
+	/* P2: RAIDEN */
+	pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_BACK_PANEL);
+	/* P3: SD CARD */
+	pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_INTERNAL);
+	/* P4: RAIDEN */
+	pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_BACK_PANEL);
+	/* P5: WWAN (Disabled) */
+	pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
+			   USB_PORT_SKIP);
+	/* P6: CAMERA */
+	pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_INTERNAL);
+	/* P7: BT */
+	pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_INTERNAL);
+
+	/* P1: HOST PORT */
+	pei_data_usb3_port(pei_data, 0, 1, 0, 0);
+	/* P2: HOST PORT */
+	pei_data_usb3_port(pei_data, 1, 1, 1, 0);
+	/* P3: RAIDEN */
+	pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0);
+	/* P4: RAIDEN */
+	pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0);
+}
+
+static unsigned long get_top_of_ram(struct udevice *dev)
+{
+	/*
+	 * Base of DPR is top of usable DRAM below 4GiB. The register has
+	 * 1 MiB alignment and reports the TOP of the range, the base
+	 * must be calculated from the size in MiB in bits 11:4.
+	 */
+	u32 dpr, tom;
+
+	dm_pci_read_config32(dev, DPR, &dpr);
+	tom = dpr & ~((1 << 20) - 1);
+
+	debug("dpt %08x tom %08x\n", dpr, tom);
+	/* Subtract DMA Protected Range size if enabled */
+	if (dpr & DPR_EPM)
+		tom -= (dpr & DPR_SIZE_MASK) << 16;
+
+	return (unsigned long)tom;
+}
+
+/**
+ * sdram_find() - Find available memory
+ *
+ * This is a bit complicated since on x86 there are system memory holes all
+ * over the place. We create a list of available memory blocks
+ *
+ * @dev:	Northbridge device
+ */
+static int sdram_find(struct udevice *dev)
+{
+	struct memory_info *info = &gd->arch.meminfo;
+	ulong top_of_ram;
+
+	top_of_ram = get_top_of_ram(dev);
+	mrc_add_memory_area(info, 0, top_of_ram);
+
+	/* Add MTRRs for memory */
+	mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30);
+
+	return 0;
+}
+
+static int prepare_mrc_cache(struct pei_data *pei_data)
+{
+	struct mrc_data_container *mrc_cache;
+	struct mrc_region entry;
+	int ret;
+
+	ret = mrccache_get_region(NULL, &entry);
+	if (ret)
+		return ret;
+	mrc_cache = mrccache_find_current(&entry);
+	if (!mrc_cache)
+		return -ENOENT;
+
+	pei_data->saved_data = mrc_cache->data;
+	pei_data->saved_data_size = mrc_cache->data_size;
+	debug("%s: at %p, size %x checksum %04x\n", __func__,
+	      pei_data->saved_data, pei_data->saved_data_size,
+	      mrc_cache->checksum);
+
+	return 0;
+}
+
+int reserve_arch(void)
+{
+	return mrccache_reserve();
+}
+
+int dram_init(void)
+{
+	struct pei_data _pei_data __aligned(8);
+	struct pei_data *pei_data = &_pei_data;
+	struct udevice *dev, *me_dev, *pch_dev;
+	struct chipset_power_state ps;
+	const void *spd_data;
+	int ret, size;
+
+	memset(pei_data, '\0', sizeof(struct pei_data));
+
+	/* Print ME state before MRC */
+	ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
+	if (ret)
+		return ret;
+	intel_me_status(me_dev);
+
+	/* Save ME HSIO version */
+	ret = uclass_first_device(UCLASS_PCH, &pch_dev);
+	if (ret)
+		return ret;
+	if (!pch_dev)
+		return -ENODEV;
+	power_state_get(pch_dev, &ps);
+
+	intel_me_hsio_version(me_dev, &ps.hsio_version, &ps.hsio_checksum);
+
+	broadwell_fill_pei_data(pei_data);
+	mainboard_fill_pei_data(pei_data);
+
+	ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
+	if (ret)
+		return ret;
+	if (!dev)
+		return -ENODEV;
+	size = 256;
+	ret = mrc_locate_spd(dev, size, &spd_data);
+	if (ret)
+		return ret;
+	memcpy(pei_data->spd_data[0][0], spd_data, size);
+	memcpy(pei_data->spd_data[1][0], spd_data, size);
+
+	ret = prepare_mrc_cache(pei_data);
+	if (ret)
+		debug("prepare_mrc_cache failed: %d\n", ret);
+
+	debug("PEI version %#x\n", pei_data->pei_version);
+	ret = mrc_common_init(dev, pei_data, true);
+	if (ret)
+		return ret;
+	debug("Memory init done\n");
+
+	ret = sdram_find(dev);
+	if (ret)
+		return ret;
+	gd->ram_size = gd->arch.meminfo.total_32bit_memory;
+	debug("RAM size %llx\n", (unsigned long long)gd->ram_size);
+
+	debug("MRC output data length %#x at %p\n", pei_data->data_to_save_size,
+	      pei_data->data_to_save);
+	/* S3 resume: don't save scrambler seed or MRC data */
+	if (pei_data->boot_mode != SLEEP_STATE_S3) {
+		/*
+		 * This will be copied to SDRAM in reserve_arch(), then written
+		 * to SPI flash in mrccache_save()
+		 */
+		gd->arch.mrc_output = (char *)pei_data->data_to_save;
+		gd->arch.mrc_output_len = pei_data->data_to_save_size;
+	}
+	gd->arch.pei_meminfo = pei_data->meminfo;
+
+	return 0;
+}
+
+/* Use this hook to save our SDRAM parameters */
+int misc_init_r(void)
+{
+	int ret;
+
+	ret = mrccache_save();
+	if (ret)
+		printf("Unable to save MRC data: %d\n", ret);
+	else
+		debug("Saved MRC cache data\n");
+
+	return 0;
+}
+
+void board_debug_uart_init(void)
+{
+	struct udevice *bus = NULL;
+
+	/* com1 / com2 decode range */
+	pci_x86_write_config(bus, PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16);
+
+	pci_x86_write_config(bus, PCH_DEV_LPC, LPC_EN, COMA_LPC_EN,
+			     PCI_SIZE_16);
+}
+
+static const struct udevice_id broadwell_syscon_ids[] = {
+	{ .compatible = "intel,me", .data = X86_SYSCON_ME },
+	{ .compatible = "intel,gma", .data = X86_SYSCON_GMA },
+	{ }
+};
+
+U_BOOT_DRIVER(syscon_intel_me) = {
+	.name = "intel_me_syscon",
+	.id = UCLASS_SYSCON,
+	.of_match = broadwell_syscon_ids,
+};
diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c
index 32f595d..7115e7a 100644
--- a/arch/x86/cpu/coreboot/sdram.c
+++ b/arch/x86/cpu/coreboot/sdram.c
@@ -9,7 +9,6 @@
 #include <common.h>
 #include <asm/e820.h>
 #include <asm/arch/sysinfo.h>
-#include <asm/arch/tables.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c
index 2b12b19..543e51d 100644
--- a/arch/x86/cpu/coreboot/tables.c
+++ b/arch/x86/cpu/coreboot/tables.c
@@ -10,7 +10,6 @@
 #include <common.h>
 #include <net.h>
 #include <asm/arch/sysinfo.h>
-#include <asm/arch/tables.h>
 
 /*
  * This needs to be in the .data section so that it's copied over during
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 6c3a748..233a6c8 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -27,6 +27,7 @@
 #include <asm/control_regs.h>
 #include <asm/cpu.h>
 #include <asm/lapic.h>
+#include <asm/microcode.h>
 #include <asm/mp.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>
@@ -71,7 +72,7 @@
  * List of cpu vendor strings along with their normalized
  * id values.
  */
-static struct {
+static const struct {
 	int vendor;
 	const char *name;
 } x86_vendors[] = {
@@ -333,6 +334,16 @@
 		c->x86_model += ((tfms >> 16) & 0xF) << 4;
 }
 
+u32 cpu_get_family_model(void)
+{
+	return gd->arch.x86_device & 0x0fff0ff0;
+}
+
+u32 cpu_get_stepping(void)
+{
+	return gd->arch.x86_mask;
+}
+
 int x86_cpu_init_f(void)
 {
 	const u32 em_rst = ~X86_CR0_EM;
@@ -459,14 +470,14 @@
 __weak void reset_cpu(ulong addr)
 {
 	/* Do a hard reset through the chipset's reset control register */
-	outb(SYS_RST | RST_CPU, PORT_RESET);
+	outb(SYS_RST | RST_CPU, IO_PORT_RESET);
 	for (;;)
 		cpu_hlt();
 }
 
 void x86_full_reset(void)
 {
-	outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET);
+	outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET);
 }
 
 int dcache_status(void)
diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile
new file mode 100644
index 0000000..804c539
--- /dev/null
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -0,0 +1,16 @@
+#
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_HAVE_MRC) += car.o
+obj-y += cpu.o
+obj-y += lpc.o
+obj-$(CONFIG_HAVE_MRC) += me_status.o
+ifndef CONFIG_TARGET_EFI
+obj-y += microcode.o
+endif
+obj-y += pch.o
+obj-$(CONFIG_HAVE_MRC) += report_platform.o
+obj-$(CONFIG_HAVE_MRC) += mrc.o
diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/intel_common/car.S
similarity index 98%
rename from arch/x86/cpu/ivybridge/car.S
rename to arch/x86/cpu/intel_common/car.S
index 1defabf..6e0db96 100644
--- a/arch/x86/cpu/ivybridge/car.S
+++ b/arch/x86/cpu/intel_common/car.S
@@ -12,12 +12,12 @@
  */
 
 #include <common.h>
+#include <asm/microcode.h>
 #include <asm/msr-index.h>
 #include <asm/mtrr.h>
 #include <asm/post.h>
 #include <asm/processor.h>
 #include <asm/processor-flags.h>
-#include <asm/arch/microcode.h>
 
 #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg))
 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1)
@@ -237,5 +237,7 @@
 	.align 4
 _dt_ucode_base_size:
 	/* These next two fields are filled in by ifdtool */
+.globl ucode_base
+ucode_base:	/* Declared in microcode.h */
 	.long	0			/* microcode base */
 	.long	0			/* microcode size */
diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c
new file mode 100644
index 0000000..93e4505
--- /dev/null
+++ b/arch/x86/cpu/intel_common/cpu.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/cpu_common.h>
+#include <asm/intel_regs.h>
+#include <asm/lapic.h>
+#include <asm/lpc_common.h>
+#include <asm/msr.h>
+#include <asm/mtrr.h>
+#include <asm/post.h>
+#include <asm/microcode.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int report_bist_failure(void)
+{
+	if (gd->arch.bist != 0) {
+		post_code(POST_BIST_FAILURE);
+		printf("BIST failed: %08x\n", gd->arch.bist);
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+int cpu_common_init(void)
+{
+	struct udevice *dev, *lpc;
+	int ret;
+
+	/* Halt if there was a built in self test failure */
+	ret = report_bist_failure();
+	if (ret)
+		return ret;
+
+	enable_lapic();
+
+	ret = microcode_update_intel();
+	if (ret && ret != -EEXIST)
+		return ret;
+
+	/* Enable upper 128bytes of CMOS */
+	writel(1 << 2, RCB_REG(RC));
+
+	/* Early chipset init required before RAM init can work */
+	uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
+
+	ret = uclass_first_device(UCLASS_LPC, &lpc);
+	if (ret)
+		return ret;
+	if (!lpc)
+		return -ENODEV;
+
+	/* Cause the SATA device to do its early init */
+	uclass_first_device(UCLASS_DISK, &dev);
+
+	return 0;
+}
+
+int cpu_set_flex_ratio_to_tdp_nominal(void)
+{
+	msr_t flex_ratio, msr;
+	u8 nominal_ratio;
+
+	/* Check for Flex Ratio support */
+	flex_ratio = msr_read(MSR_FLEX_RATIO);
+	if (!(flex_ratio.lo & FLEX_RATIO_EN))
+		return -EINVAL;
+
+	/* Check for >0 configurable TDPs */
+	msr = msr_read(MSR_PLATFORM_INFO);
+	if (((msr.hi >> 1) & 3) == 0)
+		return -EINVAL;
+
+	/* Use nominal TDP ratio for flex ratio */
+	msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+	nominal_ratio = msr.lo & 0xff;
+
+	/* See if flex ratio is already set to nominal TDP ratio */
+	if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
+		return 0;
+
+	/* Set flex ratio to nominal TDP ratio */
+	flex_ratio.lo &= ~0xff00;
+	flex_ratio.lo |= nominal_ratio << 8;
+	flex_ratio.lo |= FLEX_RATIO_LOCK;
+	msr_write(MSR_FLEX_RATIO, flex_ratio);
+
+	/* Set flex ratio in soft reset data register bits 11:6 */
+	clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6,
+			(nominal_ratio & 0x3f) << 6);
+
+	debug("CPU: Soft reset to set up flex ratio\n");
+
+	/* Set soft reset control to use register value */
+	setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
+
+	/* Issue warm reset, will be "CPU only" due to soft reset data */
+	outb(0x0, IO_PORT_RESET);
+	outb(SYS_RST | RST_CPU, IO_PORT_RESET);
+	cpu_hlt();
+
+	/* Not reached */
+	return -EINVAL;
+}
diff --git a/arch/x86/cpu/intel_common/lpc.c b/arch/x86/cpu/intel_common/lpc.c
new file mode 100644
index 0000000..03cb45b
--- /dev/null
+++ b/arch/x86/cpu/intel_common/lpc.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <pch.h>
+#include <pci.h>
+#include <asm/intel_regs.h>
+#include <asm/io.h>
+#include <asm/lpc_common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Enable Prefetching and Caching */
+static void enable_spi_prefetch(struct udevice *pch)
+{
+	u8 reg8;
+
+	dm_pci_read_config8(pch, 0xdc, &reg8);
+	reg8 &= ~(3 << 2);
+	reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+	dm_pci_write_config8(pch, 0xdc, reg8);
+}
+
+static void enable_port80_on_lpc(struct udevice *pch)
+{
+	/* Enable port 80 POST on LPC */
+	dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1);
+	clrbits_le32(RCB_REG(GCS), 4);
+}
+
+/**
+ * lpc_early_init() - set up LPC serial ports and other early things
+ *
+ * @dev:	LPC device
+ * @return 0 if OK, -ve on error
+ */
+int lpc_common_early_init(struct udevice *dev)
+{
+	struct udevice *pch = dev->parent;
+	struct reg_info {
+		u32 base;
+		u32 size;
+	} values[4], *ptr;
+	int count;
+	int i;
+
+	count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset,
+			"intel,gen-dec", (u32 *)values,
+			sizeof(values) / sizeof(u32));
+	if (count < 0)
+		return -EINVAL;
+
+	/* Set COM1/COM2 decode range */
+	dm_pci_write_config16(pch, LPC_IO_DEC, 0x0010);
+
+	/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
+	dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
+			      GAMEL_LPC_EN | COMA_LPC_EN);
+
+	/* Write all registers but use 0 if we run out of data */
+	count = count * sizeof(u32) / sizeof(values[0]);
+	for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) {
+		u32 reg = 0;
+
+		if (i < count)
+			reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
+		dm_pci_write_config32(pch, LPC_GENX_DEC(i), reg);
+	}
+
+	enable_spi_prefetch(pch);
+
+	/* This is already done in start.S, but let's do it in C */
+	enable_port80_on_lpc(pch);
+
+	return 0;
+}
+
+int lpc_set_spi_protect(struct udevice *dev, int bios_ctrl, bool protect)
+{
+	uint8_t bios_cntl;
+
+	/* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
+	dm_pci_read_config8(dev, bios_ctrl, &bios_cntl);
+	if (protect) {
+		bios_cntl &= ~BIOS_CTRL_BIOSWE;
+		bios_cntl |= BIT(5);
+	} else {
+		bios_cntl |= BIOS_CTRL_BIOSWE;
+		bios_cntl &= ~BIT(5);
+	}
+	dm_pci_write_config8(dev, bios_ctrl, bios_cntl);
+
+	return 0;
+}
diff --git a/arch/x86/cpu/ivybridge/me_status.c b/arch/x86/cpu/intel_common/me_status.c
similarity index 93%
rename from arch/x86/cpu/ivybridge/me_status.c
rename to arch/x86/cpu/intel_common/me_status.c
index 15cf69f..130d219 100644
--- a/arch/x86/cpu/ivybridge/me_status.c
+++ b/arch/x86/cpu/intel_common/me_status.c
@@ -128,7 +128,14 @@
 	[0x10] = "Required VSCC values for flash parts do not match",
 };
 
-void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes)
+
+/**
+ * _intel_me_status() - Check Intel Management Engine status
+ *
+ * struct hfs:	Firmware status
+ * struct gmes:	Management engine status
+ */
+static void _intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes)
 {
 	/* Check Current States */
 	debug("ME: FW Partition Table      : %s\n",
@@ -193,3 +200,14 @@
 	}
 	debug("\n");
 }
+
+void intel_me_status(struct udevice *me_dev)
+{
+	struct me_hfs hfs;
+	struct me_gmes gmes;
+
+	pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
+	pci_read_dword_ptr(me_dev, &gmes, PCI_ME_GMES);
+
+	_intel_me_status(&hfs, &gmes);
+}
diff --git a/arch/x86/cpu/ivybridge/microcode_intel.c b/arch/x86/cpu/intel_common/microcode.c
similarity index 95%
rename from arch/x86/cpu/ivybridge/microcode_intel.c
rename to arch/x86/cpu/intel_common/microcode.c
index 2440a97..daf0d69 100644
--- a/arch/x86/cpu/ivybridge/microcode_intel.c
+++ b/arch/x86/cpu/intel_common/microcode.c
@@ -12,10 +12,12 @@
 #include <fdtdec.h>
 #include <libfdt.h>
 #include <asm/cpu.h>
+#include <asm/microcode.h>
 #include <asm/msr.h>
 #include <asm/msr-index.h>
 #include <asm/processor.h>
-#include <asm/arch/microcode.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /**
  * struct microcode_update - standard microcode header from Intel
@@ -62,8 +64,12 @@
 	return 0;
 }
 
-static inline uint32_t microcode_read_rev(void)
+int microcode_read_rev(void)
 {
+	/* Quark does not have microcode MSRs */
+#ifdef CONFIG_INTEL_QUARK
+	return 0;
+#else
 	/*
 	 * Some Intel CPUs can be very finicky about the CPUID sequence used.
 	 * So this is implemented in assembly so that it works reliably.
@@ -88,6 +94,7 @@
 	);
 
 	return high;
+#endif
 }
 
 static void microcode_read_cpu(struct microcode_update *cpu)
diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c
new file mode 100644
index 0000000..01b6e86
--- /dev/null
+++ b/arch/x86/cpu/intel_common/mrc.c
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/cpu.h>
+#include <asm/gpio.h>
+#include <asm/intel_regs.h>
+#include <asm/mrc_common.h>
+#include <asm/pch_common.h>
+#include <asm/post.h>
+#include <asm/arch/me.h>
+#include <asm/report_platform.h>
+
+static const char *const ecc_decoder[] = {
+	"inactive",
+	"active on IO",
+	"disabled on IO",
+	"active"
+};
+
+ulong mrc_common_board_get_usable_ram_top(ulong total_size)
+{
+	struct memory_info *info = &gd->arch.meminfo;
+	uintptr_t dest_addr = 0;
+	struct memory_area *largest = NULL;
+	int i;
+
+	/* Find largest area of memory below 4GB */
+
+	for (i = 0; i < info->num_areas; i++) {
+		struct memory_area *area = &info->area[i];
+
+		if (area->start >= 1ULL << 32)
+			continue;
+		if (!largest || area->size > largest->size)
+			largest = area;
+	}
+
+	/* If no suitable area was found, return an error. */
+	assert(largest);
+	if (!largest || largest->size < (2 << 20))
+		panic("No available memory found for relocation");
+
+	dest_addr = largest->start + largest->size;
+
+	return (ulong)dest_addr;
+}
+
+void mrc_common_dram_init_banksize(void)
+{
+	struct memory_info *info = &gd->arch.meminfo;
+	int num_banks;
+	int i;
+
+	for (i = 0, num_banks = 0; i < info->num_areas; i++) {
+		struct memory_area *area = &info->area[i];
+
+		if (area->start >= 1ULL << 32)
+			continue;
+		gd->bd->bi_dram[num_banks].start = area->start;
+		gd->bd->bi_dram[num_banks].size = area->size;
+		num_banks++;
+	}
+}
+
+int mrc_add_memory_area(struct memory_info *info, uint64_t start,
+			  uint64_t end)
+{
+	struct memory_area *ptr;
+
+	if (info->num_areas == CONFIG_NR_DRAM_BANKS)
+		return -ENOSPC;
+
+	ptr = &info->area[info->num_areas];
+	ptr->start = start;
+	ptr->size = end - start;
+	info->total_memory += ptr->size;
+	if (ptr->start < (1ULL << 32))
+		info->total_32bit_memory += ptr->size;
+	debug("%d: memory %llx size %llx, total now %llx / %llx\n",
+	      info->num_areas, ptr->start, ptr->size,
+	      info->total_32bit_memory, info->total_memory);
+	info->num_areas++;
+
+	return 0;
+}
+
+/*
+ * Dump in the log memory controller configuration as read from the memory
+ * controller registers.
+ */
+void report_memory_config(void)
+{
+	u32 addr_decoder_common, addr_decode_ch[2];
+	int i;
+
+	addr_decoder_common = readl(MCHBAR_REG(0x5000));
+	addr_decode_ch[0] = readl(MCHBAR_REG(0x5004));
+	addr_decode_ch[1] = readl(MCHBAR_REG(0x5008));
+
+	debug("memcfg DDR3 clock %d MHz\n",
+	      (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100);
+	debug("memcfg channel assignment: A: %d, B % d, C % d\n",
+	      addr_decoder_common & 3,
+	      (addr_decoder_common >> 2) & 3,
+	      (addr_decoder_common >> 4) & 3);
+
+	for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
+		u32 ch_conf = addr_decode_ch[i];
+		debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
+		debug("   ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
+		debug("   enhanced interleave mode %s\n",
+		      ((ch_conf >> 22) & 1) ? "on" : "off");
+		debug("   rank interleave %s\n",
+		      ((ch_conf >> 21) & 1) ? "on" : "off");
+		debug("   DIMMA %d MB width x%d %s rank%s\n",
+		      ((ch_conf >> 0) & 0xff) * 256,
+		      ((ch_conf >> 19) & 1) ? 16 : 8,
+		      ((ch_conf >> 17) & 1) ? "dual" : "single",
+		      ((ch_conf >> 16) & 1) ? "" : ", selected");
+		debug("   DIMMB %d MB width x%d %s rank%s\n",
+		      ((ch_conf >> 8) & 0xff) * 256,
+		      ((ch_conf >> 20) & 1) ? 16 : 8,
+		      ((ch_conf >> 18) & 1) ? "dual" : "single",
+		      ((ch_conf >> 16) & 1) ? ", selected" : "");
+	}
+}
+
+int mrc_locate_spd(struct udevice *dev, int size, const void **spd_datap)
+{
+	const void *blob = gd->fdt_blob;
+	int spd_index;
+	struct gpio_desc desc[4];
+	int spd_node;
+	int node;
+	int ret;
+
+	ret = gpio_request_list_by_name(dev, "board-id-gpios", desc,
+					ARRAY_SIZE(desc), GPIOD_IS_IN);
+	if (ret < 0) {
+		debug("%s: gpio ret=%d\n", __func__, ret);
+		return ret;
+	}
+	spd_index = dm_gpio_get_values_as_int(desc, ret);
+	debug("spd index %d\n", spd_index);
+
+	node = fdt_first_subnode(blob, dev->of_offset);
+	if (node < 0)
+		return -EINVAL;
+	for (spd_node = fdt_first_subnode(blob, node);
+	     spd_node > 0;
+	     spd_node = fdt_next_subnode(blob, spd_node)) {
+		int len;
+
+		if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index)
+			continue;
+		*spd_datap = fdt_getprop(blob, spd_node, "data", &len);
+		if (len < size) {
+			printf("Missing SPD data\n");
+			return -EINVAL;
+		}
+
+		debug("Using SDRAM SPD data for '%s'\n",
+		      fdt_get_name(blob, spd_node, NULL));
+		return 0;
+	}
+
+	printf("No SPD data found for index %d\n", spd_index);
+	return -ENOENT;
+}
+
+asmlinkage void sdram_console_tx_byte(unsigned char byte)
+{
+#ifdef DEBUG
+	putc(byte);
+#endif
+}
+
+/**
+ * Find the PEI executable in the ROM and execute it.
+ *
+ * @me_dev: Management Engine device
+ * @pei_data: configuration data for UEFI PEI reference code
+ */
+static int sdram_initialise(struct udevice *dev, struct udevice *me_dev,
+			    void *pei_data, bool use_asm_linkage)
+{
+	unsigned version;
+	const char *data;
+
+	report_platform_info(dev);
+	debug("Starting UEFI PEI System Agent\n");
+
+	debug("PEI data at %p:\n", pei_data);
+
+	data = (char *)CONFIG_X86_MRC_ADDR;
+	if (data) {
+		int rv;
+		ulong start;
+
+		debug("Calling MRC at %p\n", data);
+		post_code(POST_PRE_MRC);
+		start = get_timer(0);
+		if (use_asm_linkage) {
+			asmlinkage int (*func)(void *);
+
+			func = (asmlinkage int (*)(void *))data;
+			rv = func(pei_data);
+		} else {
+			int (*func)(void *);
+
+			func = (int (*)(void *))data;
+			rv = func(pei_data);
+		}
+		post_code(POST_MRC);
+		if (rv) {
+			switch (rv) {
+			case -1:
+				printf("PEI version mismatch.\n");
+				break;
+			case -2:
+				printf("Invalid memory frequency.\n");
+				break;
+			default:
+				printf("MRC returned %x.\n", rv);
+			}
+			printf("Nonzero MRC return value.\n");
+			return -EFAULT;
+		}
+		debug("MRC execution time %lu ms\n", get_timer(start));
+	} else {
+		printf("UEFI PEI System Agent not found.\n");
+		return -ENOSYS;
+	}
+
+	version = readl(MCHBAR_REG(MCHBAR_PEI_VERSION));
+	debug("System Agent Version %d.%d.%d Build %d\n",
+	      version >> 24 , (version >> 16) & 0xff,
+	      (version >> 8) & 0xff, version & 0xff);
+
+#if CONFIG_USBDEBUG
+	/* mrc.bin reconfigures USB, so reinit it to have debug */
+	early_usbdebug_init();
+#endif
+
+	return 0;
+}
+
+int mrc_common_init(struct udevice *dev, void *pei_data, bool use_asm_linkage)
+{
+	struct udevice *me_dev;
+	int ret;
+
+	ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
+	if (ret)
+		return ret;
+
+	ret = sdram_initialise(dev, me_dev, pei_data, use_asm_linkage);
+	if (ret)
+		return ret;
+	quick_ram_check();
+	post_code(POST_DRAM);
+	report_memory_config();
+
+	return 0;
+}
diff --git a/arch/x86/cpu/intel_common/pch.c b/arch/x86/cpu/intel_common/pch.c
new file mode 100644
index 0000000..1f05b44
--- /dev/null
+++ b/arch/x86/cpu/intel_common/pch.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/pch_common.h>
+
+u32 pch_common_sir_read(struct udevice *dev, int idx)
+{
+	u32 data;
+
+	dm_pci_write_config32(dev, SATA_SIRI, idx);
+	dm_pci_read_config32(dev, SATA_SIRD, &data);
+
+	return data;
+}
+
+void pch_common_sir_write(struct udevice *dev, int idx, u32 value)
+{
+	dm_pci_write_config32(dev, SATA_SIRI, idx);
+	dm_pci_write_config32(dev, SATA_SIRD, value);
+}
diff --git a/arch/x86/cpu/ivybridge/report_platform.c b/arch/x86/cpu/intel_common/report_platform.c
similarity index 97%
rename from arch/x86/cpu/ivybridge/report_platform.c
rename to arch/x86/cpu/intel_common/report_platform.c
index c78322a..05e1cf9 100644
--- a/arch/x86/cpu/ivybridge/report_platform.c
+++ b/arch/x86/cpu/intel_common/report_platform.c
@@ -9,8 +9,8 @@
 #include <common.h>
 #include <asm/cpu.h>
 #include <asm/pci.h>
+#include <asm/report_platform.h>
 #include <asm/arch/pch.h>
-#include <asm/arch/sandybridge.h>
 
 static void report_cpu_info(void)
 {
diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c
index c40200b..10dc4d4 100644
--- a/arch/x86/cpu/interrupts.c
+++ b/arch/x86/cpu/interrupts.c
@@ -249,7 +249,7 @@
 	int ret;
 
 	/* Try to set up the interrupt router, but don't require one */
-	ret = uclass_first_device(UCLASS_IRQ, &dev);
+	ret = uclass_first_device_err(UCLASS_IRQ, &dev);
 	if (ret && ret != -ENODEV)
 		return ret;
 
diff --git a/arch/x86/cpu/ioapic.c b/arch/x86/cpu/ioapic.c
index 112a9c6..d15e86c 100644
--- a/arch/x86/cpu/ioapic.c
+++ b/arch/x86/cpu/ioapic.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/ioapic.h>
+#include <asm/lapic.h>
 
 u32 io_apic_read(u32 reg)
 {
@@ -19,3 +20,18 @@
 	writel(reg, IO_APIC_INDEX);
 	writel(val, IO_APIC_DATA);
 }
+
+void io_apic_set_id(int ioapic_id)
+{
+	int bsp_lapicid = lapicid();
+
+	debug("IOAPIC: Initialising IOAPIC at %08x\n", IO_APIC_ADDR);
+	debug("IOAPIC: Bootstrap Processor Local APIC = %#02x\n", bsp_lapicid);
+
+	if (ioapic_id) {
+		debug("IOAPIC: ID = 0x%02x\n", ioapic_id);
+		/* Set IOAPIC ID if it has been specified */
+		io_apic_write(0x00, (io_apic_read(0x00) & 0xf0ffffff) |
+			      (ioapic_id << 24));
+	}
+}
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
index 0819347..e23d01a 100644
--- a/arch/x86/cpu/ivybridge/Kconfig
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -7,43 +7,18 @@
 
 config NORTHBRIDGE_INTEL_IVYBRIDGE
 	bool
-	select CACHE_MRC_BIN
+	select CACHE_MRC_BIN if HAVE_MRC
 
 if NORTHBRIDGE_INTEL_IVYBRIDGE
 
-config CACHE_MRC_BIN
-	bool
-	default n
-
-config CACHE_MRC_SIZE_KB
-	int
-	default 512
-
 config DCACHE_RAM_BASE
-	hex
 	default 0xff7e0000
 
 config DCACHE_RAM_SIZE
-	hex
 	default 0x20000
 
-config HAVE_MRC
-        bool "Add a System Agent binary"
-        help
-          Select this option to add a System Agent binary to
-          the resulting U-Boot image. MRC stands for Memory Reference Code.
-          It is a binary blob which U-Boot uses to set up SDRAM.
-
-          Note: Without this binary U-Boot will not be able to set up its
-          SDRAM so will not boot.
-
 config DCACHE_RAM_MRC_VAR_SIZE
-	hex
 	default 0x4000
-	help
-	  This is the amount of CAR (Cache as RAM) reserved for use by the
-	  memory reference code. This should be set to 16KB (0x4000 hex)
-	  so that MRC has enough space to run.
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index 9203219..9cdb07b 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -7,16 +7,12 @@
 ifdef CONFIG_HAVE_FSP
 obj-y += fsp_configs.o ivybridge.o
 else
-obj-y += car.o
 obj-y += cpu.o
 obj-y += early_me.o
 obj-y += gma.o
 obj-y += lpc.o
-obj-y += me_status.o
 obj-y += model_206ax.o
-obj-y += microcode_intel.o
 obj-y += northbridge.o
-obj-y += report_platform.o
 obj-y += sata.o
 obj-y += sdram.o
 endif
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 9972b0a..4c039ac 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -11,8 +11,10 @@
 #include <pch.h>
 #include <syscon.h>
 #include <asm/cpu.h>
+#include <asm/intel_regs.h>
 #include <asm/io.h>
 #include <asm/lapic.h>
+#include <asm/lpc_common.h>
 #include <asm/pci.h>
 #include <asm/arch/bd82x6x.h>
 #include <asm/arch/model_206ax.h>
@@ -187,20 +189,7 @@
 
 static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
 {
-	uint8_t bios_cntl;
-
-	/* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
-	dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
-	if (protect) {
-		bios_cntl &= ~BIOS_CTRL_BIOSWE;
-		bios_cntl |= BIT(5);
-	} else {
-		bios_cntl |= BIOS_CTRL_BIOSWE;
-		bios_cntl &= ~BIT(5);
-	}
-	dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
-
-	return 0;
+	return lpc_set_spi_protect(dev, BIOS_CTRL, protect);
 }
 
 static int bd82x6x_get_gpio_base(struct udevice *dev, u32 *gbasep)
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 948833c..0f93905 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -17,15 +17,18 @@
 #include <fdtdec.h>
 #include <pch.h>
 #include <asm/cpu.h>
+#include <asm/cpu_common.h>
+#include <asm/intel_regs.h>
 #include <asm/io.h>
 #include <asm/lapic.h>
+#include <asm/lpc_common.h>
+#include <asm/microcode.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>
 #include <asm/pci.h>
 #include <asm/post.h>
 #include <asm/processor.h>
 #include <asm/arch/model_206ax.h>
-#include <asm/arch/microcode.h>
 #include <asm/arch/pch.h>
 #include <asm/arch/sandybridge.h>
 
@@ -33,51 +36,11 @@
 
 static int set_flex_ratio_to_tdp_nominal(void)
 {
-	msr_t flex_ratio, msr;
-	u8 nominal_ratio;
-
 	/* Minimum CPU revision for configurable TDP support */
 	if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
 		return -EINVAL;
 
-	/* Check for Flex Ratio support */
-	flex_ratio = msr_read(MSR_FLEX_RATIO);
-	if (!(flex_ratio.lo & FLEX_RATIO_EN))
-		return -EINVAL;
-
-	/* Check for >0 configurable TDPs */
-	msr = msr_read(MSR_PLATFORM_INFO);
-	if (((msr.hi >> 1) & 3) == 0)
-		return -EINVAL;
-
-	/* Use nominal TDP ratio for flex ratio */
-	msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
-	nominal_ratio = msr.lo & 0xff;
-
-	/* See if flex ratio is already set to nominal TDP ratio */
-	if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
-		return 0;
-
-	/* Set flex ratio to nominal TDP ratio */
-	flex_ratio.lo &= ~0xff00;
-	flex_ratio.lo |= nominal_ratio << 8;
-	flex_ratio.lo |= FLEX_RATIO_LOCK;
-	msr_write(MSR_FLEX_RATIO, flex_ratio);
-
-	/* Set flex ratio in soft reset data register bits 11:6 */
-	clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6,
-			(nominal_ratio & 0x3f) << 6);
-
-	/* Set soft reset control to use register value */
-	setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
-
-	/* Issue warm reset, will be "CPU only" due to soft reset data */
-	outb(0x0, PORT_RESET);
-	outb(SYS_RST | RST_CPU, PORT_RESET);
-	cpu_hlt();
-
-	/* Not reached */
-	return -EINVAL;
+	return cpu_set_flex_ratio_to_tdp_nominal();
 }
 
 int arch_cpu_init(void)
@@ -104,9 +67,9 @@
 	/* TODO(sjg@chromium.org): Get rid of gd->hose */
 	gd->hose = hose;
 
-	ret = uclass_first_device(UCLASS_LPC, &dev);
-	if (!dev)
-		return -ENODEV;
+	ret = uclass_first_device_err(UCLASS_LPC, &dev);
+	if (ret)
+		return ret;
 
 	/*
 	 * We should do as little as possible before the serial console is
@@ -162,17 +125,6 @@
 	pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32);
 }
 
-static int report_bist_failure(void)
-{
-	if (gd->arch.bist != 0) {
-		post_code(POST_BIST_FAILURE);
-		printf("BIST failed: %08x\n", gd->arch.bist);
-		return -EFAULT;
-	}
-
-	return 0;
-}
-
 int print_cpuinfo(void)
 {
 	enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
@@ -183,20 +135,6 @@
 	uint16_t pm1_sts;
 	int ret;
 
-	/* Halt if there was a built in self test failure */
-	ret = report_bist_failure();
-	if (ret)
-		return ret;
-
-	enable_lapic();
-
-	ret = microcode_update_intel();
-	if (ret)
-		return ret;
-
-	/* Enable upper 128bytes of CMOS */
-	writel(1 << 2, RCB_REG(RC));
-
 	/* TODO: cmos_post_init() */
 	if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) {
 		debug("soft reset detected\n");
@@ -207,17 +145,9 @@
 		reset_cpu(0);
 	}
 
-	/* Early chipset init required before RAM init can work */
-	uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
-
-	ret = uclass_first_device(UCLASS_LPC, &lpc);
+	ret = cpu_common_init();
 	if (ret)
 		return ret;
-	if (!dev)
-		return -ENODEV;
-
-	/* Cause the SATA device to do its early init */
-	uclass_first_device(UCLASS_DISK, &dev);
 
 	/* Check PM1_STS[15] to see if we are waking from Sx */
 	pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
@@ -236,15 +166,15 @@
 	post_code(POST_EARLY_INIT);
 
 	/* Enable SPD ROMs and DDR-III DRAM */
-	ret = uclass_first_device(UCLASS_I2C, &dev);
+	ret = uclass_first_device_err(UCLASS_I2C, &dev);
 	if (ret)
 		return ret;
-	if (!dev)
-		return -ENODEV;
 
 	/* Prepare USB controller early in S3 resume */
-	if (boot_mode == PEI_BOOT_RESUME)
+	if (boot_mode == PEI_BOOT_RESUME) {
+		uclass_first_device(UCLASS_LPC, &lpc);
 		enable_usb_bar(pci_get_controller(lpc->parent));
+	}
 
 	gd->arch.pei_boot_mode = boot_mode;
 
diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c
index b1df77d..cda96ab 100644
--- a/arch/x86/cpu/ivybridge/early_me.c
+++ b/arch/x86/cpu/ivybridge/early_me.c
@@ -27,35 +27,6 @@
 	[ME_HFS_ACK_CONTINUE]	= "Continue to boot"
 };
 
-static inline void pci_read_dword_ptr(struct udevice *me_dev, void *ptr,
-				      int offset)
-{
-	u32 dword;
-
-	dm_pci_read_config32(me_dev, offset, &dword);
-	memcpy(ptr, &dword, sizeof(dword));
-}
-
-static inline void pci_write_dword_ptr(struct udevice *me_dev, void *ptr,
-				       int offset)
-{
-	u32 dword = 0;
-
-	memcpy(&dword, ptr, sizeof(dword));
-	dm_pci_write_config32(me_dev, offset, dword);
-}
-
-void intel_early_me_status(struct udevice *me_dev)
-{
-	struct me_hfs hfs;
-	struct me_gmes gmes;
-
-	pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
-	pci_read_dword_ptr(me_dev, &gmes, PCI_ME_GMES);
-
-	intel_me_status(&hfs, &gmes);
-}
-
 int intel_early_me_init(struct udevice *me_dev)
 {
 	int count;
@@ -159,7 +130,7 @@
 	debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]);
 
 	/* Check status after acknowledgement */
-	intel_early_me_status(me_dev);
+	intel_me_status(me_dev);
 
 	switch (hfs.ack_data) {
 	case ME_HFS_ACK_CONTINUE:
diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
index 3b6291e..37e2e6e 100644
--- a/arch/x86/cpu/ivybridge/gma.c
+++ b/arch/x86/cpu/ivybridge/gma.c
@@ -12,6 +12,7 @@
 #include <errno.h>
 #include <fdtdec.h>
 #include <pci_rom.h>
+#include <asm/intel_regs.h>
 #include <asm/io.h>
 #include <asm/mtrr.h>
 #include <asm/pci.h>
@@ -812,9 +813,9 @@
 	writew(0x0010, RCB_REG(DISPBDF));
 	setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
 
-	ret = uclass_first_device(UCLASS_NORTHBRIDGE, &nbridge);
-	if (!nbridge)
-		return -ENODEV;
+	ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &nbridge);
+	if (ret)
+		return ret;
 	rev = bridge_silicon_revision(nbridge);
 	sandybridge_setup_graphics(nbridge, dev);
 
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 9ab5ed3..88ab797 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -13,9 +13,11 @@
 #include <rtc.h>
 #include <pci.h>
 #include <asm/acpi.h>
+#include <asm/intel_regs.h>
 #include <asm/interrupt.h>
 #include <asm/io.h>
 #include <asm/ioapic.h>
+#include <asm/lpc_common.h>
 #include <asm/pci.h>
 #include <asm/arch/pch.h>
 
@@ -404,26 +406,6 @@
 	setbits_le32(RCB_REG(0x21a8), 0x3);
 }
 
-/*
- * Enable Prefetching and Caching.
- */
-static void enable_spi_prefetch(struct udevice *pch)
-{
-	u8 reg8;
-
-	dm_pci_read_config8(pch, 0xdc, &reg8);
-	reg8 &= ~(3 << 2);
-	reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
-	dm_pci_write_config8(pch, 0xdc, reg8);
-}
-
-static void enable_port80_on_lpc(struct udevice *pch)
-{
-	/* Enable port 80 POST on LPC */
-	dm_pci_write_config32(pch, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
-	clrbits_le32(RCB_REG(GCS), 4);
-}
-
 static void set_spi_speed(void)
 {
 	u32 fdod;
@@ -440,54 +422,6 @@
 	clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);
 }
 
-/**
- * lpc_early_init() - set up LPC serial ports and other early things
- *
- * @dev:	LPC device
- * @return 0 if OK, -ve on error
- */
-static int lpc_early_init(struct udevice *dev)
-{
-	struct reg_info {
-		u32 base;
-		u32 size;
-	} values[4], *ptr;
-	int count;
-	int i;
-
-	count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset,
-			"intel,gen-dec", (u32 *)values,
-			sizeof(values) / sizeof(u32));
-	if (count < 0)
-		return -EINVAL;
-
-	/* Set COM1/COM2 decode range */
-	dm_pci_write_config16(dev->parent, LPC_IO_DEC, 0x0010);
-
-	/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
-	dm_pci_write_config16(dev->parent, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
-			      GAMEL_LPC_EN | COMA_LPC_EN);
-
-	/* Write all registers but use 0 if we run out of data */
-	count = count * sizeof(u32) / sizeof(values[0]);
-	for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) {
-		u32 reg = 0;
-
-		if (i < count)
-			reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
-		dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg);
-	}
-
-	enable_spi_prefetch(dev->parent);
-
-	/* This is already done in start.S, but let's do it in C */
-	enable_port80_on_lpc(dev->parent);
-
-	set_spi_speed();
-
-	return 0;
-}
-
 static int lpc_init_extra(struct udevice *dev)
 {
 	struct udevice *pch = dev->parent;
@@ -550,9 +484,12 @@
 
 static int bd82x6x_lpc_early_init(struct udevice *dev)
 {
+	set_spi_speed();
+
 	/* Setting up Southbridge. In the northbridge code. */
 	debug("Setting up static southbridge registers\n");
-	dm_pci_write_config32(dev->parent, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
+	dm_pci_write_config32(dev->parent, PCH_RCBA_BASE,
+			      RCB_BASE_ADDRESS | 1);
 	dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1);
 
 	/* Enable ACPI BAR */
@@ -573,7 +510,7 @@
 	int ret;
 
 	if (!(gd->flags & GD_FLG_RELOC)) {
-		ret = lpc_early_init(dev);
+		ret = lpc_common_early_init(dev);
 		if (ret) {
 			debug("%s: lpc_early_init() failed\n", __func__);
 			return ret;
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c
index 9654600..cef4256 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -17,6 +17,7 @@
 #include <asm/cpu_x86.h>
 #include <asm/lapic.h>
 #include <asm/msr.h>
+#include <asm/msr-index.h>
 #include <asm/mtrr.h>
 #include <asm/processor.h>
 #include <asm/speedstep.h>
@@ -363,7 +364,7 @@
 		msr = msr_read(MSR_PLATFORM_INFO);
 		perf_ctl.lo = msr.lo & 0xff00;
 	}
-	msr_write(IA32_PERF_CTL, perf_ctl);
+	msr_write(MSR_IA32_PERF_CTL, perf_ctl);
 
 	debug("model_x06ax: frequency set to %d\n",
 	      ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
@@ -455,9 +456,10 @@
 {
 	msr_t msr;
 
-	msr = msr_read(IA32_PERF_CTL);
+	msr = msr_read(MSR_IA32_PERF_CTL);
 	info->cpu_freq = ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK * 1000000;
-	info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU;
+	info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
+		1 << CPU_FEAT_UCODE;
 
 	return 0;
 }
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c
index a066607..f7e0bc3 100644
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -12,6 +12,7 @@
 #include <asm/msr.h>
 #include <asm/acpi.h>
 #include <asm/cpu.h>
+#include <asm/intel_regs.h>
 #include <asm/io.h>
 #include <asm/pci.h>
 #include <asm/processor.h>
@@ -167,8 +168,8 @@
 	debug("Setting up static registers\n");
 	dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1);
 	dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
-	dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1);
-	dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32);
+	dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1);
+	dm_pci_write_config32(dev, MCHBAR + 4, (0LL + MCH_BASE_ADDRESS) >> 32);
 	/* 64MB - busses 0-63 */
 	dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
 	dm_pci_write_config32(dev, PCIEXBAR + 4,
diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c
index a59d9ed..c3d1057 100644
--- a/arch/x86/cpu/ivybridge/sata.c
+++ b/arch/x86/cpu/ivybridge/sata.c
@@ -9,28 +9,13 @@
 #include <dm.h>
 #include <fdtdec.h>
 #include <asm/io.h>
+#include <asm/pch_common.h>
 #include <asm/pci.h>
 #include <asm/arch/pch.h>
 #include <asm/arch/bd82x6x.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static inline u32 sir_read(struct udevice *dev, int idx)
-{
-	u32 data;
-
-	dm_pci_write_config32(dev, SATA_SIRI, idx);
-	dm_pci_read_config32(dev, SATA_SIRD, &data);
-
-	return data;
-}
-
-static inline void sir_write(struct udevice *dev, int idx, u32 value)
-{
-	dm_pci_write_config32(dev, SATA_SIRI, idx);
-	dm_pci_write_config32(dev, SATA_SIRD, value);
-}
-
 static void common_sata_init(struct udevice *dev, unsigned int port_map)
 {
 	u32 reg32;
@@ -177,27 +162,27 @@
 		pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx);
 
 	/* Additional Programming Requirements */
-	sir_write(dev, 0x04, 0x00001600);
-	sir_write(dev, 0x28, 0xa0000033);
-	reg32 = sir_read(dev, 0x54);
+	pch_common_sir_write(dev, 0x04, 0x00001600);
+	pch_common_sir_write(dev, 0x28, 0xa0000033);
+	reg32 = pch_common_sir_read(dev, 0x54);
 	reg32 &= 0xff000000;
 	reg32 |= 0x5555aa;
-	sir_write(dev, 0x54, reg32);
-	sir_write(dev, 0x64, 0xcccc8484);
-	reg32 = sir_read(dev, 0x68);
+	pch_common_sir_write(dev, 0x54, reg32);
+	pch_common_sir_write(dev, 0x64, 0xcccc8484);
+	reg32 = pch_common_sir_read(dev, 0x68);
 	reg32 &= 0xffff0000;
 	reg32 |= 0xcccc;
-	sir_write(dev, 0x68, reg32);
-	reg32 = sir_read(dev, 0x78);
+	pch_common_sir_write(dev, 0x68, reg32);
+	reg32 = pch_common_sir_read(dev, 0x78);
 	reg32 &= 0x0000ffff;
 	reg32 |= 0x88880000;
-	sir_write(dev, 0x78, reg32);
-	sir_write(dev, 0x84, 0x001c7000);
-	sir_write(dev, 0x88, 0x88338822);
-	sir_write(dev, 0xa0, 0x001c7000);
-	sir_write(dev, 0xc4, 0x0c0c0c0c);
-	sir_write(dev, 0xc8, 0x0c0c0c0c);
-	sir_write(dev, 0xd4, 0x10000000);
+	pch_common_sir_write(dev, 0x78, reg32);
+	pch_common_sir_write(dev, 0x84, 0x001c7000);
+	pch_common_sir_write(dev, 0x88, 0x88338822);
+	pch_common_sir_write(dev, 0xa0, 0x001c7000);
+	pch_common_sir_write(dev, 0xc4, 0x0c0c0c0c);
+	pch_common_sir_write(dev, 0xc8, 0x0c0c0c0c);
+	pch_common_sir_write(dev, 0xd4, 0x10000000);
 
 	pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000);
 	pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100);
@@ -229,11 +214,9 @@
 	struct udevice *pch;
 	int ret;
 
-	ret = uclass_first_device(UCLASS_PCH, &pch);
+	ret = uclass_first_device_err(UCLASS_PCH, &pch);
 	if (ret)
 		return ret;
-	if (!pch)
-		return -ENODEV;
 
 	if (!(gd->flags & GD_FLG_RELOC))
 		bd82x6x_sata_enable(dev);
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index e23c422..e35e543 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -23,9 +23,12 @@
 #include <asm/processor.h>
 #include <asm/gpio.h>
 #include <asm/global_data.h>
+#include <asm/intel_regs.h>
 #include <asm/mrccache.h>
+#include <asm/mrc_common.h>
 #include <asm/mtrr.h>
 #include <asm/pci.h>
+#include <asm/report_platform.h>
 #include <asm/arch/me.h>
 #include <asm/arch/pei_data.h>
 #include <asm/arch/pch.h>
@@ -38,57 +41,14 @@
 #define CMOS_OFFSET_MRC_SEED_S3		156
 #define CMOS_OFFSET_MRC_SEED_CHK	160
 
-/*
- * This function looks for the highest region of memory lower than 4GB which
- * has enough space for U-Boot where U-Boot is aligned on a page boundary.
- * It overrides the default implementation found elsewhere which simply
- * picks the end of ram, wherever that may be. The location of the stack,
- * the relocation address, and how far U-Boot is moved by relocation are
- * set in the global data structure.
- */
 ulong board_get_usable_ram_top(ulong total_size)
 {
-	struct memory_info *info = &gd->arch.meminfo;
-	uintptr_t dest_addr = 0;
-	struct memory_area *largest = NULL;
-	int i;
-
-	/* Find largest area of memory below 4GB */
-
-	for (i = 0; i < info->num_areas; i++) {
-		struct memory_area *area = &info->area[i];
-
-		if (area->start >= 1ULL << 32)
-			continue;
-		if (!largest || area->size > largest->size)
-			largest = area;
-	}
-
-	/* If no suitable area was found, return an error. */
-	assert(largest);
-	if (!largest || largest->size < (2 << 20))
-		panic("No available memory found for relocation");
-
-	dest_addr = largest->start + largest->size;
-
-	return (ulong)dest_addr;
+	return mrc_common_board_get_usable_ram_top(total_size);
 }
 
 void dram_init_banksize(void)
 {
-	struct memory_info *info = &gd->arch.meminfo;
-	int num_banks;
-	int i;
-
-	for (i = 0, num_banks = 0; i < info->num_areas; i++) {
-		struct memory_area *area = &info->area[i];
-
-		if (area->start >= 1ULL << 32)
-			continue;
-		gd->bd->bi_dram[num_banks].start = area->start;
-		gd->bd->bi_dram[num_banks].size = area->size;
-		num_banks++;
-	}
+	mrc_common_dram_init_banksize();
 }
 
 static int read_seed_from_cmos(struct pei_data *pei_data)
@@ -215,166 +175,12 @@
 	return 0;
 }
 
-static const char *const ecc_decoder[] = {
-	"inactive",
-	"active on IO",
-	"disabled on IO",
-	"active"
-};
-
-/*
- * Dump in the log memory controller configuration as read from the memory
- * controller registers.
- */
-static void report_memory_config(void)
+static void post_system_agent_init(struct udevice *dev, struct udevice *me_dev,
+				   struct pei_data *pei_data)
 {
-	u32 addr_decoder_common, addr_decode_ch[2];
-	int i;
-
-	addr_decoder_common = readl(MCHBAR_REG(0x5000));
-	addr_decode_ch[0] = readl(MCHBAR_REG(0x5004));
-	addr_decode_ch[1] = readl(MCHBAR_REG(0x5008));
-
-	debug("memcfg DDR3 clock %d MHz\n",
-	      (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100);
-	debug("memcfg channel assignment: A: %d, B % d, C % d\n",
-	      addr_decoder_common & 3,
-	      (addr_decoder_common >> 2) & 3,
-	      (addr_decoder_common >> 4) & 3);
-
-	for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
-		u32 ch_conf = addr_decode_ch[i];
-		debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
-		debug("   ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
-		debug("   enhanced interleave mode %s\n",
-		      ((ch_conf >> 22) & 1) ? "on" : "off");
-		debug("   rank interleave %s\n",
-		      ((ch_conf >> 21) & 1) ? "on" : "off");
-		debug("   DIMMA %d MB width x%d %s rank%s\n",
-		      ((ch_conf >> 0) & 0xff) * 256,
-		      ((ch_conf >> 19) & 1) ? 16 : 8,
-		      ((ch_conf >> 17) & 1) ? "dual" : "single",
-		      ((ch_conf >> 16) & 1) ? "" : ", selected");
-		debug("   DIMMB %d MB width x%d %s rank%s\n",
-		      ((ch_conf >> 8) & 0xff) * 256,
-		      ((ch_conf >> 20) & 1) ? 16 : 8,
-		      ((ch_conf >> 18) & 1) ? "dual" : "single",
-		      ((ch_conf >> 16) & 1) ? ", selected" : "");
-	}
-}
-
-static void post_system_agent_init(struct pei_data *pei_data)
-{
-	/* If PCIe init is skipped, set the PEG clock gating */
-	if (!pei_data->pcie_init)
-		setbits_le32(MCHBAR_REG(0x7010), 1);
-}
-
-static asmlinkage void console_tx_byte(unsigned char byte)
-{
-#ifdef DEBUG
-	putc(byte);
-#endif
-}
-
-static int recovery_mode_enabled(void)
-{
-	return false;
-}
-
-/**
- * Find the PEI executable in the ROM and execute it.
- *
- * @dev: Northbridge device
- * @pei_data: configuration data for UEFI PEI reference code
- */
-int sdram_initialise(struct udevice *dev, struct udevice *me_dev,
-		     struct pei_data *pei_data)
-{
-	unsigned version;
-	const char *data;
 	uint16_t done;
-	int ret;
-
-	report_platform_info(dev);
-
-	/* Wait for ME to be ready */
-	ret = intel_early_me_init(me_dev);
-	if (ret)
-		return ret;
-	ret = intel_early_me_uma_size(me_dev);
-	if (ret < 0)
-		return ret;
-
-	debug("Starting UEFI PEI System Agent\n");
 
 	/*
-	 * Do not pass MRC data in for recovery mode boot,
-	 * Always pass it in for S3 resume.
-	 */
-	if (!recovery_mode_enabled() ||
-	    pei_data->boot_mode == PEI_BOOT_RESUME) {
-		ret = prepare_mrc_cache(pei_data);
-		if (ret)
-			debug("prepare_mrc_cache failed: %d\n", ret);
-	}
-
-	/* If MRC data is not found we cannot continue S3 resume. */
-	if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
-		debug("Giving up in sdram_initialize: No MRC data\n");
-		reset_cpu(0);
-	}
-
-	/* Pass console handler in pei_data */
-	pei_data->tx_byte = console_tx_byte;
-
-	debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data));
-
-	data = (char *)CONFIG_X86_MRC_ADDR;
-	if (data) {
-		int rv;
-		int (*func)(struct pei_data *);
-		ulong start;
-
-		debug("Calling MRC at %p\n", data);
-		post_code(POST_PRE_MRC);
-		start = get_timer(0);
-		func = (int (*)(struct pei_data *))data;
-		rv = func(pei_data);
-		post_code(POST_MRC);
-		if (rv) {
-			switch (rv) {
-			case -1:
-				printf("PEI version mismatch.\n");
-				break;
-			case -2:
-				printf("Invalid memory frequency.\n");
-				break;
-			default:
-				printf("MRC returned %x.\n", rv);
-			}
-			printf("Nonzero MRC return value.\n");
-			return -EFAULT;
-		}
-		debug("MRC execution time %lu ms\n", get_timer(start));
-	} else {
-		printf("UEFI PEI System Agent not found.\n");
-		return -ENOSYS;
-	}
-
-#if CONFIG_USBDEBUG
-	/* mrc.bin reconfigures USB, so reinit it to have debug */
-	early_usbdebug_init();
-#endif
-
-	version = readl(MCHBAR_REG(0x5034));
-	debug("System Agent Version %d.%d.%d Build %d\n",
-	      version >> 24 , (version >> 16) & 0xff,
-	      (version >> 8) & 0xff, version & 0xff);
-	debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len,
-	      pei_data->mrc_output);
-
-	/*
 	 * Send ME init done for SandyBridge here.  This is done inside the
 	 * SystemAgent binary on IvyBridge
 	 */
@@ -383,113 +189,33 @@
 	if (BASE_REV_SNB == done)
 		intel_early_me_init_done(dev, me_dev, ME_INIT_STATUS_SUCCESS);
 	else
-		intel_early_me_status(me_dev);
-
-	post_system_agent_init(pei_data);
-	report_memory_config();
+		intel_me_status(me_dev);
 
-	/* S3 resume: don't save scrambler seed or MRC data */
-	if (pei_data->boot_mode != PEI_BOOT_RESUME) {
-		/*
-		 * This will be copied to SDRAM in reserve_arch(), then written
-		 * to SPI flash in mrccache_save()
-		 */
-		gd->arch.mrc_output = (char *)pei_data->mrc_output;
-		gd->arch.mrc_output_len = pei_data->mrc_output_len;
-		ret = write_seeds_to_cmos(pei_data);
-		if (ret)
-			debug("Failed to write seeds to CMOS: %d\n", ret);
-	}
-
-	return 0;
+	/* If PCIe init is skipped, set the PEG clock gating */
+	if (!pei_data->pcie_init)
+		setbits_le32(MCHBAR_REG(0x7010), 1);
 }
 
-int reserve_arch(void)
+static int recovery_mode_enabled(void)
 {
-	return mrccache_reserve();
+	return false;
 }
 
-static int copy_spd(struct pei_data *peid)
+int reserve_arch(void)
 {
-	const int gpio_vector[] = {41, 42, 43, 10, -1};
-	int spd_index;
-	const void *blob = gd->fdt_blob;
-	int node, spd_node;
-	int ret, i;
-
-	for (i = 0; ; i++) {
-		if (gpio_vector[i] == -1)
-			break;
-		ret = gpio_requestf(gpio_vector[i], "spd_id%d", i);
-		if (ret) {
-			debug("%s: Could not request gpio %d\n", __func__,
-			      gpio_vector[i]);
-			return ret;
-		}
-	}
-	spd_index = gpio_get_values_as_int(gpio_vector);
-	debug("spd index %d\n", spd_index);
-	node = fdtdec_next_compatible(blob, 0, COMPAT_MEMORY_SPD);
-	if (node < 0) {
-		printf("SPD data not found.\n");
-		return -ENOENT;
-	}
-
-	for (spd_node = fdt_first_subnode(blob, node);
-	     spd_node > 0;
-	     spd_node = fdt_next_subnode(blob, spd_node)) {
-		const char *data;
-		int len;
-
-		if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index)
-			continue;
-		data = fdt_getprop(blob, spd_node, "data", &len);
-		if (len < sizeof(peid->spd_data[0])) {
-			printf("Missing SPD data\n");
-			return -EINVAL;
-		}
-
-		debug("Using SDRAM SPD data for '%s'\n",
-		      fdt_get_name(blob, spd_node, NULL));
-		memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
-		break;
-	}
-
-	if (spd_node < 0) {
-		printf("No SPD data found for index %d\n", spd_index);
-		return -ENOENT;
-	}
-
-	return 0;
+	return mrccache_reserve();
 }
 
-/**
- * add_memory_area() - Add a new usable memory area to our list
- *
- * Note: @start and @end must not span the first 4GB boundary
- *
- * @info:	Place to store memory info
- * @start:	Start of this memory area
- * @end:	End of this memory area + 1
- */
-static int add_memory_area(struct memory_info *info,
-			   uint64_t start, uint64_t end)
+static int copy_spd(struct udevice *dev, struct pei_data *peid)
 {
-	struct memory_area *ptr;
+	const void *data;
+	int ret;
 
-	if (info->num_areas == CONFIG_NR_DRAM_BANKS)
-		return -ENOSPC;
+	ret = mrc_locate_spd(dev, sizeof(peid->spd_data[0]), &data);
+	if (ret)
+		return ret;
 
-	ptr = &info->area[info->num_areas];
-	ptr->start = start;
-	ptr->size = end - start;
-	info->total_memory += ptr->size;
-	if (ptr->start < (1ULL << 32))
-		info->total_32bit_memory += ptr->size;
-	debug("%d: memory %llx size %llx, total now %llx / %llx\n",
-	      info->num_areas, ptr->start, ptr->size,
-	      info->total_32bit_memory, info->total_memory);
-	info->num_areas++;
+	memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
 
 	return 0;
 }
@@ -608,10 +334,10 @@
 	debug("Available memory below 4GB: %lluM\n", tomk >> 10);
 
 	/* Report the memory regions */
-	add_memory_area(info, 1 << 20, 2 << 28);
-	add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28);
-	add_memory_area(info, (4 << 28) + (2 << 20), tseg_base);
-	add_memory_area(info, 1ULL << 32, touud);
+	mrc_add_memory_area(info, 1 << 20, 2 << 28);
+	mrc_add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28);
+	mrc_add_memory_area(info, (4 << 28) + (2 << 20), tseg_base);
+	mrc_add_memory_area(info, 1ULL << 32, touud);
 
 	/* Add MTRRs for memory */
 	mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30);
@@ -680,9 +406,9 @@
 
 int dram_init(void)
 {
-	struct pei_data pei_data __aligned(8) = {
+	struct pei_data _pei_data __aligned(8) = {
 		.pei_version = PEI_VERSION,
-		.mchbar = DEFAULT_MCHBAR,
+		.mchbar = MCH_BASE_ADDRESS,
 		.dmibar = DEFAULT_DMIBAR,
 		.epbar = DEFAULT_EPBAR,
 		.pciexbar = CONFIG_PCIE_ECAM_BASE,
@@ -733,38 +459,84 @@
 			{ 0, 4, 0x0000 }, /* P13= Empty */
 		},
 	};
+	struct pei_data *pei_data = &_pei_data;
 	struct udevice *dev, *me_dev;
 	int ret;
 
-	ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
+	ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
 	if (ret)
 		return ret;
-	if (!dev)
-		return -ENODEV;
 	ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
 	if (ret)
 		return ret;
-	debug("Boot mode %d\n", gd->arch.pei_boot_mode);
-	debug("mrc_input %p\n", pei_data.mrc_input);
-	pei_data.boot_mode = gd->arch.pei_boot_mode;
-	ret = copy_spd(&pei_data);
-	if (!ret)
-		ret = sdram_initialise(dev, me_dev, &pei_data);
+	ret = copy_spd(dev, pei_data);
 	if (ret)
 		return ret;
+	pei_data->boot_mode = gd->arch.pei_boot_mode;
+	debug("Boot mode %d\n", gd->arch.pei_boot_mode);
+	debug("mrc_input %p\n", pei_data->mrc_input);
 
-	rcba_config();
-	quick_ram_check();
+	/*
+	 * Do not pass MRC data in for recovery mode boot,
+	 * Always pass it in for S3 resume.
+	 */
+	if (!recovery_mode_enabled() ||
+	    pei_data->boot_mode == PEI_BOOT_RESUME) {
+		ret = prepare_mrc_cache(pei_data);
+		if (ret)
+			debug("prepare_mrc_cache failed: %d\n", ret);
+	}
 
-	writew(0xCAFE, MCHBAR_REG(SSKPD));
+	/* If MRC data is not found we cannot continue S3 resume. */
+	if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
+		debug("Giving up in sdram_initialize: No MRC data\n");
+		reset_cpu(0);
+	}
 
-	post_code(POST_DRAM);
+	/* Pass console handler in pei_data */
+	pei_data->tx_byte = sdram_console_tx_byte;
 
-	ret = sdram_find(dev);
+	/* Wait for ME to be ready */
+	ret = intel_early_me_init(me_dev);
 	if (ret)
 		return ret;
+	ret = intel_early_me_uma_size(me_dev);
+	if (ret < 0)
+		return ret;
+
+	ret = mrc_common_init(dev, pei_data, false);
+	if (ret)
+		return ret;
 
+	ret = sdram_find(dev);
+	if (ret)
+		return ret;
 	gd->ram_size = gd->arch.meminfo.total_32bit_memory;
 
+	debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len,
+	      pei_data->mrc_output);
+
+	post_system_agent_init(dev, me_dev, pei_data);
+	report_memory_config();
+
+	/* S3 resume: don't save scrambler seed or MRC data */
+	if (pei_data->boot_mode != PEI_BOOT_RESUME) {
+		/*
+		 * This will be copied to SDRAM in reserve_arch(), then written
+		 * to SPI flash in mrccache_save()
+		 */
+		gd->arch.mrc_output = (char *)pei_data->mrc_output;
+		gd->arch.mrc_output_len = pei_data->mrc_output_len;
+		ret = write_seeds_to_cmos(pei_data);
+		if (ret)
+			debug("Failed to write seeds to CMOS: %d\n", ret);
+	}
+
+	writew(0xCAFE, MCHBAR_REG(SSKPD));
+	if (ret)
+		return ret;
+
+	rcba_config();
+
 	return 0;
 }
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index fc2fb5b..2604a68 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -15,6 +15,7 @@
 #include <asm/cpu.h>
 #include <asm/interrupt.h>
 #include <asm/lapic.h>
+#include <asm/microcode.h>
 #include <asm/mp.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>
@@ -195,7 +196,7 @@
 	msr_count = 2 * num_var_mtrrs + NUM_FIXED_MTRRS + 1;
 
 	if ((msr_count * sizeof(struct saved_msr)) > size) {
-		printf("Cannot mirror all %d msrs.\n", msr_count);
+		printf("Cannot mirror all %d msrs\n", msr_count);
 		return -ENOSPC;
 	}
 
@@ -247,8 +248,10 @@
 	if (!stack)
 		return -ENOMEM;
 	params->stack_top = (u32)(stack + size);
-
-	params->microcode_ptr = 0;
+#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP)
+	params->microcode_ptr = ucode_base;
+	debug("Microcode at %x\n", params->microcode_ptr);
+#endif
 	params->msr_table_ptr = (u32)msr_save;
 	ret = save_bsp_msrs(msr_save, sizeof(msr_save));
 	if (ret < 0)
@@ -283,21 +286,25 @@
 }
 
 /* Returns 1 for timeout. 0 on success */
-static int apic_wait_timeout(int total_delay, int delay_step)
+static int apic_wait_timeout(int total_delay, const char *msg)
 {
 	int total = 0;
-	int timeout = 0;
 
+	if (!(lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY))
+		return 0;
+
+	debug("Waiting for %s...", msg);
 	while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY) {
-		udelay(delay_step);
-		total += delay_step;
+		udelay(50);
+		total += 50;
 		if (total >= total_delay) {
-			timeout = 1;
-			break;
+			debug("timed out: aborting\n");
+			return -ETIMEDOUT;
 		}
 	}
+	debug("done\n");
 
-	return timeout;
+	return 0;
 }
 
 static int start_aps(int ap_count, atomic_t *num_aps)
@@ -320,73 +327,42 @@
 
 	debug("Attempting to start %d APs\n", ap_count);
 
-	if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
-		debug("Waiting for ICR not to be busy...");
-		if (apic_wait_timeout(1000, 50)) {
-			debug("timed out. Aborting.\n");
-			return -1;
-		} else {
-			debug("done.\n");
-		}
-	}
+	if (apic_wait_timeout(1000, "ICR not to be busy"))
+		return -ETIMEDOUT;
 
 	/* Send INIT IPI to all but self */
 	lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
 	lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
 		    LAPIC_DM_INIT);
-	debug("Waiting for 10ms after sending INIT.\n");
+	debug("Waiting for 10ms after sending INIT\n");
 	mdelay(10);
 
 	/* Send 1st SIPI */
-	if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
-		debug("Waiting for ICR not to be busy...");
-		if (apic_wait_timeout(1000, 50)) {
-			debug("timed out. Aborting.\n");
-			return -1;
-		} else {
-			debug("done.\n");
-		}
-	}
+	if (apic_wait_timeout(1000, "ICR not to be busy"))
+		return -ETIMEDOUT;
 
 	lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
 	lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
 		    LAPIC_DM_STARTUP | sipi_vector);
-	debug("Waiting for 1st SIPI to complete...");
-	if (apic_wait_timeout(10000, 50)) {
-		debug("timed out.\n");
-		return -1;
-	} else {
-		debug("done.\n");
-	}
+	if (apic_wait_timeout(10000, "first SIPI to complete"))
+		return -ETIMEDOUT;
 
 	/* Wait for CPUs to check in up to 200 us */
 	wait_for_aps(num_aps, ap_count, 200, 15);
 
 	/* Send 2nd SIPI */
-	if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
-		debug("Waiting for ICR not to be busy...");
-		if (apic_wait_timeout(1000, 50)) {
-			debug("timed out. Aborting.\n");
-			return -1;
-		} else {
-			debug("done.\n");
-		}
-	}
+	if (apic_wait_timeout(1000, "ICR not to be busy"))
+		return -ETIMEDOUT;
 
 	lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
 	lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
 		    LAPIC_DM_STARTUP | sipi_vector);
-	debug("Waiting for 2nd SIPI to complete...");
-	if (apic_wait_timeout(10000, 50)) {
-		debug("timed out.\n");
-		return -1;
-	} else {
-		debug("done.\n");
-	}
+	if (apic_wait_timeout(10000, "second SIPI to complete"))
+		return -ETIMEDOUT;
 
 	/* Wait for CPUs to check in */
 	if (wait_for_aps(num_aps, ap_count, 10000, 50)) {
-		debug("Not all APs checked in: %d/%d.\n",
+		debug("Not all APs checked in: %d/%d\n",
 		      atomic_read(num_aps), ap_count);
 		return -1;
 	}
@@ -410,7 +386,7 @@
 			/* Wait for the APs to check in */
 			if (wait_for_aps(&rec->cpus_entered, num_aps,
 					 timeout_us, step_us)) {
-				debug("MP record %d timeout.\n", i);
+				debug("MP record %d timeout\n", i);
 				ret = -1;
 			}
 		}
@@ -430,7 +406,7 @@
 	int ret;
 
 	cpu_get_name(processor_name);
-	debug("CPU: %s.\n", processor_name);
+	debug("CPU: %s\n", processor_name);
 
 	lapic_setup();
 
@@ -587,12 +563,16 @@
 
 int mp_init_cpu(struct udevice *cpu, void *unused)
 {
+	struct cpu_platdata *plat = dev_get_parent_platdata(cpu);
+
 	/*
 	 * Multiple APs are brought up simultaneously and they may get the same
 	 * seq num in the uclass_resolve_seq() during device_probe(). To avoid
 	 * this, set req_seq to the reg number in the device tree in advance.
 	 */
 	cpu->req_seq = fdtdec_get_int(gd->fdt_blob, cpu->of_offset, "reg", -1);
+	plat->ucode_version = microcode_read_rev();
+	plat->device_id = gd->arch.x86_device;
 
 	return device_probe(cpu);
 }
diff --git a/arch/x86/cpu/qemu/fw_cfg.c b/arch/x86/cpu/qemu/fw_cfg.c
index 5ea7a6e..a0a3d08 100644
--- a/arch/x86/cpu/qemu/fw_cfg.c
+++ b/arch/x86/cpu/qemu/fw_cfg.c
@@ -232,8 +232,7 @@
  *          be ignored.
  * @return: 0 on success, or negative value on failure
  */
-static int bios_linker_allocate(struct bios_linker_entry *entry,
-			   unsigned long *addr)
+static int bios_linker_allocate(struct bios_linker_entry *entry, u32 *addr)
 {
 	uint32_t size, align;
 	struct fw_file *file;
@@ -383,7 +382,7 @@
 }
 
 /* This function loads and patches ACPI tables provided by QEMU */
-unsigned long write_acpi_tables(unsigned long addr)
+u32 write_acpi_tables(u32 addr)
 {
 	int i, ret = 0;
 	struct fw_file *file;
diff --git a/arch/x86/cpu/sipi_vector.S b/arch/x86/cpu/sipi_vector.S
index 0c4a157..94c0f5a 100644
--- a/arch/x86/cpu/sipi_vector.S
+++ b/arch/x86/cpu/sipi_vector.S
@@ -193,6 +193,7 @@
 	mov	c_handler, %esi
 	call	*%esi
 
+	/* This matches struct sipi_param */
 	.align	4
 .globl	sipi_params
 sipi_params:
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 485868f..a5cba1c 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -18,6 +18,14 @@
 #include <generated/generic-asm-offsets.h>
 #include <generated/asm-offsets.h>
 
+/*
+ * Define this to boot U-Boot from a 32-bit program which sets the GDT
+ * differently. This can be used to boot directly from any stage of coreboot,
+ * for example, bypassing the normal payload-loading feature.
+ * This is only useful for development.
+ */
+#undef LOAD_FROM_32_BIT
+
 .section .text
 .code32
 .globl _start
@@ -68,6 +76,10 @@
 	/* Save table pointer */
 	movl	%ecx, %esi
 
+#ifdef LOAD_FROM_32_BIT
+	lgdt	gdt_ptr2
+#endif
+
 	/* Load the segement registers to match the GDT loaded in start16.S */
 	movl	$(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax
 	movw	%ax, %fs
@@ -220,3 +232,71 @@
 	.long	0
 	/* entry addr */
 	.long	CONFIG_SYS_TEXT_BASE
+
+#ifdef LOAD_FROM_32_BIT
+	/*
+	 * The following Global Descriptor Table is just enough to get us into
+	 * 'Flat Protected Mode' - It will be discarded as soon as the final
+	 * GDT is setup in a safe location in RAM
+	 */
+gdt_ptr2:
+	.word	0x1f		/* limit (31 bytes = 4 GDT entries - 1) */
+	.long	gdt_rom2	/* base */
+
+	/* Some CPUs are picky about GDT alignment... */
+	.align	16
+.globl gdt_rom2
+gdt_rom2:
+	/*
+	 * The GDT table ...
+	 *
+	 *	 Selector	Type
+	 *	 0x00		NULL
+	 *	 0x08		Unused
+	 *	 0x10		32bit code
+	 *	 0x18		32bit data/stack
+	 */
+	/* The NULL Desciptor - Mandatory */
+	.word	0x0000		/* limit_low */
+	.word	0x0000		/* base_low */
+	.byte	0x00		/* base_middle */
+	.byte	0x00		/* access */
+	.byte	0x00		/* flags + limit_high */
+	.byte	0x00		/* base_high */
+
+	/* Unused Desciptor - (matches Linux) */
+	.word	0x0000		/* limit_low */
+	.word	0x0000		/* base_low */
+	.byte	0x00		/* base_middle */
+	.byte	0x00		/* access */
+	.byte	0x00		/* flags + limit_high */
+	.byte	0x00		/* base_high */
+
+	/*
+	 * The Code Segment Descriptor:
+	 * - Base   = 0x00000000
+	 * - Size   = 4GB
+	 * - Access = Present, Ring 0, Exec (Code), Readable
+	 * - Flags  = 4kB Granularity, 32-bit
+	 */
+	.word	0xffff		/* limit_low */
+	.word	0x0000		/* base_low */
+	.byte	0x00		/* base_middle */
+	.byte	0x9b		/* access */
+	.byte	0xcf		/* flags + limit_high */
+	.byte	0x00		/* base_high */
+
+	/*
+	 * The Data Segment Descriptor:
+	 * - Base   = 0x00000000
+	 * - Size   = 4GB
+	 * - Access = Present, Ring 0, Non-Exec (Data), Writable
+	 * - Flags  = 4kB Granularity, 32-bit
+	 */
+	.word	0xffff		/* limit_low */
+	.word	0x0000		/* base_low */
+	.byte	0x00		/* base_middle */
+	.byte	0x93		/* access */
+	.byte	0xcf		/* flags + limit_high */
+	.byte	0x00		/* base_high */
+#endif
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 84feb19..23156bb 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -5,6 +5,8 @@
 dtb-y += bayleybay.dtb \
 	chromebook_link.dtb \
 	chromebox_panther.dtb \
+	chromebook_samus.dtb \
+	conga-qeval20-qa3-e3845.dtb \
 	cougarcanyon2.dtb \
 	crownbay.dtb \
 	efi.dtb \
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index f85e55c..fb1b31d 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -1,5 +1,7 @@
 /dts-v1/;
 
+#include <dt-bindings/gpio/x86-gpio.h>
+
 /include/ "skeleton.dtsi"
 /include/ "keyboard.dtsi"
 /include/ "serial.dtsi"
@@ -62,115 +64,157 @@
 		intel,duplicate-por;
 	};
 
-	spd {
-		compatible = "memory-spd";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		elpida_4Gb_1600_x16 {
-			reg = <0>;
-			data = [92 10 0b 03 04 19 02 02
-				03 52 01 08 0a 00 fe 00
-				69 78 69 3c 69 11 18 81
-				20 08 3c 3c 01 40 83 81
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 0f 11 42 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 02 fe 00
-				11 52 00 00 00 07 7f 37
-				45 42 4a 32 30 55 47 36
-				45 42 55 30 2d 47 4e 2d
-				46 20 30 20 02 fe 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00];
+	pch_pinctrl {
+		compatible = "intel,x86-pinctrl";
+		u-boot,dm-pre-reloc;
+		reg = <0 0>;
+
+		gpio_a0 {
+			gpio-offset = <0 0>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
 		};
-		samsung_4Gb_1600_1.35v_x16 {
-			reg = <1>;
-			data = [92 11 0b 03 04 19 02 02
-				03 11 01 08 0a 00 fe 00
-				69 78 69 3c 69 11 18 81
-				f0 0a 3c 3c 01 40 83 01
-				00 80 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 0f 11 02 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 80 ce 01
-				00 00 00 00 00 00 6a 04
-				4d 34 37 31 42 35 36 37
-				34 42 48 30 2d 59 4b 30
-				20 20 00 00 80 ce 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00];
-			};
-		micron_4Gb_1600_1.35v_x16 {
-			reg = <2>;
-			data = [92 11 0b 03 04 19 02 02
-				03 11 01 08 0a 00 fe 00
-				69 78 69 3c 69 11 18 81
-				20 08 3c 3c 01 40 83 05
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 0f 01 02 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 80 2c 00
-				00 00 00 00 00 00 ad 75
-				34 4b 54 46 32 35 36 36
-				34 48 5a 2d 31 47 36 45
-				31 20 45 31 80 2c 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				00 00 00 00 00 00 00 00
-				ff ff ff ff ff ff ff ff
-				ff ff ff ff ff ff ff ff
-				ff ff ff ff ff ff ff ff
-				ff ff ff ff ff ff ff ff
-				ff ff ff ff ff ff ff ff
-				ff ff ff ff ff ff ff ff
-				ff ff ff ff ff ff ff ff
-				ff ff ff ff ff ff ff ff
-				ff ff ff ff ff ff ff ff
-				ff ff ff ff ff ff ff ff];
+
+		gpio_a1 {
+			gpio-offset = <0>;
+			mode-gpio;
+			direction = <PIN_OUTPUT>;
+			output-value = <1>;
+		};
+
+		gpio_a3 {
+			gpio-offset = <0 3>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_a5 {
+			gpio-offset = <0 5>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_a6 {
+			gpio-offset = <0 6>;
+			mode-gpio;
+			direction = <PIN_OUTPUT>;
+			output-value = <1>;
+		};
+
+		gpio_a7 {
+			gpio-offset = <0 7>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			invert;
+		};
+
+		gpio_a8 {
+			gpio-offset = <0 8>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			invert;
+		};
+
+		gpio_a9 {
+			gpio-offset = <0 9>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_a10 {
+			u-boot,dm-pre-reloc;
+			gpio-offset = <0 10>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_a11 {
+			gpio-offset = <0 11>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_a12 {
+			gpio-offset = <0 12>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			invert;
+		};
+
+		gpio_a14 {
+			gpio-offset = <0 14>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			invert;
 		};
+
+		gpio_a15 {
+			gpio-offset = <0 15>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			invert;
+		};
+
+		gpio_a21 {
+			gpio-offset = <0 21>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_a24 {
+			gpio-offset = <0 24>;
+			mode-gpio;
+			output-value = <0>;
+			direction = <PIN_OUTPUT>;
+		};
+
+		gpio_a28 {
+			gpio-offset = <0 28>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_b4 {
+			gpio-offset = <0x30 4>;
+			mode-gpio;
+			direction = <PIN_OUTPUT>;
+			output-value = <1>;
+		};
+
+		gpio_b9 {
+			u-boot,dm-pre-reloc;
+			gpio-offset = <0x30 9>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_b10 {
+			u-boot,dm-pre-reloc;
+			gpio-offset = <0x30 10>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_b11 {
+			u-boot,dm-pre-reloc;
+			gpio-offset = <0x30 11>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_b25 {
+			gpio-offset = <0x30 25>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_b28 {
+			gpio-offset = <0x30 28>;
+			mode-gpio;
+			direction = <PIN_OUTPUT>;
+			output-value = <1>;
+		};
+
 	};
 
 	pci {
@@ -185,7 +229,118 @@
 		northbridge@0,0 {
 			reg = <0x00000000 0 0 0 0>;
 			compatible = "intel,bd82x6x-northbridge";
+			board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>,
+					<&gpio_b 11 0>, <&gpio_a 10 0>;
 			u-boot,dm-pre-reloc;
+			spd {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				elpida_4Gb_1600_x16 {
+					reg = <0>;
+					data = [92 10 0b 03 04 19 02 02
+						03 52 01 08 0a 00 fe 00
+						69 78 69 3c 69 11 18 81
+						20 08 3c 3c 01 40 83 81
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 11 42 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 02 fe 00
+						11 52 00 00 00 07 7f 37
+						45 42 4a 32 30 55 47 36
+						45 42 55 30 2d 47 4e 2d
+						46 20 30 20 02 fe 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00];
+				};
+				samsung_4Gb_1600_1.35v_x16 {
+					reg = <1>;
+					data = [92 11 0b 03 04 19 02 02
+						03 11 01 08 0a 00 fe 00
+						69 78 69 3c 69 11 18 81
+						f0 0a 3c 3c 01 40 83 01
+						00 80 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 11 02 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 80 ce 01
+						00 00 00 00 00 00 6a 04
+						4d 34 37 31 42 35 36 37
+						34 42 48 30 2d 59 4b 30
+						20 20 00 00 80 ce 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00];
+					};
+				micron_4Gb_1600_1.35v_x16 {
+					reg = <2>;
+					data = [92 11 0b 03 04 19 02 02
+						03 11 01 08 0a 00 fe 00
+						69 78 69 3c 69 11 18 81
+						20 08 3c 3c 01 40 83 05
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 01 02 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 80 2c 00
+						00 00 00 00 00 00 ad 75
+						34 4b 54 46 32 35 36 36
+						34 48 5a 2d 31 47 36 45
+						31 20 45 31 80 2c 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						ff ff ff ff ff ff ff ff
+						ff ff ff ff ff ff ff ff
+						ff ff ff ff ff ff ff ff
+						ff ff ff ff ff ff ff ff
+						ff ff ff ff ff ff ff ff
+						ff ff ff ff ff ff ff ff
+						ff ff ff ff ff ff ff ff
+						ff ff ff ff ff ff ff ff
+						ff ff ff ff ff ff ff ff
+						ff ff ff ff ff ff ff ff];
+				};
+			};
 		};
 
 		gma@2,0 {
@@ -249,23 +404,29 @@
 				};
 			};
 
-			gpioa {
+			gpio_a: gpioa {
 				compatible = "intel,ich6-gpio";
 				u-boot,dm-pre-reloc;
+				#gpio-cells = <2>;
+				gpio-controller;
 				reg = <0 0x10>;
 				bank-name = "A";
 			};
 
-			gpiob {
+			gpio_b: gpiob {
 				compatible = "intel,ich6-gpio";
 				u-boot,dm-pre-reloc;
+				#gpio-cells = <2>;
+				gpio-controller;
 				reg = <0x30 0x10>;
 				bank-name = "B";
 			};
 
-			gpioc {
+			gpio_c: gpioc {
 				compatible = "intel,ich6-gpio";
 				u-boot,dm-pre-reloc;
+				#gpio-cells = <2>;
+				gpio-controller;
 				reg = <0x40 0x10>;
 				bank-name = "C";
 			};
diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
new file mode 100644
index 0000000..5dd3e57
--- /dev/null
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -0,0 +1,628 @@
+/dts-v1/;
+
+#include <dt-bindings/gpio/x86-gpio.h>
+
+/include/ "skeleton.dtsi"
+/include/ "keyboard.dtsi"
+/include/ "serial.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+	model = "Google Samus";
+	compatible = "google,samus", "intel,broadwell";
+
+	aliases {
+		spi0 = &spi;
+		usb0 = &usb_0;
+		usb1 = &usb_1;
+	};
+
+	config {
+	       silent_console = <0>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "intel,core-i3-gen5";
+			reg = <0>;
+			intel,apic-id = <0>;
+			intel,slow-ramp = <3>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "intel,core-i3-gen5";
+			reg = <1>;
+			intel,apic-id = <1>;
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "intel,core-i3-gen5";
+			reg = <2>;
+			intel,apic-id = <2>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "intel,core-i3-gen5";
+			reg = <3>;
+			intel,apic-id = <3>;
+		};
+
+	};
+
+	chosen {
+		stdout-path = "/serial";
+	};
+
+	keyboard {
+		intel,duplicate-por;
+	};
+
+	pch_pinctrl {
+		compatible = "intel,x86-broadwell-pinctrl";
+		u-boot,dm-pre-reloc;
+		reg = <0 0>;
+
+		/* Put this first: it is the default */
+		gpio_unused: gpio-unused {
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			owner = <OWNER_GPIO>;
+			sense-disable;
+		};
+
+		gpio_acpi_sci: acpi-sci {
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			invert;
+			route = <ROUTE_SCI>;
+		};
+
+		gpio_acpi_smi: acpi-smi {
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			invert;
+			route = <ROUTE_SMI>;
+		};
+
+		gpio_input: gpio-input {
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			owner = <OWNER_GPIO>;
+		};
+
+		gpio_input_invert: gpio-input-invert {
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			owner = <OWNER_GPIO>;
+			invert;
+		};
+
+		gpio_native: gpio-native {
+		};
+
+		gpio_out_high: gpio-out-high {
+			mode-gpio;
+			direction = <PIN_OUTPUT>;
+			output-value = <1>;
+			owner = <OWNER_GPIO>;
+			sense-disable;
+		};
+
+		gpio_out_low: gpio-out-low {
+			mode-gpio;
+			direction = <PIN_OUTPUT>;
+			output-value = <0>;
+			owner = <OWNER_GPIO>;
+			sense-disable;
+		};
+
+		gpio_pirq: gpio-pirq {
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			owner = <OWNER_GPIO>;
+			pirq-apic = <PIRQ_APIC_ROUTE>;
+		};
+
+		soc_gpio@0 {
+			config =
+				<0 &gpio_unused 0>,	/* unused */
+				<1 &gpio_unused 0>,	/* unused */
+				<2 &gpio_unused 0>,	/* unused */
+				<3 &gpio_unused 0>,	/* unused */
+				<4 &gpio_native 0>,	/* native: i2c0_sda_gpio4 */
+				<5 &gpio_native 0>,	/* native: i2c0_scl_gpio5 */
+				<6 &gpio_native 0>,	/* native: i2c1_sda_gpio6 */
+				<7 &gpio_native 0>,	/* native: i2c1_scl_gpio7 */
+				<8 &gpio_acpi_sci 0>,	/* pch_lte_wake_l */
+				<9 &gpio_input_invert 0>,	/* trackpad_int_l (wake) */
+				<10 &gpio_acpi_sci 0>,	/* pch_wlan_wake_l */
+				<11 &gpio_unused 0>,	/* unused */
+				<12 &gpio_unused 0>,	/* unused */
+				<13 &gpio_pirq 3>,	/* trackpad_int_l (pirql) */
+				<14 &gpio_pirq 4>,	/* touch_int_l (pirqm) */
+				<15 &gpio_unused 0>,	/* unused (strap) */
+				<16 &gpio_input 0>,	/* pch_wp */
+				<17 &gpio_unused 0>,	/* unused */
+				<18 &gpio_unused 0>,	/* unused */
+				<19 &gpio_unused 0>,	/* unused */
+				<20 &gpio_native 0>,	/* pcie_wlan_clkreq_l */
+				<21 &gpio_out_high 0>,	/* pp3300_ssd_en */
+				<22 &gpio_unused 0>,	/* unused */
+				<23 &gpio_out_low 0>,	/* pp3300_autobahn_en */
+				<24 &gpio_unused 0>,	/* unused */
+				<25 &gpio_input 0>,	/* ec_in_rw */
+				<26 &gpio_unused 0>,	/* unused */
+				<27 &gpio_acpi_sci 0>,	/* pch_wake_l */
+				<28 &gpio_unused 0>,	/* unused */
+				<29 &gpio_unused 0>,	/* unused */
+				<30 &gpio_native 0>,	/* native: pch_suswarn_l */
+				<31 &gpio_native 0>,	/* native: acok_buf */
+				<32 &gpio_native 0>,	/* native: lpc_clkrun_l */
+				<33 &gpio_native 0>,	/* native: ssd_devslp */
+				<34 &gpio_acpi_smi 0>,	/* ec_smi_l */
+				<35 &gpio_acpi_smi 0>,	/* pch_nmi_dbg_l (route in nmi_en) */
+				<36 &gpio_acpi_sci 0>,	/* ec_sci_l */
+				<37 &gpio_unused 0>,	/* unused */
+				<38 &gpio_unused 0>,	/* unused */
+				<39 &gpio_unused 0>,	/* unused */
+				<40 &gpio_native 0>,	/* native: pch_usb1_oc_l */
+				<41 &gpio_native 0>,	/* native: pch_usb2_oc_l */
+				<42 &gpio_unused 0>,	/* wlan_disable_l */
+				<43 &gpio_out_high 0>,	/* pp1800_codec_en */
+				<44 &gpio_unused 0>,	/* unused */
+				<45 &gpio_acpi_sci 0>,	/* dsp_int - codec wake */
+				<46 &gpio_pirq 6>,	/* hotword_det_l_3v3 (pirqo) - codec irq */
+				<47 &gpio_out_low 0>,	/* ssd_reset_l */
+				<48 &gpio_unused 0>,	/* unused */
+				<49 &gpio_unused 0>,	/* unused */
+				<50 &gpio_unused 0>,	/* unused */
+				<51 &gpio_unused 0>,	/* unused */
+				<52 &gpio_input 0>,	/* sim_det */
+				<53 &gpio_unused 0>,	/* unused */
+				<54 &gpio_unused 0>,	/* unused */
+				<55 &gpio_unused 0>,	/* unused */
+				<56 &gpio_unused 0>,	/* unused */
+				<57 &gpio_out_high 0>,	/* codec_reset_l */
+				<58 &gpio_unused 0>,	/* unused */
+				<59 &gpio_out_high 0>,	/* lte_disable_l */
+				<60 &gpio_unused 0>,	/* unused */
+				<61 &gpio_native 0>,	/* native: pch_sus_stat */
+				<62 &gpio_native 0>,	/* native: pch_susclk */
+				<63 &gpio_native 0>,	/* native: pch_slp_s5_l */
+				<64 &gpio_unused 0>,	/* unused */
+				<65 &gpio_input 0>,	/* ram_id3 */
+				<66 &gpio_input 0>,	/* ram_id3_old (strap) */
+				<67 &gpio_input 0>,	/* ram_id0 */
+				<68 &gpio_input 0>,	/* ram_id1 */
+				<69 &gpio_input 0>,	/* ram_id2 */
+				<70 &gpio_unused 0>,	/* unused */
+				<71 &gpio_native 0>,	/* native: modphy_en */
+				<72 &gpio_unused 0>,	/* unused */
+				<73 &gpio_unused 0>,	/* unused */
+				<74 &gpio_unused 0>,	/* unused */
+				<75 &gpio_unused 0>,	/* unused */
+				<76 &gpio_unused 0>,	/* unused */
+				<77 &gpio_unused 0>,	/* unused */
+				<78 &gpio_unused 0>,	/* unused */
+				<79 &gpio_unused 0>,	/* unused */
+				<80 &gpio_unused 0>,	/* unused */
+				<81 &gpio_unused 0>,	/* unused */
+				<82 &gpio_native 0>,	/* native: ec_rcin_l */
+				<83 &gpio_native 0>,	/* gspi0_cs */
+				<84 &gpio_native 0>,	/* gspi0_clk */
+				<85 &gpio_native 0>,	/* gspi0_miso */
+				<86 &gpio_native 0>,	/* gspi0_mosi (strap) */
+				<87 &gpio_unused 0>,	/* unused */
+				<88 &gpio_unused 0>,	/* unused */
+				<89 &gpio_out_high 0>,	/* pp3300_sd_en */
+				<90 &gpio_unused 0>,	/* unused */
+				<91 &gpio_unused 0>,	/* unused */
+				<92 &gpio_unused 0>,	/* unused */
+				<93 &gpio_unused 0>,	/* unused */
+				<94 &gpio_unused 0>;	/* unused */
+		};
+	};
+
+	pci {
+		compatible = "pci-x86";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		u-boot,dm-pre-reloc;
+		ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
+			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
+			0x01000000 0x0 0x1000 0x1000 0 0xefff>;
+
+		northbridge@0,0 {
+			reg = <0x00000000 0 0 0 0>;
+			compatible = "intel,broadwell-northbridge";
+			board-id-gpios = <&gpio_c 5 0>, <&gpio_c 4 0>,
+					<&gpio_c 3 0>, <&gpio_c 1 0>;
+			u-boot,dm-pre-reloc;
+			spd {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				samsung_4 {
+					reg = <6>;
+					data = [91 20 f1 03 04 11 05 0b
+						03 11 01 08 0a 00 50 01
+						78 78 90 50 90 11 50 e0
+						10 04 3c 3c 01 90 00 00
+						00 80 00 00 00 00 00 a8
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 11 02 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 80 ce 01
+						00 00 55 00 00 00 00 00
+						4b 34 45 38 45 33 30 34
+						45 44 2d 45 47 43 45 20
+						20 20 00 00 80 ce 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00];
+				};
+				hynix-h9ccnnnbltmlar-ntm-lpddr3-32 {
+					/*
+					 * banks 8, ranks 2, rows 14,
+					 * columns 10, density 4096 mb, x32
+					 */
+					reg = <8>;
+					data = [91 20 f1 03 04 11 05 0b
+						03 11 01 08 0a 00 50 01
+						78 78 90 50 90 11 50 e0
+						10 04 3c 3c 01 90 00 00
+						00 80 00 00 00 00 00 a8
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 01 02 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 80 ad 00
+						00 00 55 00 00 00 00 00
+						48 39 43 43 4e 4e 4e 42
+						4c 54 4d 4c 41 52 2d 4e
+						54 4d 00 00 80 ad 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00];
+					};
+				samsung_8 {
+					reg = <10>;
+					data = [91 20 f1 03 04 12 05 0a
+						03 11 01 08 0a 00 50 01
+						78 78 90 50 90 11 50 e0
+						10 04 3c 3c 01 90 00 00
+						00 80 00 00 00 00 00 a8
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 11 02 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 80 ce 01
+						00 00 55 00 00 00 00 00
+						4b 34 45 36 45 33 30 34
+						45 44 2d 45 47 43 45 20
+						20 20 00 00 80 ce 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00];
+				};
+				hynix-h9ccnnnbltmlar-ntm-lpddr3-16 {
+					/*
+					 * banks 8, ranks 2, rows 14,
+					 * columns 11, density 4096 mb, x16
+					 */
+					reg = <12>;
+					data = [91 20 f1 03 04 12 05 0a
+						03 11 01 08 0a 00 50 01
+						78 78 90 50 90 11 50 e0
+						10 04 3c 3c 01 90 00 00
+						00 80 00 00 00 00 00 a8
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 01 02 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 80 ad 00
+						00 00 55 00 00 00 00 00
+						48 39 43 43 4e 4e 4e 42
+						4c 54 4d 4c 41 52 2d 4e
+						54 4d 00 00 80 ad 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00];
+				};
+				hynix-h9ccnnncltmlar-lpddr3 {
+					/*
+					 * banks 8, ranks 2, rows 15,
+					 * columns 11, density 8192 mb, x16
+					 */
+					reg = <13>;
+					data = [91 20 f1 03 05 1a 05 0a
+						03 11 01 08 0a 00 50 01
+						78 78 90 50 90 11 50 e0
+						90 06 3c 3c 01 90 00 00
+						00 80 00 00 00 00 00 a8
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 01 02 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 80 ad 00
+						00 00 55 00 00 00 00 00
+						48 39 43 43 4e 4e 4e 43
+						4c 54 4d 4c 41 52 00 00
+						00 00 00 00 80 ad 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00];
+				};
+				elpida-edfb232a1ma {
+					/*
+					 * banks 8, ranks 2, rows 15,
+					 * columns 11, density 8192 mb, x16
+					 */
+					reg = <15>;
+					data = [91 20 f1 03 05 1a 05 0a
+						03 11 01 08 0a 00 50 01
+						78 78 90 50 90 11 50 e0
+						90 06 3c 3c 01 90 00 00
+						00 80 00 00 00 00 00 a8
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 01 02 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 02 fe 00
+						00 00 00 00 00 00 00 00
+						45 44 46 42 32 33 32 41
+						31 4d 41 2d 47 44 2d 46
+						00 00 00 00 02 fe 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00];
+				};
+			};
+		};
+
+		gma@2,0 {
+			reg = <0x00001000 0 0 0 0>;
+			compatible = "intel,broadwell-igd";
+			intel,dp-hotplug = <6 6 6>;
+			intel,port-select = <1>;	/* eDP */
+			intel,power-cycle-delay = <6>;
+			intel,power-up-delay = <2000>;
+			intel,power-down-delay = <500>;
+			intel,power-backlight-on-delay = <2000>;
+			intel,power-backlight-off-delay = <2000>;
+			intel,cpu-backlight = <0x00000200>;
+			intel,pch-backlight = <0x04000200>;
+			intel,pre-graphics-delay = <200>;
+		};
+
+		me@16,0 {
+			reg = <0x0000b000 0 0 0 0>;
+			compatible = "intel,me";
+			u-boot,dm-pre-reloc;
+		};
+
+		usb_1: usb@14,0 {
+			reg = <0x0000a000 0 0 0 0>;
+			compatible = "xhci-pci";
+		};
+
+		usb_0: usb@1d,0 {
+			status = "disabled";
+			reg = <0x0000e800 0 0 0 0>;
+			compatible = "ehci-pci";
+		};
+
+		pch@1f,0 {
+			reg = <0x0000f800 0 0 0 0>;
+			compatible = "intel,broadwell-pch";
+			u-boot,dm-pre-reloc;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
+						0x80 0x80 0x80 0x80>;
+			intel,gpi-routing = <0 0 0 0 0 0 0 2
+						1 0 0 0 0 0 0 0>;
+			/* Enable EC SMI source */
+			intel,alt-gp-smi-enable = <0x0040>;
+
+			/* EC-SCI is GPIO36 */
+			intel,gpe0-en = <0 0x10 0 0>;
+
+			power-enable-gpio = <&gpio_a 23 0>;
+
+			spi: spi {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "intel,ich9-spi";
+				spi-flash@0 {
+					#size-cells = <1>;
+					#address-cells = <1>;
+					reg = <0>;
+					compatible = "winbond,w25q64",
+							"spi-flash";
+					memory-map = <0xff800000 0x00800000>;
+					rw-mrc-cache {
+						label = "rw-mrc-cache";
+						reg = <0x003e0000 0x00010000>;
+					};
+				};
+			};
+
+			gpio_a: gpioa {
+				compatible = "intel,broadwell-gpio";
+				u-boot,dm-pre-reloc;
+				#gpio-cells = <2>;
+				gpio-controller;
+				reg = <0 0>;
+				bank-name = "A";
+			};
+
+			gpio_b: gpiob {
+				compatible = "intel,broadwell-gpio";
+				u-boot,dm-pre-reloc;
+				#gpio-cells = <2>;
+				gpio-controller;
+				reg = <1 0>;
+				bank-name = "B";
+			};
+
+			gpio_c: gpioc {
+				compatible = "intel,broadwell-gpio";
+				u-boot,dm-pre-reloc;
+				#gpio-cells = <2>;
+				gpio-controller;
+				reg = <2 0>;
+				bank-name = "C";
+			};
+
+			lpc {
+				compatible = "intel,broadwell-lpc";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				u-boot,dm-pre-reloc;
+				intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
+				cros-ec@200 {
+					compatible = "google,cros-ec-lpc";
+					reg = <0x204 1 0x200 1 0x880 0x80>;
+
+					/*
+					 * Describes the flash memory within
+					 * the EC
+					 */
+					#address-cells = <1>;
+					#size-cells = <1>;
+					flash@8000000 {
+						reg = <0x08000000 0x20000>;
+						erase-value = <0xff>;
+					};
+				};
+			};
+		};
+
+		sata@1f,2 {
+			compatible = "intel,wildcatpoint-ahci";
+			reg = <0x0000fa00 0 0 0 0>;
+			u-boot,dm-pre-reloc;
+			intel,sata-mode = "ahci";
+			intel,sata-port-map = <1>;
+			intel,sata-port0-gen3-tx = <0x72>;
+			reset-gpio = <&gpio_b 15 GPIO_ACTIVE_LOW>;
+		};
+
+		smbus: smbus@1f,3 {
+			compatible = "intel,ich-i2c";
+			reg = <0x0000fb00 0 0 0 0>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	tpm {
+		reg = <0xfed40000 0x5000>;
+		compatible = "infineon,slb9635lpc";
+	};
+
+	microcode {
+		update@0 {
+#include "microcode/mc0306d4_00000018.dtsi"
+		};
+	};
+
+};
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
new file mode 100644
index 0000000..478dece
--- /dev/null
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -0,0 +1,278 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/x86-gpio.h>
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+	model = "congatec-QEVAL20-QA3-E3845";
+	compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail";
+
+	aliases {
+		serial0 = &serial;
+		spi0 = &spi;
+	};
+
+	config {
+		silent_console = <0>;
+	};
+
+	pch_pinctrl {
+		compatible = "intel,x86-pinctrl";
+	};
+
+	chosen {
+		stdout-path = "/serial";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "intel,baytrail-cpu";
+			reg = <0>;
+			intel,apic-id = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "intel,baytrail-cpu";
+			reg = <1>;
+			intel,apic-id = <2>;
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "intel,baytrail-cpu";
+			reg = <2>;
+			intel,apic-id = <4>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "intel,baytrail-cpu";
+			reg = <3>;
+			intel,apic-id = <6>;
+		};
+	};
+
+	pci {
+		compatible = "intel,pci-baytrail", "pci-x86";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		u-boot,dm-pre-reloc;
+		ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
+			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
+			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+
+		pch@1f,0 {
+			reg = <0x0000f800 0 0 0 0>;
+			compatible = "pci8086,0f1c", "intel,pch9";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			irq-router {
+				compatible = "intel,irq-router";
+				intel,pirq-config = "ibase";
+				intel,ibase-offset = <0x50>;
+				intel,pirq-link = <8 8>;
+				intel,pirq-mask = <0xdee0>;
+				intel,pirq-routing = <
+					/* BayTrail PCI devices */
+					PCI_BDF(0, 2, 0) INTA PIRQA
+					PCI_BDF(0, 3, 0) INTA PIRQA
+					PCI_BDF(0, 16, 0) INTA PIRQA
+					PCI_BDF(0, 17, 0) INTA PIRQA
+					PCI_BDF(0, 18, 0) INTA PIRQA
+					PCI_BDF(0, 19, 0) INTA PIRQA
+					PCI_BDF(0, 20, 0) INTA PIRQA
+					PCI_BDF(0, 21, 0) INTA PIRQA
+					PCI_BDF(0, 22, 0) INTA PIRQA
+					PCI_BDF(0, 23, 0) INTA PIRQA
+					PCI_BDF(0, 24, 0) INTA PIRQA
+					PCI_BDF(0, 24, 1) INTC PIRQC
+					PCI_BDF(0, 24, 2) INTD PIRQD
+					PCI_BDF(0, 24, 3) INTB PIRQB
+					PCI_BDF(0, 24, 4) INTA PIRQA
+					PCI_BDF(0, 24, 5) INTC PIRQC
+					PCI_BDF(0, 24, 6) INTD PIRQD
+					PCI_BDF(0, 24, 7) INTB PIRQB
+					PCI_BDF(0, 26, 0) INTA PIRQA
+					PCI_BDF(0, 27, 0) INTA PIRQA
+					PCI_BDF(0, 28, 0) INTA PIRQA
+					PCI_BDF(0, 28, 1) INTB PIRQB
+					PCI_BDF(0, 28, 2) INTC PIRQC
+					PCI_BDF(0, 28, 3) INTD PIRQD
+					PCI_BDF(0, 29, 0) INTA PIRQA
+					PCI_BDF(0, 30, 0) INTA PIRQA
+					PCI_BDF(0, 30, 1) INTD PIRQD
+					PCI_BDF(0, 30, 2) INTB PIRQB
+					PCI_BDF(0, 30, 3) INTC PIRQC
+					PCI_BDF(0, 30, 4) INTD PIRQD
+					PCI_BDF(0, 30, 5) INTB PIRQB
+					PCI_BDF(0, 31, 3) INTB PIRQB
+
+					/*
+					 * PCIe root ports downstream
+					 * interrupts
+					 */
+					PCI_BDF(1, 0, 0) INTA PIRQA
+					PCI_BDF(1, 0, 0) INTB PIRQB
+					PCI_BDF(1, 0, 0) INTC PIRQC
+					PCI_BDF(1, 0, 0) INTD PIRQD
+					PCI_BDF(2, 0, 0) INTA PIRQB
+					PCI_BDF(2, 0, 0) INTB PIRQC
+					PCI_BDF(2, 0, 0) INTC PIRQD
+					PCI_BDF(2, 0, 0) INTD PIRQA
+					PCI_BDF(3, 0, 0) INTA PIRQC
+					PCI_BDF(3, 0, 0) INTB PIRQD
+					PCI_BDF(3, 0, 0) INTC PIRQA
+					PCI_BDF(3, 0, 0) INTD PIRQB
+					PCI_BDF(4, 0, 0) INTA PIRQD
+					PCI_BDF(4, 0, 0) INTB PIRQA
+					PCI_BDF(4, 0, 0) INTC PIRQB
+					PCI_BDF(4, 0, 0) INTD PIRQC
+				>;
+			};
+
+			spi: spi {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "intel,ich9-spi";
+				spi-flash@0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					reg = <0>;
+					compatible = "stmicro,n25q064a",
+						"spi-flash";
+					memory-map = <0xff800000 0x00800000>;
+					rw-mrc-cache {
+						label = "rw-mrc-cache";
+						reg = <0x006f0000 0x00010000>;
+					};
+				};
+			};
+
+			gpioa {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0 0x20>;
+				bank-name = "A";
+			};
+
+			gpiob {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x20 0x20>;
+				bank-name = "B";
+			};
+
+			gpioc {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x40 0x20>;
+				bank-name = "C";
+			};
+
+			gpiod {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x60 0x20>;
+				bank-name = "D";
+			};
+
+			gpioe {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x80 0x20>;
+				bank-name = "E";
+			};
+
+			gpiof {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0xA0 0x20>;
+				bank-name = "F";
+			};
+		};
+	};
+
+	fsp {
+		compatible = "intel,baytrail-fsp";
+		fsp,mrc-init-tseg-size = <0>;
+		fsp,mrc-init-mmio-size = <0x800>;
+		fsp,mrc-init-spd-addr1 = <0xa0>;
+		fsp,mrc-init-spd-addr2 = <0xa2>;
+		fsp,emmc-boot-mode = <2>;
+		fsp,enable-sdio;
+		fsp,enable-sdcard;
+		fsp,enable-hsuart1;
+		fsp,enable-spi;
+		fsp,enable-sata;
+		fsp,sata-mode = <1>;
+		fsp,enable-lpe;
+		fsp,lpss-sio-enable-pci-mode;
+		fsp,enable-dma0;
+		fsp,enable-dma1;
+		fsp,enable-i2c0;
+		fsp,enable-i2c1;
+		fsp,enable-i2c2;
+		fsp,enable-i2c3;
+		fsp,enable-i2c4;
+		fsp,enable-i2c5;
+		fsp,enable-i2c6;
+		fsp,enable-pwm0;
+		fsp,enable-pwm1;
+		fsp,igd-dvmt50-pre-alloc = <2>;
+		fsp,aperture-size = <2>;
+		fsp,gtt-size = <2>;
+		fsp,scc-enable-pci-mode;
+		fsp,os-selection = <4>;
+		fsp,emmc45-ddr50-enabled;
+		fsp,emmc45-retune-timer-value = <8>;
+		fsp,enable-igd;
+		fsp,enable-memory-down;
+		fsp,memory-down-params {
+			compatible = "intel,baytrail-fsp-mdp";
+			fsp,dram-speed = <2>;		/* 2=1333MHz */
+			fsp,dram-type = <1>;		/* 1=DDR3L */
+			fsp,dimm-0-enable;
+			fsp,dimm-1-enable;
+			fsp,dimm-width = <1>;		/* 1=x16, 2=x32 */
+			fsp,dimm-density = <2>;		/* 2=4Gbit */
+			fsp,dimm-bus-width = <3>;	/* 3=64bits */
+			fsp,dimm-sides = <0>;		/* 0=1 ranks -> 0x2b */
+
+			/* These following values might need a re-visit */
+			fsp,dimm-tcl = <8>;
+			fsp,dimm-trpt-rcd = <8>;
+			fsp,dimm-twr = <8>;
+			fsp,dimm-twtr = <4>;
+			fsp,dimm-trrd = <6>;
+			fsp,dimm-trtp = <4>;
+			fsp,dimm-tfaw = <22>;
+		};
+	};
+
+	microcode {
+		update@0 {
+#include "microcode/m0130673322.dtsi"
+		};
+		update@1 {
+#include "microcode/m0130679901.dtsi"
+		};
+	};
+};
diff --git a/arch/x86/dts/microcode/m7240651_0000001c.dtsi b/arch/x86/dts/microcode/m7240651_0000001c.dtsi
new file mode 100644
index 0000000..ab96017
--- /dev/null
+++ b/arch/x86/dts/microcode/m7240651_0000001c.dtsi
@@ -0,0 +1,1328 @@
+/*
+ * Copyright (c) <1995-2015>, Intel Corporation.
+ * All rights reserved.
+ * Redistribution. Redistribution and use in binary form, without modification, are
+ * permitted provided that the following conditions are met:
+ *	.Redistributions must reproduce the above copyright notice and the following
+ * disclaimer in the documentation and/or other materials provided with the
+ * distribution.
+ *	.Neither the name of Intel Corporation nor the names of its suppliers may be used
+ * to endorse or promote products derived from this software without specific prior
+ * written permission.
+ *	.No reverse engineering, decompilation, or disassembly of this software is
+ * permitted.
+ *	."Binary form" includes any format commonly used for electronic conveyance
+ * which is a reversible, bit-exact translation of binary representation to ASCII or
+ * ISO text, for example, "uuencode."
+ * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date: Wed Jan 7 17:15:10 CST 2015
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x1c>;
+intel,date-code = <0x7032014>;
+intel,processor-signature = <0x40651>;
+intel,checksum = <0x4f9aa4c4>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x72>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+	0x01000000	0x1c000000	0x14200307	0x51060400
+	0xc4a49a4f	0x01000000	0x72000000	0xd04f0000
+	0x00500000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xa1000000	0x01000200	0x1c000000
+	0x02000000	0x31130000	0x02071420	0x31130000
+	0x01000000	0x51060400	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x36358054	0x2a09425b	0x907d339f	0xe56a8e53
+	0x877c79ee	0xe74bb340	0x4ada5820	0x1f5b6602
+	0xa30893a1	0xb7c4195b	0x5b421b4a	0xf6746a7d
+	0x93416281	0x0596553a	0x0b287554	0x589d31e7
+	0xa74c6248	0x30f07a50	0x6ad9323b	0x68401630
+	0xf5d28452	0x15295b72	0x80923cf6	0x42c1b744
+	0xb3a77ce6	0xe763f1d6	0x3c1ff5cd	0xa180d141
+	0xb13139cc	0xa944a5f7	0x7df76b7f	0x5fa445fc
+	0x365898f0	0x2e7e2d65	0xf3b12403	0x8c54b924
+	0xa5e7ca7b	0x79bfdedc	0x22590127	0x06c6830c
+	0xb7ee2c3d	0xc8eec561	0xc699686b	0x3105503e
+	0x44fa8bf0	0xf4a804b3	0x13f7e8ce	0x86c71229
+	0x4cc3e6fa	0x602929a5	0x89e3637d	0x017a25aa
+	0x5450b21f	0x76c63f96	0xd39fcb5b	0xa469f358
+	0xb2bee3f6	0xb05e8ba5	0xa4ebc733	0x668bfe37
+	0x03447100	0x4e0cfdf0	0x962912aa	0x84b1559a
+	0x07152000	0x3a6efbc9	0xc860ab11	0x846eff80
+	0xddab7ac3	0x7531c20f	0x348cb1b0	0x6c80ecf1
+	0x11000000	0x8e6aec93	0x0e9ee5e7	0x63a85483
+	0x70cc3265	0x6e1f946b	0x15b0efe6	0x72063a81
+	0x34a1d64b	0x2eaed2e7	0x17fd01b8	0xb10d73c6
+	0xc670afff	0x563a9699	0x48242b55	0x4f24da06
+	0x9470dbbd	0x43bd1bc4	0xdabd6685	0x2bb03087
+	0x3618fc0f	0xf583f057	0xf9b47ebc	0x900c7293
+	0x82e048b9	0xc2296a64	0xa65c78ab	0x29ded622
+	0xee3266ad	0x05c481f7	0x9f188cab	0x8848f8e9
+	0xdd1ec9df	0x9e22427c	0x2e0b3f71	0x6288ecbf
+	0x761404d7	0xdfc9cd30	0x9747886a	0x5015f54d
+	0x9ad0e3e6	0xf3af632b	0x9a7a43be	0x7e6abc2b
+	0xac4ccd36	0x835d3a4c	0xa15be322	0x9dcf0226
+	0x166b5090	0xae4d5ead	0x6ce702fd	0xf1faec41
+	0x6a658558	0x4729daf1	0xea026e9a	0x63b58a33
+	0x3e7ade73	0x04101380	0xc56229d8	0xef888c8e
+	0xfad2e07a	0x2ac82034	0x5c792e20	0x04940d3a
+	0x0879333d	0x6df5c8c1	0x9a5f9d1a	0x4d4c298d
+	0xf0a44f05	0xba3ceb1f	0x1ff4ca1f	0xfa8dce36
+	0x44567615	0x8dc04157	0x16e758d2	0x761fd567
+	0xf6fc6ee1	0xe97a8753	0x3f053256	0x6935fc3e
+	0x382e2021	0xef7d3659	0x1bc3e873	0x94b35855
+	0x26fe0138	0xadf191a2	0x1c5753b8	0x5b84d843
+	0xde9e9a91	0x904daf5e	0xb6b66c98	0x0b632a82
+	0x9ee70409	0xb6ca0da2	0x250b4705	0x6911dc62
+	0x15cee70d	0x8afdcad4	0xfab41622	0xdf58a63b
+	0x79b84df8	0xc05e3694	0x6b6cd7ff	0xd00350cf
+	0xddd6b82a	0x0ce97cb8	0xc441b377	0xd1d2bde9
+	0xca3c3405	0x13780a0d	0x22da23cc	0xc9f3aebb
+	0xd035bb82	0x277ed9c8	0xf0072c06	0x4367fc31
+	0x6eb8d7a5	0x4a9a39fb	0x98a20cea	0x0c6fc545
+	0xe034e39d	0x2287802b	0xee0fb9dc	0x39048886
+	0x0f52b54b	0x3fcd8c2f	0xf55411b3	0xc137b076
+	0x0d72cfc8	0x5e12539e	0xd6b15a49	0x8f0909dc
+	0xe569ff90	0xfa2eb54f	0x04be7de0	0x0ece5d50
+	0x8e353099	0x953a24c7	0xb376aeac	0xed2c7023
+	0xa82bba36	0xd6a4f612	0xdfa59162	0x5197e043
+	0x06866ed8	0x73d1b8e5	0x387fcf84	0x2d732a5a
+	0x57ec8dea	0xbdb45a07	0x05ea9330	0x2346dc7d
+	0x7dc0ea9e	0x5e6cae0b	0x5fd87011	0xe55c5854
+	0x30594b42	0xd02e966f	0x70c19162	0x3b249ada
+	0x60a41a7a	0x6b42fe07	0xefbc0f3e	0x2e5ef6e6
+	0x9866a716	0x74c9e22e	0x42d02dd4	0xc2d4b260
+	0xe90dca84	0x8214321b	0xe74708d8	0xc99fcf97
+	0x624eadab	0x34755e4c	0x3d4a47ba	0xe16f384b
+	0x4abdd3b1	0x48e7f266	0x297d99ff	0xcb5e9a7f
+	0x9746b708	0xe351ffd5	0x080fe8f0	0x50378abc
+	0x50b1c296	0x82dd3d99	0x1aadfcb1	0xed57c439
+	0xa987788e	0xc2851395	0x7725195e	0xe64bce5e
+	0xce0caad8	0xddb09dda	0x0556a6f0	0xfb33e1cb
+	0x7c182dd6	0x215cd643	0x2b51ffd9	0x0f671e2c
+	0x112f8694	0x6f87d52a	0x79f44703	0x9a9d7c83
+	0xb5cf88d5	0xbebc8431	0x9d20294d	0xfa3115b1
+	0x5f6060cf	0x2ec28285	0x84ec0af8	0x92097756
+	0x0e2708b0	0x47021fe6	0x82ca965b	0xd7a6f6dd
+	0x9f30fda8	0xf0eb375a	0x2259c589	0x43e9d3a1
+	0x577f43c7	0xb9c36787	0x09e4ac2a	0x65eaffd3
+	0x82336701	0x4dcc6230	0x0ea73cdc	0x3f82ec72
+	0xf0fc3d01	0x0f3cea3c	0x92986f5c	0x8b230104
+	0xa9c9f5d0	0x3a36d583	0xfe4a5920	0xf72516f3
+	0x4dbfd936	0xe2109d97	0x2196ec82	0x7eda7515
+	0x07b1481e	0x763427cf	0xcec66b8f	0xf1a168c4
+	0xe24d3019	0xde4a518a	0x49eda80d	0x58a3bb89
+	0x7fe6cd4f	0x876a231b	0xc4349cbd	0x24761ec3
+	0x941b4e8d	0x485a71ca	0x13b5aa57	0x7a0901dc
+	0xbc6a5361	0x226eb69a	0xacace9c3	0xc13d79f9
+	0x3e7dd201	0x0a3b78ec	0x0a7b8a7f	0x32bd5289
+	0x0079f978	0x745016ea	0x4f9b3b6a	0x45be9469
+	0xdb78b297	0x59107a2d	0x4d589a2a	0x71f90231
+	0xfdedd23d	0x8107d475	0xf7b38bbd	0xade2c969
+	0x3d452429	0x11a671f9	0x206a4cc4	0xf0dd5864
+	0x8d944e34	0x94108699	0xce16c2ff	0xac44a546
+	0x8022e1a0	0xd0bd4223	0x3a1564d2	0x10557cef
+	0x4bdb2f98	0xe16180aa	0x06cbb4ee	0xbb244e1c
+	0xd07a1335	0xb0e783d3	0x985b51b3	0x9c78ab34
+	0x017167c6	0xc69e173a	0x837f1b8e	0x582295bc
+	0x06c58c52	0x96e40ebb	0xc7201a04	0x64175c43
+	0xe5bfffc5	0x66adad7a	0xb5497cba	0x551f9616
+	0xb073a953	0x22c3b782	0x00d30861	0x565f461e
+	0xdf0c5bde	0x43c8b41d	0x8d0684dc	0xa8866b74
+	0x90b68be1	0xc3e6319c	0xdb45be3f	0xbc70cd9f
+	0xbbe3f1eb	0x6aed93f2	0x5f3ccc9a	0xa7d4d8c2
+	0x0e0ff1b4	0xdeaa088f	0xe358f67f	0xe4871f57
+	0x20109153	0x6cc1ab8e	0xe643de66	0x1d3e3186
+	0xf2381609	0xcfd2ab4f	0x06884af6	0xc4f3a934
+	0x8cb92e34	0xf821a26d	0x3dadc95d	0xa45c233f
+	0x29ae3af1	0x0dae8ae5	0xb0060fbb	0x07ce4601
+	0xd1ee82db	0x5eb3a5b8	0xaff1d25a	0xcdfa04c9
+	0x4d68b29c	0xc1dc4c66	0x8c05838b	0xad4b143a
+	0xfbe918d8	0xe378431a	0xc7e27e08	0xe81258c4
+	0xf10507d1	0x37dc0b04	0xd6cedc24	0x0971915d
+	0x17b54465	0x6dea1b32	0x5a4bc7b4	0x7119b193
+	0xa04dd0db	0xadfd8091	0x5b205c9b	0xe03b128e
+	0x98e35227	0xb449ab74	0xae90803b	0x954f568e
+	0xb9eb58ae	0x71b72a7c	0x59458b8d	0xb059ae4a
+	0x4b72573d	0x18f32453	0x5b4f6b3f	0x69ddc2a7
+	0x3e2fcc75	0x091ed858	0xdd5d4a72	0x86353700
+	0x27fc1bfe	0xc4d8eeeb	0xddf44d9f	0x0f15d7a3
+	0x991dcfd4	0x00386677	0xee2673ba	0x1dbb99f7
+	0xa111f717	0x9634680b	0x62437316	0xfac01e1c
+	0xd50676bd	0xaacf0ede	0xe1d7a34f	0xfecab518
+	0xcbd1de86	0xa426eb84	0x1bd25ae1	0x5a132262
+	0x2b611348	0x0d1635f4	0xefcdb98b	0xbcbefec0
+	0x68a28e90	0x6dec1461	0x2c7772de	0xf263e32d
+	0xffca07ac	0xd267134d	0x204ecb5c	0x0c48c2b8
+	0xf1880ad4	0x04af8a4c	0xdfea69ec	0xd403d608
+	0xc2726b1d	0x7922cb45	0x57a4189c	0xd5fceeb1
+	0x8abe5b6f	0x63da5686	0xef01bd5a	0xa90f3abd
+	0x48b8f807	0xdae82347	0x04748a1c	0x0dc6e20e
+	0x1037d7f4	0x50dd982e	0x93532642	0x51ae7c60
+	0x5ad6d25a	0x0aae3f44	0xc1da2b21	0xe7f1ef94
+	0x3dd8d08f	0x2987f4f3	0xeb3e61aa	0xaf162753
+	0x557bf622	0x62d57d19	0x19c6bb30	0xb8a52c45
+	0x84551269	0x8ffd8fbe	0x4138c3cd	0x4fdffa1a
+	0x0a7b326c	0x36e6fe1f	0x3d313ebc	0x2ff07422
+	0xabd14b1d	0x61f6f7ad	0xba5daec6	0xce7cc665
+	0xb401bad8	0x5ec17e06	0x9781d9cd	0x4d813af6
+	0xb1f33ea6	0xb77a0f3a	0x9712140b	0xfddf16bd
+	0xc907de80	0x9154855b	0x17795d77	0x80990379
+	0xa2b5f0c4	0xf389d17a	0x2c8e805b	0xf8486c6e
+	0x1a294bea	0xfb534124	0x7a3866d8	0x7fd8ba0f
+	0x9726fd37	0xcc688de3	0xbeb96bd5	0x3c18e90f
+	0xc78642fe	0x4e8f23a9	0xfebac657	0xda647c7e
+	0xc6b3f0f5	0x394817f2	0xbdaa2296	0xd1adb9bf
+	0xf3839d7a	0x40c9cd22	0x40d1aed0	0x1c2a84b2
+	0xde0e3519	0x83ea4c84	0xb624f803	0xd1806a2d
+	0xf53472cc	0xf922e564	0xc13e4668	0x5aa22cc2
+	0x0b48fbf6	0x3435df92	0x853a14cd	0xd197a7cb
+	0xeb4030ab	0xda2c86aa	0x5abb8deb	0xe77bf872
+	0x93be7405	0xe8a46779	0x18563dc4	0x0f8bf495
+	0xf1845360	0xd0bbd749	0x24ffe620	0x61ad9188
+	0x81fb37be	0xacc94ca1	0x5da13717	0xc8648c0d
+	0xcdd81ef3	0x381abaae	0x9835b799	0x11e758fb
+	0x2a0acde2	0x0fe63aba	0x28418753	0xf6d96bca
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+	0xef226386	0x20e7130c	0x1f9b12ab	0xb07b30ad
+	0xdd75d29d	0x09eb3647	0x06294756	0xefe36da0
+	0x0d601f05	0x11f98b78	0xc8134be8	0x04b69ec6
+	0x6df37e2a	0xeb0d9335	0xf7b87d27	0xff234b32
+	0xdc7d9fc9	0xe0b92f02	0x11aa6f37	0x42310d88
+	0xe64b36e0	0x2069733d	0x4c1b80fe	0xb6269ec7
+	0x02c85bb1	0xc63c207a	0xe3ce412e	0x90cc4eaf
+	0x88330bf0	0xba4c2e47	0x9efac5f5	0xea829249
+	0xd4373cae	0x1dc54d9c	0x18b04744	0x4ec0f396
+	0xad95f8db	0x14732778	0x812632c8	0x12a39947
+	0x2497f5a1	0x940abdcd	0x4b340eaf	0xbb52e0fc
+	0x6992bbde	0x3180705b	0x5f15dda6	0x7ee9a828
+	0x5dd3a447	0xb81da4bc	0x898c4ed4	0xd4cfa48e
+	0x3e648720	0xa061535c	0x38b0d519	0x714ea4e1
+	0x6558aaba	0x2e5d9832	0x32b10cb3	0x12f74683
+	0x8a2d1272	0x8bfea89d	0xb9b0d38a	0xc62060b8
+	0x4d6c0796	0xdde515af	0x4e69b74e	0xf9e066cb
+	0x1178ccc0	0x8c49629f	0xb18e62f7	0x82570fb4
+	0x679990e3	0xeac06852	0x845ad85e	0x66fcdced
+	0xcc8bab2a	0x4cccd967	0xa909d3da	0x16f2b84f
+	0xff70b687	0x8e964680	0x3e490510	0xcc15ff7a
+	0xffb0a318	0x30085e27	0x0c6294e7	0xf092ff84
+	0x1e8ae3ef	0xd9f4135f	0x4eeb655b	0x0b133b0e
+	0x0da4c728	0x8a9ee7d2	0x7b0579a9	0xac385286
+	0x5c9ac211	0xb0674a9c	0xe533403a	0x4dced95c
+	0x035f6f44	0xec76b93e	0xfb6db00d	0xa4ab917d
+	0xae515afe	0xaac11faa	0x78bafa84	0x5a67e774
+	0xd2c3b6b8	0x6708f12b	0x867c2e37	0x826e1ee4
+	0x4b4ba1a4	0x4d93d7cc	0xb82afd9d	0xfa715ef8
+	0x17de030b	0x2e1a71ab	0xb567360c	0xfd8f16c1
+	0x5160138f	0xd9384a40	0x345b1c4b	0x058993ea
+	0x3fcae8d7	0x4dc2e776	0x327b2dd1	0xe7d1d383
+	0xfa10dfcb	0x5ba3c956	0x54db7d48	0x37fb2526
+	0x055a1158	0x7796bad7	0xbd5a4832	0x33f01c7f
+	0xf5fc6313	0xa7298449	0x43b6e7ce	0xfd3d144a
+	0x087127c7	0xb11d0a54	0x792d388f	0x477ad5e6
+	0x7cff7375	0x17a424ab	0x4e798c03	0xae4b553d
+	0x02c30177	0x82f30375	0x98b98ed7	0x8f741f98
+	0x7e777486	0x6ad3d150	0x1c2a0d72	0x3ea2735a
+	0xd5d5116c	0x9d12505a	0x70a402b1	0x615c72a7
+	0x637f3650	0x99b10cb4	0x6a0de436	0x15621e35
+	0x61194a84	0xd34ee0d7	0xfdd70d84	0x8aca1c6d
+	0xfac6878e	0xfa7b5771	0x3022330f	0xa7ed23ee
+	0xe9763f69	0xc4d38e3c	0xa5fc726a	0xde7dbc91
+	0x65ad5383	0x7f7ad77f	0x8516fbc9	0x9623d563
+	0xcf8685c5	0x59f21315	0xc1b6b1d0	0x15eecc50
+	0x9009f44b	0x7a2a8ad7	0x766a354e	0x59a6b09d
+	0x4cca7284	0xf6ef4ec7	0x388c54e5	0x3d34a34c
+	0x49a780a3	0xc7a8bbfc	0xf25d8bec	0xf6a390f2
+	0x1cc94fda	0xf37f034e	0x2be39e36	0x760d4f1e
+	0xdfcd71e7	0x55ed5a16	0x0bb9b028	0xe533d067
+	0x033f76bd	0x8ee3d55b	0xa3e59542	0x4fdb93a2
+	0xb47a605f	0xd0a02253	0x948c4cc9	0x4dededec
+	0x715c7873	0x88bfe017	0x11095c7f	0x0f71d898
+	0x25837d56	0x8a276147	0xd09ff4b8	0x2c4fae22
+	0x2730915b	0xbb1fda31	0xd5cc59a8	0xd8dc28f6
+	0x12f2080c	0x4ad77d75	0x223648a3	0x73abafa4
+	0xfc9554f8	0x4cbaae79	0xdffe60f7	0x0a98e937
+	0xa8a8af70	0xd3cc1f77	0xae09e4ab	0x14f0caa3
+	0x63b21bc6	0x0a086fdf	0xa1a7b1a1	0x3314cbd4
+	0xb1732177	0x842a7e12	0x37ed7860	0x720daee9
+	0x2eeb8d06	0xb0098553	0x8cca4537	0x2a1c4180
+	0xf1f10adc	0x66d21bbf	0xdae7b1dd	0x030f8be5
+	0x184ef28c	0x4a1082b0	0xf5f73b3f	0x2bc852bc
+	0x1893287c	0x7e1c6291	0x8272ba61	0x2aef57e0
+	0xec90742c	0xf9d46e63	0x85e84eef	0xd32c10c2
+	0xfa96b003	0x0fa221a7	0x9bdee2e2	0x9cee99df
+	0x4071e863	0x3b4af098	0x15148a99	0xd525d447
+	0x1e8be181	0x73cd75fd	0x2f1e91da	0x9c7531a1
+	0x23c109e6	0x5172cf8b	0x69ca62a0	0x754c25f1
+	0xfa3a0cca	0x6201622b	0xc7cd058f	0x5d5ee3f5
+	0xda0a4d69	0xcded309c	0x5bd1fc91	0x1fa74d7c
+	0x65bb3381	0x0811c460	0xbe6efec8	0x41edba24
+	0xe2237b32	0xbded2338	0xe923a277	0x90732deb
+	0x73820616	0x53fd3be6	0x30df290f	0x0529d627
+	0x5216acf0	0x0df2f5e6	0xb7aae7fe	0x77a86a6e
+	0x216c1fb6	0xde9d0bca	0x4c38b816	0x803cab8e
+	0x4653e80d	0xe5323d3d	0x98336658	0xe9330b0b
+	0xf5d154d1	0x2574745c	0x0b8b22e4	0x01cb6d85
+	0x7fd416a7	0xa74c5c80	0x1752811d	0x3fcfa0d8
+	0x1740f342	0x298908ba	0x8acda280	0x63fe7f51
+	0x697caa20	0x46772da7	0x6a2f5e16	0x8d56e593
+	0xed1df3f8	0x8a8f59d1	0x7660da2f	0x805c1ba3
+	0xf2b7438d	0xc175237d	0xb7e4002a	0x38cf4010
+	0xd7884e26	0x60e3abc8	0x3e3ce1df	0xb90f753b
+	0xc3836140	0x2724bc78	0xd1014b33	0x7aad6cc2
+	0x502bb788	0x3cd6c11b	0xca0e8132	0x23a5f680
+	0x7fa541a1	0x2c73ce32	0x266d5568	0x26dca072
+	0xc0e425dd	0x04241fa6	0x102e59e1	0xc1ac9846
+	0x59e6807d	0xf7dd1309	0x4bf082da	0x43cd88b7
+	0x5628e73d	0xd244c48b	0x7bc83d1d	0xc0fb8023
+	0xd0d24f43	0x27c17ca3	0x486f80a5	0xae90bd2b
+	0xbe4e4d0c	0xba06936a	0xd95432ac	0x84fcced7
+	0xa70c8cc9	0xc6b18bea	0xe01f8516	0x658ac202
+	0x63443276	0xc3626cac	0x0dceb29b	0xba20f2e7
+	0xaf50a259	0x1f7332f4	0x43885c55	0xf5dbfbb0
+	0x3174f3c4	0x5081d664	0x9309dab9	0xd2ef2193
+	0xbf01e367	0x44eac6f6	0x5a639230	0x53edebd1
+	0x15581102	0x785a8122	0xea11c074	0x04003b30
+	0x45c97b31	0xb5fdff79	0x16ed5a0f	0xb2ab6eaf
+	0x524d6293	0x73df9c8d	0x1a6d65d5	0x442d7abc
+	0x4f260f88	0x3078b81d	0x87e6b52d	0xc3bad689
+	0x55093e7d	0x9fdbb5b3	0xb805940d	0xbe18f822
+	0xfd262e29	0xc9eb61b4	0xabddb5a6	0x3ef2e4a6
+	0xfb8c082a	0xd6b8c59f	0xa710b259	0x36dd9814
+	0xaffee9e4	0xb7f3471a	0xbb9356fc	0x44600752
+	0x374907e2	0xfafc6297	0x20fd0007	0x05f324c3
+	0xa2037e3a	0x10ab66c7	0xe44175a1	0xaa4ee6bc
+	0xe45a8ce6	0x020af65b	0x5e059ff8	0x98cc3cf1
+	0x06019b96	0x6d1c1922	0xdd0a2e8d	0x86837333
+	0x1a3e36d3	0x17e2e5f2	0xb32ef76b	0x559915a2
+	0xf9c22b32	0x079ee5dc	0x7a3d401a	0x60a10dd4
+	0x053758ce	0x2e005b70	0x3685e353	0xf4b6460b
+	0xc7d789c8	0xc8ea82f2	0x8fc74f86	0x9f68e92d
+	0x5a1e00ed	0xd0e8fada	0x197640c3	0xeaa6e62a
+	0x023a7169	0xcc7fb17b	0x98dac1fe	0xe6c807a6
+	0x0560e399	0x9fb5e511	0x0882c18e	0xf4d767f0
+	0xb508a6e8	0xd27d2026	0x4681cbc7	0xadd7f6ba
+	0x35f47df4	0xc72245c5	0x8e8b8a74	0xeb94e799
+	0x8396bff2	0x6c2bf652	0x1562b482	0x5e1d2d57
+	0xdff1c004	0xa29b50e6	0xff880a97	0x7fc22f15
+	0x89633cb9	0xd0ab4601	0xe7341887	0xc07bb55e
+	0x71eb0aaa	0x4c0f2ba5	0xa7801724	0xf43a7964
+	0x434daf5a	0x68eedb3c	0x194eca3d	0x0bbfeeba
+	0x67850a32	0xd23b1ae1	0xa6911d9b	0xce700d81
+	0x783928d1	0xae5c120d	0x71fa13b0	0x2006c22b
+	0xf72f5d3d	0x1cd744de	0x0d9fc67f	0xafe8d24a
+	0x82b5142f	0x2bbf5368	0x17959168	0x09655f9d
+	0xcab7fad9	0x51e66c7a	0x2420988f	0x847754b5
+	0x0a4974ae	0xfa654071	0xcc725340	0x6fa4583a
+	0xca3082e7	0xc0f9ce55	0xd7d2cadb	0x79a92e96
+	0x22298333	0x57c27396	0xc74fa5e2	0x4afe8a75
+	0xcf697c69	0x4f76031d	0x4621473c	0xad0abf11
+	0xc82cd007	0x2bbad261	0x39318b1c	0xdcb0e1a8
+	0x31ea902c	0x6e550361	0x784be9d0	0xb14a31e3
+	0xca23cfd2	0xa43e7604	0x72ebff4c	0xed80ec25
+	0x43baaa63	0x880434aa	0x36a6e985	0xc173ddfc
+	0x11f1dd14	0xc7ee29ec	0xaebdcf8a	0x4c8445d5
+	0xaa772022	0x024d91b3	0x048082d0	0xcbaefb3d
+	0x4b09b3a9	0x12cf71ef	0x7db43f55	0x93cdd0c1
+	0xa076bad7	0xb46de6fa	0x417dc418	0x324da83a
+	0xff365817	0x155f3cdd	0xdac35be4	0x2fd2c82c
+	0x11f1bc33	0xedce1813	0x6d7c9f85	0x5c114653
+	0x01c57aae	0x1b96107d	0xe1c9f66d	0xaea3a907
+	0xa884e213	0xf8f98e65	0x91532420	0x01ef2298
+	0x497045c1	0xce8fdb4c	0x27eb66f4	0x4f55e3f0
+	0xba804764	0x26bda14f	0xc9f7f582	0x36bc7f36
+	0x34c2aa75	0xe4f15089	0xb8f9ee73	0xd4266b10
+	0x0fc54a15	0x5aa528c9	0xf8dfec8a	0x508cea6b
+	0x22b419f8	0xcf53de4d	0xbbd7e283	0xa14d1b71
+	0x9c32638c	0x1e361701	0x95b3f6bd	0x71ade23c
+	0x7dbdaf13	0x703136d9	0xb50676c0	0x1275e5b3
+	0x15efee34	0x3389309d	0xab961f5d	0xf381dc6b
+	0x20ade074	0xce316743	0x79d44d92	0x1d4fe039
+	0x6cfce315	0xb13ec789	0xf1a3d756	0x82ae906d
+	0x26ef851b	0xd2ca8f32	0xadd6ac28	0x3bce1e22
+	0x2de58e91	0xa0e69d86	0x0a66678e	0x0556a657
+	0x19206ec1	0x078b1a5b	0x06a676bb	0x89e164b8
+	0xc37e2fb4	0x1a4dd1dd	0xea609b2d	0x4a5cab06
+	0x8a0e5f3a	0x5f92a2d8	0x150ac669	0x3dccaa31
+	0x9e0296b6	0xf351dbf1	0x5cfca2f5	0x73e865f8
+	0x078c8312	0xf50254ac	0xc9064d4a	0x4f7176d3
+	0x3effaf99	0xe134aa8f	0xb4601dc4	0x2ba07197
+	0x7bae54f0	0xdf72f3ed	0x867c5d82	0x732c07e3
+	0x24e20500	0x287fc531	0x96166ac1	0x97543ef5
+	0xed62f87e	0xfaa76a7c	0xed4ba778	0x4e115af9
+	0xa11b36aa	0xcff391a1	0xf27a1aed	0x171a552f
+	>;
diff --git a/arch/x86/dts/microcode/mc0306d4_00000018.dtsi b/arch/x86/dts/microcode/mc0306d4_00000018.dtsi
new file mode 100644
index 0000000..3c78642
--- /dev/null
+++ b/arch/x86/dts/microcode/mc0306d4_00000018.dtsi
@@ -0,0 +1,944 @@
+/*
+ * Copyright (c) <1995-2015>, Intel Corporation.
+ * All rights reserved.
+ * Redistribution. Redistribution and use in binary form, without modification, are
+ * permitted provided that the following conditions are met:
+ *	.Redistributions must reproduce the above copyright notice and the following
+ * disclaimer in the documentation and/or other materials provided with the
+ * distribution.
+ *	.Neither the name of Intel Corporation nor the names of its suppliers may be used
+ * to endorse or promote products derived from this software without specific prior
+ * written permission.
+ *	.No reverse engineering, decompilation, or disassembly of this software is
+ * permitted.
+ *	."Binary form" includes any format commonly used for electronic conveyance
+ * which is a reversible, bit-exact translation of binary representation to ASCII or
+ * ISO text, for example, "uuencode."
+ * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date: Wed Jan 7 17:15:10 CST 2015
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x18>;
+intel,date-code = <0x12052014>;
+intel,processor-signature = <0x306d4>;
+intel,checksum = <0xc839f43b>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0xc0>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+	0x01000000	0x18000000	0x14200512	0xd4060300
+	0x3bf439c8	0x01000000	0xc0000000	0xd0370000
+	0x00380000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xa1000000	0x01000200	0x18000000
+	0x00000000	0xe10d0000	0x05121420	0xe10d0000
+	0x01000000	0xd4060300	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0xdba22a66	0xbe0ad79b	0x0965992e	0xad84102f
+	0xbf2a0939	0xcb0788e2	0xea0b1e6f	0x356e583f
+	0x3f11d4e1	0x035508c3	0x0c066713	0xeaeff79b
+	0xb66e752b	0x697be02e	0xc41dfd7c	0xb2c81198
+	0x3640cf86	0xaf4c5320	0x80650437	0x6c4e2b43
+	0x542e3a6a	0xfc4da788	0xf603a581	0x516b7367
+	0xb7112bbc	0xc9adf3bc	0xfeeec896	0x49cc8b68
+	0x96f9c416	0xd25c17e0	0x587a4d45	0x13fd7aa6
+	0x429e8d09	0xc22e6df8	0xa6678a73	0x17adc426
+	0x76676608	0x1d970d05	0x7c8a9968	0xf99cac21
+	0x617be229	0x7dfd1cd6	0x83ff0035	0x873612d4
+	0x9624b727	0xf667b8e9	0x710d9262	0x34dd59e1
+	0xbac69139	0x19577a36	0xdfe9f57a	0x11fdb95c
+	0x698498f5	0x10f25341	0xa994b124	0x8839568c
+	0x38fd5bac	0x93e671d2	0x92b2e916	0xd083650c
+	0x4f1a50d2	0x00af9698	0x9faa6566	0xe98d3a0f
+	0x5fdbf0c8	0x46a5b760	0x6329a5e3	0x39eba30e
+	0xab088c0d	0x26aa5f2f	0x56bd3c1d	0x566259a8
+	0x11000000	0x70e23c2c	0x1b7d8466	0xa2f784d7
+	0xceb63ce5	0x9088234b	0x23b1d432	0x84eea8ef
+	0x9d1888e9	0xfb2b8217	0x4fa7ac69	0x07c529a6
+	0x8b0694d1	0xba372800	0x4da8ad25	0x3cfde2b9
+	0xa7554683	0x8df70fe2	0x93b7f5b8	0x459ae846
+	0x1637173b	0xb8ca3f39	0x6a9dfbd3	0xe226e104
+	0xb9d194b2	0x02d64e76	0xdd310266	0xcc89892a
+	0x448aaabe	0x4c29405c	0x4c0b2833	0x0f5839ad
+	0x7a204f3f	0x4a6b292e	0x32d1af82	0x95b6e9a1
+	0x495ffbf1	0xf7eeebb6	0xac1ab767	0x43f8274c
+	0xc579abad	0xd4a1a6aa	0x51b10e25	0x480ff530
+	0x49ec38b0	0xa647f4c6	0x65bc5a86	0x9731894e
+	0x29be8858	0x1fce1d88	0xcb901a01	0xa924d206
+	0xb539d5d4	0x7574ca33	0xfa51c12d	0xe98cf6b4
+	0x0a601353	0xecdb49b0	0x475890ad	0xd75bd0b5
+	0x544de968	0x5c07241c	0x35ca668a	0x8250fa85
+	0xe5a95b37	0x7c71c685	0x82a38388	0xa7fcfd16
+	0x7a59cb4a	0x0df22455	0x0799852c	0x48156813
+	0xbad36d9a	0x1ff36daf	0xdcd1fa2f	0x330fe0bd
+	0x128a91b0	0x45268039	0x04486df2	0x76f50789
+	0x24a188f9	0x248e3334	0x8ead8d52	0x5809c815
+	0x0e714a5a	0xd75f89e9	0xf8b8ab34	0xc4d8f517
+	0x96768393	0x85ab9591	0xd459e17c	0xd9cdf5cf
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+	0x336897b3	0x1f8b6bd4	0xe8e75259	0xcb84e61f
+	0x5447eff6	0x2d1a79a0	0xd4eddfea	0xd00a51e1
+	0x3fe09b2b	0x082d621c	0x803ef4a8	0x907fd068
+	0x0f004ca2	0x06586b32	0x114f062b	0x8695dbb1
+	0x2cd04b93	0x8b5f6611	0x44e20bd6	0xcdb157ed
+	0x460cb121	0x9d2a78eb	0x445651ec	0xb7e28e8c
+	0xe7873eda	0x1c4bb823	0x3987fe30	0x9260db87
+	0x9e48f941	0x8483c669	0x99c57df9	0xafe87033
+	0x1a0e008b	0xa365c3b9	0x1b9c2766	0x77f59bd5
+	0xeebaf899	0xdc58e157	0xeb8f6c97	0xd391dd2f
+	0x43585717	0x52c9ddde	0x6f75c456	0x56875e7c
+	0xa62a9ee9	0xdb8512af	0xfadf9ae4	0xb06622db
+	0xce2874f0	0x72f71025	0xfd30b53c	0x363480c2
+	0x73d949de	0xb4b4a51d	0xd47377f9	0x7f1c60d4
+	0x61b71d19	0x914169a0	0x90726664	0xbddf5b56
+	0xca2e404d	0x83d911d4	0x8b9e8aee	0x93de56f6
+	0xefd8a1b5	0x063da123	0xc32325a9	0xdff4070b
+	0xf8d332ca	0xbb5631e7	0x0d72d895	0xae6536cf
+	0xb720dc2e	0x3267a20f	0xb3a65513	0xef0259de
+	0x6073f44c	0xfe28a197	0x44354e41	0xf3877d1e
+	0xbe31989a	0xad7b9d10	0xefe9094d	0x6cf1203c
+	0xfd836cb8	0x2d72e93a	0xd586d005	0x47544bf8
+	0x6eba36e4	0xfaf1ed00	0x70b31a7f	0xf61de020
+	0xb394055e	0x8f6ba193	0xff117ce2	0xaa5df73b
+	0x7ef7f2b7	0x892894eb	0xcf0d3758	0x40b3cd6a
+	0x736ae2eb	0x4e704410	0xf1e0120a	0xeee9b92c
+	0x51d98895	0xdf7d90fd	0xd964bb67	0x94608454
+	0xd3f2a01c	0x6591312d	0x9c10b22e	0xe2cd787c
+	0x2171327c	0x9ccf1a68	0x1c631c38	0x388fddc8
+	0x23da128c	0xacaf8103	0xe740d8da	0x6f198b8b
+	0xdbd4fb1d	0x4968f908	0x1d61e189	0x0d47b75e
+	0xd7d78539	0x6c73fdca	0xa04b447b	0x3f68a675
+	0xedf244e6	0x7a68d0aa	0x07209716	0x211cad30
+	0x352331ef	0x63932a02	0xc1c5af9f	0xce932a20
+	0xee73803c	0x46e9accf	0x4bd7ad2a	0x54bb1661
+	0xdb10d4d7	0x914f03e0	0x8b0bf04e	0x24b7567c
+	0x9ef64615	0x70dd716f	0xf5f298ae	0x2218f373
+	0xa1d2aabb	0xb72a21e6	0x111ad091	0xffa57188
+	0x962efef9	0xdce7b034	0xe12d6a21	0xd290a7e6
+	0xa6ee6ab8	0x74d46670	0x5aea6278	0x14dffad3
+	0x60329958	0x6d95d68c	0x6b59999a	0x80ea1f16
+	0x7b816c1e	0x053eaae0	0x808877e7	0xdce419e6
+	0x403a28fa	0x477fed42	0x2480777c	0xb7785739
+	0x1d59c924	0xa7e8e142	0x9efbc2d5	0xb82808e8
+	0x806d54cf	0xe64d2c08	0x9494b0d6	0xec78f0fd
+	0xc3beba08	0xebdfdff3	0x924fe3ab	0x8ee535ad
+	0x01258771	0x5392e4ae	0x825f0e60	0x3bf41cd6
+	0xb4e9b480	0x89cd0e08	0x5b685dba	0x4fde0c10
+	0x19fd913e	0x54de85bb	0x5d1aec47	0x6753c2d0
+	0xaac97246	0x50f375ca	0x0a675816	0x4e117cd8
+	0x343b6a0f	0x5698df73	0xd0539647	0x5c5faa01
+	0xdbf32a26	0x3a253a82	0x54186e46	0x583c0d5f
+	0x1a2ad36e	0xd645fb14	0x706a19ec	0x134c40ba
+	0x8875c39e	0x8b583b19	0xc8aa626c	0x6018f07f
+	0xf4a7cfbf	0xde62fb7f	0x9c59be93	0xe00402cc
+	0x30df55c5	0x2ef3001b	0xcbcdf288	0x770a9dfa
+	0x1886b563	0x16971e68	0x49dfa90f	0xb9ddb0ea
+	0xeea0426e	0x7d2d0829	0xfcb13e15	0xa6e618c9
+	0xb024d686	0xe19cf395	0x96c81494	0x9f75e130
+	0xcf381ed5	0xae054722	0x99613f82	0x5ccb2f89
+	0xca5fa36c	0xc35748e8	0xfb7cc7fe	0x9e3b5fb7
+	0x224fe96c	0xb67737ab	0x61a1c0c9	0x5a9b39b3
+	0x848b5ed7	0x6a5f39ab	0x13d2481b	0xd0ea612f
+	0xc5d17885	0xe57789cd	0xcba8a318	0xe43fd3ac
+	0x13b454e2	0x50102618	0xcf046014	0x69601090
+	0xa0ec1a47	0xa7db9e59	0x88add3f5	0xb2b82216
+	0x3c2a6a7f	0x15eea60a	0x9a00d090	0xea63733c
+	0x7d317b24	0x08a914de	0x9b17cfbe	0xfed02775
+	0x59f09ba8	0x8074cf9d	0x57ab22b6	0x14e4868c
+	0xb5854fd1	0x4d2c53ec	0x7b622ff4	0xfc29077b
+	0xa2f7e260	0xfa978f24	0x3b7897bd	0xf45dcbb3
+	0xcc72ae95	0xdfbf2875	0xeeba4b54	0x2a4feb10
+	0x0bae1384	0x9bd07656	0x252ef6b2	0x9db74367
+	0x51b0216d	0x5c483bda	0x0f8e8eeb	0xc69db3f8
+	0x32cc1522	0x9d8a9bdc	0xaa4a31c2	0xe0b1bdb8
+	0xf24ce823	0x3a44a26a	0x267d7df5	0x4df12ff2
+	0x9482f5ca	0x147b78d2	0xc25c4d28	0x1217f735
+	0xf22c63c6	0x87b811fd	0xd41ce89c	0x8c90b884
+	0x4157cdc2	0x1742439e	0xab8856a7	0x1819942d
+	0x5d8a70d7	0x1fb5207e	0x9058d58a	0xc78b784b
+	0x20fda01e	0x7f816cc2	0x9f1c555b	0x1749477b
+	0x8a118baf	0xa133adf1	0x9de1c2e0	0xd7789802
+	0xd3134b79	0xd3f54993	0x6eabfde9	0x663e74fd
+	0xead073ed	0x6e51fcb3	0xe2a0bdc7	0x34485f45
+	0xe154b0fa	0xdd81169a	0x21974626	0x4efaade8
+	0x727937e1	0x247a7487	0x1536dc39	0x22325fc3
+	0x7e56e057	0xf34bf1b1	0x6b77bee0	0x118bb371
+	0x20a114a5	0x0702e1d1	0xa329e70a	0x83e5ef19
+	0x10f1f752	0xe0ae45c8	0x6ac475af	0xcb47e839
+	0x6459d01e	0xe8a47522	0x1f480fd9	0x6e0c6611
+	0xd6a9637a	0xf1b35f38	0x6ba628a7	0xf4416b14
+	0x497267fc	0x76ad7ddd	0x16efe4d0	0xd233f0b0
+	0xfaa51597	0x9d3697a7	0xb6909b88	0xc991a9df
+	0xddc116c6	0x4cc6a52b	0xd15e6d12	0xb1563b55
+	0x3bb99d39	0x12371eab	0xa675583b	0x53287e8b
+	0xe74070ec	0x340b4d6f	0xf33eb6b0	0x8e8c3ad6
+	0x35b4576b	0x43a1d05c	0x9198b643	0x159a622e
+	0xde1c3cd7	0xd4647fed	0x84bd7e94	0xa4d0d67a
+	0x14107be6	0x5d9f75a6	0xad1d6bd5	0x59c74b61
+	0x17212211	0x5cd5c479	0x9aba7a41	0x9c80f2e2
+	0x1dff7bc4	0x0566819e	0xf50213fc	0xd0350c46
+	0xf495b0b5	0x8c7a00f0	0xfa881cbf	0xb7cf571e
+	0x0e59231f	0xb759f5fd	0x91ef47f3	0x58ee41dd
+	0x9e65c3d2	0xa69d4ada	0xcafde4fe	0x5098e9b7
+	0x0f059288	0x605d1f4a	0xbd4914e0	0x6afaa6be
+	0x3661622a	0xe9309570	0x08f002ba	0xe9ee73da
+	0xc252f80a	0x3663b11a	0xa28797d0	0x88958ad5
+	0x1d8e5d1a	0x9c4e6ca2	0x431f1541	0x593c16fb
+	0x9d5b62fd	0xccf1aeb6	0x23fcbe26	0x9a56b544
+	0x6cf42caa	0xd3fe2546	0xcbc80fc3	0xd9ca074a
+	0xfb2c4a94	0x6ebc6cf5	0x7573610f	0x39340348
+	0x4c6de55e	0x89f3c9ec	0x5f614d03	0x9897c1c0
+	0x3ed97e01	0x522b7259	0x4d0264cf	0x14a5124a
+	0x290bbdb5	0xbbee9d25	0xf77b9d44	0x1ec5e012
+	0x0c8cdc16	0x3955a4ff	0x1d97515f	0x2e38300f
+	0x8e3fc3ee	0xc77c8545	0x864ac70c	0x8d284434
+	0x365a1b22	0xbcda59a3	0x770fa74a	0xa0056fa2
+	0xdbae9ad8	0xe8eedd38	0x5e31586e	0x0a1e34f6
+	0xb48ddc79	0xdf79f8e3	0xb2054bf4	0xba1163bc
+	0x303e80e8	0xd2e8a56c	0xde97c1d8	0xfa2b2a99
+	0xe86f7090	0x7388aab9	0xa8f282f9	0x7800daed
+	0x71e14e17	0xc9b64244	0xa85fdcd7	0x4693291a
+	0x80f76ce5	0x6001086a	0xcc580b01	0xb8c71e6e
+	0x1af096b3	0xc48de567	0xaa2e33fc	0x5bcb7fba
+	0xa77b0012	0x1f176019	0x35c1e9aa	0xe175fbbe
+	0xc4709fdd	0x5accf5dc	0x13262619	0xe10c57d9
+	0xf538e944	0x38175b54	0x1ecf81ae	0x41606deb
+	0x7c3d899c	0x58adda6b	0x1a91c782	0x04201d47
+	0x1e99b49e	0x2df3d373	0xc32ed967	0xf0d3042e
+	0x74cb3b44	0x298d582b	0xa2c41173	0x3c04031c
+	>;
diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index 0853248..9856fa6 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -390,4 +390,4 @@
 			 void *dsdt);
 int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, u8 cpu,
 			 u16 flags, u8 lint);
-unsigned long write_acpi_tables(unsigned long start);
+u32 write_acpi_tables(u32 start);
diff --git a/arch/x86/include/asm/arch-broadwell/cpu.h b/arch/x86/include/asm/arch-broadwell/cpu.h
new file mode 100644
index 0000000..eb2046b
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/cpu.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __asm_arch_cpu_h
+#define __asm_arch_cpu_h
+
+/* CPU types */
+#define HASWELL_FAMILY_ULT	0x40650
+#define BROADWELL_FAMILY_ULT	0x306d0
+
+/* Supported CPUIDs */
+#define CPUID_HASWELL_A0	0x306c1
+#define CPUID_HASWELL_B0	0x306c2
+#define CPUID_HASWELL_C0	0x306c3
+#define CPUID_HASWELL_ULT_B0	0x40650
+#define CPUID_HASWELL_ULT	0x40651
+#define CPUID_HASWELL_HALO	0x40661
+#define CPUID_BROADWELL_C0	0x306d2
+#define CPUID_BROADWELL_D0	0x306d3
+#define CPUID_BROADWELL_E0	0x306d4
+
+/* Broadwell bus clock is fixed at 100MHz */
+#define BROADWELL_BCLK		100
+
+#define BROADWELL_FAMILY_ULT	0x306d0
+
+#define CORE_THREAD_COUNT_MSR		0x35
+
+#define MSR_VR_CURRENT_CONFIG		0x601
+#define MSR_VR_MISC_CONFIG		0x603
+#define MSR_PKG_POWER_SKU		0x614
+#define MSR_DDR_RAPL_LIMIT		0x618
+#define MSR_VR_MISC_CONFIG2		0x636
+
+/* Latency times in units of 1024ns. */
+#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42
+#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73
+#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91
+#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4
+#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145
+#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef
+
+void cpu_set_power_limits(int power_limit_1_time);
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/gpio.h b/arch/x86/include/asm/arch-broadwell/gpio.h
new file mode 100644
index 0000000..0ed881b
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/gpio.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * From Coreboot src/soc/intel/broadwell/include/soc/gpio.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_GPIO
+#define __ASM_ARCH_GPIO
+
+#define GPIO_PER_BANK	32
+#define GPIO_BANKS	3
+
+struct broadwell_bank_platdata {
+	uint16_t base_addr;
+	const char *bank_name;
+	int bank;
+};
+
+/* PCH-LP GPIOBASE Registers */
+struct pch_lp_gpio_regs {
+	u32 own[GPIO_BANKS];
+	u32 reserved0;
+
+	u16 pirq_to_ioxapic;
+	u16 reserved1[3];
+	u32 blink;
+	u32 ser_blink;
+
+	u32 ser_blink_cmdsts;
+	u32 ser_blink_data;
+	u16 gpi_nmi_en;
+	u16 gpi_nmi_sts;
+	u32 reserved2;
+
+	u32 gpi_route[GPIO_BANKS];
+	u32 reserved3;
+
+	u32 reserved4[4];
+
+	u32 alt_gpi_smi_sts;
+	u32 alt_gpi_smi_en;
+	u32 reserved5[2];
+
+	u32 rst_sel[GPIO_BANKS];
+	u32 reserved6;
+
+	u32 reserved9[3];
+	u32 gpio_gc;
+
+	u32 gpi_is[GPIO_BANKS];
+	u32 reserved10;
+
+	u32 gpi_ie[GPIO_BANKS];
+	u32 reserved11;
+
+	u32 reserved12[24];
+
+	struct {
+		u32 conf_a;
+		u32 conf_b;
+	} config[GPIO_BANKS * GPIO_PER_BANK];
+};
+check_member(pch_lp_gpio_regs, gpi_ie[0], 0x90);
+check_member(pch_lp_gpio_regs, config[0], 0x100);
+
+enum {
+	CONFA_MODE_SHIFT	= 0,
+	CONFA_MODE_GPIO		= 1 << CONFA_MODE_SHIFT,
+
+	CONFA_DIR_SHIFT		= 2,
+	CONFA_DIR_INPUT		= 1 << CONFA_DIR_SHIFT,
+
+	CONFA_INVERT_SHIFT	= 3,
+	CONFA_INVERT		= 1 << CONFA_INVERT_SHIFT,
+
+	CONFA_TRIGGER_SHIFT	= 4,
+	CONFA_TRIGGER_LEVEL	= 1 << CONFA_TRIGGER_SHIFT,
+
+	CONFA_LEVEL_SHIFT	= 30,
+	CONFA_LEVEL_HIGH	= 1UL << CONFA_LEVEL_SHIFT,
+
+	CONFA_OUTPUT_SHIFT	= 31,
+	CONFA_OUTPUT_HIGH	= 1UL << CONFA_OUTPUT_SHIFT,
+
+	CONFB_SENSE_SHIFT	= 2,
+	CONFB_SENSE_DISABLE	= 1 << CONFB_SENSE_SHIFT,
+};
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/iomap.h b/arch/x86/include/asm/arch-broadwell/iomap.h
new file mode 100644
index 0000000..431bc23
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/iomap.h
@@ -0,0 +1,53 @@
+/*
+ * From Coreboot soc/intel/broadwell/include/soc/iomap.h
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __asm_arch_iomap_h
+#define __asm_arch_iomap_h
+
+#define MCFG_BASE_ADDRESS	0xf0000000
+#define MCFG_BASE_SIZE		0x4000000
+
+#define HPET_BASE_ADDRESS	0xfed00000
+
+#define MCH_BASE_ADDRESS	0xfed10000
+#define MCH_BASE_SIZE		0x8000
+
+#define DMI_BASE_ADDRESS	0xfed18000
+#define DMI_BASE_SIZE		0x1000
+
+#define EP_BASE_ADDRESS		0xfed19000
+#define EP_BASE_SIZE		0x1000
+
+#define EDRAM_BASE_ADDRESS	0xfed80000
+#define EDRAM_BASE_SIZE		0x4000
+
+#define GDXC_BASE_ADDRESS	0xfed84000
+#define GDXC_BASE_SIZE		0x1000
+
+#define RCBA_BASE_ADDRESS	0xfed1c000
+#define RCBA_BASE_SIZE		0x4000
+
+#define HPET_BASE_ADDRESS	0xfed00000
+
+#define ACPI_BASE_ADDRESS	0x1000
+#define ACPI_BASE_SIZE		0x100
+
+#define GPIO_BASE_ADDRESS	0x1400
+#define GPIO_BASE_SIZE		0x400
+
+#define SMBUS_BASE_ADDRESS	0x0400
+#define SMBUS_BASE_SIZE		0x10
+
+/* Temporary addresses used before relocation */
+#define EARLY_GTT_BAR		0xe0000000
+#define EARLY_XHCI_BAR		0xd7000000
+#define EARLY_EHCI_BAR		0xd8000000
+#define EARLY_UART_BAR		0x3f8
+#define EARLY_TEMP_MMIO		0xfed08000
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/lpc.h b/arch/x86/include/asm/arch-broadwell/lpc.h
new file mode 100644
index 0000000..a718667
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/lpc.h
@@ -0,0 +1,32 @@
+/*
+ * From coreboot soc/intel/broadwell/include/soc/lpc.h
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _ASM_ARCH_LPC_H
+#define _ASM_ARCH_LPC_H
+
+#define GEN_PMCON_1		0xa0
+#define  SMI_LOCK		(1 << 4)
+#define GEN_PMCON_2		0xa2
+#define  SYSTEM_RESET_STS	(1 << 4)
+#define  THERMTRIP_STS		(1 << 3)
+#define  SYSPWR_FLR		(1 << 1)
+#define  PWROK_FLR		(1 << 0)
+#define GEN_PMCON_3		0xa4
+#define  SUS_PWR_FLR		(1 << 14)
+#define  GEN_RST_STS		(1 << 9)
+#define  RTC_BATTERY_DEAD	(1 << 2)
+#define  PWR_FLR		(1 << 1)
+#define  SLEEP_AFTER_POWER_FAIL	(1 << 0)
+#define GEN_PMCON_LOCK		0xa6
+#define  SLP_STR_POL_LOCK	(1 << 2)
+#define  ACPI_BASE_LOCK		(1 << 1)
+#define PMIR			0xac
+#define  PMIR_CF9LOCK		(1 << 31)
+#define  PMIR_CF9GR		(1 << 20)
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/me.h b/arch/x86/include/asm/arch-broadwell/me.h
new file mode 100644
index 0000000..a66a8bb
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/me.h
@@ -0,0 +1,200 @@
+/*
+ * From coreboot soc/intel/broadwell/include/soc/me.h
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _asm_arch_me_h
+#define _asm_arch_me_h
+
+#include <asm/me_common.h>
+
+#define  ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */
+
+#define ME_HSIO_MESSAGE		(7 << 28)
+#define ME_HSIO_CMD_GETHSIOVER	1
+#define ME_HSIO_CMD_CLOSE	0
+
+/*
+ * Apparently the GMES register is renamed to HFS2 (or HFSTS2 according
+ * to ME9 BWG). Sadly the PCH EDS and the ME BWG do not match on nomenclature.
+ */
+#define PCI_ME_HFS2		0x48
+/* Infrastructure Progress Values */
+#define  ME_HFS2_PHASE_ROM		0
+#define  ME_HFS2_PHASE_BUP		1
+#define  ME_HFS2_PHASE_UKERNEL		2
+#define  ME_HFS2_PHASE_POLICY		3
+#define  ME_HFS2_PHASE_MODULE_LOAD	4
+#define  ME_HFS2_PHASE_UNKNOWN		5
+#define  ME_HFS2_PHASE_HOST_COMM	6
+/* Current State - Based on Infra Progress values. */
+/*       ROM State */
+#define  ME_HFS2_STATE_ROM_BEGIN 0
+#define  ME_HFS2_STATE_ROM_DISABLE 6
+/*       BUP State */
+#define  ME_HFS2_STATE_BUP_INIT 0
+#define  ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1
+#define  ME_HFS2_STATE_BUP_FLOW_DET 4
+#define  ME_HFS2_STATE_BUP_VSCC_ERR 8
+#define  ME_HFS2_STATE_BUP_CHECK_STRAP 0xa
+#define  ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb
+#define  ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd
+#define  ME_HFS2_STATE_BUP_M3 0x11
+#define  ME_HFS2_STATE_BUP_M0 0x12
+#define  ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13
+#define  ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15
+#define  ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17
+#define  ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18
+#define  ME_HFS2_STATE_BUP_T32_MISSING 0x1c
+#define  ME_HFS2_STATE_BUP_WAIT_DID 0x1f
+#define  ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20
+#define  ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21
+#define  ME_HFS2_STATE_BUP_ENABLE_UMA 0x22
+#define  ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23
+#define  ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24
+#define  ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25
+#define  ME_HFS2_STATE_BUP_M0_CLK 0x26
+#define  ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27
+#define  ME_HFS2_STATE_BUP_TEMP_DIS 0x28
+#define  ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32
+/*       Policy Module State */
+#define  ME_HFS2_STATE_POLICY_ENTRY 0
+#define  ME_HFS2_STATE_POLICY_RCVD_S3 3
+#define  ME_HFS2_STATE_POLICY_RCVD_S4 4
+#define  ME_HFS2_STATE_POLICY_RCVD_S5 5
+#define  ME_HFS2_STATE_POLICY_RCVD_UPD 6
+#define  ME_HFS2_STATE_POLICY_RCVD_PCR 7
+#define  ME_HFS2_STATE_POLICY_RCVD_NPCR 8
+#define  ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9
+#define  ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa
+#define  ME_HFS2_STATE_POLICY_RCVD_DID 0xb
+#define  ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc
+#define  ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd
+#define  ME_HFS2_STATE_POLICY_FPB_ERR 0xe
+#define  ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf
+#define  ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10
+/* Current PM Event Values */
+#define  ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0
+#define  ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1
+#define  ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2
+#define  ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3
+#define  ME_HFS2_PMEVENT_CLEAN_ME_RESET 4
+#define  ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5
+#define  ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6
+#define  ME_HFS2_PMEVENT_S0MO_SXM3 7
+#define  ME_HFS2_PMEVENT_SXM3_S0M0 8
+#define  ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9
+#define  ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa
+#define  ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb
+#define  ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc
+
+struct me_hfs2 {
+	u32 bist_in_progress:1;
+	u32 reserved1:2;
+	u32 invoke_mebx:1;
+	u32 cpu_replaced_sts:1;
+	u32 mbp_rdy:1;
+	u32 mfs_failure:1;
+	u32 warm_reset_request:1;
+	u32 cpu_replaced_valid:1;
+	u32 reserved2:4;
+	u32 mbp_cleared:1;
+	u32 reserved3:2;
+	u32 current_state:8;
+	u32 current_pmevent:4;
+	u32 progress_code:4;
+} __packed;
+
+#define PCI_ME_HFS5		0x68
+
+#define PCI_ME_H_GS2		0x70
+#define   PCI_ME_MBP_GIVE_UP	0x01
+
+/* ICC Messages */
+#define ICC_SET_CLOCK_ENABLES		0x3
+#define ICC_API_VERSION_LYNXPOINT	0x00030000
+
+struct icc_header {
+	u32 api_version;
+	u32 icc_command;
+	u32 icc_status;
+	u32 length;
+	u32 reserved;
+} __packed;
+
+struct icc_clock_enables_msg {
+	u32 clock_enables;
+	u32 clock_mask;
+	u32 no_response:1;
+	u32 reserved:31;
+} __packed;
+
+/*
+ * ME to BIOS Payload Datastructures and definitions. The ordering of the
+ * structures follows the ordering in the ME9 BWG.
+ */
+
+#define MBP_APPID_KERNEL 1
+#define MBP_APPID_INTEL_AT 3
+#define MBP_APPID_HWA 4
+#define MBP_APPID_ICC 5
+#define MBP_APPID_NFC 6
+/* Kernel items: */
+#define MBP_KERNEL_FW_VER_ITEM 1
+#define MBP_KERNEL_FW_CAP_ITEM 2
+#define MBP_KERNEL_ROM_BIST_ITEM 3
+#define MBP_KERNEL_PLAT_KEY_ITEM 4
+#define MBP_KERNEL_FW_TYPE_ITEM 5
+#define MBP_KERNEL_MFS_FAILURE_ITEM 6
+#define MBP_KERNEL_PLAT_TIME_ITEM 7
+/* Intel AT items: */
+#define MBP_INTEL_AT_STATE_ITEM 1
+/* ICC Items: */
+#define MBP_ICC_PROFILE_ITEM 1
+/* HWA Items: */
+#define MBP_HWA_REQUEST_ITEM 1
+/* NFC Items: */
+#define MBP_NFC_SUPPORT_DATA_ITEM 1
+
+#define MBP_MAKE_IDENT(appid, item) ((appid << 8) | item)
+#define MBP_IDENT(appid, item) \
+	MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM)
+
+struct mbp_fw_version_name {
+	u32	major_version:16;
+	u32	minor_version:16;
+	u32	hotfix_version:16;
+	u32	build_version:16;
+} __packed;
+
+struct icc_address_mask {
+	u16 icc_start_address;
+	u16 mask;
+} __packed;
+
+struct mbp_icc_profile {
+	u8	num_icc_profiles;
+	u8	icc_profile_soft_strap;
+	u8	icc_profile_index;
+	u8	reserved;
+	u32	icc_reg_bundles;
+	struct icc_address_mask icc_address_mask[0];
+} __packed;
+
+struct me_bios_payload {
+	struct mbp_fw_version_name	*fw_version_name;
+	struct mbp_mefwcaps	*fw_capabilities;
+	struct mbp_rom_bist_data *rom_bist_data;
+	struct mbp_platform_key *platform_key;
+	struct mbp_plat_type	*fw_plat_type;
+	struct mbp_icc_profile	*icc_profile;
+	struct mbp_at_state	*at_state;
+	u32		*mfsintegrity;
+	struct mbp_plat_time	*plat_time;
+	struct mbp_nfc_data	*nfc_data;
+};
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/pch.h b/arch/x86/include/asm/arch-broadwell/pch.h
new file mode 100644
index 0000000..3e346ad
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/pch.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_PCH_H
+#define __ASM_ARCH_PCH_H
+
+/* CPU bus clock is fixed at 100MHz */
+#define CPU_BCLK		100
+
+#define PMBASE			0x40
+#define ACPI_CNTL		0x44
+#define  ACPI_EN		(1 << 7)
+
+#define GPIO_BASE		0x48 /* LPC GPIO Base Address Register */
+#define GPIO_CNTL		0x4C /* LPC GPIO Control Register */
+#define  GPIO_EN		(1 << 4)
+
+#define PCIEXBAR	0x60
+
+#define  PCH_DEV_LPC		PCI_BDF(0, 0x1f, 0)
+
+/* RCB registers */
+#define OIC		0x31fe	/* 16bit */
+#define HPTC		0x3404	/* 32bit */
+#define FD		0x3418	/* 32bit */
+
+/* Function Disable 1 RCBA 0x3418 */
+#define PCH_DISABLE_ALWAYS	(1 << 0)
+
+/* PM registers */
+#define TCO1_CNT		0x60
+#define  TCO_TMR_HLT		(1 << 11)
+
+
+/* Device 0:0.0 PCI configuration space */
+
+#define EPBAR		0x40
+#define MCHBAR		0x48
+#define PCIEXBAR	0x60
+#define DMIBAR		0x68
+#define GGC		0x50	/* GMCH Graphics Control */
+#define DEVEN		0x54	/* Device Enable */
+#define  DEVEN_D7EN	(1 << 14)
+#define  DEVEN_D4EN	(1 << 7)
+#define  DEVEN_D3EN	(1 << 5)
+#define  DEVEN_D2EN	(1 << 4)
+#define  DEVEN_D1F0EN	(1 << 3)
+#define  DEVEN_D1F1EN	(1 << 2)
+#define  DEVEN_D1F2EN	(1 << 1)
+#define  DEVEN_D0EN	(1 << 0)
+#define DPR		0x5c
+#define  DPR_EPM	(1 << 2)
+#define  DPR_PRS	(1 << 1)
+#define  DPR_SIZE_MASK	0xff0
+
+#define MCHBAR_PEI_VERSION	0x5034
+#define BIOS_RESET_CPL		0x5da8
+#define EDRAMBAR		0x5408
+#define MCH_PAIR		0x5418
+#define GDXCBAR			0x5420
+
+#define PAM0		0x80
+#define PAM1		0x81
+#define PAM2		0x82
+#define PAM3		0x83
+#define PAM4		0x84
+#define PAM5		0x85
+#define PAM6		0x86
+
+/* PCODE MMIO communications live in the MCHBAR. */
+#define BIOS_MAILBOX_INTERFACE			0x5da4
+#define  MAILBOX_RUN_BUSY			(1 << 31)
+#define  MAILBOX_BIOS_CMD_READ_PCS		1
+#define  MAILBOX_BIOS_CMD_WRITE_PCS		2
+#define  MAILBOX_BIOS_CMD_READ_CALIBRATION	0x509
+#define  MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL	0x909
+#define  MAILBOX_BIOS_CMD_READ_PCH_POWER	0xa
+#define  MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT	0xb
+#define  MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE	0x26
+#define  MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE	0x27
+/* Errors are returned back in bits 7:0. */
+#define  MAILBOX_BIOS_ERROR_NONE		0
+#define  MAILBOX_BIOS_ERROR_INVALID_COMMAND	1
+#define  MAILBOX_BIOS_ERROR_TIMEOUT		2
+#define  MAILBOX_BIOS_ERROR_ILLEGAL_DATA	3
+#define  MAILBOX_BIOS_ERROR_RESERVED		4
+#define  MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID	5
+#define  MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED	6
+#define  MAILBOX_BIOS_ERROR_VR_ERROR		7
+/* Data is passed through bits 31:0 of the data register. */
+#define BIOS_MAILBOX_DATA			0x5da0
+
+/* SATA IOBP Registers */
+#define SATA_IOBP_SP0_SECRT88	0xea002688
+#define SATA_IOBP_SP1_SECRT88	0xea002488
+
+#define SATA_SECRT88_VADJ_MASK	0xff
+#define SATA_SECRT88_VADJ_SHIFT	16
+
+#define SATA_IOBP_SP0DTLE_DATA	0xea002550
+#define SATA_IOBP_SP0DTLE_EDGE	0xea002554
+#define SATA_IOBP_SP1DTLE_DATA	0xea002750
+#define SATA_IOBP_SP1DTLE_EDGE	0xea002754
+
+#define SATA_DTLE_MASK		0xF
+#define SATA_DTLE_DATA_SHIFT	24
+#define SATA_DTLE_EDGE_SHIFT	16
+
+/* Power Management */
+#define GEN_PMCON_1		0xa0
+#define  SMI_LOCK		(1 << 4)
+#define GEN_PMCON_2		0xa2
+#define  SYSTEM_RESET_STS	(1 << 4)
+#define  THERMTRIP_STS		(1 << 3)
+#define  SYSPWR_FLR		(1 << 1)
+#define  PWROK_FLR		(1 << 0)
+#define GEN_PMCON_3		0xa4
+#define  SUS_PWR_FLR		(1 << 14)
+#define  GEN_RST_STS		(1 << 9)
+#define  RTC_BATTERY_DEAD	(1 << 2)
+#define  PWR_FLR		(1 << 1)
+#define  SLEEP_AFTER_POWER_FAIL	(1 << 0)
+#define GEN_PMCON_LOCK		0xa6
+#define  SLP_STR_POL_LOCK	(1 << 2)
+#define  ACPI_BASE_LOCK		(1 << 1)
+#define PMIR			0xac
+#define  PMIR_CF9LOCK		(1 << 31)
+#define  PMIR_CF9GR		(1 << 20)
+
+/* Broadwell PCH (Wildcat Point) */
+#define PCH_WPT_HSW_U_SAMPLE	0x9cc1
+#define PCH_WPT_BDW_U_SAMPLE	0x9cc2
+#define PCH_WPT_BDW_U_PREMIUM	0x9cc3
+#define PCH_WPT_BDW_U_BASE	0x9cc5
+#define PCH_WPT_BDW_Y_SAMPLE	0x9cc6
+#define PCH_WPT_BDW_Y_PREMIUM	0x9cc7
+#define PCH_WPT_BDW_Y_BASE	0x9cc9
+#define PCH_WPT_BDW_H		0x9ccb
+
+#define SA_IGD_OPROM_VENDEV	0x80860406
+
+/* Dynamically determine if the part is ULT */
+bool cpu_is_ult(void);
+
+u32 pch_iobp_read(u32 address);
+int pch_iobp_write(u32 address, u32 data);
+int pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
+int  pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp);
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/pei_data.h b/arch/x86/include/asm/arch-broadwell/pei_data.h
new file mode 100644
index 0000000..b2cc8b8
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/pei_data.h
@@ -0,0 +1,177 @@
+/*
+ * From Coreboot soc/intel/broadwell/include/soc/pei_data.h
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef ASM_ARCH_PEI_DATA_H
+#define ASM_ARCH_PEI_DATA_H
+
+#include <linux/linkage.h>
+
+#define PEI_VERSION 22
+
+typedef void asmlinkage (*tx_byte_func)(unsigned char byte);
+
+enum board_type {
+	BOARD_TYPE_CRB_MOBILE = 0,	/* CRB Mobile */
+	BOARD_TYPE_CRB_DESKTOP,		/* CRB Desktop */
+	BOARD_TYPE_USER1,		/* SV mobile */
+	BOARD_TYPE_USER2,		/* SV desktop */
+	BOARD_TYPE_USER3,		/* SV server */
+	BOARD_TYPE_ULT,			/* ULT */
+	BOARD_TYPE_CRB_EMBDEDDED,	/* CRB Embedded */
+	BOARD_TYPE_UNKNOWN,
+};
+
+#define MAX_USB2_PORTS 14
+#define MAX_USB3_PORTS 6
+#define USB_OC_PIN_SKIP 8
+
+enum usb2_port_location {
+	USB_PORT_BACK_PANEL = 0,
+	USB_PORT_FRONT_PANEL,
+	USB_PORT_DOCK,
+	USB_PORT_MINI_PCIE,
+	USB_PORT_FLEX,
+	USB_PORT_INTERNAL,
+	USB_PORT_SKIP,
+	USB_PORT_NGFF_DEVICE_DOWN,
+};
+
+struct usb2_port_setting {
+	/*
+	 * Usb Port Length:
+	 * [16:4] = length in inches in octal format
+	 * [3:0]  = decimal point
+	 */
+	uint16_t length;
+	uint8_t enable;
+	uint8_t oc_pin;
+	uint8_t location;
+} __packed;
+
+struct usb3_port_setting {
+	uint8_t enable;
+	uint8_t oc_pin;
+	/*
+	 * Set to 0 if trace length is > 5 inches
+	 * Set to 1 if trace length is <= 5 inches
+	 */
+	uint8_t fixed_eq;
+} __packed;
+
+
+struct pei_data {
+	uint32_t pei_version;
+
+	enum board_type board_type;
+	int boot_mode;
+	int ec_present;
+	int usbdebug;
+
+	/* Base addresses */
+	uint32_t pciexbar;
+	uint16_t smbusbar;
+	uint32_t xhcibar;
+	uint32_t ehcibar;
+	uint32_t gttbar;
+	uint32_t rcba;
+	uint32_t pmbase;
+	uint32_t gpiobase;
+	uint32_t temp_mmio_base;
+	uint32_t tseg_size;
+
+	/*
+	 * 0 = leave channel enabled
+	 * 1 = disable dimm 0 on channel
+	 * 2 = disable dimm 1 on channel
+	 * 3 = disable dimm 0+1 on channel
+	 */
+	int dimm_channel0_disabled;
+	int dimm_channel1_disabled;
+	/* Set to 0 for memory down */
+	uint8_t spd_addresses[4];
+	/* Enable 2x Refresh Mode */
+	int ddr_refresh_2x;
+	/* DQ pins are interleaved on board */
+	int dq_pins_interleaved;
+	/* Limit DDR3 frequency */
+	int max_ddr3_freq;
+	/* Disable self refresh */
+	int disable_self_refresh;
+	/* Disable cmd power/CKEPD */
+	int disable_cmd_pwr;
+
+	/* USB port configuration */
+	struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
+	struct usb3_port_setting usb3_ports[MAX_USB3_PORTS];
+
+	/*
+	 * USB3 board specific PHY tuning
+	 */
+
+	/* Valid range: 0x69 - 0x80 */
+	uint8_t usb3_txout_volt_dn_amp_adj[MAX_USB3_PORTS];
+	/* Valid range: 0x80 - 0x9c */
+	uint8_t usb3_txout_imp_sc_volt_amp_adj[MAX_USB3_PORTS];
+	/* Valid range: 0x39 - 0x80 */
+	uint8_t usb3_txout_de_emp_adj[MAX_USB3_PORTS];
+	/* Valid range: 0x3d - 0x4a */
+	uint8_t usb3_txout_imp_adj_volt_amp[MAX_USB3_PORTS];
+
+	/* Console output function */
+	tx_byte_func tx_byte;
+
+	/*
+	 * DIMM SPD data for memory down configurations
+	 * [CHANNEL][SLOT][SPD]
+	 */
+	uint8_t spd_data[2][2][512];
+
+	/*
+	 * LPDDR3 DQ byte map
+	 * [CHANNEL][ITERATION][2]
+	 *
+	 * Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side)
+	 * DQByteMap[0] - ClkDQByteMap:
+	 * - If clock is per rank, program to [0xFF, 0xFF]
+	 * - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
+	 * - If clock is shared by 2 ranks but does not go to all bytes,
+	 *   Entry[i] defines which DQ bytes Group i services
+	 * DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB
+	 * DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB
+	 * DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB
+	 *                For DDR, DQByteMap[3:1] = [0xFF, 0]
+	 * DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0]
+	 *                since we have 1 CTL / rank
+	 * DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0]
+	 *                since we have 1 CA Vref
+	 */
+	uint8_t dq_map[2][6][2];
+
+	/*
+	 * LPDDR3 Map from CPU DQS pins to SDRAM DQS pins
+	 * [CHANNEL][MAX_BYTES]
+	 */
+	uint8_t dqs_map[2][8];
+
+	/* Data read from flash and passed into MRC */
+	const void *saved_data;
+	int saved_data_size;
+
+	/* Disable use of saved data (can be set by mainboard) */
+	int disable_saved_data;
+
+	/* Data from MRC that should be saved to flash */
+	void *data_to_save;
+	int data_to_save_size;
+	struct pei_memory_info meminfo;
+} __packed;
+
+void mainboard_fill_pei_data(struct pei_data *pei_data);
+void broadwell_fill_pei_data(struct pei_data *pei_data);
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/pm.h b/arch/x86/include/asm/arch-broadwell/pm.h
new file mode 100644
index 0000000..36ad842
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/pm.h
@@ -0,0 +1,129 @@
+/*
+ * From coreboot src/soc/intel/broadwell/include/soc/pm.h
+ *
+ * Copyright (C) 2016 Google, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_PM_H
+#define __ASM_ARCH_PM_H
+
+#define PM1_STS			0x00
+#define  WAK_STS		(1 << 15)
+#define  PCIEXPWAK_STS		(1 << 14)
+#define  PRBTNOR_STS		(1 << 11)
+#define  RTC_STS		(1 << 10)
+#define  PWRBTN_STS		(1 << 8)
+#define  GBL_STS		(1 << 5)
+#define  BM_STS			(1 << 4)
+#define  TMROF_STS		(1 << 0)
+#define PM1_EN			0x02
+#define  PCIEXPWAK_DIS		(1 << 14)
+#define  RTC_EN			(1 << 10)
+#define  PWRBTN_EN		(1 << 8)
+#define  GBL_EN			(1 << 5)
+#define  TMROF_EN		(1 << 0)
+#define PM1_CNT			0x04
+#define  SLP_EN			(1 << 13)
+#define  SLP_TYP		(7 << 10)
+#define   SLP_TYP_SHIFT         10
+#define   SLP_TYP_S0		0
+#define   SLP_TYP_S1		1
+#define   SLP_TYP_S3		5
+#define   SLP_TYP_S4		6
+#define   SLP_TYP_S5		7
+#define  GBL_RLS		(1 << 2)
+#define  BM_RLD			(1 << 1)
+#define  SCI_EN			(1 << 0)
+#define PM1_TMR			0x08
+#define SMI_EN			0x30
+#define  XHCI_SMI_EN		(1 << 31)
+#define  ME_SMI_EN		(1 << 30)
+#define  GPIO_UNLOCK_SMI_EN	(1 << 27)
+#define  INTEL_USB2_EN		(1 << 18)
+#define  LEGACY_USB2_EN		(1 << 17)
+#define  PERIODIC_EN		(1 << 14)
+#define  TCO_EN			(1 << 13)
+#define  MCSMI_EN		(1 << 11)
+#define  BIOS_RLS		(1 <<  7)
+#define  SWSMI_TMR_EN		(1 <<  6)
+#define  APMC_EN		(1 <<  5)
+#define  SLP_SMI_EN		(1 <<  4)
+#define  LEGACY_USB_EN		(1 <<  3)
+#define  BIOS_EN		(1 <<  2)
+#define  EOS			(1 <<  1)
+#define  GBL_SMI_EN		(1 <<  0)
+#define SMI_STS			0x34
+#define UPWRC			0x3c
+#define  UPWRC_WS		(1 << 8)
+#define  UPWRC_WE		(1 << 1)
+#define  UPWRC_SMI		(1 << 0)
+#define GPE_CNTL		0x42
+#define  SWGPE_CTRL		(1 << 1)
+#define DEVACT_STS		0x44
+#define PM2_CNT			0x50
+#define TCO1_CNT		0x60
+#define  TCO_TMR_HLT		(1 << 11)
+#define TCO1_STS		0x64
+#define  DMISCI_STS		(1 << 9)
+#define TCO2_STS		0x66
+#define  TCO2_STS_SECOND_TO	(1 << 1)
+
+#define GPE0_REG_MAX		4
+#define GPE0_REG_SIZE		32
+#define GPE0_STS(x)		(0x80 + (x * 4))
+#define  GPE_31_0		0	/* 0x80/0x90 = GPE[31:0] */
+#define  GPE_63_32		1	/* 0x84/0x94 = GPE[63:32] */
+#define  GPE_94_64		2	/* 0x88/0x98 = GPE[94:64] */
+#define  GPE_STD		3	/* 0x8c/0x9c = Standard GPE */
+#define   WADT_STS		(1 << 18)
+#define   GP27_STS		(1 << 16)
+#define   PME_B0_STS		(1 << 13)
+#define   ME_SCI_STS		(1 << 12)
+#define   PME_STS		(1 << 11)
+#define   BATLOW_STS		(1 << 10)
+#define   PCI_EXP_STS		(1 << 9)
+#define   SMB_WAK_STS		(1 << 7)
+#define   TCOSCI_STS		(1 << 6)
+#define   SWGPE_STS		(1 << 2)
+#define   HOT_PLUG_STS		(1 << 1)
+#define GPE0_EN(x)		(0x90 + (x * 4))
+#define   WADT_en		(1 << 18)
+#define   GP27_EN		(1 << 16)
+#define   PME_B0_EN		(1 << 13)
+#define   ME_SCI_EN		(1 << 12)
+#define   PME_EN		(1 << 11)
+#define   BATLOW_EN		(1 << 10)
+#define   PCI_EXP_EN		(1 << 9)
+#define   TCOSCI_EN		(1 << 6)
+#define   SWGPE_EN		(1 << 2)
+#define   HOT_PLUG_EN		(1 << 1)
+
+#define MAINBOARD_POWER_OFF	0
+#define MAINBOARD_POWER_ON	1
+#define MAINBOARD_POWER_KEEP	2
+
+#define SLEEP_STATE_S0		0
+#define SLEEP_STATE_S3		3
+#define SLEEP_STATE_S5		5
+
+struct chipset_power_state {
+	uint16_t pm1_sts;
+	uint16_t pm1_en;
+	uint32_t pm1_cnt;
+	uint16_t tco1_sts;
+	uint16_t tco2_sts;
+	uint32_t gpe0_sts[4];
+	uint32_t gpe0_en[4];
+	uint16_t gen_pmcon1;
+	uint16_t gen_pmcon2;
+	uint16_t gen_pmcon3;
+	int prev_sleep_state;
+	uint16_t hsio_version;
+	uint16_t hsio_checksum;
+};
+
+void power_state_get(struct udevice *pch_dev, struct chipset_power_state *ps);
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/rcb.h b/arch/x86/include/asm/arch-broadwell/rcb.h
new file mode 100644
index 0000000..44fcddd
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/rcb.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __asm_arch_rcba_h
+#define __asm_arch_rcba_h
+
+#define PMSYNC_CONFIG	0x33c4	/* 32bit */
+#define PMSYNC_CONFIG2	0x33cc	/* 32bit */
+
+#define DEEP_S3_POL	0x3328	/* 32bit */
+#define  DEEP_S3_EN_AC		(1 << 0)
+#define  DEEP_S3_EN_DC		(1 << 1)
+#define DEEP_S5_POL	0x3330	/* 32bit */
+#define  DEEP_S5_EN_AC		(1 << 14)
+#define  DEEP_S5_EN_DC		(1 << 15)
+#define DEEP_SX_CONFIG	0x3334	/* 32bit */
+#define  DEEP_SX_WAKE_PIN_EN	(1 << 2)
+#define  DEEP_SX_ACPRESENT_PD	(1 << 1)
+#define  DEEP_SX_GP27_PIN_EN	(1 << 0)
+#define PMSYNC_CONFIG	0x33c4	/* 32bit */
+#define PMSYNC_CONFIG2	0x33cc	/* 32bit */
+
+#define RC		0x3400	/* 32bit */
+#define HPTC		0x3404	/* 32bit */
+#define GCS		0x3410	/* 32bit */
+#define BUC		0x3414	/* 32bit */
+#define PCH_DISABLE_GBE		(1 << 5)
+#define FD		0x3418	/* 32bit */
+#define FDSW		0x3420	/* 8bit */
+#define DISPBDF		0x3424  /* 16bit */
+#define FD2		0x3428	/* 32bit */
+#define CG		0x341c	/* 32bit */
+
+/* Function Disable 1 RCBA 0x3418 */
+#define PCH_DISABLE_ALWAYS	(1 << 0)
+#define PCH_DISABLE_ADSPD	(1 << 1)
+#define PCH_DISABLE_SATA1	(1 << 2)
+#define PCH_DISABLE_SMBUS	(1 << 3)
+#define PCH_DISABLE_HD_AUDIO	(1 << 4)
+#define PCH_DISABLE_EHCI2	(1 << 13)
+#define PCH_DISABLE_LPC		(1 << 14)
+#define PCH_DISABLE_EHCI1	(1 << 15)
+#define PCH_DISABLE_PCIE(x)	(1 << (16 + x))
+#define PCH_DISABLE_THERMAL	(1 << 24)
+#define PCH_DISABLE_SATA2	(1 << 25)
+#define PCH_DISABLE_XHCI	(1 << 27)
+
+/* Function Disable 2 RCBA 0x3428 */
+#define PCH_DISABLE_KT		(1 << 4)
+#define PCH_DISABLE_IDER	(1 << 3)
+#define PCH_DISABLE_MEI2	(1 << 2)
+#define PCH_DISABLE_MEI1	(1 << 1)
+#define PCH_ENABLE_DBDF		(1 << 0)
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/spi.h b/arch/x86/include/asm/arch-broadwell/spi.h
new file mode 100644
index 0000000..aeb4926
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/spi.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This file is from coreboot soc/intel/broadwell/include/soc/spi.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _BROADWELL_SPI_H_
+#define _BROADWELL_SPI_H_
+
+/*
+ * SPI Opcode Menu setup for SPIBAR lockdown
+ * should support most common flash chips.
+ */
+
+#define SPIBAR_OFFSET		0x3800
+#define SPI_REG(x)		(RCB_REG(SPIBAR_OFFSET + (x)))
+
+/* Reigsters within the SPIBAR */
+#define SPIBAR_SSFC		0x91
+#define SPIBAR_FDOC		0xb0
+#define SPIBAR_FDOD		0xb4
+
+#define SPIBAR_PREOP		0x94
+#define SPIBAR_OPTYPE		0x96
+#define SPIBAR_OPMENU_LOWER	0x98
+#define SPIBAR_OPMENU_UPPER	0x9c
+
+#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
+#define SPI_OPTYPE_0 0x01 /* Write, no address */
+
+#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
+#define SPI_OPTYPE_1 0x03 /* Write, address required */
+
+#define SPI_OPMENU_2 0x03 /* READ: Read Data */
+#define SPI_OPTYPE_2 0x02 /* Read, address required */
+
+#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
+#define SPI_OPTYPE_3 0x00 /* Read, no address */
+
+#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
+#define SPI_OPTYPE_4 0x03 /* Write, address required */
+
+#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
+#define SPI_OPTYPE_5 0x00 /* Read, no address */
+
+#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
+#define SPI_OPTYPE_6 0x03 /* Write, address required */
+
+#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
+#define SPI_OPTYPE_7 0x02 /* Read, address required */
+
+#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
+			  (SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
+#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
+			  (SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
+
+#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
+		    (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) |  \
+		    (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) |	  \
+		    (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
+
+#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
+
+#define SPIBAR_HSFS                 0x04   /* SPI hardware sequence status */
+#define  SPIBAR_HSFS_FLOCKDN        (1 << 15)/* Flash Configuration Lock-Down */
+#define  SPIBAR_HSFS_SCIP           (1 << 5) /* SPI Cycle In Progress */
+#define  SPIBAR_HSFS_AEL            (1 << 2) /* SPI Access Error Log */
+#define  SPIBAR_HSFS_FCERR          (1 << 1) /* SPI Flash Cycle Error */
+#define  SPIBAR_HSFS_FDONE          (1 << 0) /* SPI Flash Cycle Done */
+#define SPIBAR_HSFC                 0x06   /* SPI hardware sequence control */
+#define  SPIBAR_HSFC_BYTE_COUNT(c)  (((c - 1) & 0x3f) << 8)
+#define  SPIBAR_HSFC_CYCLE_READ     (0 << 1) /* Read cycle */
+#define  SPIBAR_HSFC_CYCLE_WRITE    (2 << 1) /* Write cycle */
+#define  SPIBAR_HSFC_CYCLE_ERASE    (3 << 1) /* Erase cycle */
+#define  SPIBAR_HSFC_GO             (1 << 0) /* GO: start SPI transaction */
+#define SPIBAR_FADDR                0x08   /* SPI flash address */
+#define SPIBAR_FDATA(n)             (0x10 + (4 * n)) /* SPI flash data */
+#define SPIBAR_SSFS                 0x90
+#define  SPIBAR_SSFS_ERROR          (1 << 3)
+#define  SPIBAR_SSFS_DONE           (1 << 2)
+#define SPIBAR_SSFC                 0x91
+#define  SPIBAR_SSFC_DATA           (1 << 14)
+#define  SPIBAR_SSFC_GO             (1 << 1)
+
+#endif
diff --git a/arch/x86/include/asm/arch-coreboot/sysinfo.h b/arch/x86/include/asm/arch-coreboot/sysinfo.h
index 2d57245..12b3b5d 100644
--- a/arch/x86/include/asm/arch-coreboot/sysinfo.h
+++ b/arch/x86/include/asm/arch-coreboot/sysinfo.h
@@ -9,7 +9,7 @@
 #ifndef _COREBOOT_SYSINFO_H
 #define _COREBOOT_SYSINFO_H
 
-#include <asm/arch/tables.h>
+#include <asm/coreboot_tables.h>
 
 /* Maximum number of memory range definitions */
 #define SYSINFO_MAX_MEM_RANGES	32
@@ -56,4 +56,6 @@
 
 extern struct sysinfo_t lib_sysinfo;
 
+int get_coreboot_info(struct sysinfo_t *info);
+
 #endif
diff --git a/arch/x86/include/asm/arch-coreboot/tables.h b/arch/x86/include/asm/arch-coreboot/tables.h
deleted file mode 100644
index e254484..0000000
--- a/arch/x86/include/asm/arch-coreboot/tables.h
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * This file is part of the libpayload project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * SPDX-License-Identifier:	BSD-3-Clause
- */
-
-#ifndef _COREBOOT_TABLES_H
-#define _COREBOOT_TABLES_H
-
-#include <linux/compiler.h>
-
-struct cbuint64 {
-	u32 lo;
-	u32 hi;
-};
-
-struct cb_header {
-	u8 signature[4];
-	u32 header_bytes;
-	u32 header_checksum;
-	u32 table_bytes;
-	u32 table_checksum;
-	u32 table_entries;
-};
-
-struct cb_record {
-	u32 tag;
-	u32 size;
-};
-
-#define CB_TAG_UNUSED     0x0000
-#define CB_TAG_MEMORY     0x0001
-
-struct cb_memory_range {
-	struct cbuint64 start;
-	struct cbuint64 size;
-	u32 type;
-};
-
-#define CB_MEM_RAM          1
-#define CB_MEM_RESERVED     2
-#define CB_MEM_ACPI         3
-#define CB_MEM_NVS          4
-#define CB_MEM_UNUSABLE     5
-#define CB_MEM_VENDOR_RSVD  6
-#define CB_MEM_TABLE       16
-
-struct cb_memory {
-	u32 tag;
-	u32 size;
-	struct cb_memory_range map[0];
-};
-
-#define CB_TAG_HWRPB      0x0002
-
-struct cb_hwrpb {
-	u32 tag;
-	u32 size;
-	u64 hwrpb;
-};
-
-#define CB_TAG_MAINBOARD  0x0003
-
-struct cb_mainboard {
-	u32 tag;
-	u32 size;
-	u8 vendor_idx;
-	u8 part_number_idx;
-	u8 strings[0];
-};
-
-#define CB_TAG_VERSION        0x0004
-#define CB_TAG_EXTRA_VERSION  0x0005
-#define CB_TAG_BUILD          0x0006
-#define CB_TAG_COMPILE_TIME   0x0007
-#define CB_TAG_COMPILE_BY     0x0008
-#define CB_TAG_COMPILE_HOST   0x0009
-#define CB_TAG_COMPILE_DOMAIN 0x000a
-#define CB_TAG_COMPILER       0x000b
-#define CB_TAG_LINKER         0x000c
-#define CB_TAG_ASSEMBLER      0x000d
-
-struct cb_string {
-	u32 tag;
-	u32 size;
-	u8 string[0];
-};
-
-#define CB_TAG_SERIAL         0x000f
-
-struct cb_serial {
-	u32 tag;
-	u32 size;
-#define CB_SERIAL_TYPE_IO_MAPPED     1
-#define CB_SERIAL_TYPE_MEMORY_MAPPED 2
-	u32 type;
-	u32 baseaddr;
-	u32 baud;
-};
-
-#define CB_TAG_CONSOLE       0x00010
-
-struct cb_console {
-	u32 tag;
-	u32 size;
-	u16 type;
-};
-
-#define CB_TAG_CONSOLE_SERIAL8250 0
-#define CB_TAG_CONSOLE_VGA        1 /* OBSOLETE */
-#define CB_TAG_CONSOLE_BTEXT      2 /* OBSOLETE */
-#define CB_TAG_CONSOLE_LOGBUF     3
-#define CB_TAG_CONSOLE_SROM       4 /* OBSOLETE */
-#define CB_TAG_CONSOLE_EHCI       5
-
-#define CB_TAG_FORWARD       0x00011
-
-struct cb_forward {
-	u32 tag;
-	u32 size;
-	u64 forward;
-};
-
-#define CB_TAG_FRAMEBUFFER      0x0012
-struct cb_framebuffer {
-	u32 tag;
-	u32 size;
-
-	u64 physical_address;
-	u32 x_resolution;
-	u32 y_resolution;
-	u32 bytes_per_line;
-	u8 bits_per_pixel;
-	u8 red_mask_pos;
-	u8 red_mask_size;
-	u8 green_mask_pos;
-	u8 green_mask_size;
-	u8 blue_mask_pos;
-	u8 blue_mask_size;
-	u8 reserved_mask_pos;
-	u8 reserved_mask_size;
-};
-
-#define CB_TAG_GPIO 0x0013
-#define GPIO_MAX_NAME_LENGTH 16
-struct cb_gpio {
-	u32 port;
-	u32 polarity;
-	u32 value;
-	u8 name[GPIO_MAX_NAME_LENGTH];
-};
-
-struct cb_gpios {
-	u32 tag;
-	u32 size;
-
-	u32 count;
-	struct cb_gpio gpios[0];
-};
-
-#define CB_TAG_FDT	0x0014
-struct cb_fdt {
-	uint32_t tag;
-	uint32_t size;	/* size of the entire entry */
-	/* the actual FDT gets placed here */
-};
-
-#define CB_TAG_VDAT	0x0015
-struct cb_vdat {
-	uint32_t tag;
-	uint32_t size;	/* size of the entire entry */
-	void	 *vdat_addr;
-	uint32_t vdat_size;
-};
-
-#define CB_TAG_TIMESTAMPS	0x0016
-#define CB_TAG_CBMEM_CONSOLE	0x0017
-#define CB_TAG_MRC_CACHE	0x0018
-struct cb_cbmem_tab {
-	uint32_t tag;
-	uint32_t size;
-	void   *cbmem_tab;
-};
-
-#define CB_TAG_VBNV		0x0019
-struct cb_vbnv {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t vbnv_start;
-	uint32_t vbnv_size;
-};
-
-#define CB_TAG_CMOS_OPTION_TABLE 0x00c8
-struct cb_cmos_option_table {
-	u32 tag;
-	u32 size;
-	u32 header_length;
-};
-
-#define CB_TAG_OPTION         0x00c9
-#define CMOS_MAX_NAME_LENGTH    32
-struct cb_cmos_entries {
-	u32 tag;
-	u32 size;
-	u32 bit;
-	u32 length;
-	u32 config;
-	u32 config_id;
-	u8 name[CMOS_MAX_NAME_LENGTH];
-};
-
-
-#define CB_TAG_OPTION_ENUM    0x00ca
-#define CMOS_MAX_TEXT_LENGTH 32
-struct cb_cmos_enums {
-	u32 tag;
-	u32 size;
-	u32 config_id;
-	u32 value;
-	u8 text[CMOS_MAX_TEXT_LENGTH];
-};
-
-#define CB_TAG_OPTION_DEFAULTS 0x00cb
-#define CMOS_IMAGE_BUFFER_SIZE 128
-struct cb_cmos_defaults {
-	u32 tag;
-	u32 size;
-	u32 name_length;
-	u8 name[CMOS_MAX_NAME_LENGTH];
-	u8 default_set[CMOS_IMAGE_BUFFER_SIZE];
-};
-
-#define CB_TAG_OPTION_CHECKSUM 0x00cc
-#define CHECKSUM_NONE	0
-#define CHECKSUM_PCBIOS	1
-struct	cb_cmos_checksum {
-	u32 tag;
-	u32 size;
-	u32 range_start;
-	u32 range_end;
-	u32 location;
-	u32 type;
-};
-
-/* Helpful macros */
-
-#define MEM_RANGE_COUNT(_rec) \
-	(((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0]))
-
-#define MEM_RANGE_PTR(_rec, _idx) \
-	(((u8 *) (_rec)) + sizeof(*(_rec)) \
-	+ (sizeof((_rec)->map[0]) * (_idx)))
-
-#define MB_VENDOR_STRING(_mb) \
-	(((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx)
-
-#define MB_PART_STRING(_mb) \
-	(((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx)
-
-#define UNPACK_CB64(_in) \
-	((((u64) _in.hi) << 32) | _in.lo)
-
-struct sysinfo_t;
-
-int get_coreboot_info(struct sysinfo_t *info);
-
-#define CBMEM_TOC_RESERVED      512
-#define MAX_CBMEM_ENTRIES       16
-#define CBMEM_MAGIC             0x434f5245
-
-struct cbmem_entry {
-	u32 magic;
-	u32 id;
-	u64 base;
-	u64 size;
-} __packed;
-
-#define CBMEM_ID_FREESPACE      0x46524545
-#define CBMEM_ID_GDT            0x4c474454
-#define CBMEM_ID_ACPI           0x41435049
-#define CBMEM_ID_CBTABLE        0x43425442
-#define CBMEM_ID_PIRQ           0x49525154
-#define CBMEM_ID_MPTABLE        0x534d5054
-#define CBMEM_ID_RESUME         0x5245534d
-#define CBMEM_ID_RESUME_SCRATCH 0x52455343
-#define CBMEM_ID_SMBIOS         0x534d4254
-#define CBMEM_ID_TIMESTAMP      0x54494d45
-#define CBMEM_ID_MRCDATA        0x4d524344
-#define CBMEM_ID_CONSOLE        0x434f4e53
-#define CBMEM_ID_NONE           0x00000000
-
-#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/me.h b/arch/x86/include/asm/arch-ivybridge/me.h
index eb1b73f..bc1bc8e 100644
--- a/arch/x86/include/asm/arch-ivybridge/me.h
+++ b/arch/x86/include/asm/arch-ivybridge/me.h
@@ -9,225 +9,7 @@
 #ifndef _ASM_INTEL_ME_H
 #define _ASM_INTEL_ME_H
 
-#include <linux/compiler.h>
-#include <linux/types.h>
-
-#define ME_RETRY		100000	/* 1 second */
-#define ME_DELAY		10	/* 10 us */
-
-/*
- * Management Engine PCI registers
- */
-
-#define PCI_CPU_MEBASE_L	0x70	/* Set by MRC */
-#define PCI_CPU_MEBASE_H	0x74	/* Set by MRC */
-
-#define PCI_ME_HFS		0x40
-#define  ME_HFS_CWS_RESET	0
-#define  ME_HFS_CWS_INIT	1
-#define  ME_HFS_CWS_REC		2
-#define  ME_HFS_CWS_NORMAL	5
-#define  ME_HFS_CWS_WAIT	6
-#define  ME_HFS_CWS_TRANS	7
-#define  ME_HFS_CWS_INVALID	8
-#define  ME_HFS_STATE_PREBOOT	0
-#define  ME_HFS_STATE_M0_UMA	1
-#define  ME_HFS_STATE_M3	4
-#define  ME_HFS_STATE_M0	5
-#define  ME_HFS_STATE_BRINGUP	6
-#define  ME_HFS_STATE_ERROR	7
-#define  ME_HFS_ERROR_NONE	0
-#define  ME_HFS_ERROR_UNCAT	1
-#define  ME_HFS_ERROR_IMAGE	3
-#define  ME_HFS_ERROR_DEBUG	4
-#define  ME_HFS_MODE_NORMAL	0
-#define  ME_HFS_MODE_DEBUG	2
-#define  ME_HFS_MODE_DIS	3
-#define  ME_HFS_MODE_OVER_JMPR	4
-#define  ME_HFS_MODE_OVER_MEI	5
-#define  ME_HFS_BIOS_DRAM_ACK	1
-#define  ME_HFS_ACK_NO_DID	0
-#define  ME_HFS_ACK_RESET	1
-#define  ME_HFS_ACK_PWR_CYCLE	2
-#define  ME_HFS_ACK_S3		3
-#define  ME_HFS_ACK_S4		4
-#define  ME_HFS_ACK_S5		5
-#define  ME_HFS_ACK_GBL_RESET	6
-#define  ME_HFS_ACK_CONTINUE	7
-
-struct me_hfs {
-	u32 working_state:4;
-	u32 mfg_mode:1;
-	u32 fpt_bad:1;
-	u32 operation_state:3;
-	u32 fw_init_complete:1;
-	u32 ft_bup_ld_flr:1;
-	u32 update_in_progress:1;
-	u32 error_code:4;
-	u32 operation_mode:4;
-	u32 reserved:4;
-	u32 boot_options_present:1;
-	u32 ack_data:3;
-	u32 bios_msg_ack:4;
-} __packed;
-
-#define PCI_ME_UMA		0x44
-
-struct me_uma {
-	u32 size:6;
-	u32 reserved_1:10;
-	u32 valid:1;
-	u32 reserved_0:14;
-	u32 set_to_one:1;
-} __packed;
-
-#define PCI_ME_H_GS		0x4c
-#define  ME_INIT_DONE		1
-#define  ME_INIT_STATUS_SUCCESS	0
-#define  ME_INIT_STATUS_NOMEM	1
-#define  ME_INIT_STATUS_ERROR	2
-
-struct me_did {
-	u32 uma_base:16;
-	u32 reserved:8;
-	u32 status:4;
-	u32 init_done:4;
-} __packed;
-
-#define PCI_ME_GMES		0x48
-#define  ME_GMES_PHASE_ROM	0
-#define  ME_GMES_PHASE_BUP	1
-#define  ME_GMES_PHASE_UKERNEL	2
-#define  ME_GMES_PHASE_POLICY	3
-#define  ME_GMES_PHASE_MODULE	4
-#define  ME_GMES_PHASE_UNKNOWN	5
-#define  ME_GMES_PHASE_HOST	6
-
-struct me_gmes {
-	u32 bist_in_prog:1;
-	u32 icc_prog_sts:2;
-	u32 invoke_mebx:1;
-	u32 cpu_replaced_sts:1;
-	u32 mbp_rdy:1;
-	u32 mfs_failure:1;
-	u32 warm_rst_req_for_df:1;
-	u32 cpu_replaced_valid:1;
-	u32 reserved_1:2;
-	u32 fw_upd_ipu:1;
-	u32 reserved_2:4;
-	u32 current_state:8;
-	u32 current_pmevent:4;
-	u32 progress_code:4;
-} __packed;
-
-#define PCI_ME_HERES		0xbc
-#define  PCI_ME_EXT_SHA1	0x00
-#define  PCI_ME_EXT_SHA256	0x02
-#define PCI_ME_HER(x)		(0xc0+(4*(x)))
-
-struct me_heres {
-	u32 extend_reg_algorithm:4;
-	u32 reserved:26;
-	u32 extend_feature_present:1;
-	u32 extend_reg_valid:1;
-} __packed;
-
-/*
- * Management Engine MEI registers
- */
-
-#define MEI_H_CB_WW		0x00
-#define MEI_H_CSR		0x04
-#define MEI_ME_CB_RW		0x08
-#define MEI_ME_CSR_HA		0x0c
-
-struct mei_csr {
-	u32 interrupt_enable:1;
-	u32 interrupt_status:1;
-	u32 interrupt_generate:1;
-	u32 ready:1;
-	u32 reset:1;
-	u32 reserved:3;
-	u32 buffer_read_ptr:8;
-	u32 buffer_write_ptr:8;
-	u32 buffer_depth:8;
-} __packed;
-
-#define MEI_ADDRESS_CORE	0x01
-#define MEI_ADDRESS_AMT		0x02
-#define MEI_ADDRESS_RESERVED	0x03
-#define MEI_ADDRESS_WDT		0x04
-#define MEI_ADDRESS_MKHI	0x07
-#define MEI_ADDRESS_ICC		0x08
-#define MEI_ADDRESS_THERMAL	0x09
-
-#define MEI_HOST_ADDRESS	0
-
-struct mei_header {
-	u32 client_address:8;
-	u32 host_address:8;
-	u32 length:9;
-	u32 reserved:6;
-	u32 is_complete:1;
-} __packed;
-
-#define MKHI_GROUP_ID_CBM	0x00
-#define MKHI_GROUP_ID_FWCAPS	0x03
-#define MKHI_GROUP_ID_MDES	0x08
-#define MKHI_GROUP_ID_GEN	0xff
-
-#define MKHI_GLOBAL_RESET	0x0b
-
-#define MKHI_FWCAPS_GET_RULE	0x02
-
-#define MKHI_MDES_ENABLE	0x09
-
-#define MKHI_GET_FW_VERSION	0x02
-#define MKHI_END_OF_POST	0x0c
-#define MKHI_FEATURE_OVERRIDE	0x14
-
-struct mkhi_header {
-	u32 group_id:8;
-	u32 command:7;
-	u32 is_response:1;
-	u32 reserved:8;
-	u32 result:8;
-} __packed;
-
-struct me_fw_version {
-	u16 code_minor;
-	u16 code_major;
-	u16 code_build_number;
-	u16 code_hot_fix;
-	u16 recovery_minor;
-	u16 recovery_major;
-	u16 recovery_build_number;
-	u16 recovery_hot_fix;
-} __packed;
-
-
-#define HECI_EOP_STATUS_SUCCESS       0x0
-#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
-
-#define CBM_RR_GLOBAL_RESET	0x01
-
-#define GLOBAL_RESET_BIOS_MRC	0x01
-#define GLOBAL_RESET_BIOS_POST	0x02
-#define GLOBAL_RESET_MEBX	0x03
-
-struct me_global_reset {
-	u8 request_origin;
-	u8 reset_type;
-} __packed;
-
-enum me_bios_path {
-	ME_NORMAL_BIOS_PATH,
-	ME_S3WAKE_BIOS_PATH,
-	ME_ERROR_BIOS_PATH,
-	ME_RECOVERY_BIOS_PATH,
-	ME_DISABLE_BIOS_PATH,
-	ME_FIRMWARE_UPDATE_BIOS_PATH,
-};
+#include <asm/me_common.h>
 
 struct __packed mbp_fw_version_name {
 	u32 major_version:16;
@@ -244,46 +26,6 @@
 	u32 register_lock_mask[3];
 };
 
-struct __packed mefwcaps_sku {
-	u32 full_net:1;
-	u32 std_net:1;
-	u32 manageability:1;
-	u32 small_business:1;
-	u32 l3manageability:1;
-	u32 intel_at:1;
-	u32 intel_cls:1;
-	u32 reserved:3;
-	u32 intel_mpc:1;
-	u32 icc_over_clocking:1;
-	u32 pavp:1;
-	u32 reserved_1:4;
-	u32 ipv6:1;
-	u32 kvm:1;
-	u32 och:1;
-	u32 vlan:1;
-	u32 tls:1;
-	u32 reserved_4:1;
-	u32 wlan:1;
-	u32 reserved_5:8;
-};
-
-struct __packed tdt_state_flag {
-	u16 lock_state:1;
-	u16 authenticate_module:1;
-	u16 s3authentication:1;
-	u16 flash_wear_out:1;
-	u16 flash_variable_security:1;
-	u16 wwan3gpresent:1;
-	u16 wwan3goob:1;
-	u16 reserved:9;
-};
-
-struct __packed tdt_state_info {
-	u8 state;
-	u8 last_theft_trigger;
-	struct tdt_state_flag flags;
-};
-
 struct __packed platform_type_rule_data {
 	u32 platform_target_usage_type:4;
 	u32 platform_target_market_type:2;
@@ -299,16 +41,6 @@
 	u8 available;
 };
 
-struct __packed mbp_rom_bist_data {
-	u16 device_id;
-	u16 fuse_test_flags;
-	u32 umchid[4];
-};
-
-struct __packed mbp_platform_key {
-	u32 key[8];
-};
-
 struct __packed mbp_plat_type {
 	struct platform_type_rule_data rule_data;
 	u8 available;
@@ -325,67 +57,4 @@
 	u32 mfsintegrity;
 };
 
-struct __packed mbp_header {
-	u32 mbp_size:8;
-	u32 num_entries:8;
-	u32 rsvd:16;
-};
-
-struct __packed mbp_item_header {
-	u32 app_id:8;
-	u32 item_id:8;
-	u32 length:8;
-	u32 rsvd:8;
-};
-
-struct __packed me_fwcaps {
-	u32 id;
-	u8 length;
-	struct mefwcaps_sku caps_sku;
-	u8 reserved[3];
-};
-
-/**
- * intel_me_status() - Check Intel Management Engine status
- *
- * struct hfs:	Firmware status
- * struct gmes:	Management engine status
- */
-void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
-
-/**
- * intel_early_me_status() - Check early Management Engine Status
- *
- * @me_dev:	Management engine PCI device
- */
-void intel_early_me_status(struct udevice *me_dev);
-
-/**
- * intel_early_me_init() - Early Intel Management Engine init
- *
- * @me_dev:	Management engine PCI device
- * @return 0 if OK, -ve on error
- */
-int intel_early_me_init(struct udevice *me_dev);
-
-/**
- * intel_early_me_uma_size() - Get UMA size from the Intel Management Engine
- *
- * @me_dev:	Management engine PCI device
- * @return UMA size if OK, -EINVAL on error
- */
-int intel_early_me_uma_size(struct udevice *me_dev);
-
-/**
- * intel_early_me_init_done() - Complete Intel Management Engine init
- *
- * @dev:	Northbridge device
- * @me_dev:	Management engine PCI device
- * @status:	Status result (ME_INIT_...)
- * @return 0 to continue to boot, -EINVAL on unknown result data, -ETIMEDOUT
- * if ME did not respond
- */
-int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
-			     uint status);
-
 #endif
diff --git a/arch/x86/include/asm/arch-ivybridge/model_206ax.h b/arch/x86/include/asm/arch-ivybridge/model_206ax.h
index d2f9006..22f7929 100644
--- a/arch/x86/include/asm/arch-ivybridge/model_206ax.h
+++ b/arch/x86/include/asm/arch-ivybridge/model_206ax.h
@@ -15,13 +15,9 @@
 #define  CPUID_VMX			(1 << 5)
 #define  CPUID_SMX			(1 << 6)
 #define MSR_FEATURE_CONFIG		0x13c
-#define MSR_FLEX_RATIO			0x194
-#define  FLEX_RATIO_LOCK		(1 << 20)
-#define  FLEX_RATIO_EN			(1 << 16)
 #define IA32_PLATFORM_DCA_CAP		0x1f8
 #define IA32_MISC_ENABLE		0x1a0
 #define MSR_TEMPERATURE_TARGET		0x1a2
-#define IA32_PERF_CTL			0x199
 #define IA32_THERM_INTERRUPT		0x19b
 #define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
 #define  ENERGY_POLICY_PERFORMANCE	0
@@ -31,12 +27,8 @@
 #define MSR_LT_LOCK_MEMORY		0x2e7
 #define IA32_MC0_STATUS		0x401
 
-#define MSR_PIC_MSG_CONTROL		0x2e
-#define  PLATFORM_INFO_SET_TDP		(1 << 29)
-
 #define MSR_MISC_PWR_MGMT		0x1aa
 #define  MISC_PWR_MGMT_EIST_HW_DIS	(1 << 0)
-#define MSR_TURBO_RATIO_LIMIT		0x1ad
 
 #define MSR_PKGC3_IRTL			0x60a
 #define MSR_PKGC6_IRTL			0x60b
@@ -50,13 +42,6 @@
 #define  IRTL_33554432_NS		(5 << 10)
 #define  IRTL_RESPONSE_MASK		(0x3ff)
 
-/* long duration in low dword, short duration in high dword */
-#define  PKG_POWER_LIMIT_MASK		0x7fff
-#define  PKG_POWER_LIMIT_EN		(1 << 15)
-#define  PKG_POWER_LIMIT_CLAMP		(1 << 16)
-#define  PKG_POWER_LIMIT_TIME_SHIFT	17
-#define  PKG_POWER_LIMIT_TIME_MASK	0x7f
-
 #define MSR_PP0_CURRENT_CONFIG		0x601
 #define  PP0_CURRENT_LIMIT		(112 << 3) /* 112 A */
 #define MSR_PP1_CURRENT_CONFIG		0x602
@@ -65,11 +50,9 @@
 #define MSR_PKG_POWER_SKU		0x614
 
 #define IVB_CONFIG_TDP_MIN_CPUID	0x306a2
-#define MSR_CONFIG_TDP_NOMINAL		0x648
 #define MSR_CONFIG_TDP_LEVEL1		0x649
 #define MSR_CONFIG_TDP_LEVEL2		0x64a
 #define MSR_CONFIG_TDP_CONTROL		0x64b
-#define MSR_TURBO_ACTIVATION_RATIO	0x64c
 
 /* P-state configuration */
 #define PSS_MAX_ENTRIES			8
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
index af3e8e7..4725250 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -69,8 +69,6 @@
 #define RTC_POWER_FAILED	(1 << 1)
 #define SLEEP_AFTER_POWER_FAIL	(1 << 0)
 
-#define PMBASE			0x40
-#define ACPI_CNTL		0x44
 #define BIOS_CNTL		0xDC
 #define GPIO_BASE		0x48 /* LPC GPIO Base Address Register */
 #define GPIO_CNTL		0x4C /* LPC GPIO Control Register */
@@ -99,60 +97,11 @@
 #define GPIO_CNTL		0x4C /* LPC GPIO Control Register */
 #define GPIO_ROUT		0xb8
 
-#define LPC_IO_DEC		0x80 /* IO Decode Ranges Register */
-#define  COMB_DEC_RANGE		(1 << 4)  /* 0x2f8-0x2ff (COM2) */
-#define  COMA_DEC_RANGE		(0 << 0)  /* 0x3f8-0x3ff (COM1) */
-#define LPC_EN			0x82 /* LPC IF Enables Register */
-#define  CNF2_LPC_EN		(1 << 13) /* 0x4e/0x4f */
-#define  CNF1_LPC_EN		(1 << 12) /* 0x2e/0x2f */
-#define  MC_LPC_EN		(1 << 11) /* 0x62/0x66 */
-#define  KBC_LPC_EN		(1 << 10) /* 0x60/0x64 */
-#define  GAMEH_LPC_EN		(1 << 9)  /* 0x208/0x20f */
-#define  GAMEL_LPC_EN		(1 << 8)  /* 0x200/0x207 */
-#define  FDD_LPC_EN		(1 << 3)  /* LPC_IO_DEC[12] */
-#define  LPT_LPC_EN		(1 << 2)  /* LPC_IO_DEC[9:8] */
-#define  COMB_LPC_EN		(1 << 1)  /* LPC_IO_DEC[6:4] */
-#define  COMA_LPC_EN		(1 << 0)  /* LPC_IO_DEC[3:2] */
-#define LPC_GEN1_DEC		0x84 /* LPC IF Generic Decode Range 1 */
-#define LPC_GEN2_DEC		0x88 /* LPC IF Generic Decode Range 2 */
-#define LPC_GEN3_DEC		0x8c /* LPC IF Generic Decode Range 3 */
-#define LPC_GEN4_DEC		0x90 /* LPC IF Generic Decode Range 4 */
-#define LPC_GENX_DEC(x)		(0x84 + 4 * (x))
-#define  GEN_DEC_RANGE_256B	0xfc0000  /* 256 Bytes */
-#define  GEN_DEC_RANGE_128B	0x7c0000  /* 128 Bytes */
-#define  GEN_DEC_RANGE_64B	0x3c0000  /* 64 Bytes */
-#define  GEN_DEC_RANGE_32B	0x1c0000  /* 32 Bytes */
-#define  GEN_DEC_RANGE_16B	0x0c0000  /* 16 Bytes */
-#define  GEN_DEC_RANGE_8B	0x040000  /* 8 Bytes */
-#define  GEN_DEC_RANGE_4B	0x000000  /* 4 Bytes */
-#define  GEN_DEC_RANGE_EN	(1 << 0)  /* Range Enable */
-
 /* PCI Configuration Space (D31:F1): IDE */
 #define PCH_IDE_DEV		PCI_BDF(0, 0x1f, 1)
 #define PCH_SATA_DEV		PCI_BDF(0, 0x1f, 2)
 #define PCH_SATA2_DEV		PCI_BDF(0, 0x1f, 5)
 
-#define INTR_LN			0x3c
-#define IDE_TIM_PRI		0x40	/* IDE timings, primary */
-#define   IDE_DECODE_ENABLE	(1 << 15)
-#define   IDE_SITRE		(1 << 14)
-#define   IDE_ISP_5_CLOCKS	(0 << 12)
-#define   IDE_ISP_4_CLOCKS	(1 << 12)
-#define   IDE_ISP_3_CLOCKS	(2 << 12)
-#define   IDE_RCT_4_CLOCKS	(0 <<  8)
-#define   IDE_RCT_3_CLOCKS	(1 <<  8)
-#define   IDE_RCT_2_CLOCKS	(2 <<  8)
-#define   IDE_RCT_1_CLOCKS	(3 <<  8)
-#define   IDE_DTE1		(1 <<  7)
-#define   IDE_PPE1		(1 <<  6)
-#define   IDE_IE1		(1 <<  5)
-#define   IDE_TIME1		(1 <<  4)
-#define   IDE_DTE0		(1 <<  3)
-#define   IDE_PPE0		(1 <<  2)
-#define   IDE_IE0		(1 <<  1)
-#define   IDE_TIME0		(1 <<  0)
-#define IDE_TIM_SEC		0x42	/* IDE timings, secondary */
-
 #define IDE_SDMA_CNT		0x48	/* Synchronous DMA control */
 #define   IDE_SSDE1		(1 <<  3)
 #define   IDE_SSDE0		(1 <<  2)
@@ -211,13 +160,6 @@
 
 #define SMBUS_TIMEOUT		(10 * 1000 * 100)
 
-
-/* Root Complex Register Block */
-#define DEFAULT_RCBA		0xfed1c000
-#define RCB_REG(reg)		(DEFAULT_RCBA + (reg))
-
-#define PCH_RCBA_BASE		0xf0
-
 #define VCH		0x0000	/* 32bit */
 #define VCAP1		0x0004	/* 32bit */
 #define VCAP2		0x0008	/* 32bit */
@@ -339,16 +281,12 @@
 #define SPI_FREQ_SWSEQ	0x3893
 #define SPI_DESC_COMP0	0x38b0
 #define SPI_FREQ_WR_ERA	0x38b4
-#define SOFT_RESET_CTRL 0x38f4
-#define SOFT_RESET_DATA 0x38f8
 
 #define DIR_ROUTE(a, b, c, d) \
 		(((d) << DIR_IDR) | ((c) << DIR_ICR) | \
 			((b) << DIR_IBR) | ((a) << DIR_IAR))
 
-#define RC		0x3400	/* 32bit */
 #define HPTC		0x3404	/* 32bit */
-#define GCS		0x3410	/* 32bit */
 #define BUC		0x3414	/* 32bit */
 #define PCH_DISABLE_GBE		(1 << 5)
 #define FD		0x3418	/* 32bit */
diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
index d137d67..8e0f668 100644
--- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h
+++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
@@ -38,7 +38,6 @@
 #define IED_SIZE	0x400000
 
 /* Northbridge BARs */
-#define DEFAULT_MCHBAR		0xfed10000	/* 16 KB */
 #define DEFAULT_DMIBAR		0xfed18000	/* 4 KB */
 #define DEFAULT_EPBAR		0xfed19000	/* 4 KB */
 #define DEFAULT_RCBABASE	0xfed1c000
@@ -97,8 +96,6 @@
 /*
  * MCHBAR
  */
-#define MCHBAR_REG(reg)		(DEFAULT_MCHBAR + (reg))
-
 #define SSKPD		0x5d14	/* 16bit (scratchpad) */
 #define BIOS_RESET_CPL	0x5da8	/* 8bit */
 
@@ -116,8 +113,4 @@
  */
 int bridge_silicon_revision(struct udevice *dev);
 
-void report_platform_info(struct udevice *dev);
-
-void sandybridge_early_init(int chipset_type);
-
 #endif
diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h
new file mode 100644
index 0000000..15ccf9b
--- /dev/null
+++ b/arch/x86/include/asm/coreboot_tables.h
@@ -0,0 +1,307 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef _COREBOOT_TABLES_H
+#define _COREBOOT_TABLES_H
+
+struct cbuint64 {
+	u32 lo;
+	u32 hi;
+};
+
+struct cb_header {
+	u8 signature[4];
+	u32 header_bytes;
+	u32 header_checksum;
+	u32 table_bytes;
+	u32 table_checksum;
+	u32 table_entries;
+};
+
+struct cb_record {
+	u32 tag;
+	u32 size;
+};
+
+#define CB_TAG_UNUSED			0x0000
+#define CB_TAG_MEMORY			0x0001
+
+struct cb_memory_range {
+	struct cbuint64 start;
+	struct cbuint64 size;
+	u32 type;
+};
+
+#define CB_MEM_RAM			1
+#define CB_MEM_RESERVED			2
+#define CB_MEM_ACPI			3
+#define CB_MEM_NVS			4
+#define CB_MEM_UNUSABLE			5
+#define CB_MEM_VENDOR_RSVD		6
+#define CB_MEM_TABLE			16
+
+struct cb_memory {
+	u32 tag;
+	u32 size;
+	struct cb_memory_range map[0];
+};
+
+#define CB_TAG_HWRPB			0x0002
+
+struct cb_hwrpb {
+	u32 tag;
+	u32 size;
+	u64 hwrpb;
+};
+
+#define CB_TAG_MAINBOARD		0x0003
+
+struct cb_mainboard {
+	u32 tag;
+	u32 size;
+	u8 vendor_idx;
+	u8 part_number_idx;
+	u8 strings[0];
+};
+
+#define CB_TAG_VERSION			0x0004
+#define CB_TAG_EXTRA_VERSION		0x0005
+#define CB_TAG_BUILD			0x0006
+#define CB_TAG_COMPILE_TIME		0x0007
+#define CB_TAG_COMPILE_BY		0x0008
+#define CB_TAG_COMPILE_HOST		0x0009
+#define CB_TAG_COMPILE_DOMAIN		0x000a
+#define CB_TAG_COMPILER			0x000b
+#define CB_TAG_LINKER			0x000c
+#define CB_TAG_ASSEMBLER		0x000d
+
+struct cb_string {
+	u32 tag;
+	u32 size;
+	u8 string[0];
+};
+
+#define CB_TAG_SERIAL			0x000f
+
+struct cb_serial {
+	u32 tag;
+	u32 size;
+#define CB_SERIAL_TYPE_IO_MAPPED	1
+#define CB_SERIAL_TYPE_MEMORY_MAPPED	2
+	u32 type;
+	u32 baseaddr;
+	u32 baud;
+};
+
+#define CB_TAG_CONSOLE			0x0010
+
+struct cb_console {
+	u32 tag;
+	u32 size;
+	u16 type;
+};
+
+#define CB_TAG_CONSOLE_SERIAL8250	0
+#define CB_TAG_CONSOLE_VGA		1 /* OBSOLETE */
+#define CB_TAG_CONSOLE_BTEXT		2 /* OBSOLETE */
+#define CB_TAG_CONSOLE_LOGBUF		3
+#define CB_TAG_CONSOLE_SROM		4 /* OBSOLETE */
+#define CB_TAG_CONSOLE_EHCI		5
+
+#define CB_TAG_FORWARD			0x0011
+
+struct cb_forward {
+	u32 tag;
+	u32 size;
+	u64 forward;
+};
+
+#define CB_TAG_FRAMEBUFFER		0x0012
+
+struct cb_framebuffer {
+	u32 tag;
+	u32 size;
+	u64 physical_address;
+	u32 x_resolution;
+	u32 y_resolution;
+	u32 bytes_per_line;
+	u8 bits_per_pixel;
+	u8 red_mask_pos;
+	u8 red_mask_size;
+	u8 green_mask_pos;
+	u8 green_mask_size;
+	u8 blue_mask_pos;
+	u8 blue_mask_size;
+	u8 reserved_mask_pos;
+	u8 reserved_mask_size;
+};
+
+#define CB_TAG_GPIO			0x0013
+#define GPIO_MAX_NAME_LENGTH		16
+
+struct cb_gpio {
+	u32 port;
+	u32 polarity;
+	u32 value;
+	u8 name[GPIO_MAX_NAME_LENGTH];
+};
+
+struct cb_gpios {
+	u32 tag;
+	u32 size;
+	u32 count;
+	struct cb_gpio gpios[0];
+};
+
+#define CB_TAG_FDT			0x0014
+
+struct cb_fdt {
+	uint32_t tag;
+	uint32_t size;	/* size of the entire entry */
+	/* the actual FDT gets placed here */
+};
+
+#define CB_TAG_VDAT			0x0015
+
+struct cb_vdat {
+	uint32_t tag;
+	uint32_t size;	/* size of the entire entry */
+	void *vdat_addr;
+	uint32_t vdat_size;
+};
+
+#define CB_TAG_TIMESTAMPS		0x0016
+#define CB_TAG_CBMEM_CONSOLE		0x0017
+#define CB_TAG_MRC_CACHE		0x0018
+
+struct cb_cbmem_tab {
+	uint32_t tag;
+	uint32_t size;
+	void *cbmem_tab;
+};
+
+#define CB_TAG_VBNV			0x0019
+
+struct cb_vbnv {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t vbnv_start;
+	uint32_t vbnv_size;
+};
+
+#define CB_TAG_CMOS_OPTION_TABLE	0x00c8
+
+struct cb_cmos_option_table {
+	u32 tag;
+	u32 size;
+	u32 header_length;
+};
+
+#define CB_TAG_OPTION			0x00c9
+
+#define CMOS_MAX_NAME_LENGTH		32
+
+struct cb_cmos_entries {
+	u32 tag;
+	u32 size;
+	u32 bit;
+	u32 length;
+	u32 config;
+	u32 config_id;
+	u8 name[CMOS_MAX_NAME_LENGTH];
+};
+
+#define CB_TAG_OPTION_ENUM		0x00ca
+#define CMOS_MAX_TEXT_LENGTH		32
+
+struct cb_cmos_enums {
+	u32 tag;
+	u32 size;
+	u32 config_id;
+	u32 value;
+	u8 text[CMOS_MAX_TEXT_LENGTH];
+};
+
+#define CB_TAG_OPTION_DEFAULTS		0x00cb
+#define CMOS_IMAGE_BUFFER_SIZE		128
+
+struct cb_cmos_defaults {
+	u32 tag;
+	u32 size;
+	u32 name_length;
+	u8 name[CMOS_MAX_NAME_LENGTH];
+	u8 default_set[CMOS_IMAGE_BUFFER_SIZE];
+};
+
+#define CB_TAG_OPTION_CHECKSUM		0x00cc
+#define CHECKSUM_NONE			0
+#define CHECKSUM_PCBIOS			1
+
+struct	cb_cmos_checksum {
+	u32 tag;
+	u32 size;
+	u32 range_start;
+	u32 range_end;
+	u32 location;
+	u32 type;
+};
+
+/* Helpful macros */
+
+#define MEM_RANGE_COUNT(_rec) \
+	(((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0]))
+
+#define MEM_RANGE_PTR(_rec, _idx) \
+	(((u8 *) (_rec)) + sizeof(*(_rec)) \
+	+ (sizeof((_rec)->map[0]) * (_idx)))
+
+#define MB_VENDOR_STRING(_mb) \
+	(((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx)
+
+#define MB_PART_STRING(_mb) \
+	(((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx)
+
+#define UNPACK_CB64(_in) \
+	((((u64) _in.hi) << 32) | _in.lo)
+
+#define CBMEM_TOC_RESERVED		512
+#define MAX_CBMEM_ENTRIES		16
+#define CBMEM_MAGIC			0x434f5245
+
+struct cbmem_entry {
+	u32 magic;
+	u32 id;
+	u64 base;
+	u64 size;
+} __packed;
+
+#define CBMEM_ID_FREESPACE		0x46524545
+#define CBMEM_ID_GDT			0x4c474454
+#define CBMEM_ID_ACPI			0x41435049
+#define CBMEM_ID_CBTABLE		0x43425442
+#define CBMEM_ID_PIRQ			0x49525154
+#define CBMEM_ID_MPTABLE		0x534d5054
+#define CBMEM_ID_RESUME			0x5245534d
+#define CBMEM_ID_RESUME_SCRATCH		0x52455343
+#define CBMEM_ID_SMBIOS			0x534d4254
+#define CBMEM_ID_TIMESTAMP		0x54494d45
+#define CBMEM_ID_MRCDATA		0x4d524344
+#define CBMEM_ID_CONSOLE		0x434f4e53
+#define CBMEM_ID_NONE			0x00000000
+
+/**
+ * write_coreboot_table() - write coreboot table
+ *
+ * This writes coreboot table at a given address.
+ *
+ * @addr:	start address to write coreboot table
+ * @cfg_tables:	pointer to configuration table memory area
+ */
+void write_coreboot_table(u32 addr, struct memory_area *cfg_tables);
+
+#endif
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 18b0345..7892757 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -54,6 +54,7 @@
 	X86_NONE,
 	X86_SYSCON_ME,		/* Intel Management Engine */
 	X86_SYSCON_GMA,		/* Intel Graphics Media Accelerator */
+	X86_SYSCON_PINCONF,	/* Intel x86 pin configuration */
 };
 
 struct cpuid_result {
@@ -260,4 +261,30 @@
  */
 int cpu_jump_to_64bit(ulong setup_base, ulong target);
 
+/**
+ * cpu_get_family_model() - Get the family and model for the CPU
+ *
+ * @return the CPU ID masked with 0x0fff0ff0
+ */
+u32 cpu_get_family_model(void);
+
+/**
+ * cpu_get_stepping() - Get the stepping value for the CPU
+ *
+ * @return the CPU ID masked with 0xf
+ */
+u32 cpu_get_stepping(void);
+
+/**
+ * cpu_run_reference_code() - Run the platform reference code
+ *
+ * Some platforms require a binary blob to be executed once SDRAM is
+ * available. This is used to set up various platform features, such as the
+ * platform controller hub (PCH). This function should be implemented by the
+ * CPU-specific code.
+ *
+ * @return 0 on success, -ve on failure
+ */
+int cpu_run_reference_code(void);
+
 #endif
diff --git a/arch/x86/include/asm/cpu_common.h b/arch/x86/include/asm/cpu_common.h
new file mode 100644
index 0000000..562de3e
--- /dev/null
+++ b/arch/x86/include/asm/cpu_common.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_CPU_COMMON_H
+#define __ASM_CPU_COMMON_H
+
+#define IA32_PERF_CTL			0x199
+
+/**
+ * cpu_common_init() - Set up common CPU init
+ *
+ * This reports BIST failure, enables the LAPIC, updates microcode, enables
+ * the upper 128-bytes of CROM RAM, probes the northbridge, PCH, LPC and SATA.
+ *
+ * @return 0 if OK, -ve on error
+ */
+int cpu_common_init(void);
+
+/**
+ * cpu_set_flex_ratio_to_tdp_nominal() - Set up the maximum non-turbo rate
+ *
+ * If a change is needed, this function will do a soft reset so it takes
+ * effect.
+ *
+ * Some details are available here:
+ * http://forum.hwbot.org/showthread.php?t=76092
+ *
+ * @return 0 if OK, -ve on error
+ */
+int cpu_set_flex_ratio_to_tdp_nominal(void);
+
+#endif
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 0ca518c..3bc2ac2 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -19,6 +19,29 @@
 
 };
 
+struct dimm_info {
+	uint32_t dimm_size;
+	uint16_t ddr_type;
+	uint16_t ddr_frequency;
+	uint8_t rank_per_dimm;
+	uint8_t channel_num;
+	uint8_t dimm_num;
+	uint8_t bank_locator;
+	/* The 5th byte is '\0' for the end of string */
+	uint8_t serial[5];
+	/* The 19th byte is '\0' for the end of string */
+	uint8_t module_part_number[19];
+	uint16_t mod_id;
+	uint8_t mod_type;
+	uint8_t bus_width;
+} __packed;
+
+struct pei_memory_info {
+	uint8_t dimm_cnt;
+	/* Maximum num of dimm is 8 */
+	struct dimm_info dimm[8];
+} __packed;
+
 struct memory_area {
 	uint64_t start;
 	uint64_t size;
@@ -59,6 +82,7 @@
 	enum pei_boot_mode_t pei_boot_mode;
 	const struct pch_gpio_map *gpio_map;	/* board GPIO map */
 	struct memory_info meminfo;	/* Memory information */
+	struct pei_memory_info pei_meminfo;	/* PEI memory information */
 #ifdef CONFIG_HAVE_FSP
 	void *hob_list;			/* FSP HOB list */
 #endif
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 403851b..586ece6 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -6,148 +6,12 @@
 #ifndef _X86_GPIO_H_
 #define _X86_GPIO_H_
 
-#include <linux/compiler.h>
 #include <asm-generic/gpio.h>
 
 struct ich6_bank_platdata {
 	uint16_t base_addr;
 	const char *bank_name;
+	int offset;
 };
 
-#define GPIO_MODE_NATIVE	0
-#define GPIO_MODE_GPIO		1
-#define GPIO_MODE_NONE		1
-
-#define GPIO_DIR_OUTPUT		0
-#define GPIO_DIR_INPUT		1
-
-#define GPIO_NO_INVERT		0
-#define GPIO_INVERT		1
-
-#define GPIO_LEVEL_LOW		0
-#define GPIO_LEVEL_HIGH		1
-
-#define GPIO_NO_BLINK		0
-#define GPIO_BLINK		1
-
-#define GPIO_RESET_PWROK	0
-#define GPIO_RESET_RSMRST	1
-
-struct pch_gpio_set1 {
-	u32 gpio0:1;
-	u32 gpio1:1;
-	u32 gpio2:1;
-	u32 gpio3:1;
-	u32 gpio4:1;
-	u32 gpio5:1;
-	u32 gpio6:1;
-	u32 gpio7:1;
-	u32 gpio8:1;
-	u32 gpio9:1;
-	u32 gpio10:1;
-	u32 gpio11:1;
-	u32 gpio12:1;
-	u32 gpio13:1;
-	u32 gpio14:1;
-	u32 gpio15:1;
-	u32 gpio16:1;
-	u32 gpio17:1;
-	u32 gpio18:1;
-	u32 gpio19:1;
-	u32 gpio20:1;
-	u32 gpio21:1;
-	u32 gpio22:1;
-	u32 gpio23:1;
-	u32 gpio24:1;
-	u32 gpio25:1;
-	u32 gpio26:1;
-	u32 gpio27:1;
-	u32 gpio28:1;
-	u32 gpio29:1;
-	u32 gpio30:1;
-	u32 gpio31:1;
-} __packed;
-
-struct pch_gpio_set2 {
-	u32 gpio32:1;
-	u32 gpio33:1;
-	u32 gpio34:1;
-	u32 gpio35:1;
-	u32 gpio36:1;
-	u32 gpio37:1;
-	u32 gpio38:1;
-	u32 gpio39:1;
-	u32 gpio40:1;
-	u32 gpio41:1;
-	u32 gpio42:1;
-	u32 gpio43:1;
-	u32 gpio44:1;
-	u32 gpio45:1;
-	u32 gpio46:1;
-	u32 gpio47:1;
-	u32 gpio48:1;
-	u32 gpio49:1;
-	u32 gpio50:1;
-	u32 gpio51:1;
-	u32 gpio52:1;
-	u32 gpio53:1;
-	u32 gpio54:1;
-	u32 gpio55:1;
-	u32 gpio56:1;
-	u32 gpio57:1;
-	u32 gpio58:1;
-	u32 gpio59:1;
-	u32 gpio60:1;
-	u32 gpio61:1;
-	u32 gpio62:1;
-	u32 gpio63:1;
-} __packed;
-
-struct pch_gpio_set3 {
-	u32 gpio64:1;
-	u32 gpio65:1;
-	u32 gpio66:1;
-	u32 gpio67:1;
-	u32 gpio68:1;
-	u32 gpio69:1;
-	u32 gpio70:1;
-	u32 gpio71:1;
-	u32 gpio72:1;
-	u32 gpio73:1;
-	u32 gpio74:1;
-	u32 gpio75:1;
-} __packed;
-
-/*
- * This hilariously complex structure came from Coreboot. The
- * setup_pch_gpios() function uses it. It could be move to device tree, or
- * adjust to use masks instead of bitfields.
- */
-struct pch_gpio_map {
-	struct {
-		const struct pch_gpio_set1 *mode;
-		const struct pch_gpio_set1 *direction;
-		const struct pch_gpio_set1 *level;
-		const struct pch_gpio_set1 *reset;
-		const struct pch_gpio_set1 *invert;
-		const struct pch_gpio_set1 *blink;
-	} set1;
-	struct {
-		const struct pch_gpio_set2 *mode;
-		const struct pch_gpio_set2 *direction;
-		const struct pch_gpio_set2 *level;
-		const struct pch_gpio_set2 *reset;
-	} set2;
-	struct {
-		const struct pch_gpio_set3 *mode;
-		const struct pch_gpio_set3 *direction;
-		const struct pch_gpio_set3 *level;
-		const struct pch_gpio_set3 *reset;
-	} set3;
-};
-
-int gpio_ich6_pinctrl_init(void);
-void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
-void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
-
 #endif /* _X86_GPIO_H_ */
diff --git a/arch/x86/include/asm/intel_regs.h b/arch/x86/include/asm/intel_regs.h
new file mode 100644
index 0000000..d2a6d26
--- /dev/null
+++ b/arch/x86/include/asm/intel_regs.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_INTEL_REGS_H
+#define __ASM_INTEL_REGS_H
+
+/* Access the memory-controller hub */
+#define MCH_BASE_ADDRESS	0xfed10000
+#define MCH_BASE_SIZE		0x8000
+#define MCHBAR_REG(reg)		(MCH_BASE_ADDRESS + (reg))
+
+#define MCHBAR_PEI_VERSION	0x5034
+#define MCH_PKG_POWER_LIMIT_LO	0x59a0
+#define MCH_PKG_POWER_LIMIT_HI	0x59a4
+#define MCH_DDR_POWER_LIMIT_LO	0x58e0
+#define MCH_DDR_POWER_LIMIT_HI	0x58e4
+
+/* Access the Root Complex Register Block */
+#define RCB_BASE_ADDRESS	0xfed1c000
+#define RCB_REG(reg)		(RCB_BASE_ADDRESS + (reg))
+
+#define SOFT_RESET_CTRL		0x38f4
+#define SOFT_RESET_DATA		0x38f8
+
+#endif
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index e0b2561..3156781 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -202,7 +202,7 @@
  * Talk about misusing macros..
  */
 #define __OUT1(s,x) \
-static inline void out##s(unsigned x value, unsigned short port) {
+static inline void _out##s(unsigned x value, unsigned short port) {
 
 #define __OUT2(s,s1,s2) \
 __asm__ __volatile__ ("out" #s " %" s1 "0,%" s2 "1"
@@ -213,7 +213,7 @@
 __OUT1(s##_p,x) __OUT2(s,s1,"w") __FULL_SLOW_DOWN_IO : : "a" (value), "Nd" (port));}
 
 #define __IN1(s) \
-static inline RETURN_TYPE in##s(unsigned short port) { RETURN_TYPE _v;
+static inline RETURN_TYPE _in##s(unsigned short port) { RETURN_TYPE _v;
 
 #define __IN2(s,s1,s2) \
 __asm__ __volatile__ ("in" #s " %" s2 "1,%" s1 "0"
@@ -242,10 +242,18 @@
 __IN(l,"")
 #undef RETURN_TYPE
 
+#define inb(port)	_inb((uintptr_t)(port))
+#define inw(port)	_inw((uintptr_t)(port))
+#define inl(port)	_inl((uintptr_t)(port))
+
 __OUT(b,"b",char)
 __OUT(w,"w",short)
 __OUT(l,,int)
 
+#define outb(val, port)	_outb(val, (uintptr_t)(port))
+#define outw(val, port)	_outw(val, (uintptr_t)(port))
+#define outl(val, port)	_outl(val, (uintptr_t)(port))
+
 __INS(b)
 __INS(w)
 __INS(l)
@@ -254,6 +262,28 @@
 __OUTS(w)
 __OUTS(l)
 
+/* IO space accessors */
+#define clrio(type, addr, clear) \
+	out##type(in##type(addr) & ~(clear), (addr))
+
+#define setio(type, addr, set) \
+	out##type(in##type(addr) | (set), (addr))
+
+#define clrsetio(type, addr, clear, set) \
+	out##type((in##type(addr) & ~(clear)) | (set), (addr))
+
+#define clrio_32(addr, clear) clrio(l, addr, clear)
+#define clrio_16(addr, clear) clrio(w, addr, clear)
+#define clrio_8(addr, clear) clrio(b, addr, clear)
+
+#define setio_32(addr, set) setio(l, addr, set)
+#define setio_16(addr, set) setio(w, addr, set)
+#define setio_8(addr, set) setio(b, addr, set)
+
+#define clrsetio_32(addr, clear, set) clrsetio(l, addr, clear, set)
+#define clrsetio_16(addr, clear, set) clrsetio(w, addr, clear, set)
+#define clrsetio_8(addr, clear, set) clrsetio(b, addr, clear, set)
+
 static inline void sync(void)
 {
 }
diff --git a/arch/x86/include/asm/ioapic.h b/arch/x86/include/asm/ioapic.h
index 77c443e..2feed86 100644
--- a/arch/x86/include/asm/ioapic.h
+++ b/arch/x86/include/asm/ioapic.h
@@ -39,4 +39,6 @@
  */
 void io_apic_write(u32 reg, u32 val);
 
+void io_apic_set_id(int ioapic_id);
+
 #endif
diff --git a/arch/x86/include/asm/lpc_common.h b/arch/x86/include/asm/lpc_common.h
new file mode 100644
index 0000000..a90a22d
--- /dev/null
+++ b/arch/x86/include/asm/lpc_common.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_LPC_COMMON_H
+#define __ASM_LPC_COMMON_H
+
+#define PCH_RCBA_BASE		0xf0
+
+#define RC		0x3400	/* 32bit */
+#define GCS		0x3410	/* 32bit */
+
+#define PMBASE			0x40
+#define ACPI_CNTL		0x44
+
+#define LPC_IO_DEC		0x80 /* IO Decode Ranges Register */
+#define  COMB_DEC_RANGE		(1 << 4)  /* 0x2f8-0x2ff (COM2) */
+#define  COMA_DEC_RANGE		(0 << 0)  /* 0x3f8-0x3ff (COM1) */
+#define LPC_EN			0x82 /* LPC IF Enables Register */
+#define  CNF2_LPC_EN		(1 << 13) /* 0x4e/0x4f */
+#define  CNF1_LPC_EN		(1 << 12) /* 0x2e/0x2f */
+#define  MC_LPC_EN		(1 << 11) /* 0x62/0x66 */
+#define  KBC_LPC_EN		(1 << 10) /* 0x60/0x64 */
+#define  GAMEH_LPC_EN		(1 << 9)  /* 0x208/0x20f */
+#define  GAMEL_LPC_EN		(1 << 8)  /* 0x200/0x207 */
+#define  FDD_LPC_EN		(1 << 3)  /* LPC_IO_DEC[12] */
+#define  LPT_LPC_EN		(1 << 2)  /* LPC_IO_DEC[9:8] */
+#define  COMB_LPC_EN		(1 << 1)  /* LPC_IO_DEC[6:4] */
+#define  COMA_LPC_EN		(1 << 0)  /* LPC_IO_DEC[3:2] */
+#define LPC_GEN1_DEC		0x84 /* LPC IF Generic Decode Range 1 */
+#define LPC_GEN2_DEC		0x88 /* LPC IF Generic Decode Range 2 */
+#define LPC_GEN3_DEC		0x8c /* LPC IF Generic Decode Range 3 */
+#define LPC_GEN4_DEC		0x90 /* LPC IF Generic Decode Range 4 */
+#define LPC_GENX_DEC(x)		(0x84 + 4 * (x))
+#define  GEN_DEC_RANGE_256B	0xfc0000  /* 256 Bytes */
+#define  GEN_DEC_RANGE_128B	0x7c0000  /* 128 Bytes */
+#define  GEN_DEC_RANGE_64B	0x3c0000  /* 64 Bytes */
+#define  GEN_DEC_RANGE_32B	0x1c0000  /* 32 Bytes */
+#define  GEN_DEC_RANGE_16B	0x0c0000  /* 16 Bytes */
+#define  GEN_DEC_RANGE_8B	0x040000  /* 8 Bytes */
+#define  GEN_DEC_RANGE_4B	0x000000  /* 4 Bytes */
+#define  GEN_DEC_RANGE_EN	(1 << 0)  /* Range Enable */
+
+/**
+ * lpc_common_early_init() - Set up common LPC init
+ *
+ * This sets up the legacy decode areas, GEN_DEC, SPI prefetch and Port80. It
+ * also puts the RCB in the correct place so that RCB_REG() works.
+ *
+ * @dev:	LPC device (a child of the PCH)
+ * @return 0 on success, -ve on error
+ */
+int lpc_common_early_init(struct udevice *dev);
+
+int lpc_set_spi_protect(struct udevice *dev, int bios_ctrl, bool protect);
+
+#endif
diff --git a/arch/x86/include/asm/me_common.h b/arch/x86/include/asm/me_common.h
new file mode 100644
index 0000000..2e2251c
--- /dev/null
+++ b/arch/x86/include/asm/me_common.h
@@ -0,0 +1,373 @@
+/*
+ * From Coreboot src/southbridge/intel/bd82x6x/me.h
+ *
+ * Coreboot copies lots of code around. Here we are trying to keep the common
+ * code in a separate file to reduce code duplication and hopefully make it
+ * easier to add new platform.
+ *
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_ME_COMMON_H
+#define __ASM_ME_COMMON_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <pci.h>
+
+#define MCHBAR_PEI_VERSION	0x5034
+
+#define ME_RETRY		100000	/* 1 second */
+#define ME_DELAY		10	/* 10 us */
+
+/*
+ * Management Engine PCI registers
+ */
+
+#define PCI_CPU_MEBASE_L	0x70	/* Set by MRC */
+#define PCI_CPU_MEBASE_H	0x74	/* Set by MRC */
+
+#define PCI_ME_HFS		0x40
+#define  ME_HFS_CWS_RESET	0
+#define  ME_HFS_CWS_INIT	1
+#define  ME_HFS_CWS_REC		2
+#define  ME_HFS_CWS_NORMAL	5
+#define  ME_HFS_CWS_WAIT	6
+#define  ME_HFS_CWS_TRANS	7
+#define  ME_HFS_CWS_INVALID	8
+#define  ME_HFS_STATE_PREBOOT	0
+#define  ME_HFS_STATE_M0_UMA	1
+#define  ME_HFS_STATE_M3	4
+#define  ME_HFS_STATE_M0	5
+#define  ME_HFS_STATE_BRINGUP	6
+#define  ME_HFS_STATE_ERROR	7
+#define  ME_HFS_ERROR_NONE	0
+#define  ME_HFS_ERROR_UNCAT	1
+#define  ME_HFS_ERROR_IMAGE	3
+#define  ME_HFS_ERROR_DEBUG	4
+#define  ME_HFS_MODE_NORMAL	0
+#define  ME_HFS_MODE_DEBUG	2
+#define  ME_HFS_MODE_DIS	3
+#define  ME_HFS_MODE_OVER_JMPR	4
+#define  ME_HFS_MODE_OVER_MEI	5
+#define  ME_HFS_BIOS_DRAM_ACK	1
+#define  ME_HFS_ACK_NO_DID	0
+#define  ME_HFS_ACK_RESET	1
+#define  ME_HFS_ACK_PWR_CYCLE	2
+#define  ME_HFS_ACK_S3		3
+#define  ME_HFS_ACK_S4		4
+#define  ME_HFS_ACK_S5		5
+#define  ME_HFS_ACK_GBL_RESET	6
+#define  ME_HFS_ACK_CONTINUE	7
+
+struct me_hfs {
+	u32 working_state:4;
+	u32 mfg_mode:1;
+	u32 fpt_bad:1;
+	u32 operation_state:3;
+	u32 fw_init_complete:1;
+	u32 ft_bup_ld_flr:1;
+	u32 update_in_progress:1;
+	u32 error_code:4;
+	u32 operation_mode:4;
+	u32 reserved:4;
+	u32 boot_options_present:1;
+	u32 ack_data:3;
+	u32 bios_msg_ack:4;
+} __packed;
+
+#define PCI_ME_UMA		0x44
+
+struct me_uma {
+	u32 size:6;
+	u32 reserved_1:10;
+	u32 valid:1;
+	u32 reserved_0:14;
+	u32 set_to_one:1;
+} __packed;
+
+#define PCI_ME_H_GS		0x4c
+#define  ME_INIT_DONE		1
+#define  ME_INIT_STATUS_SUCCESS	0
+#define  ME_INIT_STATUS_NOMEM	1
+#define  ME_INIT_STATUS_ERROR	2
+
+struct me_did {
+	u32 uma_base:16;
+	u32 reserved:7;
+	u32 rapid_start:1;	/* Broadwell only */
+	u32 status:4;
+	u32 init_done:4;
+} __packed;
+
+#define PCI_ME_GMES		0x48
+#define  ME_GMES_PHASE_ROM	0
+#define  ME_GMES_PHASE_BUP	1
+#define  ME_GMES_PHASE_UKERNEL	2
+#define  ME_GMES_PHASE_POLICY	3
+#define  ME_GMES_PHASE_MODULE	4
+#define  ME_GMES_PHASE_UNKNOWN	5
+#define  ME_GMES_PHASE_HOST	6
+
+struct me_gmes {
+	u32 bist_in_prog:1;
+	u32 icc_prog_sts:2;
+	u32 invoke_mebx:1;
+	u32 cpu_replaced_sts:1;
+	u32 mbp_rdy:1;
+	u32 mfs_failure:1;
+	u32 warm_rst_req_for_df:1;
+	u32 cpu_replaced_valid:1;
+	u32 reserved_1:2;
+	u32 fw_upd_ipu:1;
+	u32 reserved_2:4;
+	u32 current_state:8;
+	u32 current_pmevent:4;
+	u32 progress_code:4;
+} __packed;
+
+#define PCI_ME_HERES		0xbc
+#define  PCI_ME_EXT_SHA1	0x00
+#define  PCI_ME_EXT_SHA256	0x02
+#define PCI_ME_HER(x)		(0xc0+(4*(x)))
+
+struct me_heres {
+	u32 extend_reg_algorithm:4;
+	u32 reserved:26;
+	u32 extend_feature_present:1;
+	u32 extend_reg_valid:1;
+} __packed;
+
+/*
+ * Management Engine MEI registers
+ */
+
+#define MEI_H_CB_WW		0x00
+#define MEI_H_CSR		0x04
+#define MEI_ME_CB_RW		0x08
+#define MEI_ME_CSR_HA		0x0c
+
+struct mei_csr {
+	u32 interrupt_enable:1;
+	u32 interrupt_status:1;
+	u32 interrupt_generate:1;
+	u32 ready:1;
+	u32 reset:1;
+	u32 reserved:3;
+	u32 buffer_read_ptr:8;
+	u32 buffer_write_ptr:8;
+	u32 buffer_depth:8;
+} __packed;
+
+#define MEI_ADDRESS_CORE	0x01
+#define MEI_ADDRESS_AMT		0x02
+#define MEI_ADDRESS_RESERVED	0x03
+#define MEI_ADDRESS_WDT		0x04
+#define MEI_ADDRESS_MKHI	0x07
+#define MEI_ADDRESS_ICC		0x08
+#define MEI_ADDRESS_THERMAL	0x09
+
+#define MEI_HOST_ADDRESS	0
+
+struct mei_header {
+	u32 client_address:8;
+	u32 host_address:8;
+	u32 length:9;
+	u32 reserved:6;
+	u32 is_complete:1;
+} __packed;
+
+#define MKHI_GROUP_ID_CBM	0x00
+#define MKHI_GROUP_ID_FWCAPS	0x03
+#define MKHI_GROUP_ID_MDES	0x08
+#define MKHI_GROUP_ID_GEN	0xff
+
+#define MKHI_GET_FW_VERSION	0x02
+#define MKHI_END_OF_POST	0x0c
+#define MKHI_FEATURE_OVERRIDE	0x14
+
+/* Ivybridge only: */
+#define MKHI_GLOBAL_RESET	0x0b
+#define MKHI_FWCAPS_GET_RULE	0x02
+#define MKHI_MDES_ENABLE	0x09
+
+/* Broadwell only: */
+#define MKHI_GLOBAL_RESET	0x0b
+#define MKHI_FWCAPS_GET_RULE	0x02
+#define MKHI_GROUP_ID_HMRFPO	0x05
+#define MKHI_HMRFPO_LOCK	0x02
+#define MKHI_HMRFPO_LOCK_NOACK	0x05
+#define MKHI_MDES_ENABLE	0x09
+#define MKHI_END_OF_POST_NOACK	0x1a
+
+struct mkhi_header {
+	u32 group_id:8;
+	u32 command:7;
+	u32 is_response:1;
+	u32 reserved:8;
+	u32 result:8;
+} __packed;
+
+struct me_fw_version {
+	u16 code_minor;
+	u16 code_major;
+	u16 code_build_number;
+	u16 code_hot_fix;
+	u16 recovery_minor;
+	u16 recovery_major;
+	u16 recovery_build_number;
+	u16 recovery_hot_fix;
+} __packed;
+
+
+#define HECI_EOP_STATUS_SUCCESS       0x0
+#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
+
+#define CBM_RR_GLOBAL_RESET	0x01
+
+#define GLOBAL_RESET_BIOS_MRC	0x01
+#define GLOBAL_RESET_BIOS_POST	0x02
+#define GLOBAL_RESET_MEBX	0x03
+
+struct me_global_reset {
+	u8 request_origin;
+	u8 reset_type;
+} __packed;
+
+enum me_bios_path {
+	ME_NORMAL_BIOS_PATH,
+	ME_S3WAKE_BIOS_PATH,
+	ME_ERROR_BIOS_PATH,
+	ME_RECOVERY_BIOS_PATH,
+	ME_DISABLE_BIOS_PATH,
+	ME_FIRMWARE_UPDATE_BIOS_PATH,
+};
+
+struct __packed mefwcaps_sku {
+	u32 full_net:1;
+	u32 std_net:1;
+	u32 manageability:1;
+	u32 small_business:1;
+	u32 l3manageability:1;
+	u32 intel_at:1;
+	u32 intel_cls:1;
+	u32 reserved:3;
+	u32 intel_mpc:1;
+	u32 icc_over_clocking:1;
+	u32 pavp:1;
+	u32 reserved_1:4;
+	u32 ipv6:1;
+	u32 kvm:1;
+	u32 och:1;
+	u32 vlan:1;
+	u32 tls:1;
+	u32 reserved_4:1;
+	u32 wlan:1;
+	u32 reserved_5:8;
+};
+
+struct __packed tdt_state_flag {
+	u16 lock_state:1;
+	u16 authenticate_module:1;
+	u16 s3authentication:1;
+	u16 flash_wear_out:1;
+	u16 flash_variable_security:1;
+	u16 wwan3gpresent:1;	/* ivybridge only */
+	u16 wwan3goob:1;	/* ivybridge only */
+	u16 reserved:9;
+};
+
+struct __packed tdt_state_info {
+	u8 state;
+	u8 last_theft_trigger;
+	struct tdt_state_flag flags;
+};
+
+struct __packed mbp_rom_bist_data {
+	u16 device_id;
+	u16 fuse_test_flags;
+	u32 umchid[4];
+};
+
+struct __packed mbp_platform_key {
+	u32 key[8];
+};
+
+struct __packed mbp_header {
+	u32 mbp_size:8;
+	u32 num_entries:8;
+	u32 rsvd:16;
+};
+
+struct __packed mbp_item_header {
+	u32 app_id:8;
+	u32 item_id:8;
+	u32 length:8;
+	u32 rsvd:8;
+};
+
+struct __packed me_fwcaps {
+	u32 id;
+	u8 length;
+	struct mefwcaps_sku caps_sku;
+	u8 reserved[3];
+};
+
+/**
+ * intel_me_status() - Check Intel Management Engine status
+ *
+ * @me_dev:	Management engine PCI device
+ */
+void intel_me_status(struct udevice *me_dev);
+
+/**
+ * intel_early_me_init() - Early Intel Management Engine init
+ *
+ * @me_dev:	Management engine PCI device
+ * @return 0 if OK, -ve on error
+ */
+int intel_early_me_init(struct udevice *me_dev);
+
+/**
+ * intel_early_me_uma_size() - Get UMA size from the Intel Management Engine
+ *
+ * @me_dev:	Management engine PCI device
+ * @return UMA size if OK, -EINVAL on error
+ */
+int intel_early_me_uma_size(struct udevice *me_dev);
+
+/**
+ * intel_early_me_init_done() - Complete Intel Management Engine init
+ *
+ * @dev:	Northbridge device
+ * @me_dev:	Management engine PCI device
+ * @status:	Status result (ME_INIT_...)
+ * @return 0 to continue to boot, -EINVAL on unknown result data, -ETIMEDOUT
+ * if ME did not respond
+ */
+int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
+			     uint status);
+
+int intel_me_hsio_version(struct udevice *dev, uint16_t *version,
+			  uint16_t *checksum);
+
+static inline void pci_read_dword_ptr(struct udevice *me_dev, void *ptr,
+				      int offset)
+{
+	u32 dword;
+
+	dm_pci_read_config32(me_dev, offset, &dword);
+	memcpy(ptr, &dword, sizeof(dword));
+}
+
+static inline void pci_write_dword_ptr(struct udevice *me_dev, void *ptr,
+				       int offset)
+{
+	u32 dword = 0;
+
+	memcpy(&dword, ptr, sizeof(dword));
+	dm_pci_write_config32(me_dev, offset, dword);
+}
+#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/microcode.h b/arch/x86/include/asm/microcode.h
similarity index 63%
rename from arch/x86/include/asm/arch-ivybridge/microcode.h
rename to arch/x86/include/asm/microcode.h
index 67f32cc..29bf060 100644
--- a/arch/x86/include/asm/arch-ivybridge/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -9,6 +9,9 @@
 
 #ifndef __ASSEMBLY__
 
+/* This is a declaration for ucode_base in start.S */
+extern u32 ucode_base;
+
 /**
  * microcode_update_intel() - Apply microcode updates
  *
@@ -18,6 +21,15 @@
  * not updates were found, -EINVAL if an update was invalid
  */
 int microcode_update_intel(void);
+
+/**
+ * microcode_read_rev() - Read the microcode version
+ *
+ * This reads the microcode version of the currently running CPU
+ *
+ * @return microcode version number
+ */
+int microcode_read_rev(void);
 #endif /* __ASSEMBLY__ */
 
 #endif
diff --git a/arch/x86/include/asm/mrc_common.h b/arch/x86/include/asm/mrc_common.h
new file mode 100644
index 0000000..cad24f2
--- /dev/null
+++ b/arch/x86/include/asm/mrc_common.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_MRC_COMMON_H
+#define __ASM_MRC_COMMON_H
+
+#include <linux/linkage.h>
+
+/**
+ * mrc_common_init() - Set up SDRAM
+ *
+ * This calls the memory reference code (MRC) to set up SDRAM
+ *
+ * @dev:	Northbridge device
+ * @pei_data:	Platform-specific data required by the MRC
+ * @use_asm_linkage: true if the call to MRC requires asmlinkage, false if it
+ * uses normal U-Boot calling
+ * @return 0 if OK, -ve on error
+ */
+int mrc_common_init(struct udevice *dev, void *pei_data, bool use_asm_linkage);
+
+asmlinkage void sdram_console_tx_byte(unsigned char byte);
+
+int mrc_locate_spd(struct udevice *dev, int size, const void **spd_datap);
+
+void report_memory_config(void);
+
+/**
+ * mrc_add_memory_area() - Add a new usable memory area to our list
+ *
+ * Note: @start and @end must not span the first 4GB boundary
+ *
+ * @info:	Place to store memory info
+ * @start:	Start of this memory area
+ * @end:	End of this memory area + 1
+ */
+int mrc_add_memory_area(struct memory_info *info, uint64_t start,
+			  uint64_t end);
+
+/*
+ * This function looks for the highest region of memory lower than 4GB which
+ * has enough space for U-Boot where U-Boot is aligned on a page boundary.
+ * It overrides the default implementation found elsewhere which simply
+ * picks the end of ram, wherever that may be. The location of the stack,
+ * the relocation address, and how far U-Boot is moved by relocation are
+ * set in the global data structure.
+ */
+ulong mrc_common_board_get_usable_ram_top(ulong total_size);
+
+void mrc_common_dram_init_banksize(void);
+
+#endif
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 38dbb31..b2a03f4 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -41,6 +41,9 @@
 #define EFER_FFXSR		(1<<_EFER_FFXSR)
 
 /* Intel MSRs. Some also available on other CPUs */
+#define MSR_PIC_MSG_CONTROL		0x2e
+#define  PLATFORM_INFO_SET_TDP		(1 << 29)
+
 #define MSR_IA32_PERFCTR0		0x000000c1
 #define MSR_IA32_PERFCTR1		0x000000c2
 #define MSR_FSB_FREQ			0x000000cd
@@ -73,14 +76,27 @@
 #define MSR_IA32_MCG_STATUS		0x0000017a
 #define MSR_IA32_MCG_CTL		0x0000017b
 
+#define MSR_FLEX_RATIO			0x194
+#define  FLEX_RATIO_LOCK		(1 << 20)
+#define  FLEX_RATIO_EN			(1 << 16)
+
 #define MSR_IA32_MISC_ENABLES		0x000001a0
+#define MSR_TEMPERATURE_TARGET		0x1a2
 #define MSR_OFFCORE_RSP_0		0x000001a6
 #define MSR_OFFCORE_RSP_1		0x000001a7
+#define MSR_MISC_PWR_MGMT		0x1aa
+#define  MISC_PWR_MGMT_EIST_HW_DIS	(1 << 0)
 #define MSR_NHM_TURBO_RATIO_LIMIT	0x000001ad
 #define MSR_IVT_TURBO_RATIO_LIMIT	0x000001ae
 
+#define MSR_IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
+#define  ENERGY_POLICY_PERFORMANCE	0
+#define  ENERGY_POLICY_NORMAL		6
+#define  ENERGY_POLICY_POWERSAVE	15
+
 #define MSR_LBR_SELECT			0x000001c8
 #define MSR_LBR_TOS			0x000001c9
+#define MSR_IA32_PLATFORM_DCA_CAP	0x1f8
 #define MSR_POWER_CTL			0x000001fc
 #define MSR_LBR_NHM_FROM		0x00000680
 #define MSR_LBR_NHM_TO			0x000006c0
@@ -147,7 +163,29 @@
 
 #define MSR_PKG_POWER_SKU_UNIT		0x00000606
 
+#define MSR_C_STATE_LATENCY_CONTROL_0	0x60a
+#define MSR_C_STATE_LATENCY_CONTROL_1	0x60b
+#define MSR_C_STATE_LATENCY_CONTROL_2	0x60c
+#define MSR_C_STATE_LATENCY_CONTROL_3	0x633
+#define MSR_C_STATE_LATENCY_CONTROL_4	0x634
+#define MSR_C_STATE_LATENCY_CONTROL_5	0x635
+#define  IRTL_VALID			(1 << 15)
+#define  IRTL_1_NS			(0 << 10)
+#define  IRTL_32_NS			(1 << 10)
+#define  IRTL_1024_NS			(2 << 10)
+#define  IRTL_32768_NS			(3 << 10)
+#define  IRTL_1048576_NS		(4 << 10)
+#define  IRTL_33554432_NS		(5 << 10)
+#define  IRTL_RESPONSE_MASK		(0x3ff)
+
 #define MSR_PKG_POWER_LIMIT		0x00000610
+/* long duration in low dword, short duration in high dword */
+#define  PKG_POWER_LIMIT_MASK		0x7fff
+#define  PKG_POWER_LIMIT_EN		(1 << 15)
+#define  PKG_POWER_LIMIT_CLAMP		(1 << 16)
+#define  PKG_POWER_LIMIT_TIME_SHIFT	17
+#define  PKG_POWER_LIMIT_TIME_MASK	0x7f
+
 #define MSR_PKG_ENERGY_STATUS		0x00000611
 #define MSR_PKG_PERF_STATUS		0x00000613
 #define MSR_PKG_POWER_INFO		0x00000614
@@ -165,7 +203,8 @@
 #define MSR_PP1_POWER_LIMIT		0x00000640
 #define MSR_PP1_ENERGY_STATUS		0x00000641
 #define MSR_PP1_POLICY			0x00000642
-
+#define MSR_CONFIG_TDP_NOMINAL		0x00000648
+#define MSR_TURBO_ACTIVATION_RATIO	0x0000064c
 #define MSR_CORE_C1_RES			0x00000660
 #define MSR_IACORE_RATIOS		0x0000066a
 #define MSR_IACORE_TURBO_RATIOS		0x0000066c
diff --git a/arch/x86/include/asm/pch_common.h b/arch/x86/include/asm/pch_common.h
new file mode 100644
index 0000000..924ccc4
--- /dev/null
+++ b/arch/x86/include/asm/pch_common.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __asm_pch_common_h
+#define __asm_pch_common_h
+
+/* Common Intel SATA registers */
+#define SATA_SIRI		0xa0 /* SATA Indexed Register Index */
+#define SATA_SIRD		0xa4 /* SATA Indexed Register Data */
+#define SATA_SP			0xd0 /* Scratchpad */
+
+#define INTR_LN			0x3c
+#define IDE_TIM_PRI		0x40	/* IDE timings, primary */
+#define   IDE_DECODE_ENABLE	(1 << 15)
+#define   IDE_SITRE		(1 << 14)
+#define   IDE_ISP_5_CLOCKS	(0 << 12)
+#define   IDE_ISP_4_CLOCKS	(1 << 12)
+#define   IDE_ISP_3_CLOCKS	(2 << 12)
+#define   IDE_RCT_4_CLOCKS	(0 <<  8)
+#define   IDE_RCT_3_CLOCKS	(1 <<  8)
+#define   IDE_RCT_2_CLOCKS	(2 <<  8)
+#define   IDE_RCT_1_CLOCKS	(3 <<  8)
+#define   IDE_DTE1		(1 <<  7)
+#define   IDE_PPE1		(1 <<  6)
+#define   IDE_IE1		(1 <<  5)
+#define   IDE_TIME1		(1 <<  4)
+#define   IDE_DTE0		(1 <<  3)
+#define   IDE_PPE0		(1 <<  2)
+#define   IDE_IE0		(1 <<  1)
+#define   IDE_TIME0		(1 <<  0)
+#define IDE_TIM_SEC		0x42	/* IDE timings, secondary */
+
+#define SERIRQ_CNTL		0x64
+
+/**
+ * pch_common_sir_read() - Read from a SATA indexed register
+ *
+ * @dev:	SATA device
+ * @idx:	Register index to read
+ * @return value read from register
+ */
+u32 pch_common_sir_read(struct udevice *dev, int idx);
+
+/**
+ * pch_common_sir_write() - Write to a SATA indexed register
+ *
+ * @dev:	SATA device
+ * @idx:	Register index to write
+ * @value:	Value to write
+ */
+void pch_common_sir_write(struct udevice *dev, int idx, u32 value);
+
+#endif
diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h
index f49ce99..6b774bd 100644
--- a/arch/x86/include/asm/post.h
+++ b/arch/x86/include/asm/post.h
@@ -29,8 +29,8 @@
 #define POST_CPU_INFO		0x2d
 #define POST_PRE_MRC		0x2e
 #define POST_MRC		0x2f
-#define POST_DRAM		0x2f
-#define POST_LAPIC		0x30
+#define POST_DRAM		0x30
+#define POST_LAPIC		0x31
 
 #define POST_RAM_FAILURE	0xea
 #define POST_BIST_FAILURE	0xeb
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 7c77b90..cefc633 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -36,7 +36,7 @@
  *
  * The naming follows Intel's naming.
  */
-#define PORT_RESET		0xcf9
+#define IO_PORT_RESET		0xcf9
 
 enum {
 	SYS_RST		= 1 << 1,	/* 0 for soft reset, 1 for hard reset */
diff --git a/arch/x86/include/asm/report_platform.h b/arch/x86/include/asm/report_platform.h
new file mode 100644
index 0000000..4607dd3
--- /dev/null
+++ b/arch/x86/include/asm/report_platform.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ARCH_REPORT_PLATFORM_H
+#define __ARCH_REPORT_PLATFORM_H
+
+/**
+ * report_platform_info() - Report platform information
+ *
+ * This reports information about the CPU and chipset.
+ *
+ * @dev:	Northbridge device
+ */
+void report_platform_info(struct udevice *dev);
+
+#endif
diff --git a/arch/x86/include/asm/sipi.h b/arch/x86/include/asm/sipi.h
index 25d7d31..da91a48 100644
--- a/arch/x86/include/asm/sipi.h
+++ b/arch/x86/include/asm/sipi.h
@@ -42,6 +42,7 @@
  * struct sipi_params - 32-bit SIP entry-point parameters
  *
  * These are used by the AP init code and must be set up before the APs start.
+ * The members must match with the sipi_params layout in sipi_vector.S.
  *
  * The stack area extends down from @stack_top, with @stack_size allocated
  * for each AP.
diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h
index 0aa6d9b..ae9f0d0 100644
--- a/arch/x86/include/asm/tables.h
+++ b/arch/x86/include/asm/tables.h
@@ -14,6 +14,11 @@
  */
 #define ROM_TABLE_ADDR	0xf0000
 
+#define ROM_TABLE_ALIGN	1024
+
+/* SeaBIOS expects coreboot tables at address range 0x0000-0x1000 */
+#define CB_TABLE_ADDR	0x800
+
 /**
  * table_compute_checksum() - Compute a table checksum
  *
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 4fc1936..dc90df2 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -10,6 +10,7 @@
 obj-y += bios_interrupts.o
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-y	+= cmd_boot.o
+obj-y	+= coreboot_table.o
 obj-$(CONFIG_EFI) += efi/
 obj-y	+= e820.o
 obj-y	+= gcc.o
@@ -22,6 +23,7 @@
 obj-y	+= northbridge-uclass.o
 obj-$(CONFIG_I8259_PIC) += i8259.o
 obj-$(CONFIG_I8254_TIMER) += i8254.o
+obj-y	+= pinctrl_ich6.o
 obj-y	+= pirq_routing.o
 obj-y	+= relocate.o
 obj-y += physmem.o
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 2ec5ad2..790f6fb 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -335,9 +335,9 @@
  * QEMU's version of write_acpi_tables is defined in
  * arch/x86/cpu/qemu/fw_cfg.c
  */
-unsigned long write_acpi_tables(unsigned long start)
+u32 write_acpi_tables(u32 start)
 {
-	unsigned long current;
+	u32 current;
 	struct acpi_rsdp *rsdp;
 	struct acpi_rsdt *rsdt;
 	struct acpi_xsdt *xsdt;
diff --git a/arch/x86/lib/coreboot_table.c b/arch/x86/lib/coreboot_table.c
new file mode 100644
index 0000000..cb45a79
--- /dev/null
+++ b/arch/x86/lib/coreboot_table.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <vbe.h>
+#include <asm/coreboot_tables.h>
+#include <asm/e820.h>
+
+/**
+ * cb_table_init() - initialize a coreboot table header
+ *
+ * This fills in the coreboot table header signature and the header bytes.
+ * Other fields are set to zero.
+ *
+ * @cbh:	coreboot table header address
+ */
+static void cb_table_init(struct cb_header *cbh)
+{
+	memset(cbh, 0, sizeof(struct cb_header));
+	memcpy(cbh->signature, "LBIO", 4);
+	cbh->header_bytes = sizeof(struct cb_header);
+}
+
+/**
+ * cb_table_add_entry() - add a coreboot table entry
+ *
+ * This increases the coreboot table entry size with added table entry length
+ * and increases entry count by 1.
+ *
+ * @cbh:	coreboot table header address
+ * @cbr:	to be added table entry address
+ * @return:	pointer to next table entry address
+ */
+static u32 cb_table_add_entry(struct cb_header *cbh, struct cb_record *cbr)
+{
+	cbh->table_bytes += cbr->size;
+	cbh->table_entries++;
+
+	return (u32)cbr + cbr->size;
+}
+
+/**
+ * cb_table_finalize() - finalize the coreboot table
+ *
+ * This calculates the checksum for all coreboot table entries as well as
+ * the checksum for the coreboot header itself.
+ *
+ * @cbh:	coreboot table header address
+ */
+static void cb_table_finalize(struct cb_header *cbh)
+{
+	struct cb_record *cbr = (struct cb_record *)(cbh + 1);
+
+	cbh->table_checksum = compute_ip_checksum(cbr, cbh->table_bytes);
+	cbh->header_checksum = compute_ip_checksum(cbh, cbh->header_bytes);
+}
+
+void write_coreboot_table(u32 addr, struct memory_area *cfg_tables)
+{
+	struct cb_header *cbh = (struct cb_header *)addr;
+	struct cb_record *cbr;
+	struct cb_memory *mem;
+	struct cb_memory_range *map;
+	struct e820entry e820[32];
+	struct cb_framebuffer *fb;
+	struct vesa_mode_info *vesa;
+	int i, num;
+
+	cb_table_init(cbh);
+	cbr = (struct cb_record *)(cbh + 1);
+
+	/*
+	 * Two type of coreboot table entries are generated by us.
+	 * They are 'struct cb_memory' and 'struct cb_framebuffer'.
+	 */
+
+	/* populate memory map table */
+	mem = (struct cb_memory *)cbr;
+	mem->tag = CB_TAG_MEMORY;
+	map = mem->map;
+
+	/* first install e820 defined memory maps */
+	num = install_e820_map(ARRAY_SIZE(e820), e820);
+	for (i = 0; i < num; i++) {
+		map->start.lo = e820[i].addr & 0xffffffff;
+		map->start.hi = e820[i].addr >> 32;
+		map->size.lo = e820[i].size & 0xffffffff;
+		map->size.hi = e820[i].size >> 32;
+		map->type = e820[i].type;
+		map++;
+	}
+
+	/* then install all configuration tables */
+	while (cfg_tables->size) {
+		map->start.lo = cfg_tables->start & 0xffffffff;
+		map->start.hi = cfg_tables->start >> 32;
+		map->size.lo = cfg_tables->size & 0xffffffff;
+		map->size.hi = cfg_tables->size >> 32;
+		map->type = CB_MEM_TABLE;
+		map++;
+		num++;
+		cfg_tables++;
+	}
+	mem->size = num * sizeof(struct cb_memory_range) +
+		    sizeof(struct cb_record);
+	cbr = (struct cb_record *)cb_table_add_entry(cbh, cbr);
+
+	/* populate framebuffer table if we have sane vesa info */
+	vesa = &mode_info.vesa;
+	if (vesa->x_resolution && vesa->y_resolution) {
+		fb = (struct cb_framebuffer *)cbr;
+		fb->tag = CB_TAG_FRAMEBUFFER;
+		fb->size = sizeof(struct cb_framebuffer);
+
+		fb->x_resolution = vesa->x_resolution;
+		fb->y_resolution = vesa->y_resolution;
+		fb->bits_per_pixel = vesa->bits_per_pixel;
+		fb->bytes_per_line = vesa->bytes_per_scanline;
+		fb->physical_address = vesa->phys_base_ptr;
+		fb->red_mask_size = vesa->red_mask_size;
+		fb->red_mask_pos = vesa->red_mask_pos;
+		fb->green_mask_size = vesa->green_mask_size;
+		fb->green_mask_pos = vesa->green_mask_pos;
+		fb->blue_mask_size = vesa->blue_mask_size;
+		fb->blue_mask_pos = vesa->blue_mask_pos;
+		fb->reserved_mask_size = vesa->reserved_mask_size;
+		fb->reserved_mask_pos = vesa->reserved_mask_pos;
+
+		cbr = (struct cb_record *)cb_table_add_entry(cbh, cbr);
+	}
+
+	cb_table_finalize(cbh);
+}
diff --git a/arch/x86/lib/fsp/fsp_car.S b/arch/x86/lib/fsp/fsp_car.S
index 15b3751..fbe8aef 100644
--- a/arch/x86/lib/fsp/fsp_car.S
+++ b/arch/x86/lib/fsp/fsp_car.S
@@ -102,6 +102,8 @@
 temp_ram_init_params:
 _dt_ucode_base_size:
 	/* These next two fields are filled in by ifdtool */
+.globl ucode_base
+ucode_base:	/* Declared in micrcode.h */
 	.long	0			/* microcode base */
 	.long	0			/* microcode size */
 	.long	CONFIG_SYS_MONITOR_BASE	/* code region base */
diff --git a/arch/x86/lib/mpspec.c b/arch/x86/lib/mpspec.c
index 0faa582..6ab43f1 100644
--- a/arch/x86/lib/mpspec.c
+++ b/arch/x86/lib/mpspec.c
@@ -297,7 +297,7 @@
 	const u32 *cell;
 	int i, ret;
 
-	ret = uclass_first_device(UCLASS_IRQ, &dev);
+	ret = uclass_first_device_err(UCLASS_IRQ, &dev);
 	if (ret && ret != -ENODEV) {
 		debug("%s: Cannot find irq router node\n", __func__);
 		return ret;
diff --git a/arch/x86/lib/pinctrl_ich6.c b/arch/x86/lib/pinctrl_ich6.c
new file mode 100644
index 0000000..3f94cdf
--- /dev/null
+++ b/arch/x86/lib/pinctrl_ich6.c
@@ -0,0 +1,216 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <pch.h>
+#include <pci.h>
+#include <asm/cpu.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GPIO_USESEL_OFFSET(x)	(x)
+#define GPIO_IOSEL_OFFSET(x)	(x + 4)
+#define GPIO_LVL_OFFSET(x)	((x) ? (x) + 8 : 0xc)
+#define GPI_INV			0x2c
+
+#define IOPAD_MODE_MASK			0x7
+#define IOPAD_PULL_ASSIGN_SHIFT		7
+#define IOPAD_PULL_ASSIGN_MASK		(0x3 << IOPAD_PULL_ASSIGN_SHIFT)
+#define IOPAD_PULL_STRENGTH_SHIFT	9
+#define IOPAD_PULL_STRENGTH_MASK	(0x3 << IOPAD_PULL_STRENGTH_SHIFT)
+
+static int ich6_pinctrl_set_value(uint16_t base, unsigned offset, int value)
+{
+	if (value)
+		setio_32(base, 1UL << offset);
+	else
+		clrio_32(base, 1UL << offset);
+
+	return 0;
+}
+
+static int ich6_pinctrl_set_function(uint16_t base, unsigned offset, int func)
+{
+	if (func)
+		setio_32(base, 1UL << offset);
+	else
+		clrio_32(base, 1UL << offset);
+
+	return 0;
+}
+
+static int ich6_pinctrl_set_direction(uint16_t base, unsigned offset, int dir)
+{
+	if (!dir)
+		setio_32(base, 1UL << offset);
+	else
+		clrio_32(base, 1UL << offset);
+
+	return 0;
+}
+
+static int ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node)
+{
+	bool is_gpio, invert;
+	u32 gpio_offset[2];
+	int pad_offset;
+	int dir, val;
+	int ret;
+
+	/*
+	 * GPIO node is not mandatory, so we only do the pinmuxing if the
+	 * node exists.
+	 */
+	ret = fdtdec_get_int_array(gd->fdt_blob, pin_node, "gpio-offset",
+				   gpio_offset, 2);
+	if (!ret) {
+		/* Do we want to force the GPIO mode? */
+		is_gpio = fdtdec_get_bool(gd->fdt_blob, pin_node, "mode-gpio");
+		if (is_gpio)
+			ich6_pinctrl_set_function(GPIO_USESEL_OFFSET(gpiobase) +
+						gpio_offset[0], gpio_offset[1],
+						1);
+
+		dir = fdtdec_get_int(gd->fdt_blob, pin_node, "direction", -1);
+		if (dir != -1)
+			ich6_pinctrl_set_direction(GPIO_IOSEL_OFFSET(gpiobase) +
+						 gpio_offset[0], gpio_offset[1],
+						 dir);
+
+		val = fdtdec_get_int(gd->fdt_blob, pin_node, "output-value",
+				     -1);
+		if (val != -1)
+			ich6_pinctrl_set_value(GPIO_LVL_OFFSET(gpiobase) +
+					     gpio_offset[0], gpio_offset[1],
+					     val);
+
+		invert = fdtdec_get_bool(gd->fdt_blob, pin_node, "invert");
+		if (invert)
+			setio_32(gpiobase + GPI_INV, 1 << gpio_offset[1]);
+		debug("gpio %#x bit %d, is_gpio %d, dir %d, val %d, invert %d\n",
+		      gpio_offset[0], gpio_offset[1], is_gpio, dir, val,
+		      invert);
+	}
+
+	/* if iobase is present, let's configure the pad */
+	if (iobase != -1) {
+		int iobase_addr;
+
+		/*
+		 * The offset for the same pin for the IOBASE and GPIOBASE are
+		 * different, so instead of maintaining a lookup table,
+		 * the device tree should provide directly the correct
+		 * value for both mapping.
+		 */
+		pad_offset = fdtdec_get_int(gd->fdt_blob, pin_node,
+					    "pad-offset", -1);
+		if (pad_offset == -1)
+			return 0;
+
+		/* compute the absolute pad address */
+		iobase_addr = iobase + pad_offset;
+
+		/*
+		 * Do we need to set a specific function mode?
+		 * If someone put also 'mode-gpio', this option will
+		 * be just ignored by the controller
+		 */
+		val = fdtdec_get_int(gd->fdt_blob, pin_node, "mode-func", -1);
+		if (val != -1)
+			clrsetbits_le32(iobase_addr, IOPAD_MODE_MASK, val);
+
+		/* Configure the pull-up/down if needed */
+		val = fdtdec_get_int(gd->fdt_blob, pin_node, "pull-assign", -1);
+		if (val != -1)
+			clrsetbits_le32(iobase_addr,
+					IOPAD_PULL_ASSIGN_MASK,
+					val << IOPAD_PULL_ASSIGN_SHIFT);
+
+		val = fdtdec_get_int(gd->fdt_blob, pin_node, "pull-strength",
+				     -1);
+		if (val != -1)
+			clrsetbits_le32(iobase_addr,
+					IOPAD_PULL_STRENGTH_MASK,
+					val << IOPAD_PULL_STRENGTH_SHIFT);
+
+		debug("%s: pad cfg [0x%x]: %08x\n", __func__, pad_offset,
+		      readl(iobase_addr));
+	}
+
+	return 0;
+}
+
+static int ich6_pinctrl_probe(struct udevice *dev)
+{
+	struct udevice *pch;
+	int pin_node;
+	int ret;
+	u32 gpiobase;
+	u32 iobase = -1;
+
+	debug("%s: start\n", __func__);
+	ret = uclass_first_device(UCLASS_PCH, &pch);
+	if (ret)
+		return ret;
+	if (!pch)
+		return -ENODEV;
+
+	/*
+	 * Get the memory/io base address to configure every pins.
+	 * IOBASE is used to configure the mode/pads
+	 * GPIOBASE is used to configure the direction and default value
+	 */
+	ret = pch_get_gpio_base(pch, &gpiobase);
+	if (ret) {
+		debug("%s: invalid GPIOBASE address (%08x)\n", __func__,
+		      gpiobase);
+		return -EINVAL;
+	}
+
+	/*
+	 * Get the IOBASE, this is not mandatory as this is not
+	 * supported by all the CPU
+	 */
+	ret = pch_get_io_base(pch, &iobase);
+	if (ret && ret != -ENOSYS) {
+		debug("%s: invalid IOBASE address (%08x)\n", __func__, iobase);
+		return -EINVAL;
+	}
+
+	for (pin_node = fdt_first_subnode(gd->fdt_blob, dev->of_offset);
+	     pin_node > 0;
+	     pin_node = fdt_next_subnode(gd->fdt_blob, pin_node)) {
+		/* Configure the pin */
+		ret = ich6_pinctrl_cfg_pin(gpiobase, iobase, pin_node);
+		if (ret != 0) {
+			debug("%s: invalid configuration for the pin %d\n",
+			      __func__, pin_node);
+			return ret;
+		}
+	}
+	debug("%s: done\n", __func__);
+
+	return 0;
+}
+
+static const struct udevice_id ich6_pinctrl_match[] = {
+	{ .compatible = "intel,x86-pinctrl", .data = X86_SYSCON_PINCONF },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(ich6_pinctrl) = {
+	.name = "ich6_pinctrl",
+	.id = UCLASS_SYSCON,
+	.of_match = ich6_pinctrl_match,
+	.probe = ich6_pinctrl_probe,
+};
diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index 14b15cf..a156f2c 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -10,6 +10,33 @@
 #include <asm/smbios.h>
 #include <asm/tables.h>
 #include <asm/acpi_table.h>
+#include <asm/coreboot_tables.h>
+
+/**
+ * Function prototype to write a specific configuration table
+ *
+ * @addr:	start address to write the table
+ * @return:	end address of the table
+ */
+typedef u32 (*table_write)(u32 addr);
+
+static table_write table_write_funcs[] = {
+#ifdef CONFIG_GENERATE_PIRQ_TABLE
+	write_pirq_routing_table,
+#endif
+#ifdef CONFIG_GENERATE_SFI_TABLE
+	write_sfi_table,
+#endif
+#ifdef CONFIG_GENERATE_MP_TABLE
+	write_mp_table,
+#endif
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+	write_acpi_tables,
+#endif
+#ifdef CONFIG_GENERATE_SMBIOS_TABLE
+	write_smbios_table,
+#endif
+};
 
 u8 table_compute_checksum(void *v, int len)
 {
@@ -39,26 +66,38 @@
 
 void write_tables(void)
 {
-	u32 __maybe_unused rom_table_end = ROM_TABLE_ADDR;
-
-#ifdef CONFIG_GENERATE_PIRQ_TABLE
-	rom_table_end = write_pirq_routing_table(rom_table_end);
-	rom_table_end = ALIGN(rom_table_end, 1024);
-#endif
-#ifdef CONFIG_GENERATE_SFI_TABLE
-	rom_table_end = write_sfi_table(rom_table_end);
-	rom_table_end = ALIGN(rom_table_end, 1024);
+	u32 rom_table_start = ROM_TABLE_ADDR;
+	u32 rom_table_end;
+#ifdef CONFIG_SEABIOS
+	u32 high_table, table_size;
+	struct memory_area cfg_tables[ARRAY_SIZE(table_write_funcs) + 1];
 #endif
-#ifdef CONFIG_GENERATE_MP_TABLE
-	rom_table_end = write_mp_table(rom_table_end);
-	rom_table_end = ALIGN(rom_table_end, 1024);
-#endif
-#ifdef CONFIG_GENERATE_ACPI_TABLE
-	rom_table_end = write_acpi_tables(rom_table_end);
-	rom_table_end = ALIGN(rom_table_end, 1024);
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(table_write_funcs); i++) {
+		rom_table_end = table_write_funcs[i](rom_table_start);
+		rom_table_end = ALIGN(rom_table_end, ROM_TABLE_ALIGN);
+
+#ifdef CONFIG_SEABIOS
+		table_size = rom_table_end - rom_table_start;
+		high_table = (u32)memalign(ROM_TABLE_ALIGN, table_size);
+		if (high_table) {
+			memset((void *)high_table, 0, table_size);
+			table_write_funcs[i](high_table);
+
+			cfg_tables[i].start = high_table;
+			cfg_tables[i].size = table_size;
+		} else {
+			printf("%d: no memory for configuration tables\n", i);
+		}
 #endif
-#ifdef CONFIG_GENERATE_SMBIOS_TABLE
-	rom_table_end = write_smbios_table(rom_table_end);
-	rom_table_end = ALIGN(rom_table_end, 1024);
+
+		rom_table_start = rom_table_end;
+	}
+
+#ifdef CONFIG_SEABIOS
+	/* make sure the last item is zero */
+	cfg_tables[i].size = 0;
+	write_coreboot_table(CB_TABLE_ADDR, cfg_tables);
 #endif
 }
diff --git a/board/Synology/common/Makefile b/board/Synology/common/Makefile
deleted file mode 100644
index e66aeb8..0000000
--- a/board/Synology/common/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y :=	cmd_syno.o
diff --git a/board/Synology/ds414/Makefile b/board/Synology/ds414/Makefile
index 0f4c32d..93be101 100644
--- a/board/Synology/ds414/Makefile
+++ b/board/Synology/ds414/Makefile
@@ -4,4 +4,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y :=	ds414.o
+obj-y	+= ds414.o
+ifndef CONFIG_SPL_BUILD
+obj-y	+= cmd_syno.o
+endif
diff --git a/board/Synology/common/cmd_syno.c b/board/Synology/ds414/cmd_syno.c
similarity index 100%
rename from board/Synology/common/cmd_syno.c
rename to board/Synology/ds414/cmd_syno.c
diff --git a/board/amazon/kc1/Kconfig b/board/amazon/kc1/Kconfig
new file mode 100644
index 0000000..1b46a8f
--- /dev/null
+++ b/board/amazon/kc1/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_KC1
+
+config SYS_BOARD
+	default "kc1"
+
+config SYS_VENDOR
+	default "amazon"
+
+config SYS_CONFIG_NAME
+	default "kc1"
+
+endif
diff --git a/board/amazon/kc1/MAINTAINERS b/board/amazon/kc1/MAINTAINERS
new file mode 100644
index 0000000..7e596d9
--- /dev/null
+++ b/board/amazon/kc1/MAINTAINERS
@@ -0,0 +1,6 @@
+KC1 BOARD
+M:	Paul Kocialkowski <contact@paulk.fr>
+S:	Maintained
+F:	board/amazon/kc1/
+F:	include/configs/kc1.h
+F:	configs/kc1_defconfig
diff --git a/board/amazon/kc1/Makefile b/board/amazon/kc1/Makefile
new file mode 100644
index 0000000..59c8347
--- /dev/null
+++ b/board/amazon/kc1/Makefile
@@ -0,0 +1,9 @@
+#
+# Amazon Kindle Fire (first generation) codename kc1 config
+#
+# Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y := kc1.o
diff --git a/board/amazon/kc1/kc1.c b/board/amazon/kc1/kc1.c
new file mode 100644
index 0000000..ca63af8
--- /dev/null
+++ b/board/amazon/kc1/kc1.c
@@ -0,0 +1,182 @@
+/*
+ * Amazon Kindle Fire (first generation) codename kc1 config
+ *
+ * Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <linux/ctype.h>
+#include <linux/usb/musb.h>
+#include <asm/omap_musb.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/gpio.h>
+#include <asm/emif.h>
+#include <twl6030.h>
+#include "kc1.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+	.board_string = "kc1"
+};
+
+static struct musb_hdrc_config musb_config = {
+	.multipoint = 1,
+	.dyn_fifo = 1,
+	.num_eps = 16,
+	.ram_bits = 12
+};
+
+static struct omap_musb_board_data musb_board_data = {
+	.interface_type	= MUSB_INTERFACE_UTMI,
+};
+
+static struct musb_hdrc_platform_data musb_platform_data = {
+	.mode = MUSB_PERIPHERAL,
+	.config = &musb_config,
+	.power = 100,
+	.platform_ops = &omap2430_ops,
+	.board_data = &musb_board_data,
+};
+
+
+void set_muxconf_regs(void)
+{
+	do_set_mux((*ctrl)->control_padconf_core_base, core_padconf_array,
+		sizeof(core_padconf_array) / sizeof(struct pad_conf_entry));
+}
+
+struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
+	struct lpddr2_device_details *lpddr2_dev_details)
+{
+	if (cs == CS1)
+		return NULL;
+
+	*lpddr2_dev_details = elpida_2G_S4_details;
+
+	return lpddr2_dev_details;
+}
+
+void emif_get_device_timings(u32 emif_nr,
+	const struct lpddr2_device_timings **cs0_device_timings,
+	const struct lpddr2_device_timings **cs1_device_timings)
+{
+	*cs0_device_timings = &elpida_2G_S4_timings;
+	*cs1_device_timings = NULL;
+}
+
+int board_init(void)
+{
+	/* GPMC init */
+	gpmc_init();
+
+	/* MACH number */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP_4430SDP;
+
+	/* ATAGs location */
+	gd->bd->bi_boot_params = OMAP44XX_DRAM_ADDR_SPACE_START + 0x100;
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	char reboot_mode[2] = { 0 };
+	u32 data = 0;
+	u32 value;
+
+	/* Reboot mode */
+
+	omap_reboot_mode(reboot_mode, sizeof(reboot_mode));
+
+	/* USB ID pin pull-up indicates factory (fastboot) cable detection. */
+	gpio_request(KC1_GPIO_USB_ID, "USB_ID");
+	gpio_direction_input(KC1_GPIO_USB_ID);
+	value = gpio_get_value(KC1_GPIO_USB_ID);
+
+	if (value)
+		reboot_mode[0] = 'b';
+
+	if (reboot_mode[0] > 0 && isascii(reboot_mode[0])) {
+		if (reboot_mode[0] == 'o')
+			twl6030_power_off();
+
+		if (!getenv("reboot-mode"))
+			setenv("reboot-mode", (char *)reboot_mode);
+
+		omap_reboot_mode_clear();
+	} else {
+		/* Reboot mode garbage may still be valid, so clear it. */
+		omap_reboot_mode_clear();
+
+		/*
+		 * When not rebooting, valid power on reasons are either the
+		 * power button, charger plug or USB plug.
+		 */
+
+		data |= twl6030_input_power_button();
+		data |= twl6030_input_charger();
+		data |= twl6030_input_usb();
+
+		if (!data)
+			twl6030_power_off();
+	}
+
+	/* Serial number */
+
+	omap_die_id_serial();
+
+	/* MUSB */
+
+	musb_register(&musb_platform_data, &musb_board_data, (void *)MUSB_BASE);
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	u32 value = 0;
+
+	gpio_request(KC1_GPIO_MBID0, "MBID0");
+	gpio_request(KC1_GPIO_MBID1, "MBID1");
+	gpio_request(KC1_GPIO_MBID2, "MBID2");
+	gpio_request(KC1_GPIO_MBID3, "MBID3");
+
+	gpio_direction_input(KC1_GPIO_MBID0);
+	gpio_direction_input(KC1_GPIO_MBID1);
+	gpio_direction_input(KC1_GPIO_MBID2);
+	gpio_direction_input(KC1_GPIO_MBID3);
+
+	value |= (gpio_get_value(KC1_GPIO_MBID0) << 0);
+	value |= (gpio_get_value(KC1_GPIO_MBID1) << 1);
+	value |= (gpio_get_value(KC1_GPIO_MBID2) << 2);
+	value |= (gpio_get_value(KC1_GPIO_MBID3) << 3);
+
+	return value;
+}
+
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	omap_die_id_get_board_serial(serialnr);
+}
+
+int fb_set_reboot_flag(void)
+{
+	return omap_reboot_mode_store("b");
+}
+
+#ifndef CONFIG_SPL_BUILD
+int board_mmc_init(bd_t *bis)
+{
+	return omap_mmc_init(1, 0, 0, -1, -1);
+}
+#endif
+
+void board_mmc_power_init(void)
+{
+	twl6030_power_mmc_init(1);
+}
diff --git a/board/amazon/kc1/kc1.h b/board/amazon/kc1/kc1.h
new file mode 100644
index 0000000..14737d7
--- /dev/null
+++ b/board/amazon/kc1/kc1.h
@@ -0,0 +1,98 @@
+/*
+ * Amazon Kindle Fire (first generation) codename kc1 config
+ *
+ * Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _KC1_H_
+#define _KC1_H_
+
+#include <asm/arch/mux_omap4.h>
+
+#define KC1_GPIO_USB_ID		52
+#define KC1_GPIO_MBID1		173
+#define KC1_GPIO_MBID0		174
+#define KC1_GPIO_MBID3		177
+#define KC1_GPIO_MBID2		178
+
+const struct pad_conf_entry core_padconf_array[] = {
+	/* GPMC */
+	{ GPMC_AD0,		(IEN  | PTU | M1) }, /* sdmmc2_dat0 */
+	{ GPMC_AD1,		(IEN  | PTU | M1) }, /* sdmmc2_dat1 */
+	{ GPMC_AD2,		(IEN  | PTU | M1) }, /* sdmmc2_dat2 */
+	{ GPMC_AD3,		(IEN  | PTU | M1) }, /* sdmmc2_dat3 */
+	{ GPMC_AD4,		(IEN  | PTU | M1) }, /* sdmmc2_dat4 */
+	{ GPMC_AD5,		(IEN  | PTU | M1) }, /* sdmmc2_dat5 */
+	{ GPMC_AD6,		(IEN  | PTU | M1) }, /* sdmmc2_dat6 */
+	{ GPMC_AD7,		(IEN  | PTU | M1) }, /* sdmmc2_dat7 */
+	{ GPMC_NOE,		(IEN  | PTU | M1) }, /* sdmmc2_clk */
+	{ GPMC_NWE,		(IEN  | PTU | M1) }, /* sdmmc2_cmd */
+	{ GPMC_NCS2,		(IEN  | PTD | M3) }, /* gpio_52 */
+	/* CAM */
+	{ CAM_SHUTTER,		(IDIS | DIS | M7) }, /* safe_mode */
+	{ CAM_STROBE,		(IDIS | DIS | M7) }, /* safe_mode */
+	{ CAM_GLOBALRESET,	(IDIS | DIS | M7) }, /* safe_mode */
+	/* HDQ */
+	{ HDQ_SIO,		(IDIS | DIS | M7) }, /* safe_mode */
+	/* I2C1 */
+	{ I2C1_SCL,		(IEN  | PTU | M0) }, /* i2c1_scl */
+	{ I2C1_SDA,		(IEN  | PTU | M0) }, /* i2c1_sda */
+	/* I2C2 */
+	{ I2C2_SCL,		(IEN  | PTU | M0) }, /* i2c2_scl */
+	{ I2C2_SDA,		(IEN  | PTU | M0) }, /* i2c2_sda */
+	/* I2C3 */
+	{ I2C3_SCL,		(IEN  | PTU | M0) }, /* i2c3_scl */
+	{ I2C3_SDA,		(IEN  | PTU | M0) }, /* i2c3_sda */
+	/* I2C4 */
+	{ I2C4_SCL,		(IEN  | PTU | M0) }, /* i2c4_scl */
+	{ I2C4_SDA,		(IEN  | PTU | M0) }, /* i2c4_sda */
+	/* MCSPI1 */
+	{ MCSPI1_CLK,		(IDIS | DIS | M7) }, /* safe_mode */
+	{ MCSPI1_SOMI,		(IDIS | DIS | M7) }, /* safe_mode */
+	{ MCSPI1_SIMO,		(IDIS | DIS | M7) }, /* safe_mode */
+	{ MCSPI1_CS0,		(IDIS | DIS | M7) }, /* safe_mode */
+	{ MCSPI1_CS1,		(IDIS | DIS | M7) }, /* safe_mode */
+	{ MCSPI1_CS2,		(IDIS | DIS | M7) }, /* safe_mode */
+	{ MCSPI1_CS3,		(IDIS | DIS | M7) }, /* safe_mode */
+	/* UART3 */
+	{ UART3_CTS_RCTX,	(IDIS | DIS | M7) }, /* safe_mode */
+	{ UART3_RTS_SD,		(IDIS | DIS | M7) }, /* safe_mode */
+	{ UART3_RX_IRRX,	(IEN  | DIS | M0) }, /* uart3_rx_irrx */
+	{ UART3_TX_IRTX,	(IDIS | DIS | M0) }, /* uart3_tx_irtx */
+	/* SDMMC5 */
+	{ SDMMC5_CLK,		(IEN  | PTU | M0) }, /* sdmmc5_clk */
+	{ SDMMC5_CMD,		(IEN  | PTU | M0) }, /* sdmmc5_cmd */
+	{ SDMMC5_DAT0,		(IEN  | PTU | M0) }, /* sdmmc5_dat0 */
+	{ SDMMC5_DAT1,		(IEN  | PTU | M0) }, /* sdmmc5_dat1 */
+	{ SDMMC5_DAT2,		(IEN  | PTU | M0) }, /* sdmmc5_dat2 */
+	{ SDMMC5_DAT3,		(IEN  | PTU | M0) }, /* sdmmc5_dat3 */
+	/* MCSPI4 */
+	{ MCSPI4_CLK,		(IEN  | DIS | M0) }, /* mcspi4_clk */
+	{ MCSPI4_SIMO,		(IEN  | DIS | M0) }, /* mcspi4_simo */
+	{ MCSPI4_SOMI,		(IEN  | DIS | M0) }, /* mcspi4_somi */
+	{ MCSPI4_CS0,		(IEN  | PTD | M0) }, /* mcspi4_cs0 */
+	/* UART4 */
+	{ UART4_RX,		(IDIS | DIS | M4) }, /* gpio_155 */
+	{ UART4_TX,		(IDIS | DIS | M7) }, /* safe_mode */
+	/* UNIPRO */
+	{ UNIPRO_TX0,		(IDIS | DIS | M7) }, /* safe_mode */
+	{ UNIPRO_TY0,		(IDIS | DIS | M7) }, /* safe_mode */
+	{ UNIPRO_TX1,		(IEN  | DIS | M3) }, /* gpio_173 */
+	{ UNIPRO_TY1,		(IEN  | DIS | M3) }, /* gpio_174 */
+	{ UNIPRO_TX2,		(IDIS | DIS | M7) }, /* safe_mode */
+	{ UNIPRO_TY2,		(IDIS | DIS | M7) }, /* safe_mode */
+	{ UNIPRO_RX0,		(IEN  | DIS | M3) }, /* gpio_175 */
+	{ UNIPRO_RY0,		(IEN  | DIS | M3) }, /* gpio_176 */
+	{ UNIPRO_RX1,		(IEN  | DIS | M3) }, /* gpio_177 */
+	{ UNIPRO_RY1,		(IEN  | DIS | M3) }, /* gpio_178 */
+	{ UNIPRO_RX2,		(IDIS | DIS | M7) }, /* safe_mode */
+	{ UNIPRO_RY2,		(IDIS | DIS | M7) }, /* safe_mode */
+	/* USBA0_OTG */
+	{ USBA0_OTG_CE,		(IDIS | PTD | M0) }, /* usba0_otg_ce */
+	{ USBA0_OTG_DP,		(IEN  | DIS | M0) }, /* usba0_otg_dp */
+	{ USBA0_OTG_DM,		(IEN  | DIS | M0) }, /* usba0_otg_dm */
+};
+
+#endif
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index 6efc8c1..973b579 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -14,6 +14,7 @@
 #include <dm/platdata.h>
 #include <dm/platform_data/serial_pl01x.h>
 #include "pcie.h"
+#include <asm/armv8/mmu.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -28,6 +29,26 @@
 	.platdata = &serial_platdata,
 };
 
+static struct mm_region vexpress64_mem_map[] = {
+	{
+		.base = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.base = 0x80000000UL,
+		.size = 0xff80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = vexpress64_mem_map;
+
 /* This function gets replaced by platforms supporting PCIe.
  * The replacement function, eg. on Juno, initialises the PCIe bus.
  */
diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c
index b926767..9131a38 100644
--- a/board/cavium/thunderx/thunderx.c
+++ b/board/cavium/thunderx/thunderx.c
@@ -10,6 +10,7 @@
 #include <linux/compiler.h>
 
 #include <cavium/atf.h>
+#include <asm/armv8/mmu.h>
 
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 #include <dm/platdata.h>
@@ -42,6 +43,29 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static struct mm_region thunderx_mem_map[] = {
+	{
+		.base = 0x000000000000UL,
+		.size = 0x40000000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE,
+	}, {
+		.base = 0x800000000000UL,
+		.size = 0x40000000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE,
+	}, {
+		.base = 0x840000000000UL,
+		.size = 0x40000000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE,
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = thunderx_mem_map;
+
 int board_init(void)
 {
 	return 0;
diff --git a/board/cm5200/fwupdate.c b/board/cm5200/fwupdate.c
index 2b92362..2ed90de 100644
--- a/board/cm5200/fwupdate.c
+++ b/board/cm5200/fwupdate.c
@@ -81,7 +81,7 @@
 	char dev[7];
 	char addr_str[16];
 	char * const argv[6] = { "fatload", "usb", dev, addr_str, nxri, NULL };
-	block_dev_desc_t *stor_dev = NULL;
+	struct blk_desc *stor_dev = NULL;
 	cmd_tbl_t *bcmd;
 
 	/* Get name of firmware directory */
@@ -117,7 +117,7 @@
 
 	/* Detect partition */
 	for (partno = -1, i = 0; i < 6; i++) {
-		if (get_partition_info(stor_dev, i, &info) == 0) {
+		if (part_get_info(stor_dev, i, &info) == 0) {
 			if (fat_register_device(stor_dev, i) == 0) {
 				/* Check if rescue image is present */
 				FW_DEBUG("Looking for firmware directory '%s'"
diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c
index 6d3b18a..b4f5d40 100644
--- a/board/compulab/cm_t54/cm_t54.c
+++ b/board/compulab/cm_t54/cm_t54.c
@@ -30,7 +30,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #if !defined(CONFIG_SPL_BUILD)
-inline void set_muxconf_regs_essential(void){};
+inline void set_muxconf_regs(void){};
 #endif
 
 const struct omap_sysinfo sysinfo = {
diff --git a/board/compulab/cm_t54/mux.c b/board/compulab/cm_t54/mux.c
index da35383..45d868f 100644
--- a/board/compulab/cm_t54/mux.c
+++ b/board/compulab/cm_t54/mux.c
@@ -75,10 +75,10 @@
 };
 
 /*
- * Routine: set_muxconf_regs_essential
+ * Routine: set_muxconf_regs
  * Description: setup board pinmux configuration.
  */
-void set_muxconf_regs_essential(void)
+void set_muxconf_regs(void)
 {
 	do_set_mux((*ctrl)->control_padconf_core_base,
 		   core_padconf_array_essential,
diff --git a/board/congatec/Kconfig b/board/congatec/Kconfig
new file mode 100644
index 0000000..1dc306e
--- /dev/null
+++ b/board/congatec/Kconfig
@@ -0,0 +1,29 @@
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+if VENDOR_CONGATEC
+
+choice
+	prompt "Mainboard model"
+	optional
+
+config TARGET_CONGA_QEVAL20_QA3_E3845
+	bool "congatec QEVAL 2.0 & conga-QA3/E3845"
+	help
+	  This is the congatec Qseven 2.0 evaluation carrier board
+	  (conga-QEVAL) equipped with the conga-QA3/E3845-4G SoM.
+	  It contains an Atom E3845 with Ethernet, micro-SD, USB 2,
+	  USB 3, SATA, serial console and HDMI 1.3 video out.
+	  It requires some binary blobs - see README.x86 for details.
+
+	  Note that PCIE_ECAM_BASE is set up by the FSP so the value used
+	  by U-Boot matches that value.
+
+endchoice
+
+source "board/congatec/conga-qeval20-qa3-e3845/Kconfig"
+
+endif
diff --git a/board/congatec/conga-qeval20-qa3-e3845/Kconfig b/board/congatec/conga-qeval20-qa3-e3845/Kconfig
new file mode 100644
index 0000000..9f31238
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/Kconfig
@@ -0,0 +1,28 @@
+if TARGET_CONGA_QEVAL20_QA3_E3845
+
+config SYS_BOARD
+	default "conga-qeval20-qa3-e3845"
+
+config SYS_VENDOR
+	default "congatec"
+
+config SYS_SOC
+	default "baytrail"
+
+config SYS_CONFIG_NAME
+	default "conga-qeval20-qa3-e3845"
+
+config SYS_TEXT_BASE
+	default 0xfff00000 if !EFI_STUB
+	default 0x01110000 if EFI_STUB
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR if !EFI_STUB
+	select INTEL_BAYTRAIL
+	select BOARD_ROMSIZE_KB_8192
+
+config PCIE_ECAM_BASE
+	default 0xe0000000
+
+endif
diff --git a/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS b/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS
new file mode 100644
index 0000000..5a4d4dc
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS
@@ -0,0 +1,7 @@
+congatec EVAL20-QA3-E3845
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/congatec/conga-qeval20-qa3-e3845
+F:	include/configs/conga-qeval20-qa3-e3845.h
+F:	configs/conga-qeval20-qa3-e3845_defconfig
+F:	arch/x86/dts/conga-qeval20-qa3-e3845.dts
diff --git a/board/congatec/conga-qeval20-qa3-e3845/Makefile b/board/congatec/conga-qeval20-qa3-e3845/Makefile
new file mode 100644
index 0000000..23b8748
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015, Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= conga-qeval20-qa3.o start.o
diff --git a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
new file mode 100644
index 0000000..6a946d5
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <winbond_w83627.h>
+#include <asm/gpio.h>
+#include <asm/ibmpc.h>
+#include <asm/pnp_def.h>
+
+int board_early_init_f(void)
+{
+	/*
+	 * The FSP enables the BayTrail internal legacy UART (again).
+	 * Disable it again, so that the Winbond one can be used.
+	 */
+	setup_internal_uart(0);
+
+	/* Enable the legacy UART in the Winbond W83627 Super IO chip */
+	winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1),
+			      UART0_BASE, UART0_IRQ);
+
+	return 0;
+}
+
+int arch_early_init_r(void)
+{
+	return 0;
+}
diff --git a/board/congatec/conga-qeval20-qa3-e3845/start.S b/board/congatec/conga-qeval20-qa3-e3845/start.S
new file mode 100644
index 0000000..2c941a4
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/start.S
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2015, Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+	jmp	early_board_init_ret
diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c
index 7110f35..bb7f778 100644
--- a/board/coreboot/coreboot/coreboot.c
+++ b/board/coreboot/coreboot/coreboot.c
@@ -12,8 +12,3 @@
 {
 	return 0;
 }
-
-void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
-{
-	return;
-}
diff --git a/board/efi/efi-x86/efi.c b/board/efi/efi-x86/efi.c
index 08958f9..1fbe36a 100644
--- a/board/efi/efi-x86/efi.c
+++ b/board/efi/efi-x86/efi.c
@@ -11,8 +11,3 @@
 {
 	return 0;
 }
-
-void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
-{
-	return;
-}
diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c
index 88b10a0..67b4afe 100644
--- a/board/freescale/ls1043aqds/eth.c
+++ b/board/freescale/ls1043aqds/eth.c
@@ -7,9 +7,11 @@
 #include <common.h>
 #include <asm/io.h>
 #include <netdev.h>
+#include <fdt_support.h>
 #include <fm_eth.h>
 #include <fsl_mdio.h>
 #include <fsl_dtsec.h>
+#include <libfdt.h>
 #include <malloc.h>
 #include <asm/arch/fsl_serdes.h>
 
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index 66d974a..ec5fdbf 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -10,6 +10,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/soc.h>
+#include <fdt_support.h>
 #include <hwconfig.h>
 #include <ahci.h>
 #include <mmc.h>
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 4f816c4..f440ce6 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -57,7 +57,7 @@
 			PAD_CTL_DSE_80ohm | PAD_CTL_HYS |	\
 			PAD_CTL_SRE_FAST)
 
-#define ETH_PHY_RESET	IMX_GPIO_NR(4, 21)
+#define ETH_PHY_POWER	IMX_GPIO_NR(4, 21)
 
 int dram_init(void)
 {
@@ -154,10 +154,9 @@
 {
 	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 
-	/* Reset LAN8720 PHY */
-	gpio_direction_output(ETH_PHY_RESET , 0);
-	udelay(25000);
-	gpio_set_value(ETH_PHY_RESET, 1);
+	/* Power up LAN8720 PHY */
+	gpio_direction_output(ETH_PHY_POWER , 1);
+	udelay(15000);
 }
 
 #define USDHC1_CD_GPIO	IMX_GPIO_NR(4, 7)
diff --git a/board/google/Kconfig b/board/google/Kconfig
index e9559c9..7ba73a2 100644
--- a/board/google/Kconfig
+++ b/board/google/Kconfig
@@ -36,9 +36,22 @@
 	  video output and a 16GB SATA solid state drive. There is no Chrome
 	  OS EC on this model.
 
+config TARGET_CHROMEBOOK_SAMUS
+	bool "Chromebook samus"
+	help
+	  This is the Chromebook Pixel released in 2015. It uses an Intel
+	  Broadwell U Core i5 or Core i7 CPU with either 8GB or 16GB of
+	  LPDDR3 SDRAM. It has PCIe WiFi and Bluetooth. It also includes a
+	  720p webcam, USB SD reader, microphone and speakers, 2 USB 3 Type
+	  C ports which can support charging and up to a 4K external display.
+	  There is a solid state drive, either 32GB or 64GB. There is a
+	  Chrome OS EC connected on LPC, and it provides a 2560x1700 high
+	  resolution touch-enabled LCD display.
+
 endchoice
 
 source "board/google/chromebook_link/Kconfig"
 source "board/google/chromebox_panther/Kconfig"
+source "board/google/chromebook_samus/Kconfig"
 
 endif
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
index d12d742..42615e1 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -17,145 +17,7 @@
 	return 0;
 }
 
-static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-	.gpio0 = GPIO_MODE_GPIO,  /* NMI_DBG# */
-	.gpio3 = GPIO_MODE_GPIO,  /* ALS_INT# */
-	.gpio5 = GPIO_MODE_GPIO,  /* SIM_DET */
-	.gpio7 = GPIO_MODE_GPIO,  /* EC_SCI# */
-	.gpio8 = GPIO_MODE_GPIO,  /* EC_SMI# */
-	.gpio9 = GPIO_MODE_GPIO,  /* RECOVERY# */
-	.gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */
-	.gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */
-	.gpio12 = GPIO_MODE_GPIO, /* TP_INT# */
-	.gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */
-	.gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */
-	.gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */
-	.gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */
-	.gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-	.gpio0 = GPIO_DIR_INPUT,
-	.gpio3 = GPIO_DIR_INPUT,
-	.gpio5 = GPIO_DIR_INPUT,
-	.gpio7 = GPIO_DIR_INPUT,
-	.gpio8 = GPIO_DIR_INPUT,
-	.gpio9 = GPIO_DIR_INPUT,
-	.gpio10 = GPIO_DIR_INPUT,
-	.gpio11 = GPIO_DIR_INPUT,
-	.gpio12 = GPIO_DIR_INPUT,
-	.gpio14 = GPIO_DIR_INPUT,
-	.gpio15 = GPIO_DIR_INPUT,
-	.gpio21 = GPIO_DIR_INPUT,
-	.gpio24 = GPIO_DIR_OUTPUT,
-	.gpio28 = GPIO_DIR_INPUT,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_level = {
-	.gpio1 = GPIO_LEVEL_HIGH,
-	.gpio6 = GPIO_LEVEL_HIGH,
-	.gpio24 = GPIO_LEVEL_LOW,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-	.gpio7 = GPIO_INVERT,
-	.gpio8 = GPIO_INVERT,
-	.gpio12 = GPIO_INVERT,
-	.gpio14 = GPIO_INVERT,
-	.gpio15 = GPIO_INVERT,
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-	.gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */
-	.gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */
-	.gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */
-	.gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */
-	.gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */
-	.gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-	.gpio36 = GPIO_DIR_OUTPUT,
-	.gpio41 = GPIO_DIR_INPUT,
-	.gpio42 = GPIO_DIR_INPUT,
-	.gpio43 = GPIO_DIR_INPUT,
-	.gpio57 = GPIO_DIR_INPUT,
-	.gpio60 = GPIO_DIR_OUTPUT,
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_level = {
-	.gpio36 = GPIO_LEVEL_HIGH,
-	.gpio60 = GPIO_LEVEL_HIGH,
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_level = {
-};
-
-static const struct pch_gpio_map link_gpio_map = {
-	.set1 = {
-		.mode      = &pch_gpio_set1_mode,
-		.direction = &pch_gpio_set1_direction,
-		.level     = &pch_gpio_set1_level,
-		.invert    = &pch_gpio_set1_invert,
-	},
-	.set2 = {
-		.mode      = &pch_gpio_set2_mode,
-		.direction = &pch_gpio_set2_direction,
-		.level     = &pch_gpio_set2_level,
-	},
-	.set3 = {
-		.mode      = &pch_gpio_set3_mode,
-		.direction = &pch_gpio_set3_direction,
-		.level     = &pch_gpio_set3_level,
-	},
-};
-
 int board_early_init_f(void)
 {
-	ich_gpio_set_gpio_map(&link_gpio_map);
-
 	return 0;
 }
-
-void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
-{
-	/* GPIO Set 1 */
-	if (gpio->set1.level)
-		outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
-	if (gpio->set1.mode)
-		outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
-	if (gpio->set1.direction)
-		outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL);
-	if (gpio->set1.reset)
-		outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1);
-	if (gpio->set1.invert)
-		outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV);
-	if (gpio->set1.blink)
-		outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK);
-
-	/* GPIO Set 2 */
-	if (gpio->set2.level)
-		outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
-	if (gpio->set2.mode)
-		outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
-	if (gpio->set2.direction)
-		outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2);
-	if (gpio->set2.reset)
-		outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2);
-
-	/* GPIO Set 3 */
-	if (gpio->set3.level)
-		outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
-	if (gpio->set3.mode)
-		outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
-	if (gpio->set3.direction)
-		outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3);
-	if (gpio->set3.reset)
-		outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3);
-}
diff --git a/board/google/chromebook_samus/Kconfig b/board/google/chromebook_samus/Kconfig
new file mode 100644
index 0000000..f2b9481
--- /dev/null
+++ b/board/google/chromebook_samus/Kconfig
@@ -0,0 +1,40 @@
+if TARGET_CHROMEBOOK_SAMUS
+
+config SYS_BOARD
+	default "chromebook_samus"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_SOC
+	default "broadwell"
+
+config SYS_CONFIG_NAME
+	default "chromebook_samus"
+
+config SYS_TEXT_BASE
+	default 0xffe00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select INTEL_BROADWELL
+	select HAVE_INTEL_ME
+	select BOARD_ROMSIZE_KB_8192
+
+config PCIE_ECAM_BASE
+	default 0xf0000000
+
+config EARLY_POST_CROS_EC
+	bool "Enable early post to Chrome OS EC"
+	default y
+
+config SYS_CAR_ADDR
+	hex
+	default 0xff7c0000
+
+config SYS_CAR_SIZE
+	hex
+	default 0x40000
+
+endif
diff --git a/board/google/chromebook_samus/MAINTAINERS b/board/google/chromebook_samus/MAINTAINERS
new file mode 100644
index 0000000..5500e46
--- /dev/null
+++ b/board/google/chromebook_samus/MAINTAINERS
@@ -0,0 +1,6 @@
+CHROMEBOOK SAMUS BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/chromebook_samus/
+F:	include/configs/chromebook_samus.h
+F:	configs/chromebook_samus_defconfig
diff --git a/board/google/chromebook_samus/Makefile b/board/google/chromebook_samus/Makefile
new file mode 100644
index 0000000..1522286
--- /dev/null
+++ b/board/google/chromebook_samus/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= samus.o
diff --git a/board/google/chromebook_samus/samus.c b/board/google/chromebook_samus/samus.c
new file mode 100644
index 0000000..3c3f5d4
--- /dev/null
+++ b/board/google/chromebook_samus/samus.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/cpu.h>
+
+int arch_early_init_r(void)
+{
+	return cpu_run_reference_code();
+}
+
+int board_early_init_f(void)
+{
+	return 0;
+}
diff --git a/board/google/chromebox_panther/panther.c b/board/google/chromebox_panther/panther.c
index d492a03..e3baf88 100644
--- a/board/google/chromebox_panther/panther.c
+++ b/board/google/chromebox_panther/panther.c
@@ -16,7 +16,3 @@
 {
 	return 0;
 }
-
-void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
-{
-}
diff --git a/board/gumstix/duovero/duovero.c b/board/gumstix/duovero/duovero.c
index 81d6c82..9671c5a 100644
--- a/board/gumstix/duovero/duovero.c
+++ b/board/gumstix/duovero/duovero.c
@@ -87,7 +87,7 @@
 	return 0;
 }
 
-void set_muxconf_regs_essential(void)
+void set_muxconf_regs(void)
 {
 	do_set_mux((*ctrl)->control_padconf_core_base,
 		   core_padconf_array_essential,
@@ -115,8 +115,12 @@
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
 }
-#endif
 
+void board_mmc_power_init(void)
+{
+	twl6030_power_mmc_init(0);
+}
+#endif
 
 #if defined(CONFIG_CMD_NET)
 
diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
index c4ae40b..1edc807 100644
--- a/board/hisilicon/hikey/hikey.c
+++ b/board/hisilicon/hikey/hikey.c
@@ -19,6 +19,7 @@
 #include <asm/arch/periph.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/hi6220.h>
+#include <asm/armv8/mmu.h>
 
 /*TODO drop this table in favour of device tree */
 static const struct hikey_gpio_platdata hi6220_gpio[] = {
@@ -87,6 +88,26 @@
 	.platdata = &serial_platdata,
 };
 
+static struct mm_region hikey_mem_map[] = {
+	{
+		.base = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.base = 0x80000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = hikey_mem_map;
+
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_uart_init(void)
 {
diff --git a/board/intel/bayleybay/bayleybay.c b/board/intel/bayleybay/bayleybay.c
index ccbe860..846b2f7 100644
--- a/board/intel/bayleybay/bayleybay.c
+++ b/board/intel/bayleybay/bayleybay.c
@@ -6,8 +6,3 @@
 
 #include <common.h>
 #include <asm/gpio.h>
-
-void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
-{
-	return;
-}
diff --git a/board/intel/cougarcanyon2/cougarcanyon2.c b/board/intel/cougarcanyon2/cougarcanyon2.c
index 31a480a..c350237 100644
--- a/board/intel/cougarcanyon2/cougarcanyon2.c
+++ b/board/intel/cougarcanyon2/cougarcanyon2.c
@@ -10,6 +10,7 @@
 #include <pci.h>
 #include <smsc_sio1007.h>
 #include <asm/ibmpc.h>
+#include <asm/lpc_common.h>
 #include <asm/pci.h>
 #include <asm/arch/pch.h>
 
@@ -51,8 +52,3 @@
 
 	return 0;
 }
-
-void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
-{
-	return;
-}
diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c
index 3a79e69..562d6d1 100644
--- a/board/intel/crownbay/crownbay.c
+++ b/board/intel/crownbay/crownbay.c
@@ -18,8 +18,3 @@
 
 	return 0;
 }
-
-void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
-{
-	return;
-}
diff --git a/board/intel/galileo/galileo.c b/board/intel/galileo/galileo.c
index 212c970..568bd4d 100644
--- a/board/intel/galileo/galileo.c
+++ b/board/intel/galileo/galileo.c
@@ -65,8 +65,3 @@
 	val |= (1 << 0);
 	outl(val, port);
 }
-
-void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
-{
-	return;
-}
diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c
index 44e5bf4..94b22ed 100644
--- a/board/intel/minnowmax/minnowmax.c
+++ b/board/intel/minnowmax/minnowmax.c
@@ -9,13 +9,5 @@
 
 int arch_early_init_r(void)
 {
-	/* do the pin-muxing */
-	gpio_ich6_pinctrl_init();
-
 	return 0;
 }
-
-void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
-{
-	return;
-}
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index e2fce50..d1a6a6f 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -34,9 +34,9 @@
 #endif
 
 static const struct ns16550_platdata igep_serial = {
-	OMAP34XX_UART3,
-	2,
-	V_NS16550_CLK
+	.base = OMAP34XX_UART3,
+	.reg_shift = 2,
+	.clock = V_NS16550_CLK
 };
 
 U_BOOT_DEVICE(igep_uart) = {
diff --git a/board/lego/ev3/Kconfig b/board/lego/ev3/Kconfig
new file mode 100644
index 0000000..14b3f0c
--- /dev/null
+++ b/board/lego/ev3/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_LEGOEV3
+
+config SYS_BOARD
+	default "ev3"
+
+config SYS_VENDOR
+	default "lego"
+
+config SYS_CONFIG_NAME
+	default "legoev3"
+
+endif
diff --git a/board/lego/ev3/MAINTAINERS b/board/lego/ev3/MAINTAINERS
new file mode 100644
index 0000000..11b3261
--- /dev/null
+++ b/board/lego/ev3/MAINTAINERS
@@ -0,0 +1,6 @@
+LEGOEV3 BOARD
+M:	David Lechner <david@lechnology.com>
+S:	Maintained
+F:	board/lego/ev3/
+F:	include/configs/legoev3.h
+F:	configs/legoev3_defconfig
diff --git a/board/lego/ev3/Makefile b/board/lego/ev3/Makefile
new file mode 100644
index 0000000..f3e717a
--- /dev/null
+++ b/board/lego/ev3/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= legoev3.o
diff --git a/board/lego/ev3/README b/board/lego/ev3/README
new file mode 100644
index 0000000..1a50ca9
--- /dev/null
+++ b/board/lego/ev3/README
@@ -0,0 +1,32 @@
+Summary
+=======
+
+LEGO MINDSTORMS EV3 is a toy robot produced by the LEGO Group. It is based
+on the davinci da850 evm. The EV3 has a 16MB spi flash and a SDHC microSD card
+reader.
+
+Booting
+=======
+
+The EV3 contains a bootloader in EEPROM that loads u-boot.bin from address 0x0
+of the spi flash memory. Using the default configuration, u-boot will check to
+see if there is a boot.scr file on the first FAT partition of the mmc. If there
+is, it will run the script and boot the kernel from the uImage file also in
+the FAT partition. Otherwise, it will load a kernel and rootfs from the flash.
+The kernel must be stored at address 0x50000 on the flash and have a maximum
+size of 3MiB. The rootfs must be a squasfs image and stored at 0x350000 in the
+flash and have a maximum size of 9.3MiB. The flash starting at 0xCB0000 is
+reserved for user data.
+
+Writing image to flash
+======================
+
+The EEPROM contains a program for uploading an image file to the flash memory.
+The program is started by holding down the right button on the EV3 when powering
+it on. You can also `run fwupdateboot` in the u-boot shell to reboot into this
+mode. The image can then be uploaded using the official LEGO MINDSTORMS EV3
+software or a 3rd party program capable of uploading a firmware file.
+
+If you are booting from the microSD card, it is enough to just write uboot.bin
+to the flash. If you are not using a microSD card, you will need to create an
+image file using the layout described above.
diff --git a/board/lego/ev3/legoev3.c b/board/lego/ev3/legoev3.c
new file mode 100644
index 0000000..a791b97
--- /dev/null
+++ b/board/lego/ev3/legoev3.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2016 David Lechner <david@lechnology.com>
+ *
+ * Based on da850evm.c
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on da830evm.c. Original Copyrights follow:
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <net.h>
+#include <netdev.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pinmux_defs.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/errno.h>
+#include <hwconfig.h>
+
+#ifdef CONFIG_DAVINCI_MMC
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u8 board_rev;
+
+#define EEPROM_I2C_ADDR		0x50
+#define EEPROM_REV_OFFSET	0x3F00
+#define EEPROM_MAC_OFFSET	0x3F06
+
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+	.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+	.host_caps = MMC_MODE_4BIT,     /* DA850 supports only 4-bit SD/MMC */
+	.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+	.version = MMC_CTLR_VERSION_2,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
+
+	/* Add slot-0 to mmc subsystem */
+	return davinci_mmc_init(bis, &mmc_sd0);
+}
+#endif
+
+const struct pinmux_resource pinmuxes[] = {
+	PINMUX_ITEM(spi0_pins_base),
+	PINMUX_ITEM(spi0_pins_scs0),
+	PINMUX_ITEM(uart1_pins_txrx),
+	PINMUX_ITEM(i2c0_pins),
+	PINMUX_ITEM(mmc0_pins),
+};
+
+const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
+
+const struct lpsc_resource lpsc[] = {
+	{ DAVINCI_LPSC_SPI0 },	/* Serial Flash */
+	{ DAVINCI_LPSC_UART1 },	/* console */
+	{ DAVINCI_LPSC_MMC_SD },
+};
+
+const int lpsc_size = ARRAY_SIZE(lpsc);
+
+u32 get_board_rev(void)
+{
+	u8 buf[2];
+
+	if (!board_rev) {
+		if (i2c_read(EEPROM_I2C_ADDR, EEPROM_REV_OFFSET, 2, buf, 2)) {
+			printf("\nBoard revision read failed!\n");
+		} else {
+			/*
+			 * Board rev 3 has MAC address at EEPROM_REV_OFFSET.
+			 * Other revisions have checksum at EEPROM_REV_OFFSET+1
+			 * to detect this.
+			 */
+			if ((buf[0] ^ buf[1]) == 0xFF)
+				board_rev = buf[0];
+			else
+				board_rev = 3;
+		}
+	}
+
+	return board_rev;
+}
+
+/*
+ * The Bluetooth MAC address serves as the board serial number.
+ */
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	u32 offset;
+	u8 buf[6];
+
+	if (!board_rev)
+		board_rev = get_board_rev();
+
+	/* Board rev 3 has MAC address where rev should be */
+	offset = (board_rev == 3) ? EEPROM_REV_OFFSET : EEPROM_MAC_OFFSET;
+
+	if (i2c_read(EEPROM_I2C_ADDR, offset, 2, buf, 6)) {
+		printf("\nBoard serial read failed!\n");
+	} else {
+		u8 *nr;
+
+		nr = (u8 *)&serialnr->low;
+		nr[0] = buf[5];
+		nr[1] = buf[4];
+		nr[2] = buf[3];
+		nr[3] = buf[2];
+		nr = (u8 *)&serialnr->high;
+		nr[0] = buf[1];
+		nr[1] = buf[0];
+		nr[2] = 0;
+		nr[3] = 0;
+	}
+}
+
+int board_early_init_f(void)
+{
+	/*
+	 * Power on required peripherals
+	 * ARM does not have access by default to PSC0 and PSC1
+	 * assuming here that the DSP bootloader has set the IOPU
+	 * such that PSC access is available to ARM
+	 */
+	if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
+		return 1;
+
+	return 0;
+}
+
+int board_init(void)
+{
+#ifndef CONFIG_USE_IRQ
+	irq_init();
+#endif
+
+	/* arch number of the board */
+	/* LEGO didn't register for a unique number and uses da850evm */
+	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	/* setup the SUSPSRC for ARM to control emulation suspend */
+	writel(readl(&davinci_syscfg_regs->suspsrc) &
+	       ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+		 DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+		 DAVINCI_SYSCFG_SUSPSRC_UART1),
+	       &davinci_syscfg_regs->suspsrc);
+
+	/* configure pinmux settings */
+	if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
+		return 1;
+
+	/* enable the console UART */
+	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+		DAVINCI_UART_PWREMU_MGMT_UTRST),
+	       &davinci_uart1_ctrl_regs->pwremu_mgmt);
+
+	return 0;
+}
diff --git a/board/lge/sniper/sniper.c b/board/lge/sniper/sniper.c
index f093f97..29a7045 100644
--- a/board/lge/sniper/sniper.c
+++ b/board/lge/sniper/sniper.c
@@ -109,7 +109,7 @@
 
 	/* Reboot mode */
 
-	reboot_mode[0] = omap_reboot_mode();
+	omap_reboot_mode(reboot_mode, sizeof(reboot_mode));
 
 	if (keys[0])
 		reboot_mode[0] = 'r';
@@ -122,6 +122,9 @@
 
 		omap_reboot_mode_clear();
 	} else {
+		/* Reboot mode garbage may still be valid, so clear it. */
+		omap_reboot_mode_clear();
+
 		/*
 		 * When not rebooting, valid power on reasons are either the
 		 * power button, charger plug or USB plug.
@@ -157,14 +160,9 @@
 	omap_die_id_get_board_serial(serialnr);
 }
 
-void reset_misc(void)
-{
-	omap_reboot_mode_store('u');
-}
-
 int fb_set_reboot_flag(void)
 {
-	return omap_reboot_mode_store('b');
+	return omap_reboot_mode_store("b");
 }
 
 #ifndef CONFIG_SPL_BUILD
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
index 668f684..51d2987 100644
--- a/board/logicpd/omap3som/omap3logic.c
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -47,9 +47,9 @@
  */
 
 static const struct ns16550_platdata omap3logic_serial = {
-	OMAP34XX_UART1,
-	2,
-	V_NS16550_CLK
+	.base = OMAP34XX_UART1,
+	.reg_shift = 2,
+	.clock = V_NS16550_CLK
 };
 
 U_BOOT_DEVICE(omap3logic_uart) = {
diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c
index 4040114..982619c 100644
--- a/board/logicpd/zoom1/zoom1.c
+++ b/board/logicpd/zoom1/zoom1.c
@@ -44,9 +44,9 @@
 };
 
 static const struct ns16550_platdata zoom1_serial = {
-	OMAP34XX_UART3,
-	2,
-	V_NS16550_CLK
+	.base = OMAP34XX_UART3,
+	.reg_shift = 2,
+	.clock = V_NS16550_CLK
 };
 
 U_BOOT_DEVICE(zoom1_uart) = {
diff --git a/board/mpl/pip405/README b/board/mpl/pip405/README
index 1b73dbe..e900c56 100644
--- a/board/mpl/pip405/README
+++ b/board/mpl/pip405/README
@@ -217,8 +217,8 @@
 Block device changes:
 ---------------------
 To allow the use of dos_part.c, mac_part.c and iso_part.c, the parameter
-block_dev_desc will be used when accessing the functions in these files. The block
-device descriptor (block_dev_desc) contains a pointer to the read routine of the
+blk_desc will be used when accessing the functions in these files. The block
+device descriptor (blk_desc) contains a pointer to the read routine of the
 device, which will be used to read blocks from the device.
 Renamed function ide_print to dev_print and moved it to the file disk/part.c to use
 it for IDE ATAPI and SCSI devices.
diff --git a/board/overo/overo.c b/board/overo/overo.c
index a38b959..40f13e5 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -68,9 +68,9 @@
 } expansion_config = {0x0};
 
 static const struct ns16550_platdata overo_serial = {
-	OMAP34XX_UART3,
-	2,
-	V_NS16550_CLK
+	.base = OMAP34XX_UART3,
+	.reg_shift = 2,
+	.clock = V_NS16550_CLK
 };
 
 U_BOOT_DEVICE(overo_uart) = {
diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c
index 21793e8..77e4482 100644
--- a/board/quipos/cairo/cairo.c
+++ b/board/quipos/cairo/cairo.c
@@ -91,9 +91,9 @@
 #endif
 
 static const struct ns16550_platdata cairo_serial = {
-	OMAP34XX_UART2,
-	2,
-	V_NS16550_CLK
+	.base = OMAP34XX_UART2,
+	.reg_shift = 2,
+	.clock = V_NS16550_CLK
 };
 
 U_BOOT_DEVICE(cairo_uart) = {
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 15b7af6..80eae9c 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -337,8 +337,8 @@
 	if (!sunxi_mmc_has_egon_boot_signature(mmc0) &&
 	    sunxi_mmc_has_egon_boot_signature(mmc1)) {
 		/* Booting from emmc / mmc2, swap */
-		mmc0->block_dev.dev = 1;
-		mmc1->block_dev.dev = 0;
+		mmc0->block_dev.devnum = 1;
+		mmc1->block_dev.devnum = 0;
 	}
 #endif
 
diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig
index 49b73ab..11ef3ca 100644
--- a/board/ti/am335x/Kconfig
+++ b/board/ti/am335x/Kconfig
@@ -38,4 +38,6 @@
 	  as the ROM only partially sets up pinmux.  We also default to using
 	  NOR for environment.
 
+source "board/ti/common/Kconfig"
+
 endif
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index f56d17ec..4330be6 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -31,6 +31,7 @@
 #include <environment.h>
 #include <watchdog.h>
 #include <environment.h>
+#include "../common/board_detect.h"
 #include "board.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -46,43 +47,9 @@
 /*
  * Read header information from EEPROM into global structure.
  */
-static int read_eeprom(struct am335x_baseboard_id *header)
+static inline int __maybe_unused read_eeprom(void)
 {
-	/* Check if baseboard eeprom is available */
-	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
-		puts("Could not probe the EEPROM; something fundamentally "
-			"wrong on the I2C bus.\n");
-		return -ENODEV;
-	}
-
-	/* read the eeprom using i2c */
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
-		     sizeof(struct am335x_baseboard_id))) {
-		puts("Could not read the EEPROM; something fundamentally"
-			" wrong on the I2C bus.\n");
-		return -EIO;
-	}
-
-	if (header->magic != 0xEE3355AA) {
-		/*
-		 * read the eeprom using i2c again,
-		 * but use only a 1 byte address
-		 */
-		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
-			     sizeof(struct am335x_baseboard_id))) {
-			puts("Could not read the EEPROM; something "
-				"fundamentally wrong on the I2C bus.\n");
-			return -EIO;
-		}
-
-		if (header->magic != 0xEE3355AA) {
-			printf("Incorrect magic number (0x%x) in EEPROM\n",
-					header->magic);
-			return -EINVAL;
-		}
-	}
-
-	return 0;
+	return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
 }
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
@@ -223,16 +190,15 @@
 
 void am33xx_spl_board_init(void)
 {
-	struct am335x_baseboard_id header;
 	int mpu_vdd;
 
-	if (read_eeprom(&header) < 0)
+	if (read_eeprom() < 0)
 		puts("Could not get board ID.\n");
 
 	/* Get the frequency */
 	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
 
-	if (board_is_bone(&header) || board_is_bone_lt(&header)) {
+	if (board_is_bone() || board_is_bone_lt()) {
 		/* BeagleBone PMIC Code */
 		int usb_cur_lim;
 
@@ -240,8 +206,7 @@
 		 * Only perform PMIC configurations if board rev > A1
 		 * on Beaglebone White
 		 */
-		if (board_is_bone(&header) && !strncmp(header.version,
-						       "00A1", 4))
+		if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
 			return;
 
 		if (i2c_probe(TPS65217_CHIP_PM))
@@ -251,7 +216,7 @@
 		 * On Beaglebone White we need to ensure we have AC power
 		 * before increasing the frequency.
 		 */
-		if (board_is_bone(&header)) {
+		if (board_is_bone()) {
 			uchar pmic_status_reg;
 			if (tps65217_reg_read(TPS65217_STATUS,
 					      &pmic_status_reg))
@@ -266,7 +231,7 @@
 		 * Override what we have detected since we know if we have
 		 * a Beaglebone Black it supports 1GHz.
 		 */
-		if (board_is_bone_lt(&header))
+		if (board_is_bone_lt())
 			dpll_mpu_opp100.m = MPUPLL_M_1000;
 
 		/*
@@ -307,7 +272,7 @@
 		 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
 		 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
 		 */
-		if (board_is_bone(&header)) {
+		if (board_is_bone()) {
 			if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 					       TPS65217_DEFLS1,
 					       TPS65217_LDO_VOLTAGE_OUT_3_3,
@@ -367,18 +332,16 @@
 
 const struct dpll_params *get_dpll_ddr_params(void)
 {
-	struct am335x_baseboard_id header;
-
 	enable_i2c0_pin_mux();
 	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-	if (read_eeprom(&header) < 0)
+	if (read_eeprom() < 0)
 		puts("Could not get board ID.\n");
 
-	if (board_is_evm_sk(&header))
+	if (board_is_evm_sk())
 		return &dpll_ddr_evm_sk;
-	else if (board_is_bone_lt(&header))
+	else if (board_is_bone_lt())
 		return &dpll_ddr_bone_black;
-	else if (board_is_evm_15_or_later(&header))
+	else if (board_is_evm_15_or_later())
 		return &dpll_ddr_evm_sk;
 	else
 		return &dpll_ddr;
@@ -403,12 +366,10 @@
 
 void set_mux_conf_regs(void)
 {
-	__maybe_unused struct am335x_baseboard_id header;
-
-	if (read_eeprom(&header) < 0)
+	if (read_eeprom() < 0)
 		puts("Could not get board ID.\n");
 
-	enable_board_pin_mux(&header);
+	enable_board_pin_mux();
 }
 
 const struct ctrl_ioregs ioregs_evmsk = {
@@ -445,12 +406,10 @@
 
 void sdram_init(void)
 {
-	__maybe_unused struct am335x_baseboard_id header;
-
-	if (read_eeprom(&header) < 0)
+	if (read_eeprom() < 0)
 		puts("Could not get board ID.\n");
 
-	if (board_is_evm_sk(&header)) {
+	if (board_is_evm_sk()) {
 		/*
 		 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 		 * This is safe enough to do on older revs.
@@ -459,15 +418,15 @@
 		gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 	}
 
-	if (board_is_evm_sk(&header))
+	if (board_is_evm_sk())
 		config_ddr(303, &ioregs_evmsk, &ddr3_data,
 			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-	else if (board_is_bone_lt(&header))
+	else if (board_is_bone_lt())
 		config_ddr(400, &ioregs_bonelt,
 			   &ddr3_beagleblack_data,
 			   &ddr3_beagleblack_cmd_ctrl_data,
 			   &ddr3_beagleblack_emif_reg_data, 0);
-	else if (board_is_evm_15_or_later(&header))
+	else if (board_is_evm_15_or_later())
 		config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
 			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 	else
@@ -496,26 +455,16 @@
 int board_late_init(void)
 {
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-	char safe_string[HDR_NAME_LEN + 1];
-	struct am335x_baseboard_id header;
+	int rc;
+	char *name = NULL;
 
-	if (read_eeprom(&header) < 0)
+	rc = read_eeprom();
+	if (rc)
 		puts("Could not get board ID.\n");
 
-	/* Now set variables based on the header. */
-	strncpy(safe_string, (char *)header.name, sizeof(header.name));
-	safe_string[sizeof(header.name)] = 0;
-	setenv("board_name", safe_string);
-
-	/* BeagleBone Green eeprom, board_rev: 0x1a 0x00 0x00 0x00 */
-	if ( (header.version[0] == 0x1a) && (header.version[1] == 0x00) &&
-	     (header.version[2] == 0x00) && (header.version[3] == 0x00) ) {
-		setenv("board_rev", "BBG1");
-	} else {
-		strncpy(safe_string, (char *)header.version, sizeof(header.version));
-		safe_string[sizeof(header.version)] = 0;
-		setenv("board_rev", safe_string);
-	}
+	if (board_is_bbg1())
+		name = "BBG1";
+	set_board_info_env(name);
 #endif
 
 	return 0;
@@ -587,7 +536,7 @@
 	int rv, n = 0;
 	uint8_t mac_addr[6];
 	uint32_t mac_hi, mac_lo;
-	__maybe_unused struct am335x_baseboard_id header;
+	__maybe_unused struct ti_am_eeprom *header;
 
 	/* try reading mac address from efuse */
 	mac_lo = readl(&cdev->macid0l);
@@ -624,11 +573,11 @@
 			eth_setenv_enetaddr("eth1addr", mac_addr);
 	}
 
-	if (read_eeprom(&header) < 0)
+	if (read_eeprom() < 0)
 		puts("Could not get board ID.\n");
 
-	if (board_is_bone(&header) || board_is_bone_lt(&header) ||
-	    board_is_idk(&header)) {
+	if (board_is_bone() || board_is_bone_lt() ||
+	    board_is_idk()) {
 		writel(MII_MODE_ENABLE, &cdev->miisel);
 		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 				PHY_INTERFACE_MODE_MII;
@@ -657,7 +606,7 @@
 #define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
 #define AR8051_RGMII_TX_CLK_DLY		0x100
 
-	if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
+	if (board_is_evm_sk() || board_is_gp_evm()) {
 		const char *devname;
 		devname = miiphy_get_current_dev();
 
diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
index bc700d5..062c345 100644
--- a/board/ti/am335x/board.h
+++ b/board/ti/am335x/board.h
@@ -11,53 +11,40 @@
 #ifndef _BOARD_H_
 #define _BOARD_H_
 
-/*
- * TI AM335x parts define a system EEPROM that defines certain sub-fields.
- * We use these fields to in turn see what board we are on, and what
- * that might require us to set or not set.
- */
-#define HDR_NO_OF_MAC_ADDR	3
-#define HDR_ETH_ALEN		6
-#define HDR_NAME_LEN		8
-
-struct am335x_baseboard_id {
-	unsigned int  magic;
-	char name[HDR_NAME_LEN];
-	char version[4];
-	char serial[12];
-	char config[32];
-	char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
-};
+static inline int board_is_bone(void)
+{
+	return board_ti_is("A335BONE");
+}
 
-static inline int board_is_bone(struct am335x_baseboard_id *header)
+static inline int board_is_bone_lt(void)
 {
-	return !strncmp(header->name, "A335BONE", HDR_NAME_LEN);
+	return board_ti_is("A335BNLT");
 }
 
-static inline int board_is_bone_lt(struct am335x_baseboard_id *header)
+static inline int board_is_bbg1(void)
 {
-	return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN);
+	return board_is_bone_lt() && !strncmp(board_ti_get_rev(), "BBG1", 4);
 }
 
-static inline int board_is_evm_sk(struct am335x_baseboard_id *header)
+static inline int board_is_evm_sk(void)
 {
-	return !strncmp("A335X_SK", header->name, HDR_NAME_LEN);
+	return board_ti_is("A335X_SK");
 }
 
-static inline int board_is_idk(struct am335x_baseboard_id *header)
+static inline int board_is_idk(void)
 {
-	return !strncmp(header->config, "SKU#02", 6);
+	return !strncmp(board_ti_get_config(), "SKU#02", 6);
 }
 
-static inline int board_is_gp_evm(struct am335x_baseboard_id *header)
+static inline int board_is_gp_evm(void)
 {
-	return !strncmp("A33515BB", header->name, HDR_NAME_LEN);
+	return board_ti_is("A33515BB");
 }
 
-static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header)
+static inline int board_is_evm_15_or_later(void)
 {
-	return (board_is_gp_evm(header) &&
-		strncmp("1.5", header->version, 3) <= 0);
+	return (board_is_gp_evm() &&
+		strncmp("1.5", board_ti_get_rev(), 3) <= 0);
 }
 
 /*
@@ -73,5 +60,5 @@
 void enable_uart4_pin_mux(void);
 void enable_uart5_pin_mux(void);
 void enable_i2c0_pin_mux(void);
-void enable_board_pin_mux(struct am335x_baseboard_id *header);
+void enable_board_pin_mux(void);
 #endif
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 79ed02f..fdf827f 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -19,6 +19,7 @@
 #include <asm/arch/mux.h>
 #include <asm/io.h>
 #include <i2c.h>
+#include "../common/board_detect.h"
 #include "board.h"
 
 static struct module_pin_mux uart0_pin_mux[] = {
@@ -312,10 +313,10 @@
 	return (1 << (val & PROFILE_MASK));
 }
 
-void enable_board_pin_mux(struct am335x_baseboard_id *header)
+void enable_board_pin_mux(void)
 {
 	/* Do board-specific muxes. */
-	if (board_is_bone(header)) {
+	if (board_is_bone()) {
 		/* Beaglebone pinmux */
 		configure_module_pin_mux(mii1_pin_mux);
 		configure_module_pin_mux(mmc0_pin_mux);
@@ -326,7 +327,7 @@
 #else
 		configure_module_pin_mux(mmc1_pin_mux);
 #endif
-	} else if (board_is_gp_evm(header)) {
+	} else if (board_is_gp_evm()) {
 		/* General Purpose EVM */
 		unsigned short profile = detect_daughter_board_profile();
 		configure_module_pin_mux(rgmii1_pin_mux);
@@ -343,17 +344,17 @@
 			configure_module_pin_mux(mmc1_pin_mux);
 			configure_module_pin_mux(spi0_pin_mux);
 		}
-	} else if (board_is_idk(header)) {
+	} else if (board_is_idk()) {
 		/* Industrial Motor Control (IDK) */
 		configure_module_pin_mux(mii1_pin_mux);
 		configure_module_pin_mux(mmc0_no_cd_pin_mux);
-	} else if (board_is_evm_sk(header)) {
+	} else if (board_is_evm_sk()) {
 		/* Starter Kit EVM */
 		configure_module_pin_mux(i2c1_pin_mux);
 		configure_module_pin_mux(gpio0_7_pin_mux);
 		configure_module_pin_mux(rgmii1_pin_mux);
 		configure_module_pin_mux(mmc0_pin_mux_sk_evm);
-	} else if (board_is_bone_lt(header)) {
+	} else if (board_is_bone_lt()) {
 		/* Beaglebone LT pinmux */
 		configure_module_pin_mux(mii1_pin_mux);
 		configure_module_pin_mux(mmc0_pin_mux);
diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds
index 78f294a..a56cc82 100644
--- a/board/ti/am335x/u-boot.lds
+++ b/board/ti/am335x/u-boot.lds
@@ -59,6 +59,36 @@
 
 	. = ALIGN(4);
 
+	.__efi_runtime_start : {
+		*(.__efi_runtime_start)
+	}
+
+	.efi_runtime : {
+		*(efi_runtime_text)
+		*(efi_runtime_data)
+	}
+
+	.__efi_runtime_stop : {
+		*(.__efi_runtime_stop)
+	}
+
+	.efi_runtime_rel_start :
+	{
+		*(.__efi_runtime_rel_start)
+	}
+
+	.efi_runtime_rel : {
+		*(.relefi_runtime_text)
+		*(.relefi_runtime_data)
+	}
+
+	.efi_runtime_rel_stop :
+	{
+		*(.__efi_runtime_rel_stop)
+	}
+
+	. = ALIGN(4);
+
 	.image_copy_end :
 	{
 		*(.__image_copy_end)
diff --git a/board/ti/am43xx/Kconfig b/board/ti/am43xx/Kconfig
index 8d1c168..9cb80cc 100644
--- a/board/ti/am43xx/Kconfig
+++ b/board/ti/am43xx/Kconfig
@@ -12,4 +12,6 @@
 config SYS_CONFIG_NAME
 	default "am43xx_evm"
 
+source "board/ti/common/Kconfig"
+
 endif
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 770726c..d208d2f 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -19,6 +19,7 @@
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/gpio.h>
 #include <asm/emif.h>
+#include "../common/board_detect.h"
 #include "board.h"
 #include <power/pmic.h>
 #include <power/tps65218.h>
@@ -37,48 +38,9 @@
 /*
  * Read header information from EEPROM into global structure.
  */
-static int read_eeprom(struct am43xx_board_id *header)
+static inline int __maybe_unused read_eeprom(void)
 {
-	/* Check if baseboard eeprom is available */
-	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
-		printf("Could not probe the EEPROM at 0x%x\n",
-		       CONFIG_SYS_I2C_EEPROM_ADDR);
-		return -ENODEV;
-	}
-
-	/* read the eeprom using i2c */
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
-		     sizeof(struct am43xx_board_id))) {
-		printf("Could not read the EEPROM\n");
-		return -EIO;
-	}
-
-	if (header->magic != 0xEE3355AA) {
-		/*
-		 * read the eeprom using i2c again,
-		 * but use only a 1 byte address
-		 */
-		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
-			     sizeof(struct am43xx_board_id))) {
-			printf("Could not read the EEPROM at 0x%x\n",
-			       CONFIG_SYS_I2C_EEPROM_ADDR);
-			return -EIO;
-		}
-
-		if (header->magic != 0xEE3355AA) {
-			printf("Incorrect magic number (0x%x) in EEPROM\n",
-			       header->magic);
-			return -EINVAL;
-		}
-	}
-
-	strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
-	am43xx_board_name[sizeof(header->name)] = 0;
-
-	strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version));
-	am43xx_board_rev[sizeof(header->version)] = 0;
-
-	return 0;
+	return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
 }
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
@@ -374,6 +336,9 @@
 {
 	int ind = get_sys_clk_index();
 
+	if (read_eeprom() < 0)
+		return NULL;
+
 	if (board_is_eposevm())
 		return &epos_evm_dpll_ddr[ind];
 	else if (board_is_gpevm() || board_is_sk())
@@ -381,7 +346,7 @@
 	else if (board_is_idk())
 		return &idk_dpll_ddr;
 
-	printf(" Board '%s' not supported\n", am43xx_board_name);
+	printf(" Board '%s' not supported\n", board_ti_get_name());
 	return NULL;
 }
 
@@ -512,16 +477,29 @@
 	}
 }
 
+void gpi2c_init(void)
+{
+	/* When needed to be invoked prior to BSS initialization */
+	static bool first_time = true;
+
+	if (first_time) {
+		enable_i2c0_pin_mux();
+		i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
+			 CONFIG_SYS_OMAP24_I2C_SLAVE);
+		first_time = false;
+	}
+}
+
 void scale_vcores(void)
 {
 	const struct dpll_params *mpu_params;
-	struct am43xx_board_id header;
 
-	enable_i2c0_pin_mux();
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-	if (read_eeprom(&header) < 0)
+	if (read_eeprom() < 0)
 		puts("Could not get board ID.\n");
 
+	/* Ensure I2C is initialized for PMIC configuration */
+	gpi2c_init();
+
 	/* Get the frequency */
 	mpu_params = get_dpll_mpu_params();
 
@@ -558,6 +536,8 @@
 
 void sdram_init(void)
 {
+	if (read_eeprom() < 0)
+		return;
 	/*
 	 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
 	 * GP EMV has 1GB DDR3 connected to EMIF
@@ -655,20 +635,7 @@
 int board_late_init(void)
 {
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-	char safe_string[HDR_NAME_LEN + 1];
-	struct am43xx_board_id header;
-
-	if (read_eeprom(&header) < 0)
-		puts("Could not get board ID.\n");
-
-	/* Now set variables based on the header. */
-	strncpy(safe_string, (char *)header.name, sizeof(header.name));
-	safe_string[sizeof(header.name)] = 0;
-	setenv("board_name", safe_string);
-
-	strncpy(safe_string, (char *)header.version, sizeof(header.version));
-	safe_string[sizeof(header.version)] = 0;
-	setenv("board_rev", safe_string);
+	set_board_info_env(NULL);
 #endif
 	return 0;
 }
diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
index eb9493e..2cf7a77 100644
--- a/board/ti/am43xx/board.h
+++ b/board/ti/am43xx/board.h
@@ -14,58 +14,37 @@
 
 #include <asm/arch/omap.h>
 
-static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START;
-static char *const am43xx_board_rev = (char *)AM4372_BOARD_VERSION_START;
-
-/*
- * TI AM437x EVMs define a system EEPROM that defines certain sub-fields.
- * We use these fields to in turn see what board we are on, and what
- * that might require us to set or not set.
- */
-#define HDR_NO_OF_MAC_ADDR	3
-#define HDR_ETH_ALEN		6
-#define HDR_NAME_LEN		8
-
-#define DEV_ATTR_MAX_OFFSET	5
-#define DEV_ATTR_MIN_OFFSET	0
-
-struct am43xx_board_id {
-	unsigned int  magic;
-	char name[HDR_NAME_LEN];
-	char version[4];
-	char serial[12];
-	char config[32];
-	char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
-};
+#define DEV_ATTR_MAX_OFFSET    5
+#define DEV_ATTR_MIN_OFFSET    0
 
 static inline int board_is_eposevm(void)
 {
-	return !strncmp(am43xx_board_name, "AM43EPOS", HDR_NAME_LEN);
+	return board_ti_is("AM43EPOS");
 }
 
 static inline int board_is_gpevm(void)
 {
-	return !strncmp(am43xx_board_name, "AM43__GP", HDR_NAME_LEN);
+	return board_ti_is("AM43__GP");
 }
 
 static inline int board_is_sk(void)
 {
-	return !strncmp(am43xx_board_name, "AM43__SK", HDR_NAME_LEN);
+	return board_ti_is("AM43__SK");
 }
 
 static inline int board_is_idk(void)
 {
-	return !strncmp(am43xx_board_name, "AM43_IDK", HDR_NAME_LEN);
+	return board_ti_is("AM43_IDK");
 }
 
 static inline int board_is_evm_14_or_later(void)
 {
-	return (board_is_gpevm() && strncmp("1.4", am43xx_board_rev, 3) <= 0);
+	return (board_is_gpevm() && strncmp("1.4", board_ti_get_rev(), 3) <= 0);
 }
 
 static inline int board_is_evm_12_or_later(void)
 {
-	return (board_is_gpevm() && strncmp("1.2", am43xx_board_rev, 3) <= 0);
+	return (board_is_gpevm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0);
 }
 
 void enable_uart0_pin_mux(void);
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index 510477d..e03b1bc 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mux.h>
+#include "../common/board_detect.h"
 #include "board.h"
 
 static struct module_pin_mux rmii1_pin_mux[] = {
diff --git a/board/ti/am57xx/Kconfig b/board/ti/am57xx/Kconfig
index bdb7795..17745ff 100644
--- a/board/ti/am57xx/Kconfig
+++ b/board/ti/am57xx/Kconfig
@@ -9,4 +9,6 @@
 config SYS_CONFIG_NAME
 	default "am57xx_evm"
 
+source "board/ti/common/Kconfig"
+
 endif
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 042f9ab..67191af 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -30,8 +30,12 @@
 #include <dwc3-omap-uboot.h>
 #include <ti-usb-phy-uboot.h>
 
+#include "../common/board_detect.h"
 #include "mux_data.h"
 
+#define board_is_x15()		board_ti_is("BBRDX15_")
+#define board_is_am572x_evm()	board_ti_is("AM572PM_")
+
 #ifdef CONFIG_DRIVER_TI_CPSW
 #include <cpsw.h>
 #endif
@@ -41,8 +45,10 @@
 /* GPIO 7_11 */
 #define GPIO_DDR_VTT_EN 203
 
+#define SYSINFO_BOARD_NAME_MAX_LEN	45
+
 const struct omap_sysinfo sysinfo = {
-	"Board: BeagleBoard x15\n"
+	"Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
 };
 
 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
@@ -58,22 +64,22 @@
 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
 	.sdram_config_init	= 0x61851b32,
 	.sdram_config		= 0x61851b32,
-	.sdram_config2		= 0x00000000,
+	.sdram_config2		= 0x08000000,
 	.ref_ctrl		= 0x000040F1,
 	.ref_ctrl_final		= 0x00001035,
-	.sdram_tim1		= 0xceef266b,
-	.sdram_tim2		= 0x328f7fda,
-	.sdram_tim3		= 0x027f88a8,
+	.sdram_tim1		= 0xcccf36ab,
+	.sdram_tim2		= 0x308f7fda,
+	.sdram_tim3		= 0x409f88a8,
 	.read_idle_ctrl		= 0x00050000,
-	.zq_config		= 0x0007190b,
+	.zq_config		= 0x5007190b,
 	.temp_alert_config	= 0x00000000,
 	.emif_ddr_phy_ctlr_1_init = 0x0024400b,
 	.emif_ddr_phy_ctlr_1	= 0x0e24400b,
 	.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
-	.emif_ddr_ext_phy_ctrl_2 = 0x00740074,
-	.emif_ddr_ext_phy_ctrl_3 = 0x00780078,
-	.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
-	.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
+	.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
+	.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
 	.emif_rd_wr_lvl_rmp_win	= 0x00000000,
 	.emif_rd_wr_lvl_rmp_ctl	= 0x80000000,
 	.emif_rd_wr_lvl_ctl	= 0x00000000,
@@ -83,65 +89,61 @@
 /* Ext phy ctrl regs 1-35 */
 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 	0x10040100,
-	0x00740074,
-	0x00780078,
-	0x007c007c,
-	0x007b007b,
-	0x00800080,
-	0x00360036,
+	0x00910091,
+	0x00950095,
+	0x009B009B,
+	0x009E009E,
+	0x00980098,
 	0x00340034,
-	0x00360036,
-	0x00350035,
 	0x00350035,
-
-	0x01ff01ff,
-	0x01ff01ff,
-	0x01ff01ff,
-	0x01ff01ff,
-	0x01ff01ff,
-
-	0x00430043,
-	0x003e003e,
-	0x004a004a,
-	0x00470047,
-	0x00400040,
-
+	0x00340034,
+	0x00310031,
+	0x00340034,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x00480048,
+	0x004A004A,
+	0x00520052,
+	0x00550055,
+	0x00500050,
 	0x00000000,
 	0x00600020,
 	0x40011080,
 	0x08102040,
-
-	0x00400040,
-	0x00400040,
-	0x00400040,
-	0x00400040,
-	0x00400040,
+	0x0,
+	0x0,
 	0x0,
 	0x0,
 	0x0,
 	0x0,
+	0x0,
+	0x0,
+	0x0,
 	0x0
 };
 
 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 	.sdram_config_init	= 0x61851b32,
 	.sdram_config		= 0x61851b32,
-	.sdram_config2		= 0x00000000,
+	.sdram_config2		= 0x08000000,
 	.ref_ctrl		= 0x000040F1,
 	.ref_ctrl_final		= 0x00001035,
-	.sdram_tim1		= 0xceef266b,
-	.sdram_tim2		= 0x328f7fda,
-	.sdram_tim3		= 0x027f88a8,
+	.sdram_tim1		= 0xcccf36ab,
+	.sdram_tim2		= 0x308f7fda,
+	.sdram_tim3		= 0x409f88a8,
 	.read_idle_ctrl		= 0x00050000,
-	.zq_config		= 0x0007190b,
+	.zq_config		= 0x5007190b,
 	.temp_alert_config	= 0x00000000,
 	.emif_ddr_phy_ctlr_1_init = 0x0024400b,
 	.emif_ddr_phy_ctlr_1	= 0x0e24400b,
 	.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
-	.emif_ddr_ext_phy_ctrl_2 = 0x00820082,
-	.emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
-	.emif_ddr_ext_phy_ctrl_4 = 0x00800080,
-	.emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
+	.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
+	.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
 	.emif_rd_wr_lvl_rmp_win	= 0x00000000,
 	.emif_rd_wr_lvl_rmp_ctl	= 0x80000000,
 	.emif_rd_wr_lvl_ctl	= 0x00000000,
@@ -150,41 +152,39 @@
 
 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 	0x10040100,
-	0x00820082,
-	0x008b008b,
-	0x00800080,
-	0x007e007e,
-	0x00800080,
-	0x00370037,
-	0x00390039,
-	0x00360036,
-	0x00370037,
+	0x00910091,
+	0x00950095,
+	0x009B009B,
+	0x009E009E,
+	0x00980098,
+	0x00340034,
 	0x00350035,
-	0x01ff01ff,
-	0x01ff01ff,
-	0x01ff01ff,
-	0x01ff01ff,
-	0x01ff01ff,
-	0x00540054,
-	0x00540054,
-	0x004e004e,
-	0x004c004c,
-	0x00400040,
-
+	0x00340034,
+	0x00310031,
+	0x00340034,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x00480048,
+	0x004A004A,
+	0x00520052,
+	0x00550055,
+	0x00500050,
 	0x00000000,
 	0x00600020,
 	0x40011080,
 	0x08102040,
-
-	0x00400040,
-	0x00400040,
-	0x00400040,
-	0x00400040,
-	0x00400040,
+	0x0,
+	0x0,
+	0x0,
 	0x0,
 	0x0,
 	0x0,
 	0x0,
+	0x0,
+	0x0,
 	0x0
 };
 
@@ -246,6 +246,66 @@
 	.iva.pmic		= &tps659038,
 };
 
+#ifdef CONFIG_SPL_BUILD
+/* No env to setup for SPL */
+static inline void setup_board_eeprom_env(void) { }
+
+/* Override function to read eeprom information */
+void do_board_detect(void)
+{
+	int rc;
+
+	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+				  CONFIG_EEPROM_CHIP_ADDRESS);
+	if (rc)
+		printf("ti_i2c_eeprom_init failed %d\n", rc);
+}
+
+#else	/* CONFIG_SPL_BUILD */
+
+/* Override function to read eeprom information: actual i2c read done by SPL*/
+void do_board_detect(void)
+{
+	char *bname = NULL;
+	int rc;
+
+	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+				  CONFIG_EEPROM_CHIP_ADDRESS);
+	if (rc)
+		printf("ti_i2c_eeprom_init failed %d\n", rc);
+
+	if (board_is_x15())
+		bname = "BeagleBoard X15";
+	else if (board_is_am572x_evm())
+		bname = "AM572x EVM";
+
+	if (bname)
+		snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
+			 "Board: %s REV %s\n", bname, board_ti_get_rev());
+}
+
+static void setup_board_eeprom_env(void)
+{
+	char *name = "beagle_x15";
+	int rc;
+
+	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+				  CONFIG_EEPROM_CHIP_ADDRESS);
+	if (rc)
+		goto invalid_eeprom;
+
+	if (board_is_am572x_evm())
+		name = "am57xx_evm";
+	else
+		printf("Unidentified board claims %s in eeprom header\n",
+		       board_ti_get_name());
+
+invalid_eeprom:
+	set_board_info_env(name);
+}
+
+#endif	/* CONFIG_SPL_BUILD */
+
 void hw_data_init(void)
 {
 	*prcm = &dra7xx_prcm;
@@ -265,6 +325,8 @@
 int board_late_init(void)
 {
 	init_sata(0);
+	setup_board_eeprom_env();
+
 	/*
 	 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 	 * This is the POWERHOLD-in-Low behavior.
@@ -273,7 +335,7 @@
 	return 0;
 }
 
-void set_muxconf_regs_essential(void)
+void set_muxconf_regs(void)
 {
 	do_set_mux32((*ctrl)->control_padconf_core_base,
 		     early_padconf, ARRAY_SIZE(early_padconf));
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index ff317ef..0ed4f52 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -73,9 +73,9 @@
 } expansion_config;
 
 static const struct ns16550_platdata beagle_serial = {
-	OMAP34XX_UART3,
-	2,
-	V_NS16550_CLK
+	.base = OMAP34XX_UART3,
+	.reg_shift = 2,
+	.clock = V_NS16550_CLK
 };
 
 U_BOOT_DEVICE(beagle_uart) = {
diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig
new file mode 100644
index 0000000..adf73ab
--- /dev/null
+++ b/board/ti/common/Kconfig
@@ -0,0 +1,5 @@
+config TI_I2C_BOARD_DETECT
+	bool "Support for Board detection for TI platforms"
+	help
+	   Support for detection board information on Texas Instrument's
+	   Evaluation Boards which have I2C based EEPROM detection
diff --git a/board/ti/common/Makefile b/board/ti/common/Makefile
new file mode 100644
index 0000000..7170eac
--- /dev/null
+++ b/board/ti/common/Makefile
@@ -0,0 +1,6 @@
+# Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o
diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
new file mode 100644
index 0000000..e0ae1a5
--- /dev/null
+++ b/board/ti/common/board_detect.c
@@ -0,0 +1,318 @@
+/*
+ * Library to support early TI EVM EEPROM handling
+ *
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla
+ *	Steve Kipisz
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/omap_common.h>
+#include <i2c.h>
+
+#include "board_detect.h"
+
+/**
+ * ti_i2c_eeprom_init - Initialize an i2c bus and probe for a device
+ * @i2c_bus: i2c bus number to initialize
+ * @dev_addr: Device address to probe for
+ *
+ * Return: 0 on success or corresponding error on failure.
+ */
+static int __maybe_unused ti_i2c_eeprom_init(int i2c_bus, int dev_addr)
+{
+	int rc;
+
+	if (i2c_bus >= 0) {
+		rc = i2c_set_bus_num(i2c_bus);
+		if (rc)
+			return rc;
+	}
+
+	return i2c_probe(dev_addr);
+}
+
+/**
+ * ti_i2c_eeprom_read - Read data from an EEPROM
+ * @dev_addr: The device address of the EEPROM
+ * @offset: Offset to start reading in the EEPROM
+ * @ep: Pointer to a buffer to read into
+ * @epsize: Size of buffer
+ *
+ * Return: 0 on success or corresponding result of i2c_read
+ */
+static int __maybe_unused ti_i2c_eeprom_read(int dev_addr, int offset,
+					     uchar *ep, int epsize)
+{
+	return i2c_read(dev_addr, offset, 2, ep, epsize);
+}
+
+/**
+ * ti_eeprom_string_cleanup() - Handle eeprom programming errors
+ * @s:	eeprom string (should be NULL terminated)
+ *
+ * Some Board manufacturers do not add a NULL termination at the
+ * end of string, instead some binary information is kludged in, hence
+ * convert the string to just printable characters of ASCII chart.
+ */
+static void __maybe_unused ti_eeprom_string_cleanup(char *s)
+{
+	int i, l;
+
+	l = strlen(s);
+	for (i = 0; i < l; i++, s++)
+		if (*s < ' ' || *s > '~') {
+			*s = 0;
+			break;
+		}
+}
+
+__weak void gpi2c_init(void)
+{
+}
+
+static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr,
+					    u32 header, u32 size, uint8_t *ep)
+{
+	u32 byte, hdr_read;
+	int rc;
+
+	gpi2c_init();
+	rc = ti_i2c_eeprom_init(bus_addr, dev_addr);
+	if (rc)
+		return rc;
+
+	/*
+	 * Read the header first then only read the other contents.
+	 */
+	byte = 2;
+	rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4);
+	if (rc)
+		return rc;
+
+	/* Corrupted data??? */
+	if (hdr_read != header) {
+		rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4);
+		/*
+		 * read the eeprom header using i2c again, but use only a
+		 * 1 byte address (some legacy boards need this..)
+		 */
+		byte = 1;
+		if (rc)
+			rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read,
+				      4);
+		if (rc)
+			return rc;
+	}
+	if (hdr_read != header)
+		return -1;
+
+	rc = i2c_read(dev_addr, 0x0, byte, ep, size);
+	if (rc)
+		return rc;
+
+	return 0;
+}
+
+int __maybe_unused ti_i2c_eeprom_am_get(int bus_addr, int dev_addr)
+{
+	int rc;
+	struct ti_am_eeprom am_ep;
+	struct ti_common_eeprom *ep;
+
+	ep = TI_EEPROM_DATA;
+	if (ep->header == TI_EEPROM_HEADER_MAGIC)
+		goto already_read;
+
+	/* Initialize with a known bad marker for i2c fails.. */
+	ep->header = TI_DEAD_EEPROM_MAGIC;
+	ep->name[0] = 0x0;
+	ep->version[0] = 0x0;
+	ep->serial[0] = 0x0;
+
+	rc = ti_i2c_eeprom_get(bus_addr, dev_addr, TI_EEPROM_HEADER_MAGIC,
+			       sizeof(am_ep), (uint8_t *)&am_ep);
+	if (rc)
+		return rc;
+
+	ep->header = am_ep.header;
+	strlcpy(ep->name, am_ep.name, TI_EEPROM_HDR_NAME_LEN + 1);
+	ti_eeprom_string_cleanup(ep->name);
+
+	/* BeagleBone Green '1' eeprom, board_rev: 0x1a 0x00 0x00 0x00 */
+	if (am_ep.version[0] == 0x1a && am_ep.version[1] == 0x00 &&
+	    am_ep.version[2] == 0x00 && am_ep.version[3] == 0x00)
+		strlcpy(ep->version, "BBG1", TI_EEPROM_HDR_REV_LEN + 1);
+	else
+		strlcpy(ep->version, am_ep.version, TI_EEPROM_HDR_REV_LEN + 1);
+	ti_eeprom_string_cleanup(ep->version);
+	strlcpy(ep->serial, am_ep.serial, TI_EEPROM_HDR_SERIAL_LEN + 1);
+	ti_eeprom_string_cleanup(ep->serial);
+	strlcpy(ep->config, am_ep.config, TI_EEPROM_HDR_CONFIG_LEN + 1);
+	ti_eeprom_string_cleanup(ep->config);
+
+	memcpy(ep->mac_addr, am_ep.mac_addr,
+	       TI_EEPROM_HDR_NO_OF_MAC_ADDR * TI_EEPROM_HDR_ETH_ALEN);
+
+already_read:
+	return 0;
+}
+
+int __maybe_unused ti_i2c_eeprom_dra7_get(int bus_addr, int dev_addr)
+{
+	int rc, offset = 0;
+	struct dra7_eeprom dra7_ep;
+	struct ti_common_eeprom *ep;
+
+	ep = TI_EEPROM_DATA;
+	if (ep->header == DRA7_EEPROM_HEADER_MAGIC)
+		goto already_read;
+
+	/* Initialize with a known bad marker for i2c fails.. */
+	ep->header = 0xADEAD12C;
+	ep->name[0] = 0x0;
+	ep->version[0] = 0x0;
+	ep->serial[0] = 0x0;
+	ep->emif1_size = 0;
+	ep->emif2_size = 0;
+
+	rc = ti_i2c_eeprom_get(bus_addr, dev_addr, DRA7_EEPROM_HEADER_MAGIC,
+			       sizeof(dra7_ep), (uint8_t *)&dra7_ep);
+	if (rc)
+		return rc;
+
+	ep->header = dra7_ep.header;
+	strlcpy(ep->name, dra7_ep.name, TI_EEPROM_HDR_NAME_LEN + 1);
+	ti_eeprom_string_cleanup(ep->name);
+
+	offset = dra7_ep.version_major - 1;
+
+	/* Rev F is skipped */
+	if (offset >= 5)
+		offset = offset + 1;
+	snprintf(ep->version, TI_EEPROM_HDR_REV_LEN + 1, "%c.%d",
+		 'A' + offset, dra7_ep.version_minor);
+	ti_eeprom_string_cleanup(ep->version);
+	ep->emif1_size = (u64)dra7_ep.emif1_size;
+	ep->emif2_size = (u64)dra7_ep.emif2_size;
+	strlcpy(ep->config, dra7_ep.config, TI_EEPROM_HDR_CONFIG_LEN + 1);
+	ti_eeprom_string_cleanup(ep->config);
+
+already_read:
+	return 0;
+}
+
+bool __maybe_unused board_ti_is(char *name_tag)
+{
+	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+	if (ep->header == TI_DEAD_EEPROM_MAGIC)
+		return false;
+	return !strncmp(ep->name, name_tag, TI_EEPROM_HDR_NAME_LEN);
+}
+
+bool __maybe_unused board_ti_rev_is(char *rev_tag, int cmp_len)
+{
+	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+	int l;
+
+	if (ep->header == TI_DEAD_EEPROM_MAGIC)
+		return false;
+
+	l = cmp_len > TI_EEPROM_HDR_REV_LEN ? TI_EEPROM_HDR_REV_LEN : cmp_len;
+	return !strncmp(ep->version, rev_tag, l);
+}
+
+char * __maybe_unused board_ti_get_rev(void)
+{
+	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+	if (ep->header == TI_DEAD_EEPROM_MAGIC)
+		return NULL;
+
+	return ep->version;
+}
+
+char * __maybe_unused board_ti_get_config(void)
+{
+	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+	if (ep->header == TI_DEAD_EEPROM_MAGIC)
+		return NULL;
+
+	return ep->config;
+}
+
+char * __maybe_unused board_ti_get_name(void)
+{
+	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+	if (ep->header == TI_DEAD_EEPROM_MAGIC)
+		return NULL;
+
+	return ep->name;
+}
+
+void __maybe_unused
+board_ti_get_eth_mac_addr(int index,
+			  u8 mac_addr[TI_EEPROM_HDR_ETH_ALEN])
+{
+	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+	if (ep->header == TI_DEAD_EEPROM_MAGIC)
+		goto fail;
+
+	if (index < 0 || index >= TI_EEPROM_HDR_NO_OF_MAC_ADDR)
+		goto fail;
+
+	memcpy(mac_addr, ep->mac_addr[index], TI_EEPROM_HDR_ETH_ALEN);
+	return;
+
+fail:
+	memset(mac_addr, 0, TI_EEPROM_HDR_ETH_ALEN);
+}
+
+u64 __maybe_unused board_ti_get_emif1_size(void)
+{
+	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+	if (ep->header != DRA7_EEPROM_HEADER_MAGIC)
+		return 0;
+
+	return ep->emif1_size;
+}
+
+u64 __maybe_unused board_ti_get_emif2_size(void)
+{
+	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+	if (ep->header != DRA7_EEPROM_HEADER_MAGIC)
+		return 0;
+
+	return ep->emif2_size;
+}
+
+void __maybe_unused set_board_info_env(char *name)
+{
+	char *unknown = "unknown";
+	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+	if (name)
+		setenv("board_name", name);
+	else if (ep->name)
+		setenv("board_name", ep->name);
+	else
+		setenv("board_name", unknown);
+
+	if (ep->version)
+		setenv("board_rev", ep->version);
+	else
+		setenv("board_rev", unknown);
+
+	if (ep->serial)
+		setenv("board_serial", ep->serial);
+	else
+		setenv("board_serial", unknown);
+}
diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h
new file mode 100644
index 0000000..eb17f6f
--- /dev/null
+++ b/board/ti/common/board_detect.h
@@ -0,0 +1,196 @@
+/*
+ * Library to support early TI EVM EEPROM handling
+ *
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __BOARD_DETECT_H
+#define __BOARD_DETECT_H
+
+/* TI EEPROM MAGIC Header identifier */
+#define TI_EEPROM_HEADER_MAGIC	0xEE3355AA
+#define TI_DEAD_EEPROM_MAGIC	0xADEAD12C
+
+#define TI_EEPROM_HDR_NAME_LEN		8
+#define TI_EEPROM_HDR_REV_LEN		4
+#define TI_EEPROM_HDR_SERIAL_LEN	12
+#define TI_EEPROM_HDR_CONFIG_LEN	32
+#define TI_EEPROM_HDR_NO_OF_MAC_ADDR	3
+#define TI_EEPROM_HDR_ETH_ALEN		6
+
+/**
+ * struct ti_am_eeprom - This structure holds data read in from the
+ *                     AM335x, AM437x, AM57xx TI EVM EEPROMs.
+ * @header: This holds the magic number
+ * @name: The name of the board
+ * @version: Board revision
+ * @serial: Board serial number
+ * @config: Reserved
+ * @mac_addr: Any MAC addresses written in the EEPROM
+ *
+ * The data is this structure is read from the EEPROM on the board.
+ * It is used for board detection which is based on name. It is used
+ * to configure specific TI boards. This allows booting of multiple
+ * TI boards with a single MLO and u-boot.
+ */
+struct ti_am_eeprom {
+	unsigned int header;
+	char name[TI_EEPROM_HDR_NAME_LEN];
+	char version[TI_EEPROM_HDR_REV_LEN];
+	char serial[TI_EEPROM_HDR_SERIAL_LEN];
+	char config[TI_EEPROM_HDR_CONFIG_LEN];
+	char mac_addr[TI_EEPROM_HDR_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN];
+} __attribute__ ((__packed__));
+
+/* DRA7 EEPROM MAGIC Header identifier */
+#define DRA7_EEPROM_HEADER_MAGIC	0xAA5533EE
+#define DRA7_EEPROM_HDR_NAME_LEN	16
+#define DRA7_EEPROM_HDR_CONFIG_LEN	4
+
+/**
+ * struct dra7_eeprom - This structure holds data read in from the DRA7 EVM
+ *			EEPROMs.
+ * @header: This holds the magic number
+ * @name: The name of the board
+ * @version_major: Board major version
+ * @version_minor: Board minor version
+ * @config: Board specific config options
+ * @emif1_size: Size of DDR attached to EMIF1
+ * @emif2_size: Size of DDR attached to EMIF2
+ *
+ * The data is this structure is read from the EEPROM on the board.
+ * It is used for board detection which is based on name. It is used
+ * to configure specific DRA7 boards. This allows booting of multiple
+ * DRA7 boards with a single MLO and u-boot.
+ */
+struct dra7_eeprom {
+	u32 header;
+	char name[DRA7_EEPROM_HDR_NAME_LEN];
+	u16 version_major;
+	u16 version_minor;
+	char config[DRA7_EEPROM_HDR_CONFIG_LEN];
+	u32 emif1_size;
+	u32 emif2_size;
+} __attribute__ ((__packed__));
+
+/**
+ * struct ti_common_eeprom - Null terminated, usable EEPROM contents.
+ * header:	Magic number
+ * @name:	NULL terminated name
+ * @version:	NULL terminated version
+ * @serial:	NULL terminated serial number
+ * @config:	NULL terminated Board specific config options
+ * @mac_addr:	MAC addresses
+ * @emif1_size:	Size of the ddr available on emif1
+ * @emif2_size:	Size of the ddr available on emif2
+ */
+struct ti_common_eeprom {
+	u32 header;
+	char name[TI_EEPROM_HDR_NAME_LEN + 1];
+	char version[TI_EEPROM_HDR_REV_LEN + 1];
+	char serial[TI_EEPROM_HDR_SERIAL_LEN + 1];
+	char config[TI_EEPROM_HDR_CONFIG_LEN + 1];
+	char mac_addr[TI_EEPROM_HDR_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN];
+	u64 emif1_size;
+	u64 emif2_size;
+};
+
+#define TI_EEPROM_DATA ((struct ti_common_eeprom *)\
+				OMAP_SRAM_SCRATCH_BOARD_EEPROM_START)
+
+/**
+ * ti_i2c_eeprom_am_get() - Consolidated eeprom data collection for AM* TI EVMs
+ * @bus_addr:	I2C bus address
+ * @dev_addr:	I2C slave address
+ *
+ * ep in SRAM is populated by the this AM generic function that consolidates
+ * the basic initialization logic common across all AM* platforms.
+ */
+int ti_i2c_eeprom_am_get(int bus_addr, int dev_addr);
+
+/**
+ * ti_i2c_eeprom_dra7_get() - Consolidated eeprom data for DRA7 TI EVMs
+ * @bus_addr:	I2C bus address
+ * @dev_addr:	I2C slave address
+ */
+int ti_i2c_eeprom_dra7_get(int bus_addr, int dev_addr);
+
+/**
+ * board_ti_is() - Board detection logic for TI EVMs
+ * @name_tag:	Tag used in eeprom for the board
+ *
+ * Return: false if board information does not match OR eeprom wasn't read.
+ *	   true otherwise
+ */
+bool board_ti_is(char *name_tag);
+
+/**
+ * board_ti_rev_is() - Compare board revision for TI EVMs
+ * @rev_tag:	Revision tag to check in eeprom
+ * @cmp_len:	How many chars to compare?
+ *
+ * NOTE: revision information is often messed up (hence the str len match) :(
+ *
+ * Return: false if board information does not match OR eeprom was'nt read.
+ *	   true otherwise
+ */
+bool board_ti_rev_is(char *rev_tag, int cmp_len);
+
+/**
+ * board_ti_get_rev() - Get board revision for TI EVMs
+ *
+ * Return: NULL if eeprom was'nt read.
+ *	   Board revision otherwise
+ */
+char *board_ti_get_rev(void);
+
+/**
+ * board_ti_get_config() - Get board config for TI EVMs
+ *
+ * Return: NULL if eeprom was'nt read.
+ *	   Board config otherwise
+ */
+char *board_ti_get_config(void);
+
+/**
+ * board_ti_get_name() - Get board name for TI EVMs
+ *
+ * Return: NULL if eeprom was'nt read.
+ *	   Board name otherwise
+ */
+char *board_ti_get_name(void);
+
+/**
+ * board_ti_get_eth_mac_addr() - Get Ethernet MAC address from EEPROM MAC list
+ * @index:	0 based index within the list of MAC addresses
+ * @mac_addr:	MAC address contained at the index is returned here
+ *
+ * Does not sanity check the mac_addr. Whatever is stored in EEPROM is returned.
+ */
+void board_ti_get_eth_mac_addr(int index, u8 mac_addr[TI_EEPROM_HDR_ETH_ALEN]);
+
+/**
+ * board_ti_get_emif1_size() - Get size of the DDR on emif1 for TI EVMs
+ *
+ * Return: NULL if eeprom was'nt read or emif1_size is not available.
+ */
+u64 board_ti_get_emif1_size(void);
+
+/**
+ * board_ti_get_emif2_size() - Get size of the DDR on emif2 for TI EVMs
+ *
+ * Return: NULL if eeprom was'nt read or emif2_size is not available.
+ */
+u64 board_ti_get_emif2_size(void);
+
+/**
+ * set_board_info_env() - Setup commonly used board information environment vars
+ * @name:	Name of the board
+ *
+ * If name is NULL, default_name is used.
+ */
+void set_board_info_env(char *name);
+
+#endif	/* __BOARD_DETECT_H */
diff --git a/board/ti/dra7xx/Kconfig b/board/ti/dra7xx/Kconfig
index 80341d9..b642113 100644
--- a/board/ti/dra7xx/Kconfig
+++ b/board/ti/dra7xx/Kconfig
@@ -17,4 +17,7 @@
 	  The DRA7xx (and AM57x) SoC has a total of 6 UARTs available to it.
 	  Depending on your specific board you may want something other than UART1
 	  here.
+
+source "board/ti/common/Kconfig"
+
 endif
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index eebec88..4e45abf 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -13,11 +13,13 @@
 #include <common.h>
 #include <palmas.h>
 #include <sata.h>
+#include <linux/string.h>
 #include <asm/gpio.h>
 #include <usb.h>
 #include <linux/usb/gadget.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/dra7xx_iodelay.h>
+#include <asm/emif.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sata.h>
@@ -27,6 +29,13 @@
 #include <ti-usb-phy-uboot.h>
 
 #include "mux_data.h"
+#include "../common/board_detect.h"
+
+#define board_is_dra74x_evm()		board_ti_is("5777xCPU")
+#define board_is_dra74x_revh_or_later() board_is_dra74x_evm() &&	\
+				(strncmp("H", board_ti_get_rev(), 1) <= 0)
+#define board_ti_get_emif_size()	board_ti_get_emif1_size() +	\
+					board_ti_get_emif2_size()
 
 #ifdef CONFIG_DRIVER_TI_CPSW
 #include <cpsw.h>
@@ -37,10 +46,215 @@
 /* GPIO 7_11 */
 #define GPIO_DDR_VTT_EN 203
 
+#define SYSINFO_BOARD_NAME_MAX_LEN	37
+
 const struct omap_sysinfo sysinfo = {
-	"Board: DRA7xx\n"
+	"Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
+};
+
+static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
+	.sdram_config_init              = 0x61851ab2,
+	.sdram_config                   = 0x61851ab2,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl                       = 0x000040F1,
+	.ref_ctrl_final			= 0x00001035,
+	.sdram_tim1                     = 0xCCCF36B3,
+	.sdram_tim2                     = 0x308F7FDA,
+	.sdram_tim3                     = 0x427F88A8,
+	.read_idle_ctrl                 = 0x00050000,
+	.zq_config                      = 0x0007190B,
+	.temp_alert_config              = 0x00000000,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400B,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400B,
+	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3        = 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
+	.emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
+	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+	.emif_rd_wr_lvl_ctl             = 0x00000000,
+	.emif_rd_wr_exec_thresh         = 0x00000305
+};
+
+static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
+	.sdram_config_init              = 0x61851B32,
+	.sdram_config                   = 0x61851B32,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl                       = 0x000040F1,
+	.ref_ctrl_final			= 0x00001035,
+	.sdram_tim1                     = 0xCCCF36B3,
+	.sdram_tim2                     = 0x308F7FDA,
+	.sdram_tim3                     = 0x427F88A8,
+	.read_idle_ctrl                 = 0x00050000,
+	.zq_config                      = 0x0007190B,
+	.temp_alert_config              = 0x00000000,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400B,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400B,
+	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3        = 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
+	.emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
+	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+	.emif_rd_wr_lvl_ctl             = 0x00000000,
+	.emif_rd_wr_exec_thresh         = 0x00000305
+};
+
+static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
+	.sdram_config_init              = 0x61862B32,
+	.sdram_config                   = 0x61862B32,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl                       = 0x0000514C,
+	.ref_ctrl_final			= 0x0000144A,
+	.sdram_tim1                     = 0xD113781C,
+	.sdram_tim2                     = 0x30717FE3,
+	.sdram_tim3                     = 0x409F86A8,
+	.read_idle_ctrl                 = 0x00050000,
+	.zq_config                      = 0x5007190B,
+	.temp_alert_config              = 0x00000000,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400D,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400D,
+	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
+	.emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,
+	.emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
+	.emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
+	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+	.emif_rd_wr_lvl_ctl             = 0x00000000,
+	.emif_rd_wr_exec_thresh         = 0x00000305
+};
+
+const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
+	.sdram_config_init              = 0x61851ab2,
+	.sdram_config                   = 0x61851ab2,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl                       = 0x000040F1,
+	.ref_ctrl_final			= 0x00001035,
+	.sdram_tim1                     = 0xCCCF36B3,
+	.sdram_tim2                     = 0x30BF7FDA,
+	.sdram_tim3                     = 0x427F8BA8,
+	.read_idle_ctrl                 = 0x00050000,
+	.zq_config                      = 0x0007190B,
+	.temp_alert_config              = 0x00000000,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400B,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400B,
+	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3        = 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
+	.emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
+	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+	.emif_rd_wr_lvl_ctl             = 0x00000000,
+	.emif_rd_wr_exec_thresh         = 0x00000305
+};
+
+const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
+	.sdram_config_init              = 0x61851B32,
+	.sdram_config                   = 0x61851B32,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl                       = 0x000040F1,
+	.ref_ctrl_final			= 0x00001035,
+	.sdram_tim1                     = 0xCCCF36B3,
+	.sdram_tim2                     = 0x308F7FDA,
+	.sdram_tim3                     = 0x427F88A8,
+	.read_idle_ctrl                 = 0x00050000,
+	.zq_config                      = 0x0007190B,
+	.temp_alert_config              = 0x00000000,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400B,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400B,
+	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3        = 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
+	.emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
+	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+	.emif_rd_wr_lvl_ctl             = 0x00000000,
+	.emif_rd_wr_exec_thresh         = 0x00000305
+};
+
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+{
+	u64 ram_size;
+
+	ram_size = board_ti_get_emif_size();
+
+	switch (omap_revision()) {
+	case DRA752_ES1_0:
+	case DRA752_ES1_1:
+	case DRA752_ES2_0:
+		switch (emif_nr) {
+		case 1:
+			if (ram_size > CONFIG_MAX_MEM_MAPPED)
+				*regs = &emif1_ddr3_532_mhz_1cs_2G;
+			else
+				*regs = &emif1_ddr3_532_mhz_1cs;
+			break;
+		case 2:
+			if (ram_size > CONFIG_MAX_MEM_MAPPED)
+				*regs = &emif2_ddr3_532_mhz_1cs_2G;
+			else
+				*regs = &emif2_ddr3_532_mhz_1cs;
+			break;
+		}
+		break;
+	case DRA722_ES1_0:
+		*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
+		break;
+	default:
+		*regs = &emif1_ddr3_532_mhz_1cs;
+	}
+}
+
+static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
+	.dmm_lisa_map_0 = 0x0,
+	.dmm_lisa_map_1 = 0x80640300,
+	.dmm_lisa_map_2 = 0xC0500220,
+	.dmm_lisa_map_3 = 0xFF020100,
+	.is_ma_present	= 0x1
+};
+
+static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
+	.dmm_lisa_map_0 = 0x0,
+	.dmm_lisa_map_1 = 0x0,
+	.dmm_lisa_map_2 = 0x80600100,
+	.dmm_lisa_map_3 = 0xFF020100,
+	.is_ma_present	= 0x1
+};
+
+const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
+	.dmm_lisa_map_0 = 0x0,
+	.dmm_lisa_map_1 = 0x0,
+	.dmm_lisa_map_2 = 0x80740300,
+	.dmm_lisa_map_3 = 0xFF020100,
+	.is_ma_present	= 0x1
 };
 
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+{
+	u64 ram_size;
+
+	ram_size = board_ti_get_emif_size();
+
+	switch (omap_revision()) {
+	case DRA752_ES1_0:
+	case DRA752_ES1_1:
+	case DRA752_ES2_0:
+		if (ram_size > CONFIG_MAX_MEM_MAPPED)
+			*dmm_lisa_regs = &lisa_map_dra7_2GB;
+		else
+			*dmm_lisa_regs = &lisa_map_dra7_1536MB;
+		break;
+	case DRA722_ES1_0:
+	default:
+		*dmm_lisa_regs = &lisa_map_2G_x_2;
+	}
+}
+
 /**
  * @brief board_init
  *
@@ -54,20 +268,77 @@
 	return 0;
 }
 
+void dram_init_banksize(void)
+{
+	u64 ram_size;
+
+	ram_size = board_ti_get_emif_size();
+
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = get_effective_memsize();
+	if (ram_size > CONFIG_MAX_MEM_MAPPED) {
+		gd->bd->bi_dram[1].start = 0x200000000;
+		gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
+	}
+}
+
 int board_late_init(void)
 {
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-	if (omap_revision() == DRA722_ES1_0)
-		setenv("board_name", "dra72x");
+	char *name = "unknown";
+
+	if (is_dra72x())
+		name = "dra72x";
 	else
-		setenv("board_name", "dra7xx");
+		name = "dra7xx";
+
+	set_board_info_env(name);
 
 	omap_die_id_serial();
 #endif
 	return 0;
 }
+
+#ifdef CONFIG_SPL_BUILD
+void do_board_detect(void)
+{
+	int rc;
+
+	rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
+				    CONFIG_EEPROM_CHIP_ADDRESS);
+	if (rc)
+		printf("ti_i2c_eeprom_init failed %d\n", rc);
+}
+
+#else
+
+void do_board_detect(void)
+{
+	char *bname = NULL;
+	int rc;
+
+	rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
+				    CONFIG_EEPROM_CHIP_ADDRESS);
+	if (rc)
+		printf("ti_i2c_eeprom_init failed %d\n", rc);
+
+	if (board_is_dra74x_evm()) {
+		bname = "DRA74x EVM";
+	/* If EEPROM is not populated */
+	} else {
+		if (is_dra72x())
+			bname = "DRA72x EVM";
+		else
+			bname = "DRA74x EVM";
+	}
+
+	if (bname)
+		snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
+			 "Board: %s REV %s\n", bname, board_ti_get_rev());
+}
+#endif	/* CONFIG_SPL_BUILD */
 
-void set_muxconf_regs_essential(void)
+void set_muxconf_regs(void)
 {
 	do_set_mux32((*ctrl)->control_padconf_core_base,
 		     early_padconf, ARRAY_SIZE(early_padconf));
@@ -82,10 +353,10 @@
 
 	switch (omap_revision()) {
 	case DRA722_ES1_0:
-		pads = core_padconf_array_essential;
-		npads = ARRAY_SIZE(core_padconf_array_essential);
-		iodelay = iodelay_cfg_array;
-		niodelays = ARRAY_SIZE(iodelay_cfg_array);
+		pads = dra72x_core_padconf_array;
+		npads = ARRAY_SIZE(dra72x_core_padconf_array);
+		iodelay = dra72_iodelay_cfg_array;
+		niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array);
 		break;
 	case DRA752_ES1_0:
 	case DRA752_ES1_1:
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index bec3b55..6db11a2 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -12,134 +12,180 @@
 
 #include <asm/arch/mux_dra7xx.h>
 
-const struct pad_conf_entry core_padconf_array_essential[] = {
-	{MMC1_CLK, (IEN | PTU | PDIS | M0)},	/* MMC1_CLK */
-	{MMC1_CMD, (IEN | PTU | PDIS | M0)},	/* MMC1_CMD */
-	{MMC1_DAT0, (IEN | PTU | PDIS | M0)},	/* MMC1_DAT0 */
-	{MMC1_DAT1, (IEN | PTU | PDIS | M0)},	/* MMC1_DAT1 */
-	{MMC1_DAT2, (IEN | PTU | PDIS | M0)},	/* MMC1_DAT2 */
-	{MMC1_DAT3, (IEN | PTU | PDIS | M0)},	/* MMC1_DAT3 */
-	{MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
-	{MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
-#if defined(CONFIG_NOR)
-	/* NOR only pin-mux */
-	{GPMC_A0  , M0 | IDIS | PDIS}, /* nor.GPMC_A[0 ] */
-	{GPMC_A1  , M0 | IDIS | PDIS}, /* nor.GPMC_A[1 ] */
-	{GPMC_A2  , M0 | IDIS | PDIS}, /* nor.GPMC_A[2 ] */
-	{GPMC_A3  , M0 | IDIS | PDIS}, /* nor.GPMC_A[3 ] */
-	{GPMC_A4  , M0 | IDIS | PDIS}, /* nor.GPMC_A[4 ] */
-	{GPMC_A5  , M0 | IDIS | PDIS}, /* nor.GPMC_A[5 ] */
-	{GPMC_A6  , M0 | IDIS | PDIS}, /* nor.GPMC_A[6 ] */
-	{GPMC_A7  , M0 | IDIS | PDIS}, /* nor.GPMC_A[7 ] */
-	{GPMC_A8  , M0 | IDIS | PDIS}, /* nor.GPMC_A[8 ] */
-	{GPMC_A9  , M0 | IDIS | PDIS}, /* nor.GPMC_A[9 ] */
-	{GPMC_A10 , M0 | IDIS | PDIS}, /* nor.GPMC_A[10] */
-	{GPMC_A11 , M0 | IDIS | PDIS}, /* nor.GPMC_A[11] */
-	{GPMC_A12 , M0 | IDIS | PDIS}, /* nor.GPMC_A[12] */
-	{GPMC_A13 , M0 | IDIS | PDIS}, /* nor.GPMC_A[13] */
-	{GPMC_A14 , M0 | IDIS | PDIS}, /* nor.GPMC_A[14] */
-	{GPMC_A15 , M0 | IDIS | PDIS}, /* nor.GPMC_A[15] */
-	{GPMC_A16 , M0 | IDIS | PDIS}, /* nor.GPMC_A[16] */
-	{GPMC_A17 , M0 | IDIS | PDIS}, /* nor.GPMC_A[17] */
-	{GPMC_A18 , M0 | IDIS | PDIS}, /* nor.GPMC_A[18] */
-	{GPMC_A19 , M0 | IDIS | PDIS}, /* nor.GPMC_A[19] */
-	{GPMC_A20 , M0 | IDIS | PDIS}, /* nor.GPMC_A[20] */
-	{GPMC_A21 , M0 | IDIS | PDIS}, /* nor.GPMC_A[21] */
-	{GPMC_A22 , M0 | IDIS | PDIS}, /* nor.GPMC_A[22] */
-	{GPMC_A23 , M0 | IDIS | PDIS}, /* nor.GPMC_A[23] */
-	{GPMC_A24 , M0 | IDIS | PDIS}, /* nor.GPMC_A[24] */
-	{GPMC_A25 , M0 | IDIS | PDIS}, /* nor.GPMC_A[25] */
-	{GPMC_A26 , M0 | IDIS | PDIS}, /* nor.GPMC_A[26] */
-#else
-	/* eMMC pinmux */
-	{GPMC_A19, (IEN | PTU | PDIS | M1)},	/* mmc2_dat4 */
-	{GPMC_A20, (IEN | PTU | PDIS | M1)},	/* mmc2_dat5 */
-	{GPMC_A21, (IEN | PTU | PDIS | M1)},	/* mmc2_dat6 */
-	{GPMC_A22, (IEN | PTU | PDIS | M1)},	/* mmc2_dat7 */
-	{GPMC_A23, (IEN | PTU | PDIS | M1)},	/* mmc2_clk */
-	{GPMC_A24, (IEN | PTU | PDIS | M1)},	/* mmc2_dat0 */
-	{GPMC_A25, (IEN | PTU | PDIS | M1)},	/* mmc2_dat1 */
-	{GPMC_A26, (IEN | PTU | PDIS | M1)},	/* mmc2_dat2 */
-	{GPMC_A27, (IEN | PTU | PDIS | M1)},	/* mmc2_dat3 */
-	{GPMC_CS1, (IEN | PTU | PDIS | M1)},	/* mmm2_cmd */
-#endif
-#if (CONFIG_CONS_INDEX == 1)
-	{UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */
-	{UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */
-	{UART1_CTSN, (IEN | PTU | PDIS | M3)},	/* UART1_CTSN */
-	{UART1_RTSN, (IEN | PTU | PDIS | M3)},	/* UART1_RTSN */
-#elif (CONFIG_CONS_INDEX == 3)
-	{UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */
-	{UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */
-#endif
-	{I2C1_SDA, (IEN | PTU | PDIS | M0)},	/* I2C1_SDA */
-	{I2C1_SCL, (IEN | PTU | PDIS | M0)},	/* I2C1_SCL */
-	{MDIO_MCLK, (PTU | PEN | M0)},		/* MDIO_MCLK  */
-	{MDIO_D, (IEN | PTU | PEN | M0)},	/* MDIO_D  */
-	{RGMII0_TXC, (PIN_OUTPUT | MANUAL_MODE | M0) },
-	{RGMII0_TXCTL, (PIN_OUTPUT | MANUAL_MODE | M0) },
-	{RGMII0_TXD3, (PIN_OUTPUT | MANUAL_MODE | M0) },
-	{RGMII0_TXD2, (PIN_OUTPUT | MANUAL_MODE | M0) },
-	{RGMII0_TXD1, (PIN_OUTPUT | MANUAL_MODE | M0) },
-	{RGMII0_TXD0, (PIN_OUTPUT | MANUAL_MODE | M0) },
-	{RGMII0_RXC, (PIN_INPUT | MANUAL_MODE | M0) },
-	{RGMII0_RXCTL, (PIN_INPUT | MANUAL_MODE | M0) },
-	{RGMII0_RXD3, (PIN_INPUT | MANUAL_MODE | M0) },
-	{RGMII0_RXD2, (PIN_INPUT | MANUAL_MODE | M0) },
-	{RGMII0_RXD1, (PIN_INPUT | MANUAL_MODE | M0) },
-	{RGMII0_RXD0, (PIN_INPUT | MANUAL_MODE | M0) },
-	{VIN2A_D12, (PIN_OUTPUT | MANUAL_MODE | M3) },
-	{VIN2A_D13, (PIN_OUTPUT | MANUAL_MODE | M3) },
-	{VIN2A_D14, (PIN_OUTPUT | MANUAL_MODE | M3) },
-	{VIN2A_D15, (PIN_OUTPUT | MANUAL_MODE | M3) },
-	{VIN2A_D16, (PIN_OUTPUT | MANUAL_MODE | M3) },
-	{VIN2A_D17, (PIN_OUTPUT | MANUAL_MODE | M3) },
-	{VIN2A_D18, (PIN_INPUT | MANUAL_MODE | M3)},
-	{VIN2A_D19, (PIN_INPUT | MANUAL_MODE | M3)},
-	{VIN2A_D20, (PIN_INPUT | MANUAL_MODE | M3)},
-	{VIN2A_D21, (PIN_INPUT | MANUAL_MODE | M3)},
-	{VIN2A_D22, (PIN_INPUT | MANUAL_MODE | M3)},
-	{VIN2A_D23, (PIN_INPUT | MANUAL_MODE | M3)},
-#if defined(CONFIG_NAND) || defined(CONFIG_NOR)
-	/* NAND / NOR pin-mux */
-	{GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0  */
-	{GPMC_AD1 , M0 | IEN | PDIS}, /* GPMC_AD1  */
-	{GPMC_AD2 , M0 | IEN | PDIS}, /* GPMC_AD2  */
-	{GPMC_AD3 , M0 | IEN | PDIS}, /* GPMC_AD3  */
-	{GPMC_AD4 , M0 | IEN | PDIS}, /* GPMC_AD4  */
-	{GPMC_AD5 , M0 | IEN | PDIS}, /* GPMC_AD5  */
-	{GPMC_AD6 , M0 | IEN | PDIS}, /* GPMC_AD6  */
-	{GPMC_AD7 , M0 | IEN | PDIS}, /* GPMC_AD7  */
-	{GPMC_AD8 , M0 | IEN | PDIS}, /* GPMC_AD8  */
-	{GPMC_AD9 , M0 | IEN | PDIS}, /* GPMC_AD9  */
-	{GPMC_AD10, M0 | IEN | PDIS}, /* GPMC_AD10 */
-	{GPMC_AD11, M0 | IEN | PDIS}, /* GPMC_AD11 */
-	{GPMC_AD12, M0 | IEN | PDIS}, /* GPMC_AD12 */
-	{GPMC_AD13, M0 | IEN | PDIS}, /* GPMC_AD13 */
-	{GPMC_AD14, M0 | IEN | PDIS}, /* GPMC_AD14 */
-	{GPMC_AD15, M0 | IEN | PDIS}, /* GPMC_AD15 */
-	{GPMC_CS0,	M0 | IDIS | PEN | PTU}, /* GPMC chip-select */
-	{GPMC_ADVN_ALE,	M0 | IDIS | PEN | PTD}, /* GPMC Addr latch */
-	{GPMC_OEN_REN,	M0 | IDIS | PEN | PTU}, /* GPMC Read enable */
-	{GPMC_WEN,	M0 | IDIS | PEN | PTU}, /* GPMC Write enable_n */
-	{GPMC_BEN0,	M0 | IDIS | PEN | PTD}, /* GPMC Byte/Column En */
-	{GPMC_WAIT0,	M0 | IEN  | PEN | PTU}, /* GPMC Wait/Ready */
-	/* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */
-#else
-	/* QSPI pin-mux */
-	{GPMC_A13, (IEN | PDIS | M1)},  /* QSPI1_RTCLK */
-	{GPMC_A14, (IEN | PDIS | M1)},  /* QSPI1_D[3] */
-	{GPMC_A15, (IEN | PDIS | M1)},  /* QSPI1_D[2] */
-	{GPMC_A16, (IEN | PDIS | M1)},  /* QSPI1_D[0] */
-	{GPMC_A17, (IEN | PDIS | M1)},  /* QSPI1_D[1] */
-	{GPMC_A18, (M1)},  /* QSPI1_SCLK */
-	{GPMC_A3, (IEN | PDIS | M1)},   /* QSPI1_CS2 */
-	{GPMC_A4, (IEN | PDIS | M1)},   /* QSPI1_CS3 */
-	{GPMC_CS2, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS0 */
-	{GPMC_CS3, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS1*/
-#endif /* CONFIG_NAND || CONFIG_NOR */
-	{USB2_DRVVBUS, (M0 | IEN | FSC) },
-	{SPI1_CS1, (PEN | IDIS | M14) },
+const struct pad_conf_entry dra72x_core_padconf_array[] = {
+	{GPMC_AD0, (M3 | PIN_INPUT)},	/* gpmc_ad0.vout3_d0 */
+	{GPMC_AD1, (M3 | PIN_INPUT)},	/* gpmc_ad1.vout3_d1 */
+	{GPMC_AD2, (M3 | PIN_INPUT)},	/* gpmc_ad2.vout3_d2 */
+	{GPMC_AD3, (M3 | PIN_INPUT)},	/* gpmc_ad3.vout3_d3 */
+	{GPMC_AD4, (M3 | PIN_INPUT)},	/* gpmc_ad4.vout3_d4 */
+	{GPMC_AD5, (M3 | PIN_INPUT)},	/* gpmc_ad5.vout3_d5 */
+	{GPMC_AD6, (M3 | PIN_INPUT)},	/* gpmc_ad6.vout3_d6 */
+	{GPMC_AD7, (M3 | PIN_INPUT)},	/* gpmc_ad7.vout3_d7 */
+	{GPMC_AD8, (M3 | PIN_INPUT)},	/* gpmc_ad8.vout3_d8 */
+	{GPMC_AD9, (M3 | PIN_INPUT)},	/* gpmc_ad9.vout3_d9 */
+	{GPMC_AD10, (M3 | PIN_INPUT)},	/* gpmc_ad10.vout3_d10 */
+	{GPMC_AD11, (M3 | PIN_INPUT)},	/* gpmc_ad11.vout3_d11 */
+	{GPMC_AD12, (M3 | PIN_INPUT)},	/* gpmc_ad12.vout3_d12 */
+	{GPMC_AD13, (M3 | PIN_INPUT)},	/* gpmc_ad13.vout3_d13 */
+	{GPMC_AD14, (M3 | PIN_INPUT)},	/* gpmc_ad14.vout3_d14 */
+	{GPMC_AD15, (M3 | PIN_INPUT)},	/* gpmc_ad15.vout3_d15 */
+	{GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a0.vout3_d16 */
+	{GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a1.vout3_d17 */
+	{GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a2.vout3_d18 */
+	{GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a3.vout3_d19 */
+	{GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a4.vout3_d20 */
+	{GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a5.vout3_d21 */
+	{GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a6.vout3_d22 */
+	{GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a7.vout3_d23 */
+	{GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a8.vout3_hsync */
+	{GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a9.vout3_vsync */
+	{GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a10.vout3_de */
+	{GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_a11.gpio2_1 */
+	{GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
+	{GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
+	{GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
+	{GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
+	{GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
+	{GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
+	{GPMC_A19, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a19.mmc2_dat4 */
+	{GPMC_A20, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a20.mmc2_dat5 */
+	{GPMC_A21, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a21.mmc2_dat6 */
+	{GPMC_A22, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a22.mmc2_dat7 */
+	{GPMC_A23, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a23.mmc2_clk */
+	{GPMC_A24, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a24.mmc2_dat0 */
+	{GPMC_A25, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a25.mmc2_dat1 */
+	{GPMC_A26, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a26.mmc2_dat2 */
+	{GPMC_A27, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a27.mmc2_dat3 */
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_cs1.mmc2_cmd */
+	{GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
+	{GPMC_CS3, (M3 | PIN_INPUT_PULLUP)},	/* gpmc_cs3.vout3_clk */
+	{VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)},	/* vin2a_clk0.vin2a_clk0 */
+	{VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)},	/* vin2a_hsync0.vin2a_hsync0 */
+	{VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)},	/* vin2a_vsync0.vin2a_vsync0 */
+	{VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)},	/* vin2a_d0.vin2a_d0 */
+	{VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)},	/* vin2a_d1.vin2a_d1 */
+	{VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)},	/* vin2a_d2.vin2a_d2 */
+	{VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)},	/* vin2a_d3.vin2a_d3 */
+	{VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)},	/* vin2a_d4.vin2a_d4 */
+	{VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)},	/* vin2a_d5.vin2a_d5 */
+	{VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)},	/* vin2a_d6.vin2a_d6 */
+	{VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)},	/* vin2a_d7.vin2a_d7 */
+	{VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)},	/* vin2a_d8.vin2a_d8 */
+	{VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)},	/* vin2a_d9.vin2a_d9 */
+	{VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)},	/* vin2a_d10.vin2a_d10 */
+	{VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)},	/* vin2a_d11.vin2a_d11 */
+	{VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_clk.vout1_clk */
+	{VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_de.vout1_de */
+	{VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_hsync.vout1_hsync */
+	{VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_vsync.vout1_vsync */
+	{VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d0.vout1_d0 */
+	{VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d1.vout1_d1 */
+	{VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d2.vout1_d2 */
+	{VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d3.vout1_d3 */
+	{VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d4.vout1_d4 */
+	{VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d5.vout1_d5 */
+	{VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d6.vout1_d6 */
+	{VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d7.vout1_d7 */
+	{VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d8.vout1_d8 */
+	{VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d9.vout1_d9 */
+	{VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d10.vout1_d10 */
+	{VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d11.vout1_d11 */
+	{VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d12.vout1_d12 */
+	{VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d13.vout1_d13 */
+	{VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d14.vout1_d14 */
+	{VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d15.vout1_d15 */
+	{VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d16.vout1_d16 */
+	{VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d17.vout1_d17 */
+	{VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d18.vout1_d18 */
+	{VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d19.vout1_d19 */
+	{VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d20.vout1_d20 */
+	{VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d21.vout1_d21 */
+	{VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d22.vout1_d22 */
+	{VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)},	/* vout1_d23.vout1_d23 */
+	{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mdio_mclk.mdio_mclk */
+	{MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mdio_d.mdio_d */
+	{RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
+	{RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
+	{RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
+	{RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
+	{RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
+	{RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
+	{VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d0.rgmii1_txc */
+	{VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d1.rgmii1_txctl */
+	{VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d2.rgmii1_txd3 */
+	{VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d3.rgmii1_txd2 */
+	{VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d4.rgmii1_txd1 */
+	{VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d5.rgmii1_txd0 */
+	{VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d6.rgmii1_rxc */
+	{VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d7.rgmii1_rxctl */
+	{VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d8.rgmii1_rxd3 */
+	{VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d9.rgmii1_rxd2 */
+	{VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d10.rgmii1_rxd1 */
+	{VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d11.rgmii1_rxd0 */
+	{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb1_drvvbus.usb1_drvvbus */
+	{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb2_drvvbus.usb2_drvvbus */
+	{GPIO6_14, (M9 | PIN_INPUT_PULLUP)},	/* gpio6_14.i2c3_sda */
+	{GPIO6_15, (M9 | PIN_INPUT_PULLUP)},	/* gpio6_15.i2c3_scl */
+	{GPIO6_16, (M14 | PIN_INPUT_PULLUP)},	/* gpio6_16.gpio6_16 */
+	{XREF_CLK1, (M5 | PIN_OUTPUT)},	/* xref_clk1.atl_clk1 */
+	{XREF_CLK2, (M5 | PIN_OUTPUT)},	/* xref_clk2.atl_clk2 */
+	{MCASP1_AXR0, (M10 | PIN_INPUT_SLEW)},	/* mcasp1_axr0.i2c5_sda */
+	{MCASP1_AXR1, (M10 | PIN_INPUT_SLEW)},	/* mcasp1_axr1.i2c5_scl */
+	{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr2.gpio5_4 */
+	{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr3.gpio5_5 */
+	{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr4.gpio5_6 */
+	{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr5.gpio5_7 */
+	{MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr6.gpio5_8 */
+	{MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr7.gpio5_9 */
+	{MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr12.mcasp7_axr0 */
+	{MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr13.mcasp7_axr1 */
+	{MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr14.mcasp7_aclkx */
+	{MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr15.mcasp7_fsx */
+	{MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_aclkr.mcasp2_aclkr */
+	{MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_aclkx.mcasp3_aclkx */
+	{MCASP3_FSX, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_fsx.mcasp3_fsx */
+	{MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_axr0.mcasp3_axr0 */
+	{MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)},	/* mcasp3_axr1.mcasp3_axr1 */
+	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
+	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_cmd.mmc1_cmd */
+	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat0.mmc1_dat0 */
+	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
+	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat2.mmc1_dat2 */
+	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
+	{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)},	/* mmc1_sdcd.gpio6_27 */
+	{MMC1_SDWP, (M14 | PIN_INPUT_SLEW)},	/* mmc1_sdwp.gpio6_28 */
+	{GPIO6_11, (M14 | PIN_INPUT_PULLUP)},	/* gpio6_11.gpio6_11 */
+	{SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_sclk.spi1_sclk */
+	{SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_d1.spi1_d1 */
+	{SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_d0.spi1_d0 */
+	{SPI1_CS0, (M0 | PIN_INPUT_PULLUP)},	/* spi1_cs0.spi1_cs0 */
+	{SPI1_CS1, (M14 | PIN_OUTPUT)},	/* spi1_cs1.gpio7_11 */
+	{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_cs2.gpio7_12 */
+	{SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi1_cs3.hdmi1_cec */
+	{SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)},	/* spi2_sclk.uart3_rxd */
+	{SPI2_D1, (M1 | PIN_INPUT_SLEW)},	/* spi2_d1.uart3_txd */
+	{SPI2_D0, (M1 | PIN_INPUT_SLEW)},	/* spi2_d0.uart3_ctsn */
+	{SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi2_cs0.uart3_rtsn */
+	{DCAN1_TX, (M15 | PULL_UP)},	/* dcan1_tx.safe for dcan1_tx */
+	{DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_rx.gpio1_15 */
+	{UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* uart1_rxd.uart1_rxd */
+	{UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* uart1_txd.uart1_txd */
+	{UART1_CTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart1_ctsn.mmc4_clk */
+	{UART1_RTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart1_rtsn.mmc4_cmd */
+	{UART2_RXD, (M3 | PIN_INPUT_PULLUP)},	/* uart2_rxd.mmc4_dat0 */
+	{UART2_TXD, (M3 | PIN_INPUT_PULLUP)},	/* uart2_txd.mmc4_dat1 */
+	{UART2_CTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart2_ctsn.mmc4_dat2 */
+	{UART2_RTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart2_rtsn.mmc4_dat3 */
+	{I2C2_SDA, (M1 | PIN_INPUT_PULLUP)},	/* i2c2_sda.hdmi1_ddc_scl */
+	{I2C2_SCL, (M1 | PIN_INPUT_PULLUP)},	/* i2c2_scl.hdmi1_ddc_sda */
+	{WAKEUP0, (M15 | PULL_UP)},	/* Wakeup0.safe for dcan1_rx */
+	{WAKEUP3, (M1 | PULL_ENA | PULL_UP)},	/* Wakeup3.sys_nirq1 */
 };
 
 const struct pad_conf_entry early_padconf[] = {
@@ -155,7 +201,7 @@
 };
 
 #ifdef CONFIG_IODELAY_RECALIBRATION
-const struct iodelay_cfg_entry iodelay_cfg_array[] = {
+const struct iodelay_cfg_entry dra72_iodelay_cfg_array[] = {
 	{0x6F0, 359, 0}, /* RGMMI0_RXC_IN */
 	{0x6FC, 129, 1896}, /* RGMMI0_RXCTL_IN */
 	{0x708, 80, 1391}, /* RGMMI0_RXD0_IN */
@@ -181,6 +227,14 @@
 	{0xA94, 1260, 0}, /* CFG_VIN2A_D15_OUT */
 	{0xAA0, 1400, 0}, /* CFG_VIN2A_D16_OUT */
 	{0xAAC, 1290, 0}, /* CFG_VIN2A_D17_OUT */
+	{0x144, 0, 0}, /* CFG_GPMC_A13_IN */
+	{0x150, 2062, 2277}, /* CFG_GPMC_A14_IN */
+	{0x15C, 1960, 2289}, /* CFG_GPMC_A15_IN */
+	{0x168, 2058, 2386}, /* CFG_GPMC_A16_IN */
+	{0x170, 0, 0 },	/* CFG_GPMC_A16_OUT */
+	{0x174, 2062, 2350}, /* CFG_GPMC_A17_IN */
+	{0x188, 0, 0}, /* CFG_GPMC_A18_OUT */
+	{0x374, 121, 0}, /* CFG_GPMC_CS2_OUT */
 };
 #endif
 
@@ -345,7 +399,7 @@
 	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
 	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat2.mmc1_dat2 */
 	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
-	{MMC1_SDCD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mmc1_sdcd.mmc1_sdcd */
+	{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)},	/* mmc1_sdcd.gpio6_27 */
 	{MMC1_SDWP, (M14 | PIN_INPUT_SLEW)},	/* mmc1_sdwp.gpio6_28 */
 	{GPIO6_11, (M14 | PIN_INPUT_PULLUP)},	/* gpio6_11.gpio6_11 */
 	{SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_sclk.spi1_sclk */
diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile
index d60496e..7ef2d2b 100644
--- a/board/ti/ks2_evm/Makefile
+++ b/board/ti/ks2_evm/Makefile
@@ -1,17 +1,17 @@
 #
 # KS2-EVM: board Makefile
-# (C) Copyright 2012-2014
+# (C) Copyright 2012-2015
 #     Texas Instruments Incorporated, <www.ti.com>
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
 obj-y += board.o
-obj-y += ddr3_cfg.o
 obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
 obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
 obj-$(CONFIG_K2E_EVM) += board_k2e.o
 obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o
 obj-$(CONFIG_K2L_EVM) += board_k2l.o
 obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o
+obj-$(CONFIG_K2L_EVM) += ddr3_cfg.o
 obj-$(CONFIG_K2G_EVM) += board_k2g.o
 obj-$(CONFIG_K2G_EVM) += ddr3_k2g.o
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 7d1709c..ca668a7 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -146,9 +146,7 @@
 
 	ddr3a_size = 0;
 	if (lpae) {
-		env = getenv("ddr3a_size");
-		if (env)
-			ddr3a_size = simple_strtol(env, NULL, 10);
+		ddr3a_size = ddr3_get_size();
 		if ((ddr3a_size != 8) && (ddr3a_size != 4))
 			ddr3a_size = 0;
 	}
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
index f58f623..cbb3077 100644
--- a/board/ti/ks2_evm/board_k2e.c
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -61,7 +61,7 @@
 
 	switch (pll) {
 	case MAIN_PLL:
-		speed = get_max_dev_speed();
+		speed = get_max_dev_speed(speeds);
 		data = &core_pll_config[speed];
 		break;
 	case PASS_PLL:
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index cdeb056..b62c412 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -23,22 +23,64 @@
 	[uart_clk]	=	SYS_CLK,
 };
 
-static struct pll_init_data main_pll_config = {MAIN_PLL, 100, 1, 4};
-static struct pll_init_data tetris_pll_config = {TETRIS_PLL, 100, 1, 4};
+static int arm_speeds[DEVSPEED_NUMSPDS] = {
+	SPD400,
+	SPD600,
+	SPD800,
+	SPD900,
+	SPD1000,
+	SPD900,
+	SPD800,
+	SPD600,
+	SPD400,
+	SPD200,
+};
+
+static int dev_speeds[DEVSPEED_NUMSPDS] = {
+	SPD600,
+	SPD800,
+	SPD900,
+	SPD1000,
+	SPD900,
+	SPD800,
+	SPD600,
+	SPD400,
+};
+
+static struct pll_init_data main_pll_config[NUM_SPDS] = {
+	[SPD400]	= {MAIN_PLL, 100, 3, 2},
+	[SPD600]	= {MAIN_PLL, 300, 6, 2},
+	[SPD800]	= {MAIN_PLL, 200, 3, 2},
+	[SPD900] =	{TETRIS_PLL, 75, 1, 2},
+	[SPD1000] =	{TETRIS_PLL, 250, 3, 2},
+};
+
+static struct pll_init_data tetris_pll_config[NUM_SPDS] = {
+	[SPD200] =	{TETRIS_PLL, 250, 3, 10},
+	[SPD400] =	{TETRIS_PLL, 100, 1, 6},
+	[SPD600] =	{TETRIS_PLL, 100, 1, 4},
+	[SPD800] =	{TETRIS_PLL, 400, 3, 4},
+	[SPD900] =	{TETRIS_PLL, 75, 1, 2},
+	[SPD1000] =	{TETRIS_PLL, 250, 3, 2},
+};
+
 static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
 static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
 static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10};
 
 struct pll_init_data *get_pll_init_data(int pll)
 {
+	int speed;
 	struct pll_init_data *data = NULL;
 
 	switch (pll) {
 	case MAIN_PLL:
-		data = &main_pll_config;
+		speed = get_max_dev_speed(dev_speeds);
+		data = &main_pll_config[speed];
 		break;
 	case TETRIS_PLL:
-		data = &tetris_pll_config;
+		speed = get_max_arm_speed(arm_speeds);
+		data = &tetris_pll_config[speed];
 		break;
 	case NSS_PLL:
 		data = &nss_pll_config;
diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c
index 0bd6b86..e217bea 100644
--- a/board/ti/ks2_evm/board_k2hk.c
+++ b/board/ti/ks2_evm/board_k2hk.c
@@ -51,11 +51,11 @@
 
 	switch (pll) {
 	case MAIN_PLL:
-		speed = get_max_dev_speed();
+		speed = get_max_dev_speed(speeds);
 		data = &core_pll_config[speed];
 		break;
 	case TETRIS_PLL:
-		speed = get_max_arm_speed();
+		speed = get_max_arm_speed(speeds);
 		data = &tetris_pll_config[speed];
 		break;
 	case PASS_PLL:
diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c
index d750ad3..2a2e005 100644
--- a/board/ti/ks2_evm/board_k2l.c
+++ b/board/ti/ks2_evm/board_k2l.c
@@ -50,11 +50,11 @@
 
 	switch (pll) {
 	case MAIN_PLL:
-		speed = get_max_dev_speed();
+		speed = get_max_dev_speed(speeds);
 		data = &core_pll_config[speed];
 		break;
 	case TETRIS_PLL:
-		speed = get_max_arm_speed();
+		speed = get_max_arm_speed(speeds);
 		data = &tetris_pll_config[speed];
 		break;
 	case PASS_PLL:
diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c
index ab44676..b6b59a4 100644
--- a/board/ti/ks2_evm/ddr3_cfg.c
+++ b/board/ti/ks2_evm/ddr3_cfg.c
@@ -9,129 +9,8 @@
 
 #include <common.h>
 
-#include <i2c.h>
 #include <asm/arch/ddr3.h>
-#include <asm/arch/hardware.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* DDR3 PHY configuration data with 1600M rate, 8GB size */
-struct ddr3_phy_config ddr3phy_1600_8g = {
-	.pllcr          = 0x0001C000ul,
-	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0           = 0x42C21590ul,
-	.ptr1           = 0xD05612C0ul,
-	.ptr2           = 0, /* not set in gel */
-	.ptr3           = 0x0D861A80ul,
-	.ptr4           = 0x0C827100ul,
-	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
-	.dcr_val        = ((1 << 10)),
-	.dtpr0          = 0xA19DBB66ul,
-	.dtpr1          = 0x32868300ul,
-	.dtpr2          = 0x50035200ul,
-	.mr0            = 0x00001C70ul,
-	.mr1            = 0x00000006ul,
-	.mr2            = 0x00000018ul,
-	.dtcr           = 0x730035C7ul,
-	.pgcr2          = 0x00F07A12ul,
-	.zq0cr1         = 0x0000005Dul,
-	.zq1cr1         = 0x0000005Bul,
-	.zq2cr1         = 0x0000005Bul,
-	.pir_v1         = 0x00000033ul,
-	.pir_v2         = 0x0000FF81ul,
-};
-
-/* DDR3 EMIF configuration data with 1600M rate, 8GB size */
-struct ddr3_emif_config ddr3_1600_8g = {
-	.sdcfg          = 0x6200CE6Aul,
-	.sdtim1         = 0x16709C55ul,
-	.sdtim2         = 0x00001D4Aul,
-	.sdtim3         = 0x435DFF54ul,
-	.sdtim4         = 0x553F0CFFul,
-	.zqcfg          = 0xF0073200ul,
-	.sdrfc          = 0x00001869ul,
-};
-
-#ifdef CONFIG_K2HK_EVM
-/* DDR3 PHY configuration data with 1333M rate, and 2GB size */
-struct ddr3_phy_config ddr3phy_1333_2g = {
-	.pllcr          = 0x0005C000ul,
-	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0           = 0x42C21590ul,
-	.ptr1           = 0xD05612C0ul,
-	.ptr2           = 0, /* not set in gel */
-	.ptr3           = 0x0B4515C2ul,
-	.ptr4           = 0x0A6E08B4ul,
-	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
-	.dcr_val        = ((1 << 10)),
-	.dtpr0          = 0x8558AA55ul,
-	.dtpr1          = 0x32857280ul,
-	.dtpr2          = 0x5002C200ul,
-	.mr0            = 0x00001A60ul,
-	.mr1            = 0x00000006ul,
-	.mr2            = 0x00000010ul,
-	.dtcr           = 0x710035C7ul,
-	.pgcr2          = 0x00F065B8ul,
-	.zq0cr1         = 0x0000005Dul,
-	.zq1cr1         = 0x0000005Bul,
-	.zq2cr1         = 0x0000005Bul,
-	.pir_v1         = 0x00000033ul,
-	.pir_v2         = 0x0000FF81ul,
-};
-
-/* DDR3 EMIF configuration data with 1333M rate, and 2GB size */
-struct ddr3_emif_config ddr3_1333_2g = {
-	.sdcfg          = 0x62008C62ul,
-	.sdtim1         = 0x125C8044ul,
-	.sdtim2         = 0x00001D29ul,
-	.sdtim3         = 0x32CDFF43ul,
-	.sdtim4         = 0x543F0ADFul,
-	.zqcfg          = 0x70073200ul,
-	.sdrfc          = 0x00001457ul,
-};
-#endif
-
-#ifdef CONFIG_K2E_EVM
-/* DDR3 PHY configuration data with 1600M rate, and 4GB size  */
-struct ddr3_phy_config ddr3phy_1600_4g = {
-	.pllcr          = 0x0001C000ul,
-	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0           = 0x42C21590ul,
-	.ptr1           = 0xD05612C0ul,
-	.ptr2           = 0, /* not set in gel */
-	.ptr3           = 0x08861A80ul,
-	.ptr4           = 0x0C827100ul,
-	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
-	.dcr_val        = ((1 << 10)),
-	.dtpr0          = 0x9D9CBB66ul,
-	.dtpr1          = 0x12840300ul,
-	.dtpr2          = 0x5002D200ul,
-	.mr0            = 0x00001C70ul,
-	.mr1            = 0x00000006ul,
-	.mr2            = 0x00000018ul,
-	.dtcr           = 0x710035C7ul,
-	.pgcr2          = 0x00F07A12ul,
-	.zq0cr1         = 0x0001005Dul,
-	.zq1cr1         = 0x0001005Bul,
-	.zq2cr1         = 0x0001005Bul,
-	.pir_v1         = 0x00000033ul,
-	.pir_v2         = 0x0000FF81ul,
-};
-
-/* DDR3 EMIF configuration data with 1600M rate, and 4GB size  */
-struct ddr3_emif_config ddr3_1600_4g = {
-	.sdcfg          = 0x6200CE62ul,
-	.sdtim1         = 0x166C9855ul,
-	.sdtim2         = 0x00001D4Aul,
-	.sdtim3         = 0x421DFF53ul,
-	.sdtim4         = 0x543F07FFul,
-	.zqcfg          = 0x70073200ul,
-	.sdrfc          = 0x00001869ul,
-};
-#endif
+#include "ddr3_cfg.h"
 
 struct ddr3_phy_config ddr3phy_1600_2g = {
 	.pllcr          = 0x0001C000ul,
@@ -168,39 +47,3 @@
 	.zqcfg          = 0x70073200ul,
 	.sdrfc          = 0x00001869ul,
 };
-
-int ddr3_get_dimm_params(char *dimm_name)
-{
-	int ret;
-	int old_bus;
-	u8 spd_params[256];
-
-	i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
-
-	old_bus = i2c_get_bus_num();
-	i2c_set_bus_num(1);
-
-	ret = i2c_read(0x53, 0, 1, spd_params, 256);
-
-	i2c_set_bus_num(old_bus);
-
-	dimm_name[0] = '\0';
-
-	if (ret) {
-		puts("Cannot read DIMM params\n");
-		return 1;
-	}
-
-	/*
-	 * We need to convert spd data to dimm parameters
-	 * and to DDR3 EMIF and PHY regirsters values.
-	 * For now we just return DIMM type string value.
-	 * Caller may use this value to choose appropriate
-	 * a pre-set DDR3 configuration
-	 */
-
-	strncpy(dimm_name, (char *)&spd_params[0x80], 18);
-	dimm_name[18] = '\0';
-
-	return 0;
-}
diff --git a/board/ti/ks2_evm/ddr3_cfg.h b/board/ti/ks2_evm/ddr3_cfg.h
index 5bd786c..f95edde 100644
--- a/board/ti/ks2_evm/ddr3_cfg.h
+++ b/board/ti/ks2_evm/ddr3_cfg.h
@@ -10,18 +10,11 @@
 #ifndef __DDR3_CFG_H
 #define __DDR3_CFG_H
 
-extern struct ddr3_phy_config ddr3phy_1600_8g;
-extern struct ddr3_emif_config ddr3_1600_8g;
-
-extern struct ddr3_phy_config ddr3phy_1333_2g;
-extern struct ddr3_emif_config ddr3_1333_2g;
-
-extern struct ddr3_phy_config ddr3phy_1600_4g;
-extern struct ddr3_emif_config ddr3_1600_4g;
+#include <asm/arch/ddr3.h>
 
 extern struct ddr3_phy_config ddr3phy_1600_2g;
 extern struct ddr3_emif_config ddr3_1600_2g;
 
-int ddr3_get_dimm_params(char *dimm_name);
+int ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb *spd_cb);
 
 #endif /* __DDR3_CFG_H */
diff --git a/board/ti/ks2_evm/ddr3_k2e.c b/board/ti/ks2_evm/ddr3_k2e.c
index 35ffb42..e82aa66 100644
--- a/board/ti/ks2_evm/ddr3_k2e.c
+++ b/board/ti/ks2_evm/ddr3_k2e.c
@@ -1,7 +1,7 @@
 /*
  * Keystone2: DDR3 initialization
  *
- * (C) Copyright 2014
+ * (C) Copyright 2014-2015
  *     Texas Instruments Incorporated, <www.ti.com>
  *
  * SPDX-License-Identifier:     GPL-2.0+
@@ -12,42 +12,37 @@
 #include <asm/arch/ddr3.h>
 
 static struct pll_init_data ddr3_400 = DDR3_PLL_400;
+static struct pll_init_data ddr3_333 = DDR3_PLL_333;
 
 u32 ddr3_init(void)
 {
-	u32 ddr3_size;
-	char dimm_name[32];
+	struct ddr3_spd_cb spd_cb;
 
-	if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1))
-		init_pll(&ddr3_400);
+	if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
+		printf("Sorry, I don't know how to configure DDR3A.\n"
+		       "Bye :(\n");
+		for (;;)
+			;
+	}
 
-	ddr3_get_dimm_params(dimm_name);
+	printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
 
-	printf("Detected SO-DIMM [%s]\n", dimm_name);
+	printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
+	if (spd_cb.ddrspdclock == 1600)
+		init_pll(&ddr3_400);
+	else
+		init_pll(&ddr3_333);
 
 	/* Reset DDR3 PHY after PLL enabled */
 	ddr3_reset_ddrphy();
 
-	if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
-		/* 8G SO-DIMM */
-		ddr3_size = 8;
-		printf("DRAM: 8 GiB\n");
-		ddr3phy_1600_8g.zq0cr1 |= 0x10000;
-		ddr3phy_1600_8g.zq1cr1 |= 0x10000;
-		ddr3phy_1600_8g.zq2cr1 |= 0x10000;
-		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
-		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g);
-	} else if (!strcmp(dimm_name, "18KSF51272HZ-1G6K2")) {
-		/* 4G SO-DIMM */
-		ddr3_size = 4;
-		printf("DRAM: 4 GiB\n");
-		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g);
-		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g);
-	} else {
-		printf("Unknown SO-DIMM. Cannot configure DDR3\n");
-		while (1)
-			;
-	}
+	spd_cb.phy_cfg.zq0cr1 |= 0x10000;
+	spd_cb.phy_cfg.zq1cr1 |= 0x10000;
+	spd_cb.phy_cfg.zq2cr1 |= 0x10000;
+	ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
+	ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
+
+	printf("DRAM: %d GiB\n", spd_cb.ddr_size_gbyte);
 
-	return ddr3_size;
+	return (u32)spd_cb.ddr_size_gbyte;
 }
diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c
index b36eb27..f848422 100644
--- a/board/ti/ks2_evm/ddr3_k2hk.c
+++ b/board/ti/ks2_evm/ddr3_k2hk.c
@@ -17,77 +17,48 @@
 
 u32 ddr3_init(void)
 {
-	char dimm_name[32];
 	u32 ddr3_size;
+	struct ddr3_spd_cb spd_cb;
 
-	ddr3_get_dimm_params(dimm_name);
+	if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
+		printf("Sorry, I don't know how to configure DDR3A.\n"
+		       "Bye :(\n");
+		for (;;)
+			;
+	}
 
-	printf("Detected SO-DIMM [%s]\n", dimm_name);
+	printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
 
-	if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
-		init_pll(&ddr3a_400);
-		if (cpu_revision() > 0) {
-			if (cpu_revision() > 1) {
-				/* PG 2.0 */
-				/* Reset DDR3A PHY after PLL enabled */
-				ddr3_reset_ddrphy();
-				ddr3phy_1600_8g.zq0cr1 |= 0x10000;
-				ddr3phy_1600_8g.zq1cr1 |= 0x10000;
-				ddr3phy_1600_8g.zq2cr1 |= 0x10000;
-				ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
-						 &ddr3phy_1600_8g);
-			} else {
-				/* PG 1.1 */
-				ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
-						 &ddr3phy_1600_8g);
-			}
+	if ((cpu_revision() > 1) ||
+	    (__raw_readl(KS2_RSTCTRL_RSTYPE) & 0x1)) {
+		printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
+		if (spd_cb.ddrspdclock == 1600)
+			init_pll(&ddr3a_400);
+		else
+			init_pll(&ddr3a_333);
+	}
 
-			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
-					  &ddr3_1600_8g);
-			printf("DRAM:  Capacity 8 GiB (includes reported below)\n");
-			ddr3_size = 8;
-		} else {
-			ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
-			ddr3_1600_8g.sdcfg |= 0x1000;
-			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
-					  &ddr3_1600_8g);
-			printf("DRAM:  Capacity 4 GiB (includes reported below)\n");
-			ddr3_size = 4;
+	if (cpu_revision() > 0) {
+		if (cpu_revision() > 1) {
+			/* PG 2.0 */
+			/* Reset DDR3A PHY after PLL enabled */
+			ddr3_reset_ddrphy();
+			spd_cb.phy_cfg.zq0cr1 |= 0x10000;
+			spd_cb.phy_cfg.zq1cr1 |= 0x10000;
+			spd_cb.phy_cfg.zq2cr1 |= 0x10000;
 		}
-	} else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
-		init_pll(&ddr3a_333);
-		if (cpu_revision() > 0) {
-			if (cpu_revision() > 1) {
-				/* PG 2.0 */
-				/* Reset DDR3A PHY after PLL enabled */
-				ddr3_reset_ddrphy();
-				ddr3phy_1333_2g.zq0cr1 |= 0x10000;
-				ddr3phy_1333_2g.zq1cr1 |= 0x10000;
-				ddr3phy_1333_2g.zq2cr1 |= 0x10000;
-				ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
-						 &ddr3phy_1333_2g);
-			} else {
-				/* PG 1.1 */
-				ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
-						 &ddr3phy_1333_2g);
-			}
-			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
-					  &ddr3_1333_2g);
-			ddr3_size = 2;
-			printf("DRAM:  2 GiB");
-		} else {
-			ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
-			ddr3_1333_2g.sdcfg |= 0x1000;
-			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
-					  &ddr3_1333_2g);
-			ddr3_size = 1;
-			printf("DRAM:  1 GiB");
-		}
+		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
+
+		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
+
+		ddr3_size = spd_cb.ddr_size_gbyte;
 	} else {
-		printf("Unknown SO-DIMM. Cannot configure DDR3\n");
-		while (1)
-			;
+		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
+		spd_cb.emif_cfg.sdcfg |= 0x1000;
+		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
+		ddr3_size = spd_cb.ddr_size_gbyte / 2;
 	}
+	printf("DRAM: %d GiB (includes reported below)\n", ddr3_size);
 
 	/* Apply the workaround for PG 1.0 and 1.1 Silicons */
 	if (cpu_revision() <= 1)
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index 853f196..50da410 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -198,7 +198,7 @@
 	return 0;
 }
 
-void set_muxconf_regs_essential(void)
+void set_muxconf_regs(void)
 {
 	do_set_mux((*ctrl)->control_padconf_core_base,
 		   core_padconf_array_essential,
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index eb9ce63..13b5daf 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -11,6 +11,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
 #include <asm/gpio.h>
+#include <twl6030.h>
 
 #include "panda_mux_data.h"
 
@@ -267,7 +268,7 @@
 	return 0;
 }
 
-void set_muxconf_regs_essential(void)
+void set_muxconf_regs(void)
 {
 	do_set_mux((*ctrl)->control_padconf_core_base,
 		   core_padconf_array_essential,
@@ -291,6 +292,11 @@
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
 }
+
+void board_mmc_power_init(void)
+{
+	twl6030_power_mmc_init(0);
+}
 #endif
 
 #ifdef CONFIG_USB_EHCI
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
index 1e9ef9e..6037cdd 100644
--- a/board/ti/sdp4430/sdp.c
+++ b/board/ti/sdp4430/sdp.c
@@ -53,7 +53,7 @@
 	return 0;
 }
 
-void set_muxconf_regs_essential(void)
+void set_muxconf_regs(void)
 {
 	do_set_mux((*ctrl)->control_padconf_core_base,
 		   core_padconf_array_essential,
@@ -80,6 +80,12 @@
 	omap_mmc_init(1, 0, 0, -1, -1);
 	return 0;
 }
+
+void board_mmc_power_init(void)
+{
+	twl6030_power_mmc_init(0);
+	twl6030_power_mmc_init(1);
+}
 #endif
 
 /*
diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
index 1a447c7..965252f 100644
--- a/board/timll/devkit8000/devkit8000.c
+++ b/board/timll/devkit8000/devkit8000.c
@@ -46,9 +46,9 @@
 };
 
 static const struct ns16550_platdata devkit8000_serial = {
-	OMAP34XX_UART3,
-	2,
-	V_NS16550_CLK
+	.base = OMAP34XX_UART3,
+	.reg_shift = 2,
+	.clock = V_NS16550_CLK
 };
 
 U_BOOT_DEVICE(devkit8000_uart) = {
diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c
index ac44e32..27056e1 100644
--- a/board/vscom/baltos/board.c
+++ b/board/vscom/baltos/board.c
@@ -10,6 +10,7 @@
 
 #include <common.h>
 #include <errno.h>
+#include <libfdt.h>
 #include <spl.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
diff --git a/board/work-microwave/work_92105/Makefile b/board/work-microwave/work_92105/Makefile
index ba31c8e..e26c673 100644
--- a/board/work-microwave/work_92105/Makefile
+++ b/board/work-microwave/work_92105/Makefile
@@ -5,6 +5,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y	:= work_92105.o work_92105_display.o
-
-obj-$(CONFIG_SPL_BUILD) += work_92105_spl.o
+ifdef CONFIG_SPL_BUILD
+obj-y	+= work_92105_spl.o
+else
+obj-y	+= work_92105.o work_92105_display.o
+endif
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 2ed0263..7cdff04 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -148,6 +148,13 @@
 	help
 	  Boot an application image from the memory.
 
+config CMD_BOOTEFI
+	bool "bootefi"
+	depends on EFI_LOADER
+	default y
+	help
+	  Boot an EFI image from memory.
+
 config CMD_ELF
 	bool "bootelf, bootvx"
 	default y
diff --git a/cmd/Makefile b/cmd/Makefile
index 03f7e0a..7604621 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -21,6 +21,7 @@
 obj-$(CONFIG_CMD_BDI) += bdinfo.o
 obj-$(CONFIG_CMD_BEDBUG) += bedbug.o
 obj-$(CONFIG_CMD_BMP) += bmp.o
+obj-$(CONFIG_CMD_BOOTEFI) += bootefi.o
 obj-$(CONFIG_CMD_BOOTMENU) += bootmenu.o
 obj-$(CONFIG_CMD_BOOTLDR) += bootldr.o
 obj-$(CONFIG_CMD_BOOTSTAGE) += bootstage.o
diff --git a/cmd/bmp.c b/cmd/bmp.c
index 01b3d39..fb6fe3f 100644
--- a/cmd/bmp.c
+++ b/cmd/bmp.c
@@ -246,18 +246,14 @@
 	addr = map_to_sysmem(bmp);
 
 #ifdef CONFIG_DM_VIDEO
-	ret = uclass_first_device(UCLASS_VIDEO, &dev);
+	ret = uclass_first_device_err(UCLASS_VIDEO, &dev);
 	if (!ret) {
-		if (!dev)
-			ret = -ENODEV;
-		if (!ret) {
-			bool align = false;
+		bool align = false;
 
 # ifdef CONFIG_SPLASH_SCREEN_ALIGN
-			align = true;
+		align = true;
 # endif /* CONFIG_SPLASH_SCREEN_ALIGN */
-			ret = video_bmp_display(dev, addr, x, y, align);
-		}
+		ret = video_bmp_display(dev, addr, x, y, align);
 	}
 #elif defined(CONFIG_LCD)
 	ret = lcd_display_bitmap(addr, x, y);
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
new file mode 100644
index 0000000..2f0b90a
--- /dev/null
+++ b/cmd/bootefi.c
@@ -0,0 +1,206 @@
+/*
+ *  EFI application loader
+ *
+ *  Copyright (c) 2016 Alexander Graf
+ *
+ *  SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <efi_loader.h>
+#include <errno.h>
+#include <libfdt.h>
+#include <libfdt_env.h>
+
+/*
+ * When booting using the "bootefi" command, we don't know which
+ * physical device the file came from. So we create a pseudo-device
+ * called "bootefi" with the device path /bootefi.
+ *
+ * In addition to the originating device we also declare the file path
+ * of "bootefi" based loads to be /bootefi.
+ */
+static struct efi_device_path_file_path bootefi_image_path[] = {
+	{
+		.dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE,
+		.dp.sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH,
+		.dp.length = sizeof(bootefi_image_path[0]),
+		.str = { 'b','o','o','t','e','f','i' },
+	}, {
+		.dp.type = DEVICE_PATH_TYPE_END,
+		.dp.sub_type = DEVICE_PATH_SUB_TYPE_END,
+		.dp.length = sizeof(bootefi_image_path[0]),
+	}
+};
+
+static efi_status_t bootefi_open_dp(void *handle, efi_guid_t *protocol,
+			void **protocol_interface, void *agent_handle,
+			void *controller_handle, uint32_t attributes)
+{
+	*protocol_interface = bootefi_image_path;
+	return EFI_SUCCESS;
+}
+
+/* The EFI loaded_image interface for the image executed via "bootefi" */
+static struct efi_loaded_image loaded_image_info = {
+	.device_handle = bootefi_image_path,
+	.file_path = bootefi_image_path,
+};
+
+/* The EFI object struct for the image executed via "bootefi" */
+static struct efi_object loaded_image_info_obj = {
+	.handle = &loaded_image_info,
+	.protocols = {
+		{
+			/*
+			 * When asking for the loaded_image interface, just
+			 * return handle which points to loaded_image_info
+			 */
+			.guid = &efi_guid_loaded_image,
+			.open = &efi_return_handle,
+		},
+		{
+			/*
+			 * When asking for the device path interface, return
+			 * bootefi_image_path
+			 */
+			.guid = &efi_guid_device_path,
+			.open = &bootefi_open_dp,
+		},
+	},
+};
+
+/* The EFI object struct for the device the "bootefi" image was loaded from */
+static struct efi_object bootefi_device_obj = {
+	.handle = bootefi_image_path,
+	.protocols = {
+		{
+			/* When asking for the device path interface, return
+			 * bootefi_image_path */
+			.guid = &efi_guid_device_path,
+			.open = &bootefi_open_dp,
+		}
+	},
+};
+
+/*
+ * Load an EFI payload into a newly allocated piece of memory, register all
+ * EFI objects it would want to access and jump to it.
+ */
+static unsigned long do_bootefi_exec(void *efi)
+{
+	ulong (*entry)(void *image_handle, struct efi_system_table *st);
+	ulong fdt_pages, fdt_size, fdt_start, fdt_end;
+	bootm_headers_t img = { 0 };
+
+	/*
+	 * gd lives in a fixed register which may get clobbered while we execute
+	 * the payload. So save it here and restore it on every callback entry
+	 */
+	efi_save_gd();
+
+	/* Update system table to point to our currently loaded FDT */
+
+	if (working_fdt) {
+		/* Prepare fdt for payload */
+		if (image_setup_libfdt(&img, working_fdt, 0, NULL)) {
+			printf("ERROR: Failed to process device tree\n");
+			return -EINVAL;
+		}
+
+		/* Link to it in the efi tables */
+		systab.tables[0].guid = EFI_FDT_GUID;
+		systab.tables[0].table = working_fdt;
+		systab.nr_tables = 1;
+
+		/* And reserve the space in the memory map */
+		fdt_start = ((ulong)working_fdt) & ~EFI_PAGE_MASK;
+		fdt_end = ((ulong)working_fdt) + fdt_totalsize(working_fdt);
+		fdt_size = (fdt_end - fdt_start) + EFI_PAGE_MASK;
+		fdt_pages = fdt_size >> EFI_PAGE_SHIFT;
+		/* Give a bootloader the chance to modify the device tree */
+		fdt_pages += 2;
+		efi_add_memory_map(fdt_start, fdt_pages,
+				   EFI_BOOT_SERVICES_DATA, true);
+
+	} else {
+		printf("WARNING: No device tree loaded, expect boot to fail\n");
+		systab.nr_tables = 0;
+	}
+
+	/* Load the EFI payload */
+	entry = efi_load_pe(efi, &loaded_image_info);
+	if (!entry)
+		return -ENOENT;
+
+	/* Initialize and populate EFI object list */
+	INIT_LIST_HEAD(&efi_obj_list);
+	list_add_tail(&loaded_image_info_obj.link, &efi_obj_list);
+	list_add_tail(&bootefi_device_obj.link, &efi_obj_list);
+#ifdef CONFIG_PARTITIONS
+	efi_disk_register();
+#endif
+
+	/* Call our payload! */
+#ifdef DEBUG_EFI
+	printf("%s:%d Jumping to 0x%lx\n", __func__, __LINE__, (long)entry);
+#endif
+	return entry(&loaded_image_info, &systab);
+}
+
+
+/* Interpreter command to boot an arbitrary EFI image from memory */
+static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	char *saddr;
+	unsigned long addr;
+	int r = 0;
+
+	if (argc < 2)
+		return 1;
+	saddr = argv[1];
+
+	addr = simple_strtoul(saddr, NULL, 16);
+
+	printf("## Starting EFI application at 0x%08lx ...\n", addr);
+	r = do_bootefi_exec((void *)addr);
+	printf("## Application terminated, r = %d\n", r);
+
+	if (r != 0)
+		r = 1;
+
+	return r;
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char bootefi_help_text[] =
+	"<image address>\n"
+	"  - boot EFI payload stored at address <image address>\n"
+	"\n"
+	"Since most EFI payloads want to have a device tree provided, please\n"
+	"make sure you load a device tree using the fdt addr command before\n"
+	"executing bootefi.\n";
+#endif
+
+U_BOOT_CMD(
+	bootefi, 2, 0, do_bootefi,
+	"Boots an EFI payload from memory\n",
+	bootefi_help_text
+);
+
+void efi_set_bootdev(const char *dev, const char *devnr)
+{
+	char devname[16] = { 0 }; /* dp->str is u16[16] long */
+	char *colon;
+
+	/* Assemble the condensed device name we use in efi_disk.c */
+	snprintf(devname, sizeof(devname), "%s%s", dev, devnr);
+	colon = strchr(devname, ':');
+	if (colon)
+		*colon = '\0';
+
+	/* Patch the bootefi_image_path to the target device */
+	memset(bootefi_image_path[0].str, 0, sizeof(bootefi_image_path[0].str));
+	ascii2unicode(bootefi_image_path[0].str, devname);
+}
diff --git a/cmd/cbfs.c b/cmd/cbfs.c
index 35d8a7a..779e9c0 100644
--- a/cmd/cbfs.c
+++ b/cmd/cbfs.c
@@ -103,7 +103,7 @@
 	printf("     size              type  name\n");
 	printf("------------------------------------------\n");
 	while (file) {
-		u32 type = file_cbfs_type(file);
+		int type = file_cbfs_type(file);
 		char *type_name = NULL;
 		const char *filename = file_cbfs_name(file);
 
@@ -140,7 +140,8 @@
 		case CBFS_COMPONENT_CMOS_LAYOUT:
 			type_name = "cmos layout";
 			break;
-		case -1UL:
+		case -1:
+		case 0:
 			type_name = "null";
 			break;
 		}
diff --git a/cmd/cpu.c b/cmd/cpu.c
index b4af64f5..bc4dc5c 100644
--- a/cmd/cpu.c
+++ b/cmd/cpu.c
@@ -14,6 +14,7 @@
 static const char *cpu_feature_name[CPU_FEAT_COUNT] = {
 	"L1 cache",
 	"MMU",
+	"Microcode",
 };
 
 static int print_cpu_list(bool detail)
@@ -58,6 +59,12 @@
 			}
 		}
 		printf("\n");
+		if (info.features & (1 << CPU_FEAT_UCODE)) {
+			printf("\tMicrocode version %#x\n",
+			       plat->ucode_version);
+		}
+		if (info.features & (1 << CPU_FEAT_DEVICE_ID))
+			printf("\tDevice ID %#lx\n", plat->device_id);
 	}
 
 	return 0;
diff --git a/cmd/cramfs.c b/cmd/cramfs.c
index 270701b..c103491 100644
--- a/cmd/cramfs.c
+++ b/cmd/cramfs.c
@@ -29,7 +29,6 @@
 # define DEBUGF(fmt, args...)
 #endif
 
-#ifdef CONFIG_CRAMFS_CMDLINE
 #include <flash.h>
 
 #ifdef CONFIG_SYS_NO_FLASH
@@ -201,7 +200,3 @@
 	"[ directory ]\n"
 	"    - list files in a directory.\n"
 );
-
-#endif /* #ifdef CONFIG_CRAMFS_CMDLINE */
-
-/***************************************************/
diff --git a/cmd/disk.c b/cmd/disk.c
index 3025225..2fd1717 100644
--- a/cmd/disk.c
+++ b/cmd/disk.c
@@ -20,9 +20,9 @@
 #if defined(CONFIG_IMAGE_FORMAT_LEGACY)
 	image_header_t *hdr;
 #endif
-	block_dev_desc_t *dev_desc;
+	struct blk_desc *dev_desc;
 
-#if defined(CONFIG_FIT)
+#if CONFIG_IS_ENABLED(FIT)
 	const void *fit_hdr = NULL;
 #endif
 
@@ -38,14 +38,14 @@
 
 	bootstage_mark(BOOTSTAGE_ID_IDE_BOOT_DEVICE);
 
-	part = get_device_and_partition(intf, (argc == 3) ? argv[2] : NULL,
+	part = blk_get_device_part_str(intf, (argc == 3) ? argv[2] : NULL,
 					&dev_desc, &info, 1);
 	if (part < 0) {
 		bootstage_error(BOOTSTAGE_ID_IDE_TYPE);
 		return 1;
 	}
 
-	dev = dev_desc->dev;
+	dev = dev_desc->devnum;
 	bootstage_mark(BOOTSTAGE_ID_IDE_TYPE);
 
 	printf("\nLoading from %s device %d, partition %d: "
@@ -56,7 +56,7 @@
 	      ", Block Size: %ld\n",
 	      info.start, info.size, info.blksz);
 
-	if (dev_desc->block_read(dev_desc, info.start, 1, (ulong *)addr) != 1) {
+	if (blk_dread(dev_desc, info.start, 1, (ulong *)addr) != 1) {
 		printf("** Read error on %d:%d\n", dev, part);
 		bootstage_error(BOOTSTAGE_ID_IDE_PART_READ);
 		return 1;
@@ -82,7 +82,7 @@
 		cnt = image_get_image_size(hdr);
 		break;
 #endif
-#if defined(CONFIG_FIT)
+#if CONFIG_IS_ENABLED(FIT)
 	case IMAGE_FORMAT_FIT:
 		fit_hdr = (const void *) addr;
 		puts("Fit image detected...\n");
@@ -100,15 +100,15 @@
 	cnt /= info.blksz;
 	cnt -= 1;
 
-	if (dev_desc->block_read(dev_desc, info.start + 1, cnt,
-				 (ulong *)(addr + info.blksz)) != cnt) {
+	if (blk_dread(dev_desc, info.start + 1, cnt,
+		      (ulong *)(addr + info.blksz)) != cnt) {
 		printf("** Read error on %d:%d\n", dev, part);
 		bootstage_error(BOOTSTAGE_ID_IDE_READ);
 		return 1;
 	}
 	bootstage_mark(BOOTSTAGE_ID_IDE_READ);
 
-#if defined(CONFIG_FIT)
+#if CONFIG_IS_ENABLED(FIT)
 	/* This cannot be done earlier,
 	 * we need complete FIT image in RAM first */
 	if (genimg_get_format((void *) addr) == IMAGE_FORMAT_FIT) {
diff --git a/cmd/fat.c b/cmd/fat.c
index aae993d..4e20746 100644
--- a/cmd/fat.c
+++ b/cmd/fat.c
@@ -69,7 +69,7 @@
 			 char * const argv[])
 {
 	int dev, part;
-	block_dev_desc_t *dev_desc;
+	struct blk_desc *dev_desc;
 	disk_partition_t info;
 
 	if (argc < 2) {
@@ -77,11 +77,11 @@
 		return 0;
 	}
 
-	part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1);
+	part = blk_get_device_part_str(argv[1], argv[2], &dev_desc, &info, 1);
 	if (part < 0)
 		return 1;
 
-	dev = dev_desc->dev;
+	dev = dev_desc->devnum;
 	if (fat_set_blk_dev(dev_desc, &info) != 0) {
 		printf("\n** Unable to use %s %d:%d for fatinfo **\n",
 			argv[1], dev, part);
@@ -105,7 +105,7 @@
 	int ret;
 	unsigned long addr;
 	unsigned long count;
-	block_dev_desc_t *dev_desc = NULL;
+	struct blk_desc *dev_desc = NULL;
 	disk_partition_t info;
 	int dev = 0;
 	int part = 1;
@@ -114,11 +114,11 @@
 	if (argc < 5)
 		return cmd_usage(cmdtp);
 
-	part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1);
+	part = blk_get_device_part_str(argv[1], argv[2], &dev_desc, &info, 1);
 	if (part < 0)
 		return 1;
 
-	dev = dev_desc->dev;
+	dev = dev_desc->devnum;
 
 	if (fat_set_blk_dev(dev_desc, &info) != 0) {
 		printf("\n** Unable to use %s %d:%d for fatwrite **\n",
diff --git a/cmd/fs.c b/cmd/fs.c
index 8f8f1b2..be8f289 100644
--- a/cmd/fs.c
+++ b/cmd/fs.c
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <command.h>
 #include <fs.h>
+#include <efi_loader.h>
 
 static int do_size_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
@@ -26,6 +27,7 @@
 static int do_load_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
 				char * const argv[])
 {
+	efi_set_bootdev(argv[1], (argc > 2) ? argv[2] : "");
 	return do_load(cmdtp, flag, argc, argv, FS_TYPE_ANY);
 }
 
diff --git a/cmd/gpio.c b/cmd/gpio.c
index 693998e..ecdc453 100644
--- a/cmd/gpio.c
+++ b/cmd/gpio.c
@@ -119,7 +119,7 @@
 {
 	unsigned int gpio;
 	enum gpio_cmd sub_cmd;
-	ulong value;
+	int value;
 	const char *str_cmd, *str_gpio = NULL;
 	int ret;
 #ifdef CONFIG_DM_GPIO
@@ -197,15 +197,35 @@
 		value = gpio_get_value(gpio);
 	} else {
 		switch (sub_cmd) {
-			case GPIO_SET:    value = 1; break;
-			case GPIO_CLEAR:  value = 0; break;
-			case GPIO_TOGGLE: value = !gpio_get_value(gpio); break;
-			default:          goto show_usage;
+		case GPIO_SET:
+			value = 1;
+			break;
+		case GPIO_CLEAR:
+			value = 0;
+			break;
+		case GPIO_TOGGLE:
+			value = gpio_get_value(gpio);
+			if (!IS_ERR_VALUE(value))
+				value = !value;
+			break;
+		default:
+			goto show_usage;
 		}
 		gpio_direction_output(gpio, value);
 	}
-	printf("gpio: pin %s (gpio %i) value is %lu\n",
-		str_gpio, gpio, value);
+	printf("gpio: pin %s (gpio %i) value is ", str_gpio, gpio);
+	if (IS_ERR_VALUE(value))
+		printf("unknown (ret=%d)\n", value);
+	else
+		printf("%d\n", value);
+	if (sub_cmd != GPIO_INPUT && !IS_ERR_VALUE(value)) {
+		int nval = gpio_get_value(gpio);
+
+		if (IS_ERR_VALUE(nval))
+			printf("   Warning: no access to GPIO output value\n");
+		else if (nval != value)
+			printf("   Warning: value of pin is still %d\n", nval);
+	}
 
 	if (ret != -EBUSY)
 		gpio_free(gpio);
diff --git a/cmd/gpt.c b/cmd/gpt.c
index d94d553..8ffaef3 100644
--- a/cmd/gpt.c
+++ b/cmd/gpt.c
@@ -168,7 +168,7 @@
  * @return - zero on success, otherwise error
  *
  */
-static int set_gpt_info(block_dev_desc_t *dev_desc,
+static int set_gpt_info(struct blk_desc *dev_desc,
 			const char *str_part,
 			char **str_disk_guid,
 			disk_partition_t **partitions,
@@ -328,7 +328,7 @@
 	return errno;
 }
 
-static int gpt_default(block_dev_desc_t *blk_dev_desc, const char *str_part)
+static int gpt_default(struct blk_desc *blk_dev_desc, const char *str_part)
 {
 	int ret;
 	char *str_disk_guid;
@@ -356,7 +356,7 @@
 	return ret;
 }
 
-static int gpt_verify(block_dev_desc_t *blk_dev_desc, const char *str_part)
+static int gpt_verify(struct blk_desc *blk_dev_desc, const char *str_part)
 {
 	ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1,
 				     blk_dev_desc->blksz);
@@ -408,7 +408,7 @@
 	int ret = CMD_RET_SUCCESS;
 	int dev = 0;
 	char *ep;
-	block_dev_desc_t *blk_dev_desc = NULL;
+	struct blk_desc *blk_dev_desc = NULL;
 
 	if (argc < 4 || argc > 5)
 		return CMD_RET_USAGE;
@@ -418,7 +418,7 @@
 		printf("'%s' is not a number\n", argv[3]);
 		return CMD_RET_USAGE;
 	}
-	blk_dev_desc = get_dev(argv[2], dev);
+	blk_dev_desc = blk_get_dev(argv[2], dev);
 	if (!blk_dev_desc) {
 		printf("%s: %s dev %d NOT available\n",
 		       __func__, argv[2], dev);
diff --git a/cmd/host.c b/cmd/host.c
index ba1460e..8d84415 100644
--- a/cmd/host.c
+++ b/cmd/host.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <fs.h>
 #include <part.h>
 #include <sandboxblockdev.h>
@@ -67,7 +68,7 @@
 	int dev;
 	printf("%3s %12s %s\n", "dev", "blocks", "path");
 	for (dev = min_dev; dev <= max_dev; dev++) {
-		block_dev_desc_t *blk_dev;
+		struct blk_desc *blk_dev;
 		int ret;
 
 		printf("%3d ", dev);
@@ -80,7 +81,13 @@
 
 			continue;
 		}
-		struct host_block_dev *host_dev = blk_dev->priv;
+		struct host_block_dev *host_dev;
+
+#ifdef CONFIG_BLK
+		host_dev = dev_get_priv(blk_dev->bdev);
+#else
+		host_dev = blk_dev->priv;
+#endif
 		printf("%12lu %s\n", (unsigned long)blk_dev->lba,
 		       host_dev->filename);
 	}
@@ -92,7 +99,7 @@
 {
 	int dev;
 	char *ep;
-	block_dev_desc_t *blk_dev;
+	struct blk_desc *blk_dev;
 	int ret;
 
 	if (argc < 1 || argc > 3)
diff --git a/cmd/ide.c b/cmd/ide.c
index f19a7ce..c4c08c8 100644
--- a/cmd/ide.c
+++ b/cmd/ide.c
@@ -10,6 +10,7 @@
  */
 
 #include <common.h>
+#include <blk.h>
 #include <config.h>
 #include <watchdog.h>
 #include <command.h>
@@ -53,7 +54,7 @@
 
 static int ide_bus_ok[CONFIG_SYS_IDE_MAXBUS];
 
-block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
+struct blk_desc ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
 /* ------------------------------------------------------------------------- */
 
 #ifdef CONFIG_IDE_RESET
@@ -62,7 +63,7 @@
 #define ide_reset()	/* dummy */
 #endif
 
-static void  ide_ident (block_dev_desc_t *dev_desc);
+static void ide_ident(struct blk_desc *dev_desc);
 static uchar ide_wait  (int dev, ulong t);
 
 #define IDE_TIME_OUT	2000	/* 2 sec timeout */
@@ -78,8 +79,8 @@
 #endif
 
 #ifdef CONFIG_ATAPI
-static void	atapi_inquiry(block_dev_desc_t *dev_desc);
-static ulong atapi_read(block_dev_desc_t *block_dev, lbaint_t blknr,
+static void	atapi_inquiry(struct blk_desc *dev_desc);
+static ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr,
 			lbaint_t blkcnt, void *buffer);
 #endif
 
@@ -137,7 +138,7 @@
 					++ok;
 					if (dev)
 						putc('\n');
-					print_part(&ide_dev_desc[dev]);
+					part_print(&ide_dev_desc[dev]);
 				}
 			}
 			if (!ok) {
@@ -171,7 +172,7 @@
 			int dev = (int) simple_strtoul(argv[2], NULL, 10);
 
 			if (ide_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) {
-				print_part(&ide_dev_desc[dev]);
+				part_print(&ide_dev_desc[dev]);
 			} else {
 				printf("\nIDE device %d not available\n",
 				       dev);
@@ -187,7 +188,7 @@
 		if (strcmp(argv[1], "read") == 0) {
 			ulong addr = simple_strtoul(argv[2], NULL, 16);
 			ulong cnt = simple_strtoul(argv[4], NULL, 16);
-			block_dev_desc_t *dev_desc;
+			struct blk_desc *dev_desc;
 			ulong n;
 
 #ifdef CONFIG_SYS_64BIT_LBA
@@ -203,8 +204,7 @@
 #endif
 
 			dev_desc = &ide_dev_desc[curr_device];
-			n = dev_desc->block_read(dev_desc, blk, cnt,
-						 (ulong *)addr);
+			n = blk_dread(dev_desc, blk, cnt, (ulong *)addr);
 			/* flush cache after read */
 			flush_cache(addr,
 				    cnt * ide_dev_desc[curr_device].blksz);
@@ -418,7 +418,7 @@
 		int led = (IDE_BUS(i) == 0) ? LED_IDE1 : LED_IDE2;
 		ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
 		ide_dev_desc[i].if_type = IF_TYPE_IDE;
-		ide_dev_desc[i].dev = i;
+		ide_dev_desc[i].devnum = i;
 		ide_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
 		ide_dev_desc[i].blksz = 0;
 		ide_dev_desc[i].log2blksz =
@@ -435,7 +435,7 @@
 
 		if ((ide_dev_desc[i].lba > 0) && (ide_dev_desc[i].blksz > 0)) {
 			/* initialize partition type */
-			init_part(&ide_dev_desc[i]);
+			part_init(&ide_dev_desc[i]);
 			if (curr_device < 0)
 				curr_device = i;
 		}
@@ -446,7 +446,7 @@
 /* ------------------------------------------------------------------------- */
 
 #ifdef CONFIG_PARTITIONS
-block_dev_desc_t *ide_get_dev(int dev)
+struct blk_desc *ide_get_dev(int dev)
 {
 	return (dev < CONFIG_SYS_IDE_MAXDEVICE) ? &ide_dev_desc[dev] : NULL;
 }
@@ -541,7 +541,7 @@
 
 /* -------------------------------------------------------------------------
  */
-static void ide_ident(block_dev_desc_t *dev_desc)
+static void ide_ident(struct blk_desc *dev_desc)
 {
 	unsigned char c;
 	hd_driveid_t iop;
@@ -551,7 +551,7 @@
 #endif
 	int device;
 
-	device = dev_desc->dev;
+	device = dev_desc->devnum;
 	printf("  Device %d: ", device);
 
 	ide_led(DEVICE_LED(device), 1);	/* LED on       */
@@ -713,10 +713,10 @@
 
 /* ------------------------------------------------------------------------- */
 
-ulong ide_read(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
 	       void *buffer)
 {
-	int device = block_dev->dev;
+	int device = block_dev->devnum;
 	ulong n = 0;
 	unsigned char c;
 	unsigned char pwrsave = 0;	/* power save */
@@ -839,10 +839,10 @@
 /* ------------------------------------------------------------------------- */
 
 
-ulong ide_write(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
 		const void *buffer)
 {
-	int device = block_dev->dev;
+	int device = block_dev->devnum;
 	ulong n = 0;
 	unsigned char c;
 
@@ -1301,14 +1301,14 @@
 }
 
 
-static void atapi_inquiry(block_dev_desc_t *dev_desc)
+static void atapi_inquiry(struct blk_desc *dev_desc)
 {
 	unsigned char ccb[12];	/* Command descriptor block */
 	unsigned char iobuf[64];	/* temp buf */
 	unsigned char c;
 	int device;
 
-	device = dev_desc->dev;
+	device = dev_desc->devnum;
 	dev_desc->type = DEV_TYPE_UNKNOWN;	/* not yet valid */
 	dev_desc->block_read = atapi_read;
 
@@ -1394,10 +1394,10 @@
 #define ATAPI_READ_BLOCK_SIZE	2048	/* assuming CD part */
 #define ATAPI_READ_MAX_BLOCK	(ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE)
 
-ulong atapi_read(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
 		 void *buffer)
 {
-	int device = block_dev->dev;
+	int device = block_dev->devnum;
 	ulong n = 0;
 	unsigned char ccb[12];	/* Command descriptor block */
 	ulong cnt;
diff --git a/cmd/mmc.c b/cmd/mmc.c
index 1c7156f..fb4382e 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -424,7 +424,7 @@
 static int do_mmc_part(cmd_tbl_t *cmdtp, int flag,
 		       int argc, char * const argv[])
 {
-	block_dev_desc_t *mmc_dev;
+	struct blk_desc *mmc_dev;
 	struct mmc *mmc;
 
 	mmc = init_mmc_device(curr_device, false);
@@ -433,7 +433,7 @@
 
 	mmc_dev = mmc_get_dev(curr_device);
 	if (mmc_dev != NULL && mmc_dev->type != DEV_TYPE_UNKNOWN) {
-		print_part(mmc_dev);
+		part_print(mmc_dev);
 		return CMD_RET_SUCCESS;
 	}
 
diff --git a/cmd/mmc_spi.c b/cmd/mmc_spi.c
index a2138b8..0c44d06 100644
--- a/cmd/mmc_spi.c
+++ b/cmd/mmc_spi.c
@@ -72,8 +72,8 @@
 		printf("Failed to create MMC Device\n");
 		return 1;
 	}
-	printf("%s: %d at %u:%u hz %u mode %u\n", mmc->cfg->name, mmc->block_dev.dev,
-	       bus, cs, speed, mode);
+	printf("%s: %d at %u:%u hz %u mode %u\n", mmc->cfg->name,
+	       mmc->block_dev.devnum, bus, cs, speed, mode);
 	mmc_init(mmc);
 	return 0;
 
diff --git a/cmd/nvedit.c b/cmd/nvedit.c
index 5ae9d9d..9cf884e 100644
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -45,6 +45,7 @@
 	!defined(CONFIG_ENV_IS_IN_DATAFLASH)	&& \
 	!defined(CONFIG_ENV_IS_IN_MMC)		&& \
 	!defined(CONFIG_ENV_IS_IN_FAT)		&& \
+	!defined(CONFIG_ENV_IS_IN_EXT4)		&& \
 	!defined(CONFIG_ENV_IS_IN_NAND)		&& \
 	!defined(CONFIG_ENV_IS_IN_NVRAM)	&& \
 	!defined(CONFIG_ENV_IS_IN_ONENAND)	&& \
@@ -53,7 +54,7 @@
 	!defined(CONFIG_ENV_IS_IN_UBI)		&& \
 	!defined(CONFIG_ENV_IS_NOWHERE)
 # error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\
-SPI_FLASH|NVRAM|MMC|FAT|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
+SPI_FLASH|NVRAM|MMC|FAT|EXT4|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
 #endif
 
 /*
diff --git a/cmd/part.c b/cmd/part.c
index 5599509..414031e 100644
--- a/cmd/part.c
+++ b/cmd/part.c
@@ -29,7 +29,7 @@
 static int do_part_uuid(int argc, char * const argv[])
 {
 	int part;
-	block_dev_desc_t *dev_desc;
+	struct blk_desc *dev_desc;
 	disk_partition_t info;
 
 	if (argc < 2)
@@ -37,7 +37,7 @@
 	if (argc > 3)
 		return CMD_RET_USAGE;
 
-	part = get_device_and_partition(argv[0], argv[1], &dev_desc, &info, 0);
+	part = blk_get_device_part_str(argv[0], argv[1], &dev_desc, &info, 0);
 	if (part < 0)
 		return 1;
 
@@ -52,7 +52,7 @@
 static int do_part_list(int argc, char * const argv[])
 {
 	int ret;
-	block_dev_desc_t *desc;
+	struct blk_desc *desc;
 	char *var = NULL;
 	bool bootable = false;
 	int i;
@@ -81,7 +81,7 @@
 			return CMD_RET_USAGE;
 	}
 
-	ret = get_device(argv[0], argv[1], &desc);
+	ret = blk_get_device_by_str(argv[0], argv[1], &desc);
 	if (ret < 0)
 		return 1;
 
@@ -92,7 +92,7 @@
 
 		for (p = 1; p < 128; p++) {
 			char t[5];
-			int r = get_partition_info(desc, p, &info);
+			int r = part_get_info(desc, p, &info);
 
 			if (r != 0)
 				continue;
@@ -107,14 +107,14 @@
 		return 0;
 	}
 
-	print_part(desc);
+	part_print(desc);
 
 	return 0;
 }
 
 static int do_part_start(int argc, char * const argv[])
 {
-	block_dev_desc_t *desc;
+	struct blk_desc *desc;
 	disk_partition_t info;
 	char buf[512] = { 0 };
 	int part;
@@ -128,11 +128,11 @@
 
 	part = simple_strtoul(argv[2], NULL, 0);
 
-	ret = get_device(argv[0], argv[1], &desc);
+	ret = blk_get_device_by_str(argv[0], argv[1], &desc);
 	if (ret < 0)
 		return 1;
 
-	err = get_partition_info(desc, part, &info);
+	err = part_get_info(desc, part, &info);
 	if (err)
 		return 1;
 
@@ -148,7 +148,7 @@
 
 static int do_part_size(int argc, char * const argv[])
 {
-	block_dev_desc_t *desc;
+	struct blk_desc *desc;
 	disk_partition_t info;
 	char buf[512] = { 0 };
 	int part;
@@ -162,11 +162,11 @@
 
 	part = simple_strtoul(argv[2], NULL, 0);
 
-	ret = get_device(argv[0], argv[1], &desc);
+	ret = blk_get_device_by_str(argv[0], argv[1], &desc);
 	if (ret < 0)
 		return 1;
 
-	err = get_partition_info(desc, part, &info);
+	err = part_get_info(desc, part, &info);
 	if (err)
 		return 1;
 
diff --git a/cmd/read.c b/cmd/read.c
index 8710288..61d8ce7 100644
--- a/cmd/read.c
+++ b/cmd/read.c
@@ -15,7 +15,7 @@
 int do_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	char *ep;
-	block_dev_desc_t *dev_desc = NULL;
+	struct blk_desc *dev_desc = NULL;
 	int dev;
 	int part = 0;
 	disk_partition_t part_info;
@@ -39,7 +39,7 @@
 		part = (int)simple_strtoul(++ep, NULL, 16);
 	}
 
-	dev_desc = get_dev(argv[1], dev);
+	dev_desc = blk_get_dev(argv[1], dev);
 	if (dev_desc == NULL) {
 		printf("Block device %s %d not supported\n", argv[1], dev);
 		return 1;
@@ -50,14 +50,14 @@
 	cnt = simple_strtoul(argv[5], NULL, 16);
 
 	if (part != 0) {
-		if (get_partition_info(dev_desc, part, &part_info)) {
+		if (part_get_info(dev_desc, part, &part_info)) {
 			printf("Cannot find partition %d\n", part);
 			return 1;
 		}
 		offset = part_info.start;
 		limit = part_info.size;
 	} else {
-		/* Largest address not available in block_dev_desc_t. */
+		/* Largest address not available in struct blk_desc. */
 		limit = ~0;
 	}
 
@@ -66,7 +66,7 @@
 		return 1;
 	}
 
-	if (dev_desc->block_read(dev_desc, offset + blk, cnt, addr) < 0) {
+	if (blk_read(dev_desc, offset + blk, cnt, addr) < 0) {
 		printf("Error reading blocks\n");
 		return 1;
 	}
diff --git a/cmd/reiser.c b/cmd/reiser.c
index 8871564..cbdad36 100644
--- a/cmd/reiser.c
+++ b/cmd/reiser.c
@@ -34,13 +34,13 @@
 {
 	char *filename = "/";
 	int dev, part;
-	block_dev_desc_t *dev_desc=NULL;
+	struct blk_desc *dev_desc = NULL;
 	disk_partition_t info;
 
 	if (argc < 3)
 		return CMD_RET_USAGE;
 
-	part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1);
+	part = blk_get_device_part_str(argv[1], argv[2], &dev_desc, &info, 1);
 	if (part < 0)
 		return 1;
 
@@ -48,7 +48,7 @@
 	    filename = argv[3];
 	}
 
-	dev = dev_desc->dev;
+	dev = dev_desc->devnum;
 	PRINTF("Using device %s %d:%d, directory: %s\n", argv[1], dev, part, filename);
 
 	reiserfs_set_blk_dev(dev_desc, &info);
@@ -82,7 +82,7 @@
 	int dev, part;
 	ulong addr = 0, filelen;
 	disk_partition_t info;
-	block_dev_desc_t *dev_desc = NULL;
+	struct blk_desc *dev_desc = NULL;
 	unsigned long count;
 	char *addr_str;
 
@@ -122,11 +122,11 @@
 		return 1;
 	}
 
-	part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1);
+	part = blk_get_device_part_str(argv[1], argv[2], &dev_desc, &info, 1);
 	if (part < 0)
 		return 1;
 
-	dev = dev_desc->dev;
+	dev = dev_desc->devnum;
 
 	printf("Loading file \"%s\" from %s device %d%c%c\n",
 		filename, argv[1], dev,
diff --git a/cmd/sata.c b/cmd/sata.c
index 76bacea..c8de9a3 100644
--- a/cmd/sata.c
+++ b/cmd/sata.c
@@ -16,18 +16,18 @@
 #include <sata.h>
 
 static int sata_curr_device = -1;
-block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
+struct blk_desc sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
 
-static unsigned long sata_bread(block_dev_desc_t *block_dev, lbaint_t start,
+static unsigned long sata_bread(struct blk_desc *block_dev, lbaint_t start,
 				lbaint_t blkcnt, void *dst)
 {
-	return sata_read(block_dev->dev, start, blkcnt, dst);
+	return sata_read(block_dev->devnum, start, blkcnt, dst);
 }
 
-static unsigned long sata_bwrite(block_dev_desc_t *block_dev, lbaint_t start,
+static unsigned long sata_bwrite(struct blk_desc *block_dev, lbaint_t start,
 				 lbaint_t blkcnt, const void *buffer)
 {
-	return sata_write(block_dev->dev, start, blkcnt, buffer);
+	return sata_write(block_dev->devnum, start, blkcnt, buffer);
 }
 
 int __sata_initialize(void)
@@ -36,9 +36,9 @@
 	int i;
 
 	for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++) {
-		memset(&sata_dev_desc[i], 0, sizeof(struct block_dev_desc));
+		memset(&sata_dev_desc[i], 0, sizeof(struct blk_desc));
 		sata_dev_desc[i].if_type = IF_TYPE_SATA;
-		sata_dev_desc[i].dev = i;
+		sata_dev_desc[i].devnum = i;
 		sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
 		sata_dev_desc[i].type = DEV_TYPE_HARDDISK;
 		sata_dev_desc[i].lba = 0;
@@ -52,7 +52,7 @@
 			rc = scan_sata(i);
 			if (!rc && (sata_dev_desc[i].lba > 0) &&
 				(sata_dev_desc[i].blksz > 0))
-				init_part(&sata_dev_desc[i]);
+				part_init(&sata_dev_desc[i]);
 		}
 	}
 	sata_curr_device = 0;
@@ -75,7 +75,7 @@
 int sata_stop(void) __attribute__((weak, alias("__sata_stop")));
 
 #ifdef CONFIG_PARTITIONS
-block_dev_desc_t *sata_get_dev(int dev)
+struct blk_desc *sata_get_dev(int dev)
 {
 	return (dev < CONFIG_SYS_SATA_MAX_DEVICE) ? &sata_dev_desc[dev] : NULL;
 }
@@ -131,7 +131,7 @@
 					++ok;
 					if (dev)
 						putc ('\n');
-					print_part(&sata_dev_desc[dev]);
+					part_print(&sata_dev_desc[dev]);
 				}
 			}
 			if (!ok) {
@@ -164,7 +164,7 @@
 			int dev = (int)simple_strtoul(argv[2], NULL, 10);
 
 			if (sata_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) {
-				print_part(&sata_dev_desc[dev]);
+				part_print(&sata_dev_desc[dev]);
 			} else {
 				printf("\nSATA device %d not available\n", dev);
 				rc = 1;
diff --git a/cmd/scsi.c b/cmd/scsi.c
index bc7d1b6..8991125 100644
--- a/cmd/scsi.c
+++ b/cmd/scsi.c
@@ -48,7 +48,7 @@
 
 static int scsi_curr_dev; /* current device */
 
-static block_dev_desc_t scsi_dev_desc[CONFIG_SYS_SCSI_MAX_DEVICE];
+static struct blk_desc scsi_dev_desc[CONFIG_SYS_SCSI_MAX_DEVICE];
 
 /********************************************************************************
  *  forward declerations of some Setup Routines
@@ -66,9 +66,9 @@
 
 static int scsi_read_capacity(ccb *pccb, lbaint_t *capacity,
 			      unsigned long *blksz);
-static ulong scsi_read(block_dev_desc_t *block_dev, lbaint_t blknr,
+static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr,
 		       lbaint_t blkcnt, void *buffer);
-static ulong scsi_write(block_dev_desc_t *block_dev, lbaint_t blknr,
+static ulong scsi_write(struct blk_desc *block_dev, lbaint_t blknr,
 			lbaint_t blkcnt, const void *buffer);
 
 
@@ -99,7 +99,7 @@
 		scsi_dev_desc[i].revision[0]=0;
 		scsi_dev_desc[i].removable = false;
 		scsi_dev_desc[i].if_type=IF_TYPE_SCSI;
-		scsi_dev_desc[i].dev=i;
+		scsi_dev_desc[i].devnum = i;
 		scsi_dev_desc[i].part_type=PART_TYPE_UNKNOWN;
 		scsi_dev_desc[i].block_read=scsi_read;
 		scsi_dev_desc[i].block_write = scsi_write;
@@ -156,7 +156,7 @@
 			scsi_dev_desc[scsi_max_devs].log2blksz =
 				LOG2(scsi_dev_desc[scsi_max_devs].blksz);
 			scsi_dev_desc[scsi_max_devs].type=perq;
-			init_part(&scsi_dev_desc[scsi_max_devs]);
+			part_init(&scsi_dev_desc[scsi_max_devs]);
 removable:
 			if(mode==1) {
 				printf ("  Device %d: ", scsi_max_devs);
@@ -239,12 +239,13 @@
 #endif
 
 #ifdef CONFIG_PARTITIONS
-block_dev_desc_t * scsi_get_dev(int dev)
+struct blk_desc *scsi_get_dev(int dev)
 {
 	return (dev < CONFIG_SYS_SCSI_MAX_DEVICE) ? &scsi_dev_desc[dev] : NULL;
 }
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 /******************************************************************************
  * scsi boot command intepreter. Derived from diskboot
  */
@@ -301,7 +302,7 @@
 						if (dev)
 							printf("\n");
 						debug ("print_part of %x\n",dev);
-							print_part(&scsi_dev_desc[dev]);
+						part_print(&scsi_dev_desc[dev]);
 					}
 				}
 				if (!ok)
@@ -329,7 +330,7 @@
 			if (strncmp(argv[1],"part",4) == 0) {
 				int dev = (int)simple_strtoul(argv[2], NULL, 10);
 				if(scsi_dev_desc[dev].type != DEV_TYPE_UNKNOWN) {
-					print_part(&scsi_dev_desc[dev]);
+					part_print(&scsi_dev_desc[dev]);
 				}
 				else {
 					printf ("\nSCSI device %d not available\n", dev);
@@ -368,6 +369,27 @@
 	return CMD_RET_USAGE;
 }
 
+U_BOOT_CMD(
+	scsi, 5, 1, do_scsi,
+	"SCSI sub-system",
+	"reset - reset SCSI controller\n"
+	"scsi info  - show available SCSI devices\n"
+	"scsi scan  - (re-)scan SCSI bus\n"
+	"scsi device [dev] - show or set current device\n"
+	"scsi part [dev] - print partition table of one or all SCSI devices\n"
+	"scsi read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n"
+	"     to memory address `addr'\n"
+	"scsi write addr blk# cnt - write `cnt' blocks starting at block\n"
+	"     `blk#' from memory address `addr'"
+);
+
+U_BOOT_CMD(
+	scsiboot, 3, 1, do_scsiboot,
+	"boot from SCSI device",
+	"loadAddr dev:part"
+);
+#endif
+
 /****************************************************************************************
  * scsi_read
  */
@@ -376,10 +398,10 @@
 #define SCSI_MAX_READ_BLK 0xFFFF
 #define SCSI_LBA48_READ	0xFFFFFFF
 
-static ulong scsi_read(block_dev_desc_t *block_dev, lbaint_t blknr,
+static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr,
 		       lbaint_t blkcnt, void *buffer)
 {
-	int device = block_dev->dev;
+	int device = block_dev->devnum;
 	lbaint_t start, blks;
 	uintptr_t buf_addr;
 	unsigned short smallblks = 0;
@@ -443,10 +465,10 @@
 /* Almost the maximum amount of the scsi_ext command.. */
 #define SCSI_MAX_WRITE_BLK 0xFFFF
 
-static ulong scsi_write(block_dev_desc_t *block_dev, lbaint_t blknr,
+static ulong scsi_write(struct blk_desc *block_dev, lbaint_t blknr,
 			lbaint_t blkcnt, const void *buffer)
 {
-	int device = block_dev->dev;
+	int device = block_dev->devnum;
 	lbaint_t start, blks;
 	uintptr_t buf_addr;
 	unsigned short smallblks;
@@ -710,24 +732,3 @@
 	pccb->cmdlen=6;
 	pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
 }
-
-
-U_BOOT_CMD(
-	scsi, 5, 1, do_scsi,
-	"SCSI sub-system",
-	"reset - reset SCSI controller\n"
-	"scsi info  - show available SCSI devices\n"
-	"scsi scan  - (re-)scan SCSI bus\n"
-	"scsi device [dev] - show or set current device\n"
-	"scsi part [dev] - print partition table of one or all SCSI devices\n"
-	"scsi read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n"
-	"     to memory address `addr'\n"
-	"scsi write addr blk# cnt - write `cnt' blocks starting at block\n"
-	"     `blk#' from memory address `addr'"
-);
-
-U_BOOT_CMD(
-	scsiboot, 3, 1, do_scsiboot,
-	"boot from SCSI device",
-	"loadAddr dev:part"
-);
diff --git a/cmd/tpm.c b/cmd/tpm.c
index 6edf3e9..312503f 100644
--- a/cmd/tpm.c
+++ b/cmd/tpm.c
@@ -447,8 +447,8 @@
 {
 	int rc;
 
-	rc = uclass_first_device(UCLASS_TPM, devp);
-	if (rc || !*devp) {
+	rc = uclass_first_device_err(UCLASS_TPM, devp);
+	if (rc) {
 		printf("Could not find TPM (ret=%d)\n", rc);
 		return CMD_RET_FAILURE;
 	}
diff --git a/cmd/unzip.c b/cmd/unzip.c
index 0686be6..a8bcb1f 100644
--- a/cmd/unzip.c
+++ b/cmd/unzip.c
@@ -43,7 +43,7 @@
 static int do_gzwrite(cmd_tbl_t *cmdtp, int flag,
 		      int argc, char * const argv[])
 {
-	block_dev_desc_t *bdev;
+	struct blk_desc *bdev;
 	int ret;
 	unsigned char *addr;
 	unsigned long length;
@@ -53,7 +53,7 @@
 
 	if (argc < 5)
 		return CMD_RET_USAGE;
-	ret = get_device(argv[1], argv[2], &bdev);
+	ret = blk_get_device_by_str(argv[1], argv[2], &bdev);
 	if (ret < 0)
 		return CMD_RET_FAILURE;
 
diff --git a/cmd/usb.c b/cmd/usb.c
index c7b642c..9ed5dc6 100644
--- a/cmd/usb.c
+++ b/cmd/usb.c
@@ -625,7 +625,7 @@
 	int i;
 	extern char usb_started;
 #ifdef CONFIG_USB_STORAGE
-	block_dev_desc_t *stor_dev;
+	struct blk_desc *stor_dev;
 #endif
 
 	if (argc < 2)
@@ -727,7 +727,7 @@
 					if (devno)
 						printf("\n");
 					debug("print_part of %x\n", devno);
-					print_part(stor_dev);
+					part_print(stor_dev);
 				}
 			}
 		} else {
@@ -737,7 +737,7 @@
 			    stor_dev->type != DEV_TYPE_UNKNOWN) {
 				ok++;
 				debug("print_part of %x\n", devno);
-				print_part(stor_dev);
+				part_print(stor_dev);
 			}
 		}
 		if (!ok) {
@@ -759,8 +759,7 @@
 			printf("\nUSB read: device %d block # %ld, count %ld"
 				" ... ", usb_stor_curr_dev, blk, cnt);
 			stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
-			n = stor_dev->block_read(stor_dev, blk, cnt,
-						 (ulong *)addr);
+			n = blk_dread(stor_dev, blk, cnt, (ulong *)addr);
 			printf("%ld blocks read: %s\n", n,
 				(n == cnt) ? "OK" : "ERROR");
 			if (n == cnt)
@@ -781,8 +780,7 @@
 			printf("\nUSB write: device %d block # %ld, count %ld"
 				" ... ", usb_stor_curr_dev, blk, cnt);
 			stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
-			n = stor_dev->block_write(stor_dev, blk, cnt,
-						(ulong *)addr);
+			n = blk_dwrite(stor_dev, blk, cnt, (ulong *)addr);
 			printf("%ld blocks write: %s\n", n,
 				(n == cnt) ? "OK" : "ERROR");
 			if (n == cnt)
diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
index 0415591..14eed98 100644
--- a/cmd/usb_mass_storage.c
+++ b/cmd/usb_mass_storage.c
@@ -19,7 +19,7 @@
 static int ums_read_sector(struct ums *ums_dev,
 			   ulong start, lbaint_t blkcnt, void *buf)
 {
-	block_dev_desc_t *block_dev = &ums_dev->block_dev;
+	struct blk_desc *block_dev = &ums_dev->block_dev;
 	lbaint_t blkstart = start + ums_dev->start_sector;
 
 	return block_dev->block_read(block_dev, blkstart, blkcnt, buf);
@@ -28,7 +28,7 @@
 static int ums_write_sector(struct ums *ums_dev,
 			    ulong start, lbaint_t blkcnt, const void *buf)
 {
-	block_dev_desc_t *block_dev = &ums_dev->block_dev;
+	struct blk_desc *block_dev = &ums_dev->block_dev;
 	lbaint_t blkstart = start + ums_dev->start_sector;
 
 	return block_dev->block_write(block_dev, blkstart, blkcnt, buf);
@@ -53,7 +53,7 @@
 static int ums_init(const char *devtype, const char *devnums)
 {
 	char *s, *t, *devnum, *name;
-	block_dev_desc_t *block_dev;
+	struct blk_desc *block_dev;
 	int ret;
 	struct ums *ums_new;
 
@@ -69,7 +69,7 @@
 		if (!devnum)
 			break;
 
-		ret = get_device(devtype, devnum, &block_dev);
+		ret = blk_get_device_by_str(devtype, devnum, &block_dev);
 		if (ret < 0)
 			goto cleanup;
 
@@ -100,7 +100,7 @@
 		ums[ums_count].block_dev = *block_dev;
 
 		printf("UMS: LUN %d, dev %d, hwpart %d, sector %#x, count %#x\n",
-		       ums_count, ums[ums_count].block_dev.dev,
+		       ums_count, ums[ums_count].block_dev.devnum,
 		       ums[ums_count].block_dev.hwpart,
 		       ums[ums_count].start_sector,
 		       ums[ums_count].num_sectors);
diff --git a/cmd/zfs.c b/cmd/zfs.c
index 0aed29e..93067a9 100644
--- a/cmd/zfs.c
+++ b/cmd/zfs.c
@@ -39,7 +39,7 @@
 	int part;
 	ulong addr = 0;
 	disk_partition_t info;
-	block_dev_desc_t *dev_desc;
+	struct blk_desc *dev_desc;
 	char buf[12];
 	unsigned long count;
 	const char *addr_str;
@@ -80,11 +80,11 @@
 		return 1;
 	}
 
-	part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1);
+	part = blk_get_device_part_str(argv[1], argv[2], &dev_desc, &info, 1);
 	if (part < 0)
 		return 1;
 
-	dev = dev_desc->dev;
+	dev = dev_desc->devnum;
 	printf("Loading file \"%s\" from %s device %d%c%c\n",
 		filename, argv[1], dev,
 		part ? ':' : ' ', part ? part + '0' : ' ');
@@ -135,7 +135,7 @@
 {
 	const char *filename = "/";
 	int part;
-	block_dev_desc_t *dev_desc;
+	struct blk_desc *dev_desc;
 	disk_partition_t info;
 	struct device_s vdev;
 
@@ -145,7 +145,7 @@
 	if (argc == 4)
 		filename = argv[3];
 
-	part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1);
+	part = blk_get_device_part_str(argv[1], argv[2], &dev_desc, &info, 1);
 	if (part < 0)
 		return 1;
 
diff --git a/common/Makefile b/common/Makefile
index 117178a..c96442b 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -46,6 +46,7 @@
 obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
 obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
 obj-$(CONFIG_ENV_IS_IN_FAT) += env_fat.o
+obj-$(CONFIG_ENV_IS_IN_EXT4) += env_ext4.o
 obj-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
 obj-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o
 obj-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o
@@ -55,7 +56,7 @@
 obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
 
 obj-$(CONFIG_CMD_BEDBUG) += bedbug.o
-obj-$(CONFIG_OF_LIBFDT) += fdt_support.o
+obj-$(CONFIG_$(SPL_)OF_LIBFDT) += fdt_support.o
 
 obj-$(CONFIG_MII) += miiphyutil.o
 obj-$(CONFIG_CMD_MII) += miiphyutil.o
@@ -105,6 +106,7 @@
 obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
 obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
 obj-$(CONFIG_ENV_IS_IN_FAT) += env_fat.o
+obj-$(CONFIG_ENV_IS_IN_EXT4) += env_ext4.o
 obj-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
 obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
 obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
@@ -129,9 +131,9 @@
 endif
 obj-y += image.o
 obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o
-obj-$(CONFIG_OF_LIBFDT) += image-fdt.o
-obj-$(CONFIG_FIT) += image-fit.o
-obj-$(CONFIG_FIT_SIGNATURE) += image-sig.o
+obj-$(CONFIG_$(SPL_)OF_LIBFDT) += image-fdt.o
+obj-$(CONFIG_$(SPL_)FIT) += image-fit.o
+obj-$(CONFIG_$(SPL_)FIT_SIGNATURE) += image-sig.o
 obj-$(CONFIG_IO_TRACE) += iotrace.o
 obj-y += memsize.o
 obj-y += stdio.o
diff --git a/common/board_f.c b/common/board_f.c
index 622093a..109025a 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -1096,6 +1096,13 @@
 		hang();
 
 	/*
+	 * The pre-relocation drivers may be using memory that has now gone
+	 * away. Mark serial as unavailable - this will fall back to the debug
+	 * UART if available.
+	 */
+	gd->flags &= ~GD_FLG_SERIAL_READY;
+
+	/*
 	 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
 	 * Transfer execution from Flash to RAM by calculating the address
 	 * of the in-RAM copy of board_init_r() and calling it
diff --git a/common/board_r.c b/common/board_r.c
index 52a9b26..ad02549 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -65,6 +65,7 @@
 #ifdef CONFIG_AVR32
 #include <asm/arch/mmu.h>
 #endif
+#include <efi_loader.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -177,6 +178,9 @@
 	*/
 	gd->fdt_blob += gd->reloc_off;
 #endif
+#ifdef CONFIG_EFI_LOADER
+	efi_runtime_relocate(gd->relocaddr, NULL);
+#endif
 
 	return 0;
 }
@@ -318,11 +322,13 @@
 	/* Save the pre-reloc driver model and start a new one */
 	gd->dm_root_f = gd->dm_root;
 	gd->dm_root = NULL;
+#ifdef CONFIG_TIMER
+	gd->timer = NULL;
+#endif
 	ret = dm_init_and_scan(false);
 	if (ret)
 		return ret;
 #ifdef CONFIG_TIMER_EARLY
-	gd->timer = NULL;
 	ret = dm_timer_init();
 	if (ret)
 		return ret;
@@ -791,6 +797,9 @@
 #ifdef CONFIG_CLOCKS
 	set_cpu_clk_info, /* Setup clock information */
 #endif
+#ifdef CONFIG_EFI_LOADER
+	efi_memory_init,
+#endif
 	stdio_init_tables,
 	initr_serial,
 	initr_announce,
diff --git a/common/bootm.c b/common/bootm.c
index df27089..c965326 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -108,7 +108,7 @@
 		images.os.arch = image_get_arch(os_hdr);
 		break;
 #endif
-#if defined(CONFIG_FIT)
+#if IMAGE_ENABLE_FIT
 	case IMAGE_FORMAT_FIT:
 		if (fit_image_get_type(images.fit_hdr_os,
 				       images.fit_noffset_os,
@@ -180,7 +180,7 @@
 		/* Kernel entry point is the setup.bin */
 	} else if (images.legacy_hdr_valid) {
 		images.ep = image_get_ep(&images.legacy_hdr_os_copy);
-#if defined(CONFIG_FIT)
+#if IMAGE_ENABLE_FIT
 	} else if (images.fit_uname_os) {
 		int ret;
 
@@ -234,7 +234,7 @@
 		return 1;
 	}
 
-#if defined(CONFIG_OF_LIBFDT)
+#if IMAGE_ENABLE_OF_LIBFDT
 	/* find flattened device tree */
 	ret = boot_get_fdt(flag, argc, argv, IH_ARCH_DEFAULT, &images,
 			   &images.ft_addr, &images.ft_len);
@@ -245,7 +245,7 @@
 	set_working_fdt_addr((ulong)images.ft_addr);
 #endif
 
-#if defined(CONFIG_FIT)
+#if IMAGE_ENABLE_FIT
 	/* find all of the loadables */
 	ret = boot_get_loadable(argc, argv, &images, IH_ARCH_DEFAULT,
 			       NULL, NULL);
@@ -644,7 +644,7 @@
 		}
 	}
 #endif
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_LMB)
+#if IMAGE_ENABLE_OF_LIBFDT && defined(CONFIG_LMB)
 	if (!ret && (states & BOOTM_STATE_FDT)) {
 		boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr);
 		ret = boot_relocate_fdt(&images->lmb, &images->ft_addr,
@@ -788,7 +788,7 @@
 	const void *buf;
 	const char	*fit_uname_config = NULL;
 	const char	*fit_uname_kernel = NULL;
-#if defined(CONFIG_FIT)
+#if IMAGE_ENABLE_FIT
 	int		os_noffset;
 #endif
 
@@ -849,7 +849,7 @@
 		bootstage_mark(BOOTSTAGE_ID_DECOMP_IMAGE);
 		break;
 #endif
-#if defined(CONFIG_FIT)
+#if IMAGE_ENABLE_FIT
 	case IMAGE_FORMAT_FIT:
 		os_noffset = fit_image_load(images, img_addr,
 				&fit_uname_kernel, &fit_uname_config,
diff --git a/common/env_ext4.c b/common/env_ext4.c
new file mode 100644
index 0000000..ce748ed
--- /dev/null
+++ b/common/env_ext4.c
@@ -0,0 +1,127 @@
+/*
+ * (c) Copyright 2016 by VRT Technology
+ *
+ * Author:
+ *  Stuart Longland <stuartl@vrt.com.au>
+ *
+ * Based on FAT environment driver
+ * (c) Copyright 2011 by Tigris Elektronik GmbH
+ *
+ * Author:
+ *  Maximilian Schwerin <mvs@tigris.de>
+ *
+ * and EXT4 filesystem implementation
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <command.h>
+#include <environment.h>
+#include <linux/stddef.h>
+#include <malloc.h>
+#include <search.h>
+#include <errno.h>
+#include <ext4fs.h>
+#include <mmc.h>
+
+char *env_name_spec = "EXT4";
+
+env_t *env_ptr;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int env_init(void)
+{
+	/* use default */
+	gd->env_addr = (ulong)&default_environment[0];
+	gd->env_valid = 1;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_SAVEENV
+int saveenv(void)
+{
+	env_t	env_new;
+	block_dev_desc_t *dev_desc = NULL;
+	disk_partition_t info;
+	int dev, part;
+	int err;
+
+	err = env_export(&env_new);
+	if (err)
+		return err;
+
+	part = get_device_and_partition(EXT4_ENV_INTERFACE,
+					EXT4_ENV_DEVICE_AND_PART,
+					&dev_desc, &info, 1);
+	if (part < 0)
+		return 1;
+
+	dev = dev_desc->dev;
+	ext4fs_set_blk_dev(dev_desc, &info);
+
+	if (!ext4fs_mount(info.size)) {
+		printf("\n** Unable to use %s %s for saveenv **\n",
+		       EXT4_ENV_INTERFACE, EXT4_ENV_DEVICE_AND_PART);
+		return 1;
+	}
+
+	err = ext4fs_write(EXT4_ENV_FILE, (void *)&env_new, sizeof(env_t));
+	ext4fs_close();
+
+	if (err == -1) {
+		printf("\n** Unable to write \"%s\" from %s%d:%d **\n",
+			EXT4_ENV_FILE, EXT4_ENV_INTERFACE, dev, part);
+		return 1;
+	}
+
+	puts("done\n");
+	return 0;
+}
+#endif /* CONFIG_CMD_SAVEENV */
+
+void env_relocate_spec(void)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
+	block_dev_desc_t *dev_desc = NULL;
+	disk_partition_t info;
+	int dev, part;
+	int err;
+
+	part = get_device_and_partition(EXT4_ENV_INTERFACE,
+					EXT4_ENV_DEVICE_AND_PART,
+					&dev_desc, &info, 1);
+	if (part < 0)
+		goto err_env_relocate;
+
+	dev = dev_desc->dev;
+	ext4fs_set_blk_dev(dev_desc, &info);
+
+	if (!ext4fs_mount(info.size)) {
+		printf("\n** Unable to use %s %s for loading the env **\n",
+		       EXT4_ENV_INTERFACE, EXT4_ENV_DEVICE_AND_PART);
+		goto err_env_relocate;
+	}
+
+	err = ext4_read_file(EXT4_ENV_FILE, buf, 0, CONFIG_ENV_SIZE);
+	ext4fs_close();
+
+	if (err == -1) {
+		printf("\n** Unable to read \"%s\" from %s%d:%d **\n",
+			EXT4_ENV_FILE, EXT4_ENV_INTERFACE, dev, part);
+		goto err_env_relocate;
+	}
+
+	env_import(buf, 1);
+	return;
+
+err_env_relocate:
+	set_default_env(NULL);
+}
diff --git a/common/env_fat.c b/common/env_fat.c
index d79d864..75616d4 100644
--- a/common/env_fat.c
+++ b/common/env_fat.c
@@ -38,7 +38,7 @@
 int saveenv(void)
 {
 	env_t	env_new;
-	block_dev_desc_t *dev_desc = NULL;
+	struct blk_desc *dev_desc = NULL;
 	disk_partition_t info;
 	int dev, part;
 	int err;
@@ -48,13 +48,13 @@
 	if (err)
 		return err;
 
-	part = get_device_and_partition(FAT_ENV_INTERFACE,
+	part = blk_get_device_part_str(FAT_ENV_INTERFACE,
 					FAT_ENV_DEVICE_AND_PART,
 					&dev_desc, &info, 1);
 	if (part < 0)
 		return 1;
 
-	dev = dev_desc->dev;
+	dev = dev_desc->devnum;
 	if (fat_set_blk_dev(dev_desc, &info) != 0) {
 		printf("\n** Unable to use %s %d:%d for saveenv **\n",
 		       FAT_ENV_INTERFACE, dev, part);
@@ -77,18 +77,18 @@
 void env_relocate_spec(void)
 {
 	ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
-	block_dev_desc_t *dev_desc = NULL;
+	struct blk_desc *dev_desc = NULL;
 	disk_partition_t info;
 	int dev, part;
 	int err;
 
-	part = get_device_and_partition(FAT_ENV_INTERFACE,
+	part = blk_get_device_part_str(FAT_ENV_INTERFACE,
 					FAT_ENV_DEVICE_AND_PART,
 					&dev_desc, &info, 1);
 	if (part < 0)
 		goto err_env_relocate;
 
-	dev = dev_desc->dev;
+	dev = dev_desc->devnum;
 	if (fat_set_blk_dev(dev_desc, &info) != 0) {
 		printf("\n** Unable to use %s %d:%d for loading the env **\n",
 		       FAT_ENV_INTERFACE, dev, part);
diff --git a/common/fb_mmc.c b/common/fb_mmc.c
index 6e742da..e3abcc8 100644
--- a/common/fb_mmc.c
+++ b/common/fb_mmc.c
@@ -6,6 +6,7 @@
 
 #include <config.h>
 #include <common.h>
+#include <blk.h>
 #include <errno.h>
 #include <fastboot.h>
 #include <fb_mmc.h>
@@ -22,15 +23,15 @@
 static char *response_str;
 
 struct fb_mmc_sparse {
-	block_dev_desc_t	*dev_desc;
+	struct blk_desc	*dev_desc;
 };
 
-static int get_partition_info_efi_by_name_or_alias(block_dev_desc_t *dev_desc,
+static int part_get_info_efi_by_name_or_alias(struct blk_desc *dev_desc,
 		const char *name, disk_partition_t *info)
 {
 	int ret;
 
-	ret = get_partition_info_efi_by_name(dev_desc, name, info);
+	ret = part_get_info_efi_by_name(dev_desc, name, info);
 	if (ret) {
 		/* strlen("fastboot_partition_alias_") + 32(part_name) + 1 */
 		char env_alias_name[25 + 32 + 1];
@@ -41,7 +42,7 @@
 		strncat(env_alias_name, name, 32);
 		aliased_part_name = getenv(env_alias_name);
 		if (aliased_part_name != NULL)
-			ret = get_partition_info_efi_by_name(dev_desc,
+			ret = part_get_info_efi_by_name(dev_desc,
 					aliased_part_name, info);
 	}
 	return ret;
@@ -55,17 +56,17 @@
 			       char *data)
 {
 	struct fb_mmc_sparse *sparse = priv;
-	block_dev_desc_t *dev_desc = sparse->dev_desc;
+	struct blk_desc *dev_desc = sparse->dev_desc;
 	int ret;
 
-	ret = dev_desc->block_write(dev_desc, offset, size, data);
+	ret = blk_dwrite(dev_desc, offset, size, data);
 	if (!ret)
 		return -EIO;
 
 	return ret;
 }
 
-static void write_raw_image(block_dev_desc_t *dev_desc, disk_partition_t *info,
+static void write_raw_image(struct blk_desc *dev_desc, disk_partition_t *info,
 		const char *part_name, void *buffer,
 		unsigned int download_bytes)
 {
@@ -84,9 +85,9 @@
 
 	puts("Flashing Raw Image\n");
 
-	blks = dev_desc->block_write(dev_desc, info->start, blkcnt, buffer);
+	blks = blk_dwrite(dev_desc, info->start, blkcnt, buffer);
 	if (blks != blkcnt) {
-		error("failed writing to device %d\n", dev_desc->dev);
+		error("failed writing to device %d\n", dev_desc->devnum);
 		fastboot_fail(response_str, "failed writing to device");
 		return;
 	}
@@ -100,13 +101,13 @@
 			void *download_buffer, unsigned int download_bytes,
 			char *response)
 {
-	block_dev_desc_t *dev_desc;
+	struct blk_desc *dev_desc;
 	disk_partition_t info;
 
 	/* initialize the response buffer */
 	response_str = response;
 
-	dev_desc = get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+	dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
 	if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
 		error("invalid mmc device\n");
 		fastboot_fail(response_str, "invalid mmc device");
@@ -131,7 +132,7 @@
 		printf("........ success\n");
 		fastboot_okay(response_str, "");
 		return;
-	} else if (get_partition_info_efi_by_name_or_alias(dev_desc, cmd, &info)) {
+	} else if (part_get_info_efi_by_name_or_alias(dev_desc, cmd, &info)) {
 		error("cannot find partition: '%s'\n", cmd);
 		fastboot_fail(response_str, "cannot find partition");
 		return;
@@ -165,7 +166,7 @@
 void fb_mmc_erase(const char *cmd, char *response)
 {
 	int ret;
-	block_dev_desc_t *dev_desc;
+	struct blk_desc *dev_desc;
 	disk_partition_t info;
 	lbaint_t blks, blks_start, blks_size, grp_size;
 	struct mmc *mmc = find_mmc_device(CONFIG_FASTBOOT_FLASH_MMC_DEV);
@@ -179,14 +180,14 @@
 	/* initialize the response buffer */
 	response_str = response;
 
-	dev_desc = get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+	dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
 	if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
 		error("invalid mmc device");
 		fastboot_fail(response_str, "invalid mmc device");
 		return;
 	}
 
-	ret = get_partition_info_efi_by_name_or_alias(dev_desc, cmd, &info);
+	ret = part_get_info_efi_by_name_or_alias(dev_desc, cmd, &info);
 	if (ret) {
 		error("cannot find partition: '%s'", cmd);
 		fastboot_fail(response_str, "cannot find partition");
@@ -207,7 +208,7 @@
 
 	blks = dev_desc->block_erase(dev_desc, blks_start, blks_size);
 	if (blks != blks_size) {
-		error("failed erasing from device %d", dev_desc->dev);
+		error("failed erasing from device %d", dev_desc->devnum);
 		fastboot_fail(response_str, "failed erasing from device");
 		return;
 	}
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 75d0858..ced119e 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -940,7 +940,8 @@
 /* Max address size we deal with */
 #define OF_MAX_ADDR_CELLS	4
 #define OF_BAD_ADDR	FDT_ADDR_T_NONE
-#define OF_CHECK_COUNTS(na)	((na) > 0 && (na) <= OF_MAX_ADDR_CELLS)
+#define OF_CHECK_COUNTS(na, ns)	((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \
+			(ns) > 0)
 
 /* Debug utility */
 #ifdef DEBUG
@@ -1108,7 +1109,7 @@
 
 	/* Cound address cells & copy address locally */
 	bus->count_cells(blob, parent, &na, &ns);
-	if (!OF_CHECK_COUNTS(na)) {
+	if (!OF_CHECK_COUNTS(na, ns)) {
 		printf("%s: Bad cell count for %s\n", __FUNCTION__,
 		       fdt_get_name(blob, node_offset, NULL));
 		goto bail;
@@ -1135,7 +1136,7 @@
 		/* Get new parent bus and counts */
 		pbus = &of_busses[0];
 		pbus->count_cells(blob, parent, &pna, &pns);
-		if (!OF_CHECK_COUNTS(pna)) {
+		if (!OF_CHECK_COUNTS(pna, pns)) {
 			printf("%s: Bad cell count for %s\n", __FUNCTION__,
 				fdt_get_name(blob, node_offset, NULL));
 			break;
diff --git a/common/image-fdt.c b/common/image-fdt.c
index 79fa655..6cac7db 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -231,7 +231,7 @@
 	ulong		fdt_addr;
 	char		*fdt_blob = NULL;
 	void		*buf;
-#if defined(CONFIG_FIT)
+#if CONFIG_IS_ENABLED(FIT)
 	const char	*fit_uname_config = images->fit_uname_cfg;
 	const char	*fit_uname_fdt = NULL;
 	ulong		default_addr;
@@ -246,7 +246,7 @@
 	if (argc > 2)
 		select = argv[2];
 	if (select || genimg_has_config(images)) {
-#if defined(CONFIG_FIT)
+#if CONFIG_IS_ENABLED(FIT)
 		if (select) {
 			/*
 			 * If the FDT blob comes from the FIT image and the
@@ -276,7 +276,7 @@
 				debug("*  fdt: cmdline image address = 0x%08lx\n",
 				      fdt_addr);
 			}
-#if defined(CONFIG_FIT)
+#if CONFIG_IS_ENABLED(FIT)
 		} else {
 			/* use FIT configuration provided in first bootm
 			 * command argument
@@ -351,7 +351,7 @@
 			 * (libfdt based) and raw FDT blob (also libfdt
 			 * based).
 			 */
-#if defined(CONFIG_FIT)
+#if CONFIG_IS_ENABLED(FIT)
 			/* check FDT blob vs FIT blob */
 			if (fit_check_format(buf)) {
 				ulong load, len;
@@ -502,8 +502,9 @@
 	fdt_fixup_ethernet(blob);
 
 	/* Delete the old LMB reservation */
-	lmb_free(lmb, (phys_addr_t)(u32)(uintptr_t)blob,
-		 (phys_size_t)fdt_totalsize(blob));
+	if (lmb)
+		lmb_free(lmb, (phys_addr_t)(u32)(uintptr_t)blob,
+			 (phys_size_t)fdt_totalsize(blob));
 
 	ret = fdt_shrink_to_minimum(blob);
 	if (ret < 0)
@@ -515,7 +516,8 @@
 		fdt_set_totalsize(blob, of_size);
 	}
 	/* Create a new LMB reservation */
-	lmb_reserve(lmb, (ulong)blob, of_size);
+	if (lmb)
+		lmb_reserve(lmb, (ulong)blob, of_size);
 
 	fdt_initrd(blob, *initrd_start, *initrd_end);
 	if (!ft_verify_fdt(blob))
diff --git a/common/image-fit.c b/common/image-fit.c
index fbd9e0d..25f8a11 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -433,7 +433,7 @@
 
 	if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
 	    (type == IH_TYPE_RAMDISK)) {
-		fit_image_get_entry(fit, image_noffset, &entry);
+		ret = fit_image_get_entry(fit, image_noffset, &entry);
 		printf("%s  Entry Point:  ", p);
 		if (ret)
 			printf("unavailable\n");
@@ -675,6 +675,34 @@
 	return 0;
 }
 
+static int fit_image_get_address(const void *fit, int noffset, char *name,
+			  ulong *load)
+{
+	int len, cell_len;
+	const fdt32_t *cell;
+	uint64_t load64 = 0;
+
+	cell = fdt_getprop(fit, noffset, name, &len);
+	if (cell == NULL) {
+		fit_get_debug(fit, noffset, name, len);
+		return -1;
+	}
+
+	if (len > sizeof(ulong)) {
+		printf("Unsupported %s address size\n", name);
+		return -1;
+	}
+
+	cell_len = len >> 2;
+	/* Use load64 to avoid compiling warning for 32-bit target */
+	while (cell_len--) {
+		load64 = (load64 << 32) | uimage_to_cpu(*cell);
+		cell++;
+	}
+	*load = (ulong)load64;
+
+	return 0;
+}
 /**
  * fit_image_get_load() - get load addr property for given component image node
  * @fit: pointer to the FIT format image header
@@ -690,17 +718,7 @@
  */
 int fit_image_get_load(const void *fit, int noffset, ulong *load)
 {
-	int len;
-	const uint32_t *data;
-
-	data = fdt_getprop(fit, noffset, FIT_LOAD_PROP, &len);
-	if (data == NULL) {
-		fit_get_debug(fit, noffset, FIT_LOAD_PROP, len);
-		return -1;
-	}
-
-	*load = uimage_to_cpu(*data);
-	return 0;
+	return fit_image_get_address(fit, noffset, FIT_LOAD_PROP, load);
 }
 
 /**
@@ -722,17 +740,7 @@
  */
 int fit_image_get_entry(const void *fit, int noffset, ulong *entry)
 {
-	int len;
-	const uint32_t *data;
-
-	data = fdt_getprop(fit, noffset, FIT_ENTRY_PROP, &len);
-	if (data == NULL) {
-		fit_get_debug(fit, noffset, FIT_ENTRY_PROP, len);
-		return -1;
-	}
-
-	*entry = uimage_to_cpu(*data);
-	return 0;
+	return fit_image_get_address(fit, noffset, FIT_ENTRY_PROP, entry);
 }
 
 /**
@@ -1101,8 +1109,9 @@
 			 * Direct child node of the images parent node,
 			 * i.e. component image node.
 			 */
-			printf("   Hash(es) for Image %u (%s): ", count++,
+			printf("   Hash(es) for Image %u (%s): ", count,
 			       fit_get_name(fit, noffset, NULL));
+			count++;
 
 			if (!fit_image_verify(fit, noffset))
 				return 0;
diff --git a/common/image.c b/common/image.c
index 1d7543d..26d6c9a 100644
--- a/common/image.c
+++ b/common/image.c
@@ -29,7 +29,7 @@
 #include <image.h>
 #include <mapmem.h>
 
-#if defined(CONFIG_FIT) || defined(CONFIG_OF_LIBFDT)
+#if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT
 #include <libfdt.h>
 #include <fdt_support.h>
 #endif
@@ -608,11 +608,9 @@
 	return (get_table_entry_name(uimage_type, "Unknown Image", type));
 }
 
-const char *genimg_get_type_short_name(uint8_t type)
+static const char *genimg_get_short_name(const table_entry_t *table, int val)
 {
-	const table_entry_t *table;
-
-	table = get_table_entry(uimage_type, type);
+	table = get_table_entry(table, val);
 	if (!table)
 		return "unknown";
 #if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC)
@@ -622,12 +620,32 @@
 #endif
 }
 
+const char *genimg_get_type_short_name(uint8_t type)
+{
+	return genimg_get_short_name(uimage_type, type);
+}
+
 const char *genimg_get_comp_name(uint8_t comp)
 {
 	return (get_table_entry_name(uimage_comp, "Unknown Compression",
 					comp));
 }
 
+const char *genimg_get_comp_short_name(uint8_t comp)
+{
+	return genimg_get_short_name(uimage_comp, comp);
+}
+
+const char *genimg_get_os_short_name(uint8_t os)
+{
+	return genimg_get_short_name(uimage_os, os);
+}
+
+const char *genimg_get_arch_short_name(uint8_t arch)
+{
+	return genimg_get_short_name(uimage_arch, arch);
+}
+
 /**
  * get_table_entry_id - translate short entry name to id
  * @table: pointer to a translation table for entries of a specific type
@@ -707,7 +725,7 @@
 		kernel_addr = load_addr;
 		debug("*  kernel: default image load address = 0x%08lx\n",
 		      load_addr);
-#if defined(CONFIG_FIT)
+#if CONFIG_IS_ENABLED(FIT)
 	} else if (fit_parse_conf(img_addr, load_addr, &kernel_addr,
 				  fit_uname_config)) {
 		debug("*  kernel: config '%s' from image at 0x%08lx\n",
@@ -762,7 +780,7 @@
 	if (image_check_magic(hdr))
 		return IMAGE_FORMAT_LEGACY;
 #endif
-#if defined(CONFIG_FIT) || defined(CONFIG_OF_LIBFDT)
+#if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT
 	if (fdt_check_header(img_addr) == 0)
 		return IMAGE_FORMAT_FIT;
 #endif
@@ -799,7 +817,7 @@
 
 		/* get header size */
 		h_size = image_get_header_size();
-#if defined(CONFIG_FIT)
+#if IMAGE_ENABLE_FIT
 		if (sizeof(struct fdt_header) > h_size)
 			h_size = sizeof(struct fdt_header);
 #endif
@@ -821,7 +839,7 @@
 					ram_addr, d_size);
 			break;
 #endif
-#if defined(CONFIG_FIT)
+#if IMAGE_ENABLE_FIT
 		case IMAGE_FORMAT_FIT:
 			d_size = fit_get_size(buf) - h_size;
 			debug("   FIT/FDT format image found at 0x%08lx, "
@@ -862,7 +880,7 @@
  */
 int genimg_has_config(bootm_headers_t *images)
 {
-#if defined(CONFIG_FIT)
+#if IMAGE_ENABLE_FIT
 	if (images->fit_uname_cfg)
 		return 1;
 #endif
@@ -903,7 +921,7 @@
 #ifdef CONFIG_SUPPORT_RAW_INITRD
 	char *end;
 #endif
-#if defined(CONFIG_FIT)
+#if IMAGE_ENABLE_FIT
 	const char	*fit_uname_config = images->fit_uname_cfg;
 	const char	*fit_uname_ramdisk = NULL;
 	ulong		default_addr;
@@ -934,7 +952,7 @@
 		debug("## Skipping init Ramdisk\n");
 		rd_len = rd_data = 0;
 	} else if (select || genimg_has_config(images)) {
-#if defined(CONFIG_FIT)
+#if IMAGE_ENABLE_FIT
 		if (select) {
 			/*
 			 * If the init ramdisk comes from the FIT image and
@@ -965,7 +983,7 @@
 						"0x%08lx\n",
 						rd_addr);
 			}
-#if defined(CONFIG_FIT)
+#if IMAGE_ENABLE_FIT
 		} else {
 			/* use FIT configuration provided in first bootm
 			 * command argument. If the property is not defined,
@@ -1008,7 +1026,7 @@
 			rd_load = image_get_load(rd_hdr);
 			break;
 #endif
-#if defined(CONFIG_FIT)
+#if IMAGE_ENABLE_FIT
 		case IMAGE_FORMAT_FIT:
 			rd_noffset = fit_image_load(images,
 					rd_addr, &fit_uname_ramdisk,
@@ -1184,14 +1202,14 @@
 int boot_get_setup(bootm_headers_t *images, uint8_t arch,
 		   ulong *setup_start, ulong *setup_len)
 {
-#if defined(CONFIG_FIT)
+#if IMAGE_ENABLE_FIT
 	return boot_get_setup_fit(images, arch, setup_start, setup_len);
 #else
 	return -ENOENT;
 #endif
 }
 
-#if defined(CONFIG_FIT)
+#if IMAGE_ENABLE_FIT
 int boot_get_loadable(int argc, char * const argv[], bootm_headers_t *images,
 		uint8_t arch, const ulong *ld_start, ulong * const ld_len)
 {
diff --git a/common/malloc_simple.c b/common/malloc_simple.c
index 479a1e4..0f6bcbc 100644
--- a/common/malloc_simple.c
+++ b/common/malloc_simple.c
@@ -19,12 +19,15 @@
 	void *ptr;
 
 	new_ptr = gd->malloc_ptr + bytes;
-	debug("%s: size=%zx, ptr=%lx, limit=%lx\n", __func__, bytes, new_ptr,
+	debug("%s: size=%zx, ptr=%lx, limit=%lx: ", __func__, bytes, new_ptr,
 	      gd->malloc_limit);
-	if (new_ptr > gd->malloc_limit)
+	if (new_ptr > gd->malloc_limit) {
+		debug("space exhausted\n");
 		return NULL;
+	}
 	ptr = map_sysmem(gd->malloc_base + gd->malloc_ptr, bytes);
 	gd->malloc_ptr = ALIGN(new_ptr, sizeof(new_ptr));
+	debug("%lx\n", (ulong)ptr);
 
 	return ptr;
 }
diff --git a/common/spl/Makefile b/common/spl/Makefile
index 10a4589..2e0f695 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -10,6 +10,7 @@
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
+obj-$(CONFIG_SPL_LOAD_FIT) += spl_fit.o
 obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o
 obj-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o
 obj-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o
diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index a42fbd0..b77dbf4 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -10,7 +10,7 @@
 #include <image.h>
 
 #ifdef CONFIG_SPL_EXT_SUPPORT
-int spl_load_image_ext(block_dev_desc_t *block_dev,
+int spl_load_image_ext(struct blk_desc *block_dev,
 						int partition,
 						const char *filename)
 {
@@ -22,8 +22,7 @@
 	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
 						sizeof(struct image_header));
 
-	if (get_partition_info(block_dev,
-			       partition, &part_info)) {
+	if (part_get_info(block_dev, partition, &part_info)) {
 		printf("spl: no partition table found\n");
 		return -1;
 	}
@@ -64,15 +63,14 @@
 }
 
 #ifdef CONFIG_SPL_OS_BOOT
-int spl_load_image_ext_os(block_dev_desc_t *block_dev, int partition)
+int spl_load_image_ext_os(struct blk_desc *block_dev, int partition)
 {
 	int err;
 	__maybe_unused loff_t filelen, actlen;
 	disk_partition_t part_info = {};
 	__maybe_unused char *file;
 
-	if (get_partition_info(block_dev,
-			       partition, &part_info)) {
+	if (part_get_info(block_dev, partition, &part_info)) {
 		printf("spl: no partition table found\n");
 		return -1;
 	}
@@ -137,7 +135,7 @@
 			CONFIG_SPL_FS_LOAD_KERNEL_NAME);
 }
 #else
-int spl_load_image_ext_os(block_dev_desc_t *block_dev, int partition)
+int spl_load_image_ext_os(struct blk_desc *block_dev, int partition)
 {
 	return -ENOSYS;
 }
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index 0daadbe..d761b26 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -19,7 +19,7 @@
 static int fat_registered;
 
 #ifdef CONFIG_SPL_FAT_SUPPORT
-static int spl_register_fat_device(block_dev_desc_t *block_dev, int partition)
+static int spl_register_fat_device(struct blk_desc *block_dev, int partition)
 {
 	int err = 0;
 
@@ -39,7 +39,7 @@
 	return err;
 }
 
-int spl_load_image_fat(block_dev_desc_t *block_dev,
+int spl_load_image_fat(struct blk_desc *block_dev,
 						int partition,
 						const char *filename)
 {
@@ -72,7 +72,7 @@
 }
 
 #ifdef CONFIG_SPL_OS_BOOT
-int spl_load_image_fat_os(block_dev_desc_t *block_dev, int partition)
+int spl_load_image_fat_os(struct blk_desc *block_dev, int partition)
 {
 	int err;
 	__maybe_unused char *file;
@@ -121,7 +121,7 @@
 			CONFIG_SPL_FS_LOAD_KERNEL_NAME);
 }
 #else
-int spl_load_image_fat_os(block_dev_desc_t *block_dev, int partition)
+int spl_load_image_fat_os(struct blk_desc *block_dev, int partition)
 {
 	return -ENOSYS;
 }
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
new file mode 100644
index 0000000..1a5c027
--- /dev/null
+++ b/common/spl/spl_fit.c
@@ -0,0 +1,194 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <image.h>
+#include <libfdt.h>
+#include <spl.h>
+
+static ulong fdt_getprop_u32(const void *fdt, int node, const char *prop)
+{
+	const u32 *cell;
+	int len;
+
+	cell = fdt_getprop(fdt, node, prop, &len);
+	if (len != sizeof(*cell))
+		return -1U;
+	return fdt32_to_cpu(*cell);
+}
+
+static int spl_fit_select_fdt(const void *fdt, int images, int *fdt_offsetp)
+{
+	const char *name, *fdt_name;
+	int conf, node, fdt_node;
+	int len;
+
+	*fdt_offsetp = 0;
+	conf = fdt_path_offset(fdt, FIT_CONFS_PATH);
+	if (conf < 0) {
+		debug("%s: Cannot find /configurations node: %d\n", __func__,
+		      conf);
+		return -EINVAL;
+	}
+	for (node = fdt_first_subnode(fdt, conf);
+	     node >= 0;
+	     node = fdt_next_subnode(fdt, node)) {
+		name = fdt_getprop(fdt, node, "description", &len);
+		if (!name)
+			return -EINVAL;
+		if (board_fit_config_name_match(name))
+			continue;
+
+		debug("Selecting config '%s'", name);
+		fdt_name = fdt_getprop(fdt, node, FIT_FDT_PROP, &len);
+		if (!fdt_name) {
+			debug("%s: Cannot find fdt name property: %d\n",
+			      __func__, len);
+			return -EINVAL;
+		}
+
+		debug(", fdt '%s'\n", fdt_name);
+		fdt_node = fdt_subnode_offset(fdt, images, fdt_name);
+		if (fdt_node < 0) {
+			debug("%s: Cannot find fdt node '%s': %d\n",
+			      __func__, fdt_name, fdt_node);
+			return -EINVAL;
+		}
+
+		*fdt_offsetp = fdt_getprop_u32(fdt, fdt_node, "data-offset");
+		len = fdt_getprop_u32(fdt, fdt_node, "data-size");
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+		printf("FIT: Selected '%s'\n", name);
+#endif
+
+		return len;
+	}
+
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+	printf("No matching DT out of these options:\n");
+	for (node = fdt_first_subnode(fdt, conf);
+	     node >= 0;
+	     node = fdt_next_subnode(fdt, node)) {
+		name = fdt_getprop(fdt, node, "name", &len);
+		printf("   %s\n", name);
+	}
+#endif
+
+	return -ENOENT;
+}
+
+int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
+{
+	int sectors;
+	ulong size, load;
+	unsigned long count;
+	int node, images;
+	void *load_ptr;
+	int fdt_offset, fdt_len;
+	int data_offset, data_size;
+	int base_offset;
+	int src_sector;
+	void *dst;
+
+	/*
+	 * Figure out where the external images start. This is the base for the
+	 * data-offset properties in each image.
+	 */
+	size = fdt_totalsize(fit);
+	size = (size + 3) & ~3;
+	base_offset = (size + 3) & ~3;
+
+	/*
+	 * So far we only have one block of data from the FIT. Read the entire
+	 * thing, including that first block, placing it so it finishes before
+	 * where we will load the image.
+	 *
+	 * Note that we will load the image such that its first byte will be
+	 * at the load address. Since that byte may be part-way through a
+	 * block, we may load the image up to one block before the load
+	 * address. So take account of that here by subtracting an addition
+	 * block length from the FIT start position.
+	 *
+	 * In fact the FIT has its own load address, but we assume it cannot
+	 * be before CONFIG_SYS_TEXT_BASE.
+	 */
+	fit = (void *)(CONFIG_SYS_TEXT_BASE - size - info->bl_len);
+	sectors = (size + info->bl_len - 1) / info->bl_len;
+	count = info->read(info, sector, sectors, fit);
+	debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu\n",
+	      sector, sectors, fit, count);
+	if (count == 0)
+		return -EIO;
+
+	/* find the firmware image to load */
+	images = fdt_path_offset(fit, FIT_IMAGES_PATH);
+	if (images < 0) {
+		debug("%s: Cannot find /images node: %d\n", __func__, images);
+		return -1;
+	}
+	node = fdt_first_subnode(fit, images);
+	if (node < 0) {
+		debug("%s: Cannot find first image node: %d\n", __func__, node);
+		return -1;
+	}
+
+	/* Get its information and set up the spl_image structure */
+	data_offset = fdt_getprop_u32(fit, node, "data-offset");
+	data_size = fdt_getprop_u32(fit, node, "data-size");
+	load = fdt_getprop_u32(fit, node, "load");
+	debug("data_offset=%x, data_size=%x\n", data_offset, data_size);
+	spl_image.load_addr = load;
+	spl_image.entry_point = load;
+	spl_image.os = IH_OS_U_BOOT;
+
+	/*
+	 * Work out where to place the image. We read it so that the first
+	 * byte will be at 'load'. This may mean we need to load it starting
+	 * before then, since we can only read whole blocks.
+	 */
+	sectors = (data_size + info->bl_len - 1) / info->bl_len;
+	data_offset += base_offset;
+	load_ptr = (void *)load;
+	debug("U-Boot size %x, data %p\n", data_size, load_ptr);
+	dst = load_ptr - (data_offset % info->bl_len);
+
+	/* Read the image */
+	src_sector = sector + data_offset / info->bl_len;
+	debug("image: data_offset=%x, dst=%p, src_sector=%x, sectors=%x\n",
+	      data_offset, dst, src_sector, sectors);
+	count = info->read(info, src_sector, sectors, dst);
+	if (count != sectors)
+		return -EIO;
+
+	/* Figure out which device tree the board wants to use */
+	fdt_len = spl_fit_select_fdt(fit, images, &fdt_offset);
+	if (fdt_len < 0)
+		return fdt_len;
+
+	/*
+	 * Read the device tree and place it after the image. There may be
+	 * some extra data before it since we can only read entire blocks.
+	 */
+	dst = load_ptr + data_size;
+	fdt_offset += base_offset;
+	count = info->read(info, sector + fdt_offset / info->bl_len, sectors,
+			   dst);
+	debug("fit read %x sectors to %x, dst %p, data_offset %x\n",
+	      sectors, spl_image.load_addr, dst, fdt_offset);
+	if (count != sectors)
+		return -EIO;
+
+	/*
+	 * Copy the device tree so that it starts immediately after the image.
+	 * After this we will have the U-Boot image and its device tree ready
+	 * for us to start.
+	 */
+	memcpy(dst, dst + fdt_offset % info->bl_len, fdt_len);
+
+	return 0;
+}
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index c27a250..c0e76be 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -18,41 +18,80 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static int mmc_load_legacy(struct mmc *mmc, ulong sector,
+			   struct image_header *header)
+{
+	u32 image_size_sectors;
+	unsigned long count;
+
+	spl_parse_image_header(header);
+	/* convert size to sectors - round up */
+	image_size_sectors = (spl_image.size + mmc->read_bl_len - 1) /
+			     mmc->read_bl_len;
+
+	/* Read the header too to avoid extra memcpy */
+	count = mmc->block_dev.block_read(&mmc->block_dev, sector,
+					  image_size_sectors,
+					  (void *)(ulong)spl_image.load_addr);
+	debug("read %x sectors to %x\n", image_size_sectors,
+	      spl_image.load_addr);
+	if (count != image_size_sectors)
+		return -EIO;
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+static ulong h_spl_load_read(struct spl_load_info *load, ulong sector,
+			     ulong count, void *buf)
+{
+	struct mmc *mmc = load->dev;
+
+	return mmc->block_dev.block_read(&mmc->block_dev, sector, count, buf);
+}
+#endif
+
 static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector)
 {
 	unsigned long count;
-	u32 image_size_sectors;
 	struct image_header *header;
+	int ret = 0;
 
 	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
 					 sizeof(struct image_header));
 
 	/* read image header to find the image size & load address */
 	count = mmc->block_dev.block_read(&mmc->block_dev, sector, 1, header);
-	debug("read sector %lx, count=%lu\n", sector, count);
-	if (count == 0)
+	debug("hdr read sector %lx, count=%lu\n", sector, count);
+	if (count == 0) {
+		ret = -EIO;
 		goto end;
+	}
 
-	if (image_get_magic(header) != IH_MAGIC) {
+	switch (image_get_magic(header)) {
+	case IH_MAGIC:
+		ret = mmc_load_legacy(mmc, sector, header);
+		break;
+#ifdef CONFIG_SPL_LOAD_FIT
+	case FDT_MAGIC: {
+		struct spl_load_info load;
+
+		debug("Found FIT\n");
+		load.dev = mmc;
+		load.priv = NULL;
+		load.bl_len = mmc->read_bl_len;
+		load.read = h_spl_load_read;
+		ret = spl_load_simple_fit(&load, sector, header);
+		break;
+	}
+#endif
+	default:
 		puts("bad magic\n");
 		return -1;
 	}
 
-	spl_parse_image_header(header);
-
-	/* convert size to sectors - round up */
-	image_size_sectors = (spl_image.size + mmc->read_bl_len - 1) /
-			     mmc->read_bl_len;
-
-	/* Read the header too to avoid extra memcpy */
-	count = mmc->block_dev.block_read(&mmc->block_dev, sector,
-					  image_size_sectors,
-					  (void *)(ulong)spl_image.load_addr);
-	debug("read %x sectors to %x\n", image_size_sectors,
-	      spl_image.load_addr);
-
 end:
-	if (count == 0) {
+	if (ret) {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
 		puts("spl: mmc block read error\n");
 #endif
@@ -122,7 +161,7 @@
 	disk_partition_t info;
 	int err;
 
-	err = get_partition_info(&mmc->block_dev, partition, &info);
+	err = part_get_info(&mmc->block_dev, partition, &info);
 	if (err) {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
 		puts("spl: partition error\n");
diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
index e08afe2..d0bd0b0 100644
--- a/common/spl/spl_nor.c
+++ b/common/spl/spl_nor.c
@@ -59,7 +59,7 @@
 	spl_parse_image_header(
 			(const struct image_header *)CONFIG_SYS_UBOOT_BASE);
 
-	memcpy((void *)spl_image.load_addr,
+	memcpy((void *)(unsigned long)spl_image.load_addr,
 	       (void *)(CONFIG_SYS_UBOOT_BASE + sizeof(struct image_header)),
 	       spl_image.size);
 
diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c
index 3ba4c24..1719946 100644
--- a/common/spl/spl_sata.c
+++ b/common/spl/spl_sata.c
@@ -23,7 +23,7 @@
 int spl_sata_load_image(void)
 {
 	int err;
-	block_dev_desc_t *stor_dev;
+	struct blk_desc *stor_dev;
 
 	err = init_sata(CONFIG_SPL_SATA_BOOT_DEVICE);
 	if (err) {
diff --git a/common/spl/spl_usb.c b/common/spl/spl_usb.c
index 588b85c..c42848e 100644
--- a/common/spl/spl_usb.c
+++ b/common/spl/spl_usb.c
@@ -25,7 +25,7 @@
 int spl_usb_load_image(void)
 {
 	int err;
-	block_dev_desc_t *stor_dev;
+	struct blk_desc *stor_dev;
 
 	usb_stop();
 	err = usb_init();
diff --git a/common/usb_storage.c b/common/usb_storage.c
index 8737cf7..1472824 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -43,6 +43,7 @@
 #include <asm/byteorder.h>
 #include <asm/processor.h>
 #include <dm/device-internal.h>
+#include <dm/lists.h>
 
 #include <part.h>
 #include <usb.h>
@@ -67,7 +68,9 @@
 
 static int usb_max_devs; /* number of highest available usb device */
 
-static block_dev_desc_t usb_dev_desc[USB_MAX_STOR_DEV];
+#ifndef CONFIG_BLK
+static struct blk_desc usb_dev_desc[USB_MAX_STOR_DEV];
+#endif
 
 struct us_data;
 typedef int (*trans_cmnd)(ccb *cb, struct us_data *data);
@@ -108,26 +111,45 @@
 #define USB_MAX_XFER_BLK	20
 #endif
 
+#ifndef CONFIG_BLK
 static struct us_data usb_stor[USB_MAX_STOR_DEV];
+#endif
 
 #define USB_STOR_TRANSPORT_GOOD	   0
 #define USB_STOR_TRANSPORT_FAILED -1
 #define USB_STOR_TRANSPORT_ERROR  -2
 
 int usb_stor_get_info(struct usb_device *dev, struct us_data *us,
-		      block_dev_desc_t *dev_desc);
+		      struct blk_desc *dev_desc);
 int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,
 		      struct us_data *ss);
-static unsigned long usb_stor_read(block_dev_desc_t *block_dev, lbaint_t blknr,
+#ifdef CONFIG_BLK
+static unsigned long usb_stor_read(struct udevice *dev, lbaint_t blknr,
+				   lbaint_t blkcnt, void *buffer);
+static unsigned long usb_stor_write(struct udevice *dev, lbaint_t blknr,
+				    lbaint_t blkcnt, const void *buffer);
+#else
+static unsigned long usb_stor_read(struct blk_desc *block_dev, lbaint_t blknr,
 				   lbaint_t blkcnt, void *buffer);
-static unsigned long usb_stor_write(block_dev_desc_t *block_dev, lbaint_t blknr,
+static unsigned long usb_stor_write(struct blk_desc *block_dev, lbaint_t blknr,
 				    lbaint_t blkcnt, const void *buffer);
+#endif
 void uhci_show_temp_int_td(void);
 
 #ifdef CONFIG_PARTITIONS
-block_dev_desc_t *usb_stor_get_dev(int index)
+struct blk_desc *usb_stor_get_dev(int index)
 {
+#ifdef CONFIG_BLK
+	struct udevice *dev;
+	int ret;
+
+	ret = blk_get_device(IF_TYPE_USB, index, &dev);
+	if (ret)
+		return NULL;
+	return dev_get_uclass_platdata(dev);
+#else
 	return (index < usb_max_devs) ? &usb_dev_desc[index] : NULL;
+#endif
 }
 #endif
 
@@ -142,6 +164,20 @@
  */
 int usb_stor_info(void)
 {
+	int count = 0;
+#ifdef CONFIG_BLK
+	struct udevice *dev;
+
+	for (blk_first_device(IF_TYPE_USB, &dev);
+	     dev;
+	     blk_next_device(&dev)) {
+		struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+		printf("  Device %d: ", desc->devnum);
+		dev_print(desc);
+		count++;
+	}
+#else
 	int i;
 
 	if (usb_max_devs > 0) {
@@ -151,8 +187,12 @@
 		}
 		return 0;
 	}
+#endif
+	if (!count) {
+		printf("No storage devices, perhaps not 'usb start'ed..?\n");
+		return 1;
+	}
 
-	printf("No storage devices, perhaps not 'usb start'ed..?\n");
 	return 1;
 }
 
@@ -171,52 +211,110 @@
 	return (len > 0) ? *result : 0;
 }
 
-static int usb_stor_probe_device(struct usb_device *dev)
+static int usb_stor_probe_device(struct usb_device *udev)
 {
-	if (dev == NULL)
+	int lun, max_lun;
+
+#ifdef CONFIG_BLK
+	struct us_data *data;
+	char dev_name[30], *str;
+	int ret;
+#else
+	int start;
+
+	if (udev == NULL)
 		return -ENOENT; /* no more devices available */
+#endif
 
 	debug("\n\nProbing for storage\n");
-	if (usb_storage_probe(dev, 0, &usb_stor[usb_max_devs])) {
-		/* OK, it's a storage device.  Iterate over its LUNs
-			* and populate `usb_dev_desc'.
-			*/
-		int lun, max_lun, start = usb_max_devs;
+#ifdef CONFIG_BLK
+	/*
+	 * We store the us_data in the mass storage device's platdata. It
+	 * is shared by all LUNs (block devices) attached to this mass storage
+	 * device.
+	 */
+	data = dev_get_platdata(udev->dev);
+	if (!usb_storage_probe(udev, 0, data))
+		return 0;
+	max_lun = usb_get_max_lun(data);
+	for (lun = 0; lun <= max_lun; lun++) {
+		struct blk_desc *blkdev;
+		struct udevice *dev;
 
-		max_lun = usb_get_max_lun(&usb_stor[usb_max_devs]);
-		for (lun = 0;
-			lun <= max_lun && usb_max_devs < USB_MAX_STOR_DEV;
-			lun++) {
-			struct block_dev_desc *blkdev;
+		snprintf(dev_name, sizeof(dev_name), "%s.lun%d",
+			 udev->dev->name, lun);
+		str = strdup(dev_name);
+		if (!str)
+			return -ENOMEM;
+		ret = blk_create_device(udev->dev, "usb_storage_blk", str,
+				IF_TYPE_USB, usb_max_devs, 512, 0, &dev);
+		if (ret) {
+			debug("Cannot bind driver\n");
+			return ret;
+		}
 
-			blkdev = &usb_dev_desc[usb_max_devs];
-			memset(blkdev, '\0', sizeof(block_dev_desc_t));
-			blkdev->if_type = IF_TYPE_USB;
-			blkdev->dev = usb_max_devs;
-			blkdev->part_type = PART_TYPE_UNKNOWN;
-			blkdev->target = 0xff;
-			blkdev->type = DEV_TYPE_UNKNOWN;
-			blkdev->block_read = usb_stor_read;
-			blkdev->block_write = usb_stor_write;
-			blkdev->lun = lun;
-			blkdev->priv = dev;
+		blkdev = dev_get_uclass_platdata(dev);
+		blkdev->target = 0xff;
+		blkdev->lun = lun;
 
-			if (usb_stor_get_info(dev, &usb_stor[start],
-					      &usb_dev_desc[usb_max_devs]) ==
-					      1) {
-				usb_max_devs++;
-				debug("%s: Found device %p\n", __func__, dev);
-			}
+		ret = usb_stor_get_info(udev, data, blkdev);
+		if (ret == 1)
+			ret = blk_prepare_device(dev);
+		if (!ret) {
+			usb_max_devs++;
+			debug("%s: Found device %p\n", __func__, udev);
+		} else {
+			debug("usb_stor_get_info: Invalid device\n");
+			ret = device_unbind(dev);
+			if (ret)
+				return ret;
 		}
 	}
-
-	/* if storage device */
+#else
+	/* We don't have space to even probe if we hit the maximum */
 	if (usb_max_devs == USB_MAX_STOR_DEV) {
 		printf("max USB Storage Device reached: %d stopping\n",
 		       usb_max_devs);
 		return -ENOSPC;
 	}
 
+	if (!usb_storage_probe(udev, 0, &usb_stor[usb_max_devs]))
+		return 0;
+
+	/*
+	 * OK, it's a storage device.  Iterate over its LUNs and populate
+	 * usb_dev_desc'
+	 */
+	start = usb_max_devs;
+
+	max_lun = usb_get_max_lun(&usb_stor[usb_max_devs]);
+	for (lun = 0; lun <= max_lun && usb_max_devs < USB_MAX_STOR_DEV;
+	     lun++) {
+		struct blk_desc *blkdev;
+
+		blkdev = &usb_dev_desc[usb_max_devs];
+		memset(blkdev, '\0', sizeof(struct blk_desc));
+		blkdev->if_type = IF_TYPE_USB;
+		blkdev->devnum = usb_max_devs;
+		blkdev->part_type = PART_TYPE_UNKNOWN;
+		blkdev->target = 0xff;
+		blkdev->type = DEV_TYPE_UNKNOWN;
+		blkdev->block_read = usb_stor_read;
+		blkdev->block_write = usb_stor_write;
+		blkdev->lun = lun;
+		blkdev->priv = udev;
+
+		if (usb_stor_get_info(udev, &usb_stor[start],
+				      &usb_dev_desc[usb_max_devs]) == 1) {
+			debug("partype: %d\n", blkdev->part_type);
+			part_init(blkdev);
+			debug("partype: %d\n", blkdev->part_type);
+			usb_max_devs++;
+			debug("%s: Found device %p\n", __func__, udev);
+		}
+	}
+#endif
+
 	return 0;
 }
 
@@ -1011,7 +1109,7 @@
  * device with proper values (as reported by 'usb info').
  *
  * Vendor and product length limits are taken from the definition of
- * block_dev_desc_t in include/part.h.
+ * struct blk_desc in include/part.h.
  */
 static void usb_bin_fixup(struct usb_device_descriptor descriptor,
 				unsigned char vendor[],
@@ -1026,39 +1124,50 @@
 }
 #endif /* CONFIG_USB_BIN_FIXUP */
 
-static unsigned long usb_stor_read(block_dev_desc_t *block_dev, lbaint_t blknr,
+#ifdef CONFIG_BLK
+static unsigned long usb_stor_read(struct udevice *dev, lbaint_t blknr,
+				   lbaint_t blkcnt, void *buffer)
+#else
+static unsigned long usb_stor_read(struct blk_desc *block_dev, lbaint_t blknr,
 				   lbaint_t blkcnt, void *buffer)
+#endif
 {
-	int device = block_dev->dev;
 	lbaint_t start, blks;
 	uintptr_t buf_addr;
 	unsigned short smallblks;
-	struct usb_device *dev;
+	struct usb_device *udev;
 	struct us_data *ss;
 	int retry;
 	ccb *srb = &usb_ccb;
+#ifdef CONFIG_BLK
+	struct blk_desc *block_dev;
+#endif
 
 	if (blkcnt == 0)
 		return 0;
-
-	device &= 0xff;
 	/* Setup  device */
-	debug("\nusb_read: dev %d\n", device);
-	dev = usb_dev_desc[device].priv;
-	if (!dev) {
+#ifdef CONFIG_BLK
+	block_dev = dev_get_uclass_platdata(dev);
+	udev = dev_get_parent_priv(dev_get_parent(dev));
+	debug("\nusb_read: udev %d\n", block_dev->devnum);
+#else
+	debug("\nusb_read: udev %d\n", block_dev->devnum);
+	udev = usb_dev_desc[block_dev->devnum].priv;
+	if (!udev) {
 		debug("%s: No device\n", __func__);
 		return 0;
 	}
-	ss = (struct us_data *)dev->privptr;
+#endif
+	ss = (struct us_data *)udev->privptr;
 
 	usb_disable_asynch(1); /* asynch transfer not allowed */
-	srb->lun = usb_dev_desc[device].lun;
+	srb->lun = block_dev->lun;
 	buf_addr = (uintptr_t)buffer;
 	start = blknr;
 	blks = blkcnt;
 
-	debug("\nusb_read: dev %d startblk " LBAF ", blccnt " LBAF
-	      " buffer %" PRIxPTR "\n", device, start, blks, buf_addr);
+	debug("\nusb_read: dev %d startblk " LBAF ", blccnt " LBAF " buffer %"
+	      PRIxPTR "\n", block_dev->devnum, start, blks, buf_addr);
 
 	do {
 		/* XXX need some comment here */
@@ -1071,7 +1180,7 @@
 retry_it:
 		if (smallblks == USB_MAX_XFER_BLK)
 			usb_show_progress();
-		srb->datalen = usb_dev_desc[device].blksz * smallblks;
+		srb->datalen = block_dev->blksz * smallblks;
 		srb->pdata = (unsigned char *)buf_addr;
 		if (usb_read_10(srb, ss, start, smallblks)) {
 			debug("Read ERROR\n");
@@ -1097,38 +1206,52 @@
 	return blkcnt;
 }
 
-static unsigned long usb_stor_write(block_dev_desc_t *block_dev, lbaint_t blknr,
+#ifdef CONFIG_BLK
+static unsigned long usb_stor_write(struct udevice *dev, lbaint_t blknr,
+				    lbaint_t blkcnt, const void *buffer)
+#else
+static unsigned long usb_stor_write(struct blk_desc *block_dev, lbaint_t blknr,
 				    lbaint_t blkcnt, const void *buffer)
+#endif
 {
-	int device = block_dev->dev;
 	lbaint_t start, blks;
 	uintptr_t buf_addr;
 	unsigned short smallblks;
-	struct usb_device *dev;
+	struct usb_device *udev;
 	struct us_data *ss;
 	int retry;
 	ccb *srb = &usb_ccb;
+#ifdef CONFIG_BLK
+	struct blk_desc *block_dev;
+#endif
 
 	if (blkcnt == 0)
 		return 0;
 
-	device &= 0xff;
 	/* Setup  device */
-	debug("\nusb_write: dev %d\n", device);
-	dev = usb_dev_desc[device].priv;
-	if (!dev)
+#ifdef CONFIG_BLK
+	block_dev = dev_get_uclass_platdata(dev);
+	udev = dev_get_parent_priv(dev_get_parent(dev));
+	debug("\nusb_read: udev %d\n", block_dev->devnum);
+#else
+	debug("\nusb_read: udev %d\n", block_dev->devnum);
+	udev = usb_dev_desc[block_dev->devnum].priv;
+	if (!udev) {
+		debug("%s: No device\n", __func__);
 		return 0;
-	ss = (struct us_data *)dev->privptr;
+	}
+#endif
+	ss = (struct us_data *)udev->privptr;
 
 	usb_disable_asynch(1); /* asynch transfer not allowed */
 
-	srb->lun = usb_dev_desc[device].lun;
+	srb->lun = block_dev->lun;
 	buf_addr = (uintptr_t)buffer;
 	start = blknr;
 	blks = blkcnt;
 
-	debug("\nusb_write: dev %d startblk " LBAF ", blccnt " LBAF
-	      " buffer %" PRIxPTR "\n", device, start, blks, buf_addr);
+	debug("\nusb_write: dev %d startblk " LBAF ", blccnt " LBAF " buffer %"
+	      PRIxPTR "\n", block_dev->devnum, start, blks, buf_addr);
 
 	do {
 		/* If write fails retry for max retry count else
@@ -1143,7 +1266,7 @@
 retry_it:
 		if (smallblks == USB_MAX_XFER_BLK)
 			usb_show_progress();
-		srb->datalen = usb_dev_desc[device].blksz * smallblks;
+		srb->datalen = block_dev->blksz * smallblks;
 		srb->pdata = (unsigned char *)buf_addr;
 		if (usb_write_10(srb, ss, start, smallblks)) {
 			debug("Write ERROR\n");
@@ -1289,7 +1412,7 @@
 }
 
 int usb_stor_get_info(struct usb_device *dev, struct us_data *ss,
-		      block_dev_desc_t *dev_desc)
+		      struct blk_desc *dev_desc)
 {
 	unsigned char perq, modi;
 	ALLOC_CACHE_ALIGN_BUFFER(u32, cap, 2);
@@ -1372,11 +1495,7 @@
 	dev_desc->log2blksz = LOG2(dev_desc->blksz);
 	dev_desc->type = perq;
 	debug(" address %d\n", dev_desc->target);
-	debug("partype: %d\n", dev_desc->part_type);
-
-	init_part(dev_desc);
 
-	debug("partype: %d\n", dev_desc->part_type);
 	return 1;
 }
 
@@ -1404,6 +1523,9 @@
 	.id	= UCLASS_MASS_STORAGE,
 	.of_match = usb_mass_storage_ids,
 	.probe = usb_mass_storage_probe,
+#ifdef CONFIG_BLK
+	.platdata_auto_alloc_size	= sizeof(struct us_data),
+#endif
 };
 
 UCLASS_DRIVER(usb_mass_storage) = {
@@ -1420,5 +1542,17 @@
 };
 
 U_BOOT_USB_DEVICE(usb_mass_storage, mass_storage_id_table);
+#endif
 
+#ifdef CONFIG_BLK
+static const struct blk_ops usb_storage_ops = {
+	.read	= usb_stor_read,
+	.write	= usb_stor_write,
+};
+
+U_BOOT_DRIVER(usb_storage_blk) = {
+	.name		= "usb_storage_blk",
+	.id		= UCLASS_BLK,
+	.ops		= &usb_storage_ops,
+};
 #endif
diff --git a/common/xyzModem.c b/common/xyzModem.c
index 56f4bca..5656aac 100644
--- a/common/xyzModem.c
+++ b/common/xyzModem.c
@@ -446,7 +446,7 @@
   /* Verify checksum/CRC */
   if (xyz.crc_mode)
     {
-      cksum = cyg_crc16 (xyz.pkt, xyz.len);
+      cksum = crc16_ccitt(0, xyz.pkt, xyz.len);
       if (cksum != ((xyz.crc1 << 8) | xyz.crc2))
 	{
 	  ZM_DEBUG (zm_dprintf ("CRC error - recvd: %02x%02x, computed: %x\n",
diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig
index a0d29a0..d4b768d 100644
--- a/configs/10m50_defconfig
+++ b/configs/10m50_defconfig
@@ -4,6 +4,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="10m50_devboard"
 CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig
index 9d249c7..5fdaee0 100644
--- a/configs/3c120_defconfig
+++ b/configs/3c120_defconfig
@@ -4,6 +4,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard"
 CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index af96f5b..6235d1f 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -8,6 +8,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig
index cba2cfd..3cddc12 100644
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -9,6 +9,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index 45cc5ab..6000d9b 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -13,6 +13,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index 11691a2..6342f6b 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -15,6 +15,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index b5181c6..95c67d6 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -8,6 +8,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
index e27698d..dc6413b 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -6,6 +6,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index 03481f6..13a3999 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -9,6 +9,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index 001d31b..66d8f98 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -11,6 +11,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig
index 67bea5a..cf9f161 100644
--- a/configs/Ainol_AW1_defconfig
+++ b/configs/Ainol_AW1_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ainol-aw1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig
index 82e01ba..949f1e0 100644
--- a/configs/Ampe_A76_defconfig
+++ b/configs/Ampe_A76_defconfig
@@ -15,6 +15,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig
index 8f1be3e..f149b67 100644
--- a/configs/Auxtek-T003_defconfig
+++ b/configs/Auxtek-T003_defconfig
@@ -8,6 +8,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t003"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig
index 434b007..c176059 100644
--- a/configs/Auxtek-T004_defconfig
+++ b/configs/Auxtek-T004_defconfig
@@ -6,6 +6,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig
index e50833a..0e2b0a8 100644
--- a/configs/B4420QDS_NAND_defconfig
+++ b/configs/B4420QDS_NAND_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4860QDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/B4420QDS_SPIFLASH_defconfig b/configs/B4420QDS_SPIFLASH_defconfig
index b53a1cf..98751919 100644
--- a/configs/B4420QDS_SPIFLASH_defconfig
+++ b/configs/B4420QDS_SPIFLASH_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4860QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/B4420QDS_defconfig b/configs/B4420QDS_defconfig
index 8308b95..c2f903b 100644
--- a/configs/B4420QDS_defconfig
+++ b/configs/B4420QDS_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4860QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig
index a8f05db..5533cb3 100644
--- a/configs/B4860QDS_NAND_defconfig
+++ b/configs/B4860QDS_NAND_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4860QDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig
index 1a61dc3..051dccb 100644
--- a/configs/B4860QDS_SECURE_BOOT_defconfig
+++ b/configs/B4860QDS_SECURE_BOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4860QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/B4860QDS_SPIFLASH_defconfig b/configs/B4860QDS_SPIFLASH_defconfig
index 0875ee7..e6807df 100644
--- a/configs/B4860QDS_SPIFLASH_defconfig
+++ b/configs/B4860QDS_SPIFLASH_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4860QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
index 11db5bc..b7832db 100644
--- a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4860QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/B4860QDS_defconfig b/configs/B4860QDS_defconfig
index 54ceec7b..e68c19f 100644
--- a/configs/B4860QDS_defconfig
+++ b/configs/B4860QDS_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4860QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
index 5e0e09b..a199806 100644
--- a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9131RDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND,SYS_CLK_100"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -9,3 +13,4 @@
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/BSC9131RDB_NAND_defconfig b/configs/BSC9131RDB_NAND_defconfig
index 4f666f1..1f2d2b8 100644
--- a/configs/BSC9131RDB_NAND_defconfig
+++ b/configs/BSC9131RDB_NAND_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9131RDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -9,3 +13,4 @@
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
index ca90c83..e9c3723 100644
--- a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9131RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH,SYS_CLK_100"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -8,3 +12,4 @@
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/BSC9131RDB_SPIFLASH_defconfig b/configs/BSC9131RDB_SPIFLASH_defconfig
index 2902a68..f46c0ca 100644
--- a/configs/BSC9131RDB_SPIFLASH_defconfig
+++ b/configs/BSC9131RDB_SPIFLASH_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9131RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -8,3 +12,4 @@
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
index 15e3862..b3829f5 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
index 48f1c3c..88f2ade 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_100"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
index b909789..568470b 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
index 06b411d..58bf069 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_133"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
index 6f37d36..13e8325 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
index 4993dc9..92c4e28 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
index d69047e..291c879 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
index f9129ca..bb49265 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
index d11e9e3..076a99e 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
index 4c22ce6..3e21ef4 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
index f350c34..5c4ba30 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
index 1862f0c..047f315 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
index 5173a5b..1aa92e5 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
index a1a5cd3..66500e7 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
index 14ed190..3531479 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
index 6e5fbaf..7ceec10 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index 6cbb76c..f7e0bb7 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -7,6 +7,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index 4f4a07be..9197b00 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -9,6 +9,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -16,5 +17,5 @@
 CONFIG_CMD_GPIO=y
 CONFIG_NETCONSOLE=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_USB_EHCI_HCD=y
 CONFIG_AXP_ALDO4_VOLT=2500
+CONFIG_USB_EHCI_HCD=y
diff --git a/configs/C29XPCIE_NAND_defconfig b/configs/C29XPCIE_NAND_defconfig
index bef3771..bea850f 100644
--- a/configs/C29XPCIE_NAND_defconfig
+++ b/configs/C29XPCIE_NAND_defconfig
@@ -3,6 +3,10 @@
 CONFIG_TARGET_C29XPCIE=y
 CONFIG_SPL=y
 CONFIG_TPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
@@ -11,3 +15,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig
index 110e597..c6e5e08 100644
--- a/configs/C29XPCIE_NOR_SECBOOT_defconfig
+++ b/configs/C29XPCIE_NOR_SECBOOT_defconfig
@@ -1,7 +1,13 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_C29XPCIE=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +15,5 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
index de0beb6..53889f1 100644
--- a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
+++ b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
@@ -1,7 +1,13 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_C29XPCIE=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +15,5 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/C29XPCIE_SPIFLASH_defconfig b/configs/C29XPCIE_SPIFLASH_defconfig
index d2d9262..e236129 100644
--- a/configs/C29XPCIE_SPIFLASH_defconfig
+++ b/configs/C29XPCIE_SPIFLASH_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_C29XPCIE=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/C29XPCIE_defconfig b/configs/C29XPCIE_defconfig
index 373db16..214aff7 100644
--- a/configs/C29XPCIE_defconfig
+++ b/configs/C29XPCIE_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_C29XPCIE=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index 78b2c51..950c803 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -6,6 +6,7 @@
 CONFIG_USB0_VBUS_PIN="PB10"
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/CPCI4052_defconfig b/configs/CPCI4052_defconfig
index ba4a13ea..49810ff 100644
--- a/configs/CPCI4052_defconfig
+++ b/configs/CPCI4052_defconfig
@@ -1,8 +1,10 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_CPCI4052=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig
index e027a47..4a395cd 100644
--- a/configs/CSQ_CS908_defconfig
+++ b/configs/CSQ_CS908_defconfig
@@ -7,6 +7,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig
index dedf772..db1b8b1 100644
--- a/configs/Chuwi_V7_CW0825_defconfig
+++ b/configs/Chuwi_V7_CW0825_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-chuwi-v7-cw0825"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index feaeb98..c21733d 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -17,6 +17,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-colombus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index 2f5e75d..3f3e15a 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -6,6 +6,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index a45fbb0..eadd791 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -6,6 +6,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index 8cbaea6..0025308 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -11,6 +11,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Cyrus_P5020_defconfig b/configs/Cyrus_P5020_defconfig
index e4deda9..999eb32 100644
--- a/configs/Cyrus_P5020_defconfig
+++ b/configs/Cyrus_P5020_defconfig
@@ -2,6 +2,9 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_CYRUS=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5020"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -9,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/Cyrus_P5040_defconfig b/configs/Cyrus_P5040_defconfig
index 026d37a..310bedf 100644
--- a/configs/Cyrus_P5040_defconfig
+++ b/configs/Cyrus_P5040_defconfig
@@ -2,6 +2,9 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_CYRUS=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5040"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -9,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig
index 5973fbf..5de4381 100644
--- a/configs/Empire_electronix_d709_defconfig
+++ b/configs/Empire_electronix_d709_defconfig
@@ -16,6 +16,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-d709"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig
index 83f2004..92986ca 100644
--- a/configs/Hummingbird_A31_defconfig
+++ b/configs/Hummingbird_A31_defconfig
@@ -9,6 +9,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig
index 45739cd..8ffdd92 100644
--- a/configs/Hyundai_A7HD_defconfig
+++ b/configs/Hyundai_A7HD_defconfig
@@ -15,6 +15,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
index d460c32..f0433b9 100644
--- a/configs/Lamobo_R1_defconfig
+++ b/configs/Lamobo_R1_defconfig
@@ -7,6 +7,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,SATAPWR=SUNXI_GPB(3)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig
index ca3b1dd..e5c400d 100644
--- a/configs/Linksprite_pcDuino3_Nano_defconfig
+++ b/configs/Linksprite_pcDuino3_Nano_defconfig
@@ -8,6 +8,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3-nano"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
index 1f245e7..d1f93ea 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -6,6 +6,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig
index 7e2f942..2b71e90 100644
--- a/configs/Linksprite_pcDuino_defconfig
+++ b/configs/Linksprite_pcDuino_defconfig
@@ -6,6 +6,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig
index 32c65fb..aba8d01 100644
--- a/configs/MK808C_defconfig
+++ b/configs/MK808C_defconfig
@@ -5,6 +5,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig
index 2aec6d9..4ab53dd 100644
--- a/configs/MPC8308RDB_defconfig
+++ b/configs/MPC8308RDB_defconfig
@@ -1,5 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8308RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig
index d736191..4fa6a8c 100644
--- a/configs/MPC8313ERDB_33_defconfig
+++ b/configs/MPC8313ERDB_33_defconfig
@@ -1,7 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8313ERDB=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig
index 583fde8..beca636 100644
--- a/configs/MPC8313ERDB_66_defconfig
+++ b/configs/MPC8313ERDB_66_defconfig
@@ -1,7 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8313ERDB=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig
index 7faa2fe..af4d66a 100644
--- a/configs/MPC8313ERDB_NAND_33_defconfig
+++ b/configs/MPC8313ERDB_NAND_33_defconfig
@@ -2,7 +2,10 @@
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8313ERDB=y
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ,NAND"
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig
index bb4a35d..1c01c61 100644
--- a/configs/MPC8313ERDB_NAND_66_defconfig
+++ b/configs/MPC8313ERDB_NAND_66_defconfig
@@ -2,7 +2,10 @@
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8313ERDB=y
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ,NAND"
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig
index 3d9dede..429a125 100644
--- a/configs/MPC8315ERDB_defconfig
+++ b/configs/MPC8315ERDB_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8315ERDB=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig
index 337a0dd..a611fae 100644
--- a/configs/MPC8323ERDB_defconfig
+++ b/configs/MPC8323ERDB_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8323ERDB=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig
index cd29b89..2ae7298 100644
--- a/configs/MPC832XEMDS_ATM_defconfig
+++ b/configs/MPC832XEMDS_ATM_defconfig
@@ -1,6 +1,9 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC832XEMDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig
index 071fe08..100734d 100644
--- a/configs/MPC832XEMDS_HOST_33_defconfig
+++ b/configs/MPC832XEMDS_HOST_33_defconfig
@@ -1,6 +1,9 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC832XEMDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M,PQ_MDS_PIB=1"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig
index 789c8b1..abfceac 100644
--- a/configs/MPC832XEMDS_HOST_66_defconfig
+++ b/configs/MPC832XEMDS_HOST_66_defconfig
@@ -1,6 +1,9 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC832XEMDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M,PQ_MDS_PIB=1"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig
index 7f5c55a..caa57c5 100644
--- a/configs/MPC832XEMDS_SLAVE_defconfig
+++ b/configs/MPC832XEMDS_SLAVE_defconfig
@@ -1,6 +1,9 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC832XEMDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCISLAVE"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig
index 2ea5868..98aa648 100644
--- a/configs/MPC832XEMDS_defconfig
+++ b/configs/MPC832XEMDS_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC832XEMDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig
index f4d1d45..cd43a7c 100644
--- a/configs/MPC8349EMDS_defconfig
+++ b/configs/MPC8349EMDS_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8349EMDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig
index 445beb6..0fd62ba 100644
--- a/configs/MPC8349ITXGP_defconfig
+++ b/configs/MPC8349ITXGP_defconfig
@@ -1,7 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8349ITX=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000"
 CONFIG_SYS_PROMPT="MPC8349E-mITX-GP> "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig
index c260a46..717d75a 100644
--- a/configs/MPC8349ITX_LOWBOOT_defconfig
+++ b/configs/MPC8349ITX_LOWBOOT_defconfig
@@ -1,7 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8349ITX=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX,SYS_TEXT_BASE=0xFE000000"
 CONFIG_SYS_PROMPT="MPC8349E-mITX> "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig
index 5b234c6..bc49a39 100644
--- a/configs/MPC8349ITX_defconfig
+++ b/configs/MPC8349ITX_defconfig
@@ -1,7 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8349ITX=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX"
 CONFIG_SYS_PROMPT="MPC8349E-mITX> "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig
index 972e0f8..fd6721c 100644
--- a/configs/MPC837XEMDS_HOST_defconfig
+++ b/configs/MPC837XEMDS_HOST_defconfig
@@ -1,6 +1,9 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC837XEMDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig
index 9ddddde..eaee581 100644
--- a/configs/MPC837XEMDS_defconfig
+++ b/configs/MPC837XEMDS_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC837XEMDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index c77fe0c..a135f0a 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC837XERDB=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8536DS_36BIT_defconfig b/configs/MPC8536DS_36BIT_defconfig
index fdea51d..af1ea37 100644
--- a/configs/MPC8536DS_36BIT_defconfig
+++ b/configs/MPC8536DS_36BIT_defconfig
@@ -1,6 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8536DS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +10,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8536DS_SDCARD_defconfig b/configs/MPC8536DS_SDCARD_defconfig
index a7492fd..b91b4e4 100644
--- a/configs/MPC8536DS_SDCARD_defconfig
+++ b/configs/MPC8536DS_SDCARD_defconfig
@@ -1,6 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8536DS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +10,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8536DS_SPIFLASH_defconfig b/configs/MPC8536DS_SPIFLASH_defconfig
index e2a4226..9163118 100644
--- a/configs/MPC8536DS_SPIFLASH_defconfig
+++ b/configs/MPC8536DS_SPIFLASH_defconfig
@@ -1,6 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8536DS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +10,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8536DS_defconfig b/configs/MPC8536DS_defconfig
index c07b84a..ff5f90b 100644
--- a/configs/MPC8536DS_defconfig
+++ b/configs/MPC8536DS_defconfig
@@ -1,9 +1,12 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8536DS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8540ADS_defconfig b/configs/MPC8540ADS_defconfig
index 1239ba8..c1923f0 100644
--- a/configs/MPC8540ADS_defconfig
+++ b/configs/MPC8540ADS_defconfig
@@ -1,4 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8540ADS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8541CDS_defconfig b/configs/MPC8541CDS_defconfig
index 0c5cc13..99a1f8c 100644
--- a/configs/MPC8541CDS_defconfig
+++ b/configs/MPC8541CDS_defconfig
@@ -1,4 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8541CDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8541CDS_legacy_defconfig b/configs/MPC8541CDS_legacy_defconfig
index 3ae3a3d..f79c2f2 100644
--- a/configs/MPC8541CDS_legacy_defconfig
+++ b/configs/MPC8541CDS_legacy_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8541CDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8544DS_defconfig b/configs/MPC8544DS_defconfig
index e4e2f9c..9790d8a 100644
--- a/configs/MPC8544DS_defconfig
+++ b/configs/MPC8544DS_defconfig
@@ -1,6 +1,9 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8544DS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index 5e635e0..dd4b9d0 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -1,7 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8548CDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index ac2c090..1cddf9e 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig
@@ -1,6 +1,9 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8548CDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig
index 3e1ecd7..8ac3360 100644
--- a/configs/MPC8548CDS_legacy_defconfig
+++ b/configs/MPC8548CDS_legacy_defconfig
@@ -1,7 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8548CDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8555CDS_defconfig b/configs/MPC8555CDS_defconfig
index 9a7c16e..0d183db 100644
--- a/configs/MPC8555CDS_defconfig
+++ b/configs/MPC8555CDS_defconfig
@@ -1,4 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8555CDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8555CDS_legacy_defconfig b/configs/MPC8555CDS_legacy_defconfig
index eb6382c..0a31799 100644
--- a/configs/MPC8555CDS_legacy_defconfig
+++ b/configs/MPC8555CDS_legacy_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8555CDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8560ADS_defconfig b/configs/MPC8560ADS_defconfig
index aa84d28..6f33234 100644
--- a/configs/MPC8560ADS_defconfig
+++ b/configs/MPC8560ADS_defconfig
@@ -1,3 +1,6 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8560ADS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8568MDS_defconfig b/configs/MPC8568MDS_defconfig
index 36b5c3b..3efd2e5 100644
--- a/configs/MPC8568MDS_defconfig
+++ b/configs/MPC8568MDS_defconfig
@@ -1,4 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8568MDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8569MDS_ATM_defconfig b/configs/MPC8569MDS_ATM_defconfig
index 186126b..193561a 100644
--- a/configs/MPC8569MDS_ATM_defconfig
+++ b/configs/MPC8569MDS_ATM_defconfig
@@ -1,7 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8569MDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="ATM"
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8569MDS_defconfig b/configs/MPC8569MDS_defconfig
index bfb51d2..e5467ab 100644
--- a/configs/MPC8569MDS_defconfig
+++ b/configs/MPC8569MDS_defconfig
@@ -1,6 +1,9 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8569MDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8572DS_36BIT_defconfig b/configs/MPC8572DS_36BIT_defconfig
index 878404b..c260aee 100644
--- a/configs/MPC8572DS_36BIT_defconfig
+++ b/configs/MPC8572DS_36BIT_defconfig
@@ -1,7 +1,12 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8572DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8572DS_defconfig b/configs/MPC8572DS_defconfig
index 8b42ea3..5e000ea 100644
--- a/configs/MPC8572DS_defconfig
+++ b/configs/MPC8572DS_defconfig
@@ -1,6 +1,11 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8572DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8610HPCD_defconfig b/configs/MPC8610HPCD_defconfig
index bdde5d0..515edb5 100644
--- a/configs/MPC8610HPCD_defconfig
+++ b/configs/MPC8610HPCD_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC86xx=y
 CONFIG_TARGET_MPC8610HPCD=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig
index 46f8077..98298b7 100644
--- a/configs/MPC8641HPCN_36BIT_defconfig
+++ b/configs/MPC8641HPCN_36BIT_defconfig
@@ -1,6 +1,9 @@
 CONFIG_PPC=y
 CONFIG_MPC86xx=y
 CONFIG_TARGET_MPC8641HPCN=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PHYS_64BIT"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig
index 25056d6..2e0254f 100644
--- a/configs/MPC8641HPCN_defconfig
+++ b/configs/MPC8641HPCN_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC86xx=y
 CONFIG_TARGET_MPC8641HPCN=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig
index 73fd4e8..7903510 100644
--- a/configs/MSI_Primo73_defconfig
+++ b/configs/MSI_Primo73_defconfig
@@ -10,6 +10,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-primo73"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig
index 11f3203..b77f9e0 100644
--- a/configs/MSI_Primo81_defconfig
+++ b/configs/MSI_Primo81_defconfig
@@ -13,6 +13,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-primo81"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig
index 806fb64..ef71194 100644
--- a/configs/Marsboard_A10_defconfig
+++ b/configs/Marsboard_A10_defconfig
@@ -4,6 +4,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig
index 6127098..e04bc75 100644
--- a/configs/Mele_A1000G_quad_defconfig
+++ b/configs/Mele_A1000G_quad_defconfig
@@ -7,6 +7,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
index 93707e4..95068c8 100644
--- a/configs/Mele_A1000_defconfig
+++ b/configs/Mele_A1000_defconfig
@@ -6,6 +6,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig
index bfe2a29..0b83431 100644
--- a/configs/Mele_I7_defconfig
+++ b/configs/Mele_I7_defconfig
@@ -7,6 +7,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-i7"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
index 0ed5da1..5dd61c0 100644
--- a/configs/Mele_M3_defconfig
+++ b/configs/Mele_M3_defconfig
@@ -9,6 +9,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig
index fdb5ba4..3cdd67f 100644
--- a/configs/Mele_M5_defconfig
+++ b/configs/Mele_M5_defconfig
@@ -8,6 +8,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m5"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,STATUSLED=234"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index da76226..6ae2e0b 100644
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -7,6 +7,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-m9"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig
index 8013359..8425d1f 100644
--- a/configs/Mini-X_defconfig
+++ b/configs/Mini-X_defconfig
@@ -6,6 +6,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/MiniFAP_defconfig b/configs/MiniFAP_defconfig
index 1e5fd75..6b999ed 100644
--- a/configs/MiniFAP_defconfig
+++ b/configs/MiniFAP_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="MINIFAP"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/O2D300_defconfig b/configs/O2D300_defconfig
index db88295..5bb5a44 100644
--- a/configs/O2D300_defconfig
+++ b/configs/O2D300_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2D300=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/O2DNT2_RAMBOOT_defconfig b/configs/O2DNT2_RAMBOOT_defconfig
index ca54ca5..8865937 100644
--- a/configs/O2DNT2_RAMBOOT_defconfig
+++ b/configs/O2DNT2_RAMBOOT_defconfig
@@ -1,8 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2DNT2=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000"
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="++++++++++"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/O2DNT2_defconfig b/configs/O2DNT2_defconfig
index a4ead75..9364366 100644
--- a/configs/O2DNT2_defconfig
+++ b/configs/O2DNT2_defconfig
@@ -1,7 +1,9 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2DNT2=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="++++++++++"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/O2D_defconfig b/configs/O2D_defconfig
index 3248fc9..d57021f 100644
--- a/configs/O2D_defconfig
+++ b/configs/O2D_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2D=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/O2I_defconfig b/configs/O2I_defconfig
index 5d51be6..7c3ff8c 100644
--- a/configs/O2I_defconfig
+++ b/configs/O2I_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2I=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_O2M110_defconfig b/configs/O2MNT_O2M110_defconfig
index 22e7e98..9a38f11 100644
--- a/configs/O2MNT_O2M110_defconfig
+++ b/configs/O2MNT_O2M110_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2MNT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M110\""
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_O2M112_defconfig b/configs/O2MNT_O2M112_defconfig
index 5342719..a60bfdd 100644
--- a/configs/O2MNT_O2M112_defconfig
+++ b/configs/O2MNT_O2M112_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2MNT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M112\""
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_O2M113_defconfig b/configs/O2MNT_O2M113_defconfig
index bcbb598..8037be4 100644
--- a/configs/O2MNT_O2M113_defconfig
+++ b/configs/O2MNT_O2M113_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2MNT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M113\""
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_defconfig b/configs/O2MNT_defconfig
index a29f70a..60666bd 100644
--- a/configs/O2MNT_defconfig
+++ b/configs/O2MNT_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2MNT=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/O3DNT_defconfig b/configs/O3DNT_defconfig
index 8411294..053e048 100644
--- a/configs/O3DNT_defconfig
+++ b/configs/O3DNT_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O3DNT=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
index 330ee47..bd43df3 100644
--- a/configs/Orangepi_defconfig
+++ b/configs/Orangepi_defconfig
@@ -10,6 +10,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
index 4156c35..1e790e8 100644
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -12,6 +12,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
index c533f97..70140f4 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index 8c0f763..a0a8d06 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -3,6 +3,10 @@
 CONFIG_TARGET_P1010RDB=y
 CONFIG_SPL=y
 CONFIG_TPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
index c09e73e..ef2c1ef 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index 32580d8..7df594d 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index d656b21..6d6710f 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
index 7d31491..775ed29 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index 981d4db..60f736f 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
index d49b5a7..406334a 100644
--- a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index f638ff2..1dd5cef 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -3,6 +3,10 @@
 CONFIG_TARGET_P1010RDB=y
 CONFIG_SPL=y
 CONFIG_TPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
index 8a4793d..d969d0e 100644
--- a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index f00c54f..fefbf64 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index 384d0e7..e5f29c0 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
index 751cc54..5540a61 100644
--- a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index fc4afce..d551d3f 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
index 40e2f26..a8fbfaa 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 6321123..627d953 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -3,6 +3,10 @@
 CONFIG_TARGET_P1010RDB=y
 CONFIG_SPL=y
 CONFIG_TPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
index 982f829..2215969 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index 521a3d4..980cf7c 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index ac6ee07..f98ccb3 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
index 2363aec..2fd6c47 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index 875e4d5..33bff1f 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
index 51286af..2cfc763 100644
--- a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index 47e249c..c9c6de9 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -3,6 +3,10 @@
 CONFIG_TARGET_P1010RDB=y
 CONFIG_SPL=y
 CONFIG_TPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
index aa68725..29ae621 100644
--- a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index c07fa85..5fa7e72 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index 7a431b5..4379db5 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
index d3d9e49..1b478e4 100644
--- a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index 256bdf4..f92483f 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
index ef36139..fd24450 100644
--- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
@@ -2,8 +2,13 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD,36BIT"
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig
index 0cbe477..83f7f76 100644
--- a/configs/P1020MBG-PC_36BIT_defconfig
+++ b/configs/P1020MBG-PC_36BIT_defconfig
@@ -1,8 +1,13 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,36BIT"
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020MBG-PC_SDCARD_defconfig b/configs/P1020MBG-PC_SDCARD_defconfig
index 4771767..a128d0c 100644
--- a/configs/P1020MBG-PC_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_SDCARD_defconfig
@@ -2,8 +2,13 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD"
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020MBG-PC_defconfig b/configs/P1020MBG-PC_defconfig
index 9c25cfc..4e4de4b 100644
--- a/configs/P1020MBG-PC_defconfig
+++ b/configs/P1020MBG-PC_defconfig
@@ -1,8 +1,13 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG"
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 0ecaaff..7817039 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -3,6 +3,10 @@
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
 CONFIG_TPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index 32d3606..f2aae6e 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index da260a7..b54ab14 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index 3fad0b9..aec845c 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index 09616da..6a2affe 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -3,6 +3,10 @@
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
 CONFIG_TPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index 4ed2f7c..4ebb430 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index 3a26800..91aed54 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index 734824e..a6fb793 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index c45b2a8..3cfe779 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -3,6 +3,10 @@
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
 CONFIG_TPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index bdfc29e..7d8f0db 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index 4ebcfea..486ff91 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index 3c97423..69930fe 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
index 27259c3..d2cac5b 100644
--- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
@@ -2,8 +2,13 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT,SDCARD"
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig
index ace09b0..da1d409 100644
--- a/configs/P1020UTM-PC_36BIT_defconfig
+++ b/configs/P1020UTM-PC_36BIT_defconfig
@@ -1,8 +1,13 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT"
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020UTM-PC_SDCARD_defconfig b/configs/P1020UTM-PC_SDCARD_defconfig
index 42e6d1c..9028763 100644
--- a/configs/P1020UTM-PC_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_SDCARD_defconfig
@@ -2,8 +2,13 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD"
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1020UTM-PC_defconfig b/configs/P1020UTM-PC_defconfig
index 9a5a04f..8e42e59 100644
--- a/configs/P1020UTM-PC_defconfig
+++ b/configs/P1020UTM-PC_defconfig
@@ -1,8 +1,13 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM"
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig
index d6ec2ad..1a9e1a8 100644
--- a/configs/P1021RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1021RDB-PC_36BIT_NAND_defconfig
@@ -3,6 +3,10 @@
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
 CONFIG_TPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
index 9414eab..4487d01 100644
--- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
index 429d249..f0cd301 100644
--- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig
index 236d67a..f2dcdeb 100644
--- a/configs/P1021RDB-PC_36BIT_defconfig
+++ b/configs/P1021RDB-PC_36BIT_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig
index e1410b6..c14adaf 100644
--- a/configs/P1021RDB-PC_NAND_defconfig
+++ b/configs/P1021RDB-PC_NAND_defconfig
@@ -3,6 +3,10 @@
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
 CONFIG_TPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig
index 8950dcd..21b154a 100644
--- a/configs/P1021RDB-PC_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig
index 8760a60..61f56e1 100644
--- a/configs/P1021RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1021RDB-PC_defconfig b/configs/P1021RDB-PC_defconfig
index fd52fcf..2b4c7e7 100644
--- a/configs/P1021RDB-PC_defconfig
+++ b/configs/P1021RDB-PC_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1022DS_36BIT_NAND_defconfig b/configs/P1022DS_36BIT_NAND_defconfig
index a57ab4a..2a83e6a 100644
--- a/configs/P1022DS_36BIT_NAND_defconfig
+++ b/configs/P1022DS_36BIT_NAND_defconfig
@@ -3,6 +3,10 @@
 CONFIG_TARGET_P1022DS=y
 CONFIG_SPL=y
 CONFIG_TPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1022DS_36BIT_SDCARD_defconfig b/configs/P1022DS_36BIT_SDCARD_defconfig
index 0e68138..34b61f4 100644
--- a/configs/P1022DS_36BIT_SDCARD_defconfig
+++ b/configs/P1022DS_36BIT_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1022DS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1022DS_36BIT_SPIFLASH_defconfig b/configs/P1022DS_36BIT_SPIFLASH_defconfig
index 130b7cf..c9b06fe 100644
--- a/configs/P1022DS_36BIT_SPIFLASH_defconfig
+++ b/configs/P1022DS_36BIT_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1022DS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1022DS_36BIT_defconfig b/configs/P1022DS_36BIT_defconfig
index 5646062..fe781aa 100644
--- a/configs/P1022DS_36BIT_defconfig
+++ b/configs/P1022DS_36BIT_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1022DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1022DS_NAND_defconfig b/configs/P1022DS_NAND_defconfig
index ef08a9e..5f8c788 100644
--- a/configs/P1022DS_NAND_defconfig
+++ b/configs/P1022DS_NAND_defconfig
@@ -3,6 +3,10 @@
 CONFIG_TARGET_P1022DS=y
 CONFIG_SPL=y
 CONFIG_TPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1022DS_SDCARD_defconfig b/configs/P1022DS_SDCARD_defconfig
index 8ff94af..3072c16 100644
--- a/configs/P1022DS_SDCARD_defconfig
+++ b/configs/P1022DS_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1022DS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1022DS_SPIFLASH_defconfig b/configs/P1022DS_SPIFLASH_defconfig
index ecc48cc..e6eac27 100644
--- a/configs/P1022DS_SPIFLASH_defconfig
+++ b/configs/P1022DS_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1022DS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1022DS_defconfig b/configs/P1022DS_defconfig
index 40c6621..dfe7696 100644
--- a/configs/P1022DS_defconfig
+++ b/configs/P1022DS_defconfig
@@ -1,9 +1,14 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1022DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1023RDB_defconfig b/configs/P1023RDB_defconfig
index 2478f30..5a8966f 100644
--- a/configs/P1023RDB_defconfig
+++ b/configs/P1023RDB_defconfig
@@ -1,6 +1,11 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1023RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig
index 3f96330..6c3e547 100644
--- a/configs/P1024RDB_36BIT_defconfig
+++ b/configs/P1024RDB_36BIT_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,36BIT"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1024RDB_NAND_defconfig b/configs/P1024RDB_NAND_defconfig
index 05c06b6..ee181de 100644
--- a/configs/P1024RDB_NAND_defconfig
+++ b/configs/P1024RDB_NAND_defconfig
@@ -3,6 +3,10 @@
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
 CONFIG_TPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1024RDB_SDCARD_defconfig b/configs/P1024RDB_SDCARD_defconfig
index ad081e5..b874f55 100644
--- a/configs/P1024RDB_SDCARD_defconfig
+++ b/configs/P1024RDB_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1024RDB_SPIFLASH_defconfig b/configs/P1024RDB_SPIFLASH_defconfig
index 12158de..8e8c1af 100644
--- a/configs/P1024RDB_SPIFLASH_defconfig
+++ b/configs/P1024RDB_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1024RDB_defconfig b/configs/P1024RDB_defconfig
index 3d13da9..d0e363c 100644
--- a/configs/P1024RDB_defconfig
+++ b/configs/P1024RDB_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig
index 453c057..aff4ae0 100644
--- a/configs/P1025RDB_36BIT_defconfig
+++ b/configs/P1025RDB_36BIT_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,36BIT"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig
index 1c5e06a..8b0fdd9 100644
--- a/configs/P1025RDB_NAND_defconfig
+++ b/configs/P1025RDB_NAND_defconfig
@@ -3,6 +3,10 @@
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
 CONFIG_TPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig
index fc01fe6..7d39a34 100644
--- a/configs/P1025RDB_SDCARD_defconfig
+++ b/configs/P1025RDB_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig
index 0a37298..945d51f 100644
--- a/configs/P1025RDB_SPIFLASH_defconfig
+++ b/configs/P1025RDB_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P1025RDB_defconfig b/configs/P1025RDB_defconfig
index fe21544..176cd74 100644
--- a/configs/P1025RDB_defconfig
+++ b/configs/P1025RDB_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index 578bfc5..e6ebb61 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -3,6 +3,10 @@
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
 CONFIG_TPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index 19c795a..d4f00e6 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index bdc5e43..ac345f6 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index b9d4a47..e8e56b6 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index ea9f830..641784b 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -3,6 +3,10 @@
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
 CONFIG_TPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index 997887d..1484ac2 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index e547ea4..2226979 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index fdad880..09416fb 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 540b79d..c9eb16a 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index e879d94..036fd70 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig
index 114fc32..2896693 100644
--- a/configs/P2041RDB_SECURE_BOOT_defconfig
+++ b/configs/P2041RDB_SECURE_BOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 6feec40..f488251 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
index 45ba154..0afbd0c 100644
--- a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 9a455ef..c234c71 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -1,9 +1,14 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
index 783089b..da81767 100644
--- a/configs/P3041DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index d8fa407..db083a0 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index 385bcc8..43a7c59 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig
index 5d463a2..b9bdac0 100644
--- a/configs/P3041DS_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_SECURE_BOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index 2c52861..8b861d3 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
index 6925f99..c341b51 100644
--- a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index b41254d..3cc04a9 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -1,9 +1,14 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index 4a0a65d..492910b 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P4080DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig
index 92e1c1d..760194c 100644
--- a/configs/P4080DS_SECURE_BOOT_defconfig
+++ b/configs/P4080DS_SECURE_BOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P4080DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index c503a70..ae2e13a 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P4080DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
index f9b877b..baf548e 100644
--- a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P4080DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index 319f1c7..e2b96c3 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -1,9 +1,14 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P4080DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
index 46b78bc..cb57053 100644
--- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5020DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P5020DS_NAND_defconfig b/configs/P5020DS_NAND_defconfig
index 259371c..a9ea36b 100644
--- a/configs/P5020DS_NAND_defconfig
+++ b/configs/P5020DS_NAND_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5020DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P5020DS_SDCARD_defconfig b/configs/P5020DS_SDCARD_defconfig
index 2da6f48..fb7bda6 100644
--- a/configs/P5020DS_SDCARD_defconfig
+++ b/configs/P5020DS_SDCARD_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5020DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig
index aeb7949..9d9ff67 100644
--- a/configs/P5020DS_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_SECURE_BOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5020DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P5020DS_SPIFLASH_defconfig b/configs/P5020DS_SPIFLASH_defconfig
index ae06e9c..bc6c190 100644
--- a/configs/P5020DS_SPIFLASH_defconfig
+++ b/configs/P5020DS_SPIFLASH_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5020DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
index 53a279e..a7d32bc 100644
--- a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5020DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P5020DS_defconfig b/configs/P5020DS_defconfig
index e133570..00731af 100644
--- a/configs/P5020DS_defconfig
+++ b/configs/P5020DS_defconfig
@@ -1,9 +1,14 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5020DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
index 063e0f7..229cd56 100644
--- a/configs/P5040DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index 2c5f058..eeff54d 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index d78bea0..6fafb44 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig
index ca1c87c..9e35593 100644
--- a/configs/P5040DS_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_SECURE_BOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index 4c403b6..28230ad 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index 4c01789..388c1c0 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -1,9 +1,14 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/PLU405_defconfig b/configs/PLU405_defconfig
index 546376f..52850dd 100644
--- a/configs/PLU405_defconfig
+++ b/configs/PLU405_defconfig
@@ -1,8 +1,10 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_PLU405=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/PMC405DE_defconfig b/configs/PMC405DE_defconfig
index 53fccf5..1155bd1 100644
--- a/configs/PMC405DE_defconfig
+++ b/configs/PMC405DE_defconfig
@@ -1,8 +1,10 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_PMC405DE=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/PMC440_defconfig b/configs/PMC440_defconfig
index 984497a..156d813 100644
--- a/configs/PMC440_defconfig
+++ b/configs/PMC440_defconfig
@@ -1,8 +1,10 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_PMC440=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index 20d3f93..2dd8d7e 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -6,6 +6,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig
index a5f8e6a..c61ed7b 100644
--- a/configs/Sinovoip_BPI_M2_defconfig
+++ b/configs/Sinovoip_BPI_M2_defconfig
@@ -7,6 +7,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sinovoip-bpi-m2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
index b96be50..2ff0058 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -1,15 +1,11 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_MACH_SUN8I_A83T=y
+CONFIG_DRAM_TYPE=7
 CONFIG_DRAM_CLK=480
 CONFIG_DRAM_ZQ=15355
 CONFIG_DRAM_ODT_EN=y
-CONFIG_DRAM_TYPE=7
-CONFIG_SYS_EXTRA_OPTIONS=""
-#CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-#CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_AXP_GPIO=y
-#CONFIG_USB_MUSB_HOST=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-sinovoip-bpi-m3"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
@@ -17,10 +13,6 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_AXP_DCDC1_VOLT=3000
-CONFIG_AXP_DCDC2_VOLT=900
-CONFIG_AXP_DCDC3_VOLT=900
-CONFIG_AXP_DCDC4_VOLT=0
 CONFIG_AXP_DCDC5_VOLT=1200
 CONFIG_AXP_ALDO2_VOLT=0
 CONFIG_AXP_ALDO3_VOLT=0
-CONFIG_AXP_DLDO4_VOLT=0
diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig
index 4fe6af8..28d7e1f 100644
--- a/configs/T1023RDB_NAND_defconfig
+++ b/configs/T1023RDB_NAND_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T102XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -11,3 +15,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig
index 84febc5..ce3bc30 100644
--- a/configs/T1023RDB_SDCARD_defconfig
+++ b/configs/T1023RDB_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T102XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -11,3 +15,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig
index 8e355be..0030f8d 100644
--- a/configs/T1023RDB_SECURE_BOOT_defconfig
+++ b/configs/T1023RDB_SECURE_BOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T102XRDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig
index b72fc86..7b9c518 100644
--- a/configs/T1023RDB_SPIFLASH_defconfig
+++ b/configs/T1023RDB_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T102XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -11,3 +15,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig
index eb5d4ef..d3131cb 100644
--- a/configs/T1023RDB_defconfig
+++ b/configs/T1023RDB_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T102XRDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
index 5a30ab4..c4b2f1a 100644
--- a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
@@ -1,7 +1,13 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T102XQDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -10,3 +16,5 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig
index 39dc0a6..7a7cf65 100644
--- a/configs/T1024QDS_DDR4_defconfig
+++ b/configs/T1024QDS_DDR4_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T102XQDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
@@ -8,3 +12,4 @@
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig
index 4425bb2..308e009 100644
--- a/configs/T1024QDS_NAND_defconfig
+++ b/configs/T1024QDS_NAND_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T102XQDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
@@ -11,3 +15,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig
index 97e32ca..c12abf4 100644
--- a/configs/T1024QDS_SDCARD_defconfig
+++ b/configs/T1024QDS_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T102XQDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
@@ -11,3 +15,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig
index aa5dcde..bd96807 100644
--- a/configs/T1024QDS_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_SECURE_BOOT_defconfig
@@ -1,7 +1,13 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T102XQDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -10,3 +16,5 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig
index beaac8b..8874033 100644
--- a/configs/T1024QDS_SPIFLASH_defconfig
+++ b/configs/T1024QDS_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T102XQDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
@@ -11,3 +15,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig
index 7bb2ea6..42b9552 100644
--- a/configs/T1024QDS_defconfig
+++ b/configs/T1024QDS_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T102XQDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index 065e168..e2e9373 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T102XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index ae4f8cf..c68982c 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T102XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig
index e24c91b..9f29bbf 100644
--- a/configs/T1024RDB_SECURE_BOOT_defconfig
+++ b/configs/T1024RDB_SECURE_BOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T102XRDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 91aad61..712eec4 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T102XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index d43ec06..b1f5549 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T102XRDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig
index e96c984..b2fe48a 100644
--- a/configs/T1040D4RDB_NAND_defconfig
+++ b/configs/T1040D4RDB_NAND_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig
index e90d39d..f93b541 100644
--- a/configs/T1040D4RDB_SDCARD_defconfig
+++ b/configs/T1040D4RDB_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig
index 17f7585..1e1c5cc 100644
--- a/configs/T1040D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig
index 0191a63..ee68bf7 100644
--- a/configs/T1040D4RDB_SPIFLASH_defconfig
+++ b/configs/T1040D4RDB_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig
index 6feecb3..744e37d 100644
--- a/configs/T1040D4RDB_defconfig
+++ b/configs/T1040D4RDB_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040QDS_DDR4_defconfig b/configs/T1040QDS_DDR4_defconfig
index 52b67c8..6a4332a 100644
--- a/configs/T1040QDS_DDR4_defconfig
+++ b/configs/T1040QDS_DDR4_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1040QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SYS_FSL_DDR4"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig
index d98b87a..46fed6d 100644
--- a/configs/T1040QDS_SECURE_BOOT_defconfig
+++ b/configs/T1040QDS_SECURE_BOOT_defconfig
@@ -1,7 +1,13 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1040QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -10,3 +16,5 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig
index 56eb500..5b1ddb6 100644
--- a/configs/T1040QDS_defconfig
+++ b/configs/T1040QDS_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1040QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig
index 74f22d2..7198bb2 100644
--- a/configs/T1040RDB_NAND_defconfig
+++ b/configs/T1040RDB_NAND_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig
index a0f9f2d..a60420b 100644
--- a/configs/T1040RDB_SDCARD_defconfig
+++ b/configs/T1040RDB_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig
index 7b19069..7bc8872 100644
--- a/configs/T1040RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040RDB_SECURE_BOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT,T1040RDB"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig
index 3305e49..3492c83 100644
--- a/configs/T1040RDB_SPIFLASH_defconfig
+++ b/configs/T1040RDB_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig
index 8b7816d..17cdce3 100644
--- a/configs/T1040RDB_defconfig
+++ b/configs/T1040RDB_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 8c77cda..99e6723 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index 0a3b0f8..9101b9b 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig
index f856f7d..9764c1d 100644
--- a/configs/T1042D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index 307de29..1d1799b 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 1549200..56f9f4e 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig
index fb229df..f079ccb 100644
--- a/configs/T1042RDB_PI_NAND_defconfig
+++ b/configs/T1042RDB_PI_NAND_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig
index 3743a1f..b78eb28 100644
--- a/configs/T1042RDB_PI_SDCARD_defconfig
+++ b/configs/T1042RDB_PI_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig
index ce3e54e..11df100 100644
--- a/configs/T1042RDB_PI_SPIFLASH_defconfig
+++ b/configs/T1042RDB_PI_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig
index 18d3967..dd4a2cc 100644
--- a/configs/T1042RDB_PI_defconfig
+++ b/configs/T1042RDB_PI_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig
index cdcfccf..65d51c7 100644
--- a/configs/T1042RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042RDB_SECURE_BOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig
index 2a11421..421ebd6 100644
--- a/configs/T1042RDB_defconfig
+++ b/configs/T1042RDB_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T104XRDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 13f40b4..55463a6 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T208XQDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
@@ -11,3 +15,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index a72830e..4074a65 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T208XQDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
@@ -11,3 +15,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index 6a50147..7beaad7 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -1,7 +1,13 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T208XQDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -10,3 +16,5 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index dc66fd3..7c7b131 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T208XQDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
@@ -11,3 +15,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index ca842a4..e30048a 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T208XQDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -12,3 +16,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index 3d2be66..a2236e1 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T208XQDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index e2eead4..9753814 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T208XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index fc61d1a..75d33c5 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T208XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig
index fe4a439..33f7d5f 100644
--- a/configs/T2080RDB_SECURE_BOOT_defconfig
+++ b/configs/T2080RDB_SECURE_BOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T208XRDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 4fbaf65..07a5b06 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T208XRDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
index 95720ee..c1549c1 100644
--- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T208XRDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index bc2fc92..ab5453c 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T208XRDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig
index 57f327c..6275d27 100644
--- a/configs/T2081QDS_NAND_defconfig
+++ b/configs/T2081QDS_NAND_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T208XQDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
@@ -11,3 +15,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig
index 74a134e..9c805d0 100644
--- a/configs/T2081QDS_SDCARD_defconfig
+++ b/configs/T2081QDS_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T208XQDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
@@ -11,3 +15,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig
index 85d48c3..2cef3ec 100644
--- a/configs/T2081QDS_SPIFLASH_defconfig
+++ b/configs/T2081QDS_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T208XQDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
@@ -11,3 +15,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
index 70f87d7..b8bb371 100644
--- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T208XQDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -12,3 +16,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig
index 23ed67c..f8488b6 100644
--- a/configs/T2081QDS_defconfig
+++ b/configs/T2081QDS_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T208XQDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T4160QDS_NAND_defconfig b/configs/T4160QDS_NAND_defconfig
index bf88846..255ae58 100644
--- a/configs/T4160QDS_NAND_defconfig
+++ b/configs/T4160QDS_NAND_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240QDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T4160QDS_SDCARD_defconfig b/configs/T4160QDS_SDCARD_defconfig
index dcb9ac8..c74aecf 100644
--- a/configs/T4160QDS_SDCARD_defconfig
+++ b/configs/T4160QDS_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240QDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig
index 42e6508..f430c34 100644
--- a/configs/T4160QDS_SECURE_BOOT_defconfig
+++ b/configs/T4160QDS_SECURE_BOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T4160QDS_defconfig b/configs/T4160QDS_defconfig
index d87eb23..191370f 100644
--- a/configs/T4160QDS_defconfig
+++ b/configs/T4160QDS_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig
index 708374b..1ffecc3 100644
--- a/configs/T4160RDB_defconfig
+++ b/configs/T4160RDB_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240QDS_NAND_defconfig b/configs/T4240QDS_NAND_defconfig
index 4ee998b..8bd2174 100644
--- a/configs/T4240QDS_NAND_defconfig
+++ b/configs/T4240QDS_NAND_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240QDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240QDS_SDCARD_defconfig b/configs/T4240QDS_SDCARD_defconfig
index 6a3320a..fa4f1dd 100644
--- a/configs/T4240QDS_SDCARD_defconfig
+++ b/configs/T4240QDS_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240QDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig
index 861ac5c..2737244 100644
--- a/configs/T4240QDS_SECURE_BOOT_defconfig
+++ b/configs/T4240QDS_SECURE_BOOT_defconfig
@@ -1,10 +1,18 @@
 CONFIG_PPC=y
+# CONFIG_SYS_MALLOC_F is not set
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SECURE_BOOT"
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
index 0adca74..10513aa 100644
--- a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -10,3 +14,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240QDS_defconfig b/configs/T4240QDS_defconfig
index 7d8e826..a6525aa 100644
--- a/configs/T4240QDS_defconfig
+++ b/configs/T4240QDS_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240QDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index 009ec04..a124477 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240RDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
@@ -9,3 +13,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index 217471a..fc622c9 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240RDB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
@@ -8,3 +12,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200S_HIGHBOOT_defconfig b/configs/TQM5200S_HIGHBOOT_defconfig
index 4c38482..c7c0931 100644
--- a/configs/TQM5200S_HIGHBOOT_defconfig
+++ b/configs/TQM5200S_HIGHBOOT_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200S_defconfig b/configs/TQM5200S_defconfig
index a01bd39..cb1119b 100644
--- a/configs/TQM5200S_defconfig
+++ b/configs/TQM5200S_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_B_HIGHBOOT_defconfig b/configs/TQM5200_B_HIGHBOOT_defconfig
index dac1eef..30327a9 100644
--- a/configs/TQM5200_B_HIGHBOOT_defconfig
+++ b/configs/TQM5200_B_HIGHBOOT_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,SYS_TEXT_BASE=0xFFF00000"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_B_defconfig b/configs/TQM5200_B_defconfig
index 8417ce2..d21c148 100644
--- a/configs/TQM5200_B_defconfig
+++ b/configs/TQM5200_B_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_STK100_defconfig b/configs/TQM5200_STK100_defconfig
index 9e381f4..1f88448 100644
--- a/configs/TQM5200_STK100_defconfig
+++ b/configs/TQM5200_STK100_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="STK52XX_REV100"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_defconfig b/configs/TQM5200_defconfig
index d82a5be..7803ea1 100644
--- a/configs/TQM5200_defconfig
+++ b/configs/TQM5200_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM823L_LCD_defconfig b/configs/TQM823L_LCD_defconfig
index ebe9bdf..74cdec6 100644
--- a/configs/TQM823L_LCD_defconfig
+++ b/configs/TQM823L_LCD_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM823L=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="LCD,NEC_NL6448BC20"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM823L_defconfig b/configs/TQM823L_defconfig
index 05e69c3..08d1af6 100644
--- a/configs/TQM823L_defconfig
+++ b/configs/TQM823L_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM823L=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM823M_defconfig b/configs/TQM823M_defconfig
index 4c9ead8..666a339 100644
--- a/configs/TQM823M_defconfig
+++ b/configs/TQM823M_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM823M=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig
index f88beef..26ddc10 100644
--- a/configs/TQM834x_defconfig
+++ b/configs/TQM834x_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_TQM834X=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM850L_defconfig b/configs/TQM850L_defconfig
index 47c4070..2d78e79 100644
--- a/configs/TQM850L_defconfig
+++ b/configs/TQM850L_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM850L=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM850M_defconfig b/configs/TQM850M_defconfig
index e4784b5..4c66cc1 100644
--- a/configs/TQM850M_defconfig
+++ b/configs/TQM850M_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM850M=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM855L_defconfig b/configs/TQM855L_defconfig
index e0b03af..6bebf60 100644
--- a/configs/TQM855L_defconfig
+++ b/configs/TQM855L_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM855L=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM855M_defconfig b/configs/TQM855M_defconfig
index 32496bf..e600cd0 100644
--- a/configs/TQM855M_defconfig
+++ b/configs/TQM855M_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM855M=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM860L_defconfig b/configs/TQM860L_defconfig
index b83a07b..2295e42 100644
--- a/configs/TQM860L_defconfig
+++ b/configs/TQM860L_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM860L=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM860M_defconfig b/configs/TQM860M_defconfig
index d95ad79..81e5fbf 100644
--- a/configs/TQM860M_defconfig
+++ b/configs/TQM860M_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM860M=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM862L_defconfig b/configs/TQM862L_defconfig
index 75c8801..41dd2fd 100644
--- a/configs/TQM862L_defconfig
+++ b/configs/TQM862L_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM862L=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM862M_defconfig b/configs/TQM862M_defconfig
index d5f8222..9915cc9 100644
--- a/configs/TQM862M_defconfig
+++ b/configs/TQM862M_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM862M=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM866M_defconfig b/configs/TQM866M_defconfig
index 74f12e2..ef1f78c 100644
--- a/configs/TQM866M_defconfig
+++ b/configs/TQM866M_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM866M=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM885D_defconfig b/configs/TQM885D_defconfig
index bcad969..7fbdd86 100644
--- a/configs/TQM885D_defconfig
+++ b/configs/TQM885D_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM885D=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TTTech_defconfig b/configs/TTTech_defconfig
index d239a73..ade4fa8 100644
--- a/configs/TTTech_defconfig
+++ b/configs/TTTech_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM823L=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ104V7DS01"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/TWR-P1025_defconfig b/configs/TWR-P1025_defconfig
index 2b0a2ab..199ebf1 100644
--- a/configs/TWR-P1025_defconfig
+++ b/configs/TWR-P1025_defconfig
@@ -1,8 +1,13 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1_TWR=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025"
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/UCP1020_SPIFLASH_defconfig b/configs/UCP1020_SPIFLASH_defconfig
index a075bcc..52750f4 100644
--- a/configs/UCP1020_SPIFLASH_defconfig
+++ b/configs/UCP1020_SPIFLASH_defconfig
@@ -2,6 +2,10 @@
 CONFIG_MPC85xx=y
 CONFIG_TARGET_UCP1020=y
 CONFIG_TARGET_UCP1020_SPIFLASH=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="\x1b"
@@ -14,3 +18,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig
index c8da464..0633752 100644
--- a/configs/UCP1020_defconfig
+++ b/configs/UCP1020_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_UCP1020=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_PROMPT="B$ "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n"
@@ -14,3 +18,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig
index dc71dde..46e697a 100644
--- a/configs/UTOO_P66_defconfig
+++ b/configs/UTOO_P66_defconfig
@@ -20,6 +20,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-utoo-p66"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/VOM405_defconfig b/configs/VOM405_defconfig
index 53ac1bf..045fb78 100644
--- a/configs/VOM405_defconfig
+++ b/configs/VOM405_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_VOM405=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig
index a01b4c1..ce1e1fd 100644
--- a/configs/Wexler_TAB7200_defconfig
+++ b/configs/Wexler_TAB7200_defconfig
@@ -13,6 +13,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig
index c3ceedb..31d09d4 100644
--- a/configs/Wits_Pro_A20_DKT_defconfig
+++ b/configs/Wits_Pro_A20_DKT_defconfig
@@ -11,6 +11,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wits-pro-a20-dkt"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig
index eb1b531..7cc9051 100644
--- a/configs/Wobo_i5_defconfig
+++ b/configs/Wobo_i5_defconfig
@@ -7,6 +7,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-wobo-i5"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
index cdde2bc..2e11f7c 100644
--- a/configs/Yones_Toptech_BD1078_defconfig
+++ b/configs/Yones_Toptech_BD1078_defconfig
@@ -19,6 +19,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/a3m071_defconfig b/configs/a3m071_defconfig
index 3a6188e..0662d40 100644
--- a/configs/a3m071_defconfig
+++ b/configs/a3m071_defconfig
@@ -2,5 +2,8 @@
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_A3M071=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_LIB_RAND=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/a4m072_defconfig b/configs/a4m072_defconfig
index 4a02293..bbc140d 100644
--- a/configs/a4m072_defconfig
+++ b/configs/a4m072_defconfig
@@ -1,7 +1,9 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_A4M072=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR="asdfg"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/a4m2k_defconfig b/configs/a4m2k_defconfig
index 22db933..dbc5de8 100644
--- a/configs/a4m2k_defconfig
+++ b/configs/a4m2k_defconfig
@@ -2,6 +2,9 @@
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_A3M071=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="A4M2K"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_LIB_RAND=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ac14xx_defconfig b/configs/ac14xx_defconfig
index 608b56a..3d74576 100644
--- a/configs/ac14xx_defconfig
+++ b/configs/ac14xx_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC512X=y
 CONFIG_TARGET_AC14XX=y
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_PROMPT="ac14xx> "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/acadia_defconfig b/configs/acadia_defconfig
index 51efe06..6434f4b 100644
--- a/configs/acadia_defconfig
+++ b/configs/acadia_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_ACADIA=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/alt_defconfig b/configs/alt_defconfig
index aaf6a99..4ea33ef 100644
--- a/configs/alt_defconfig
+++ b/configs/alt_defconfig
@@ -20,3 +20,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index 91bb63f..276a650 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -5,9 +5,11 @@
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig
index 8803da5..4ba2579 100644
--- a/configs/am335x_boneblack_defconfig
+++ b/configs/am335x_boneblack_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
@@ -16,3 +17,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 7753ab5..836950c 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
@@ -15,3 +16,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig
index bde7b8a..f336dfd 100644
--- a/configs/am335x_evm_nor_defconfig
+++ b/configs/am335x_evm_nor_defconfig
@@ -4,6 +4,7 @@
 CONFIG_NOR=y
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
@@ -11,3 +12,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig
index 94dfb5a..707014b 100644
--- a/configs/am335x_evm_norboot_defconfig
+++ b/configs/am335x_evm_norboot_defconfig
@@ -2,9 +2,11 @@
 CONFIG_TARGET_AM335X_EVM=y
 CONFIG_NOR=y
 CONFIG_NOR_BOOT=y
+CONFIG_FIT=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 9757142..665dad3 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -11,3 +12,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig
index 0329948..17370bb 100644
--- a/configs/am335x_evm_usbspl_defconfig
+++ b/configs/am335x_evm_usbspl_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND,SPL_USBETH_SUPPORT"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -11,3 +12,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_gp_evm_defconfig b/configs/am335x_gp_evm_defconfig
index 49461e2..7f12972 100644
--- a/configs/am335x_gp_evm_defconfig
+++ b/configs/am335x_gp_evm_defconfig
@@ -4,6 +4,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -15,6 +16,6 @@
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
-CONFIG_RSA=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
+CONFIG_RSA=y
diff --git a/configs/am335x_igep0033_defconfig b/configs/am335x_igep0033_defconfig
index 8f6bf02..5d448c3 100644
--- a/configs/am335x_igep0033_defconfig
+++ b/configs/am335x_igep0033_defconfig
@@ -8,3 +8,4 @@
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index d6cd92e..0b6c11f 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -3,9 +3,11 @@
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index c7699e0..9ac43f0 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -12,3 +12,4 @@
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_GPIO=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
index 3e916db..149a028 100644
--- a/configs/am437x_sk_evm_defconfig
+++ b/configs/am437x_sk_evm_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="am437x-sk-evm"
@@ -15,12 +17,10 @@
 CONFIG_DM=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_DMA=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 1ba1c8b..8ef28f3 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -11,3 +11,4 @@
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index ff2acf0..7143597 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -10,3 +10,4 @@
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 095f4d0..a9a862b 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -9,3 +9,4 @@
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index be99599..2c73dbe 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -10,3 +10,4 @@
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index c5e4670..1090287 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -12,7 +12,6 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_DM_MMC=y
diff --git a/configs/am57xx_evm_nodt_defconfig b/configs/am57xx_evm_nodt_defconfig
index e351be4..7641db5 100644
--- a/configs/am57xx_evm_nodt_defconfig
+++ b/configs/am57xx_evm_nodt_defconfig
@@ -8,3 +8,4 @@
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index f939bdb..b370d6c 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TEGRA30=y
 CONFIG_TARGET_APALIS_T30=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis"
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Apalis T30 # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
@@ -11,7 +12,6 @@
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_NFS is not set
-CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_PCI_TEGRA=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig
index 3a7a8c1..3d6fe7b 100644
--- a/configs/apf27_defconfig
+++ b/configs/apf27_defconfig
@@ -4,3 +4,4 @@
 CONFIG_SYS_PROMPT="BIOS> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/apx4devkit_defconfig b/configs/apx4devkit_defconfig
index 5727929..e69fce2 100644
--- a/configs/apx4devkit_defconfig
+++ b/configs/apx4devkit_defconfig
@@ -4,3 +4,4 @@
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/arches_defconfig b/configs/arches_defconfig
index 245e6fa..9a2cf6d 100644
--- a/configs/arches_defconfig
+++ b/configs/arches_defconfig
@@ -3,5 +3,6 @@
 CONFIG_TARGET_CANYONLANDS=y
 CONFIG_ARCHES=y
 CONFIG_DEFAULT_DEVICE_TREE="arches"
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_CONTROL=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/aria_defconfig b/configs/aria_defconfig
index 1c073bf..5848709 100644
--- a/configs/aria_defconfig
+++ b/configs/aria_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_MPC512X=y
 CONFIG_TARGET_ARIA=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig
index b83e7ea..7e2c026 100644
--- a/configs/aristainetos2_defconfig
+++ b/configs/aristainetos2_defconfig
@@ -1,9 +1,11 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_ARISTAINETOS2=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig
index cdad556..88670df 100644
--- a/configs/aristainetos2b_defconfig
+++ b/configs/aristainetos2b_defconfig
@@ -1,9 +1,11 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_ARISTAINETOS2B=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig
index 15fc3a9..e808c21 100644
--- a/configs/aristainetos_defconfig
+++ b/configs/aristainetos_defconfig
@@ -1,9 +1,11 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_ARISTAINETOS=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig
index 240d72d..dc326e1 100644
--- a/configs/armadillo-800eva_defconfig
+++ b/configs/armadillo-800eva_defconfig
@@ -18,3 +18,4 @@
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_MISC is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig
index ee47a3d..b323e98 100644
--- a/configs/arndale_defconfig
+++ b/configs/arndale_defconfig
@@ -4,6 +4,8 @@
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale"
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_BEST_MATCH=y
 CONFIG_SYS_PROMPT="ARNDALE # "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/aspenite_defconfig b/configs/aspenite_defconfig
index 812122f..d3ac8d8 100644
--- a/configs/aspenite_defconfig
+++ b/configs/aspenite_defconfig
@@ -6,3 +6,4 @@
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91rm9200ek_defconfig b/configs/at91rm9200ek_defconfig
index e743b53..7c99aa0 100644
--- a/configs/at91rm9200ek_defconfig
+++ b/configs/at91rm9200ek_defconfig
@@ -4,3 +4,4 @@
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91rm9200ek_ram_defconfig b/configs/at91rm9200ek_ram_defconfig
index 2043923..96a4536 100644
--- a/configs/at91rm9200ek_ram_defconfig
+++ b/configs/at91rm9200ek_ram_defconfig
@@ -5,3 +5,4 @@
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig
index 3c52fef..a71a21f 100644
--- a/configs/at91sam9260ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs0_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig
index 3b98493..5884ffa 100644
--- a/configs/at91sam9260ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs1_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig
index 0eac59b..9d49a1a 100644
--- a/configs/at91sam9260ek_nandflash_defconfig
+++ b/configs/at91sam9260ek_nandflash_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig
index b902f60..2bdc4a6 100644
--- a/configs/at91sam9261ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs0_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig
index c370ae7..0f6946a 100644
--- a/configs/at91sam9261ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs3_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig
index d7a98c6..6a5a850 100644
--- a/configs/at91sam9261ek_nandflash_defconfig
+++ b/configs/at91sam9261ek_nandflash_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig
index f2edb9f..1ca4f46 100644
--- a/configs/at91sam9263ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9263ek_dataflash_cs0_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig
index f2edb9f..1ca4f46 100644
--- a/configs/at91sam9263ek_dataflash_defconfig
+++ b/configs/at91sam9263ek_dataflash_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig
index c69e740..15306e6 100644
--- a/configs/at91sam9263ek_nandflash_defconfig
+++ b/configs/at91sam9263ek_nandflash_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig
index b5cd0da..2cf8cb9 100644
--- a/configs/at91sam9263ek_norflash_boot_defconfig
+++ b/configs/at91sam9263ek_norflash_boot_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig
index 790fcc2..abb044c 100644
--- a/configs/at91sam9263ek_norflash_defconfig
+++ b/configs/at91sam9263ek_norflash_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig
index a18d776..173990e 100644
--- a/configs/at91sam9g10ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig
index 7c4a62c..551bfea 100644
--- a/configs/at91sam9g10ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig
index 98a14f4..505c5ed 100644
--- a/configs/at91sam9g10ek_nandflash_defconfig
+++ b/configs/at91sam9g10ek_nandflash_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig
index 4c669f4..c5d0e68 100644
--- a/configs/at91sam9g20ek_2mmc_defconfig
+++ b/configs/at91sam9g20ek_2mmc_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
index 8c39f19..b8ec67c 100644
--- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig
+++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig
index ed2cbf9..0317cae 100644
--- a/configs/at91sam9g20ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig
index 06d52de..c87188f 100644
--- a/configs/at91sam9g20ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig
index 8bc3fee..7b13e96 100644
--- a/configs/at91sam9g20ek_nandflash_defconfig
+++ b/configs/at91sam9g20ek_nandflash_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig
index 6e4e6a4..c4d3962 100644
--- a/configs/at91sam9m10g45ek_mmc_defconfig
+++ b/configs/at91sam9m10g45ek_mmc_defconfig
@@ -11,3 +11,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig
index 825129c..4d42256 100644
--- a/configs/at91sam9m10g45ek_nandflash_defconfig
+++ b/configs/at91sam9m10g45ek_nandflash_defconfig
@@ -11,3 +11,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig
index 6f2390b..6f45120 100644
--- a/configs/at91sam9n12ek_mmc_defconfig
+++ b/configs/at91sam9n12ek_mmc_defconfig
@@ -9,3 +9,4 @@
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig
index ec16f34..df099b2 100644
--- a/configs/at91sam9n12ek_nandflash_defconfig
+++ b/configs/at91sam9n12ek_nandflash_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig
index 655c574..20cf592 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig
index e1ca59d..6dc8dbc 100644
--- a/configs/at91sam9rlek_dataflash_defconfig
+++ b/configs/at91sam9rlek_dataflash_defconfig
@@ -13,3 +13,4 @@
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig
index 7202997..dcf8ec6 100644
--- a/configs/at91sam9rlek_mmc_defconfig
+++ b/configs/at91sam9rlek_mmc_defconfig
@@ -13,3 +13,4 @@
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig
index 220f95f..3e825aa 100644
--- a/configs/at91sam9rlek_nandflash_defconfig
+++ b/configs/at91sam9rlek_nandflash_defconfig
@@ -13,3 +13,4 @@
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig
index 43b32d1..b6154da 100644
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig
index 29fdf31..b782e25 100644
--- a/configs/at91sam9x5ek_mmc_defconfig
+++ b/configs/at91sam9x5ek_mmc_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig
index 004ee25..66be263 100644
--- a/configs/at91sam9x5ek_nandflash_defconfig
+++ b/configs/at91sam9x5ek_nandflash_defconfig
@@ -11,3 +11,4 @@
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
index c574422..0eba857 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -11,3 +11,4 @@
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig
index 14e49bc..57e4481 100644
--- a/configs/at91sam9xeek_dataflash_cs0_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs0_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig
index d04c6e6..f6b585b 100644
--- a/configs/at91sam9xeek_dataflash_cs1_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs1_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig
index 795e1c2..0d1c2c3 100644
--- a/configs/at91sam9xeek_nandflash_defconfig
+++ b/configs/at91sam9xeek_nandflash_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/axm_defconfig b/configs/axm_defconfig
index 25e4570..65c13eb 100644
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -13,3 +13,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USE_TINY_PRINTF=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig
index ce4a584..944547c 100644
--- a/configs/ba10_tv_box_defconfig
+++ b/configs/ba10_tv_box_defconfig
@@ -9,6 +9,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/bamboo_defconfig b/configs/bamboo_defconfig
index 6ecdbcc..a5491cf 100644
--- a/configs/bamboo_defconfig
+++ b/configs/bamboo_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_BAMBOO=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index 0879d1e..dfafb0b 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -9,16 +9,19 @@
 CONFIG_VGA_BIOS_ADDR=0xfffa0000
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_FIT=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
-CONFIG_BOOTSTAGE=y
-CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/bcm911360_entphn-ns_defconfig b/configs/bcm911360_entphn-ns_defconfig
index 58c0ff6..c1b41eb 100644
--- a/configs/bcm911360_entphn-ns_defconfig
+++ b/configs/bcm911360_entphn-ns_defconfig
@@ -5,3 +5,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/bcm911360_entphn_defconfig b/configs/bcm911360_entphn_defconfig
index 2589cb1..ed1dea5 100644
--- a/configs/bcm911360_entphn_defconfig
+++ b/configs/bcm911360_entphn_defconfig
@@ -5,3 +5,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig
index ba430e6..8fcde6c 100644
--- a/configs/bcm911360k_defconfig
+++ b/configs/bcm911360k_defconfig
@@ -5,3 +5,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/bcm958300k-ns_defconfig b/configs/bcm958300k-ns_defconfig
index 14db5a1..670b57f 100644
--- a/configs/bcm958300k-ns_defconfig
+++ b/configs/bcm958300k-ns_defconfig
@@ -5,3 +5,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig
index ba430e6..8fcde6c 100644
--- a/configs/bcm958300k_defconfig
+++ b/configs/bcm958300k_defconfig
@@ -5,3 +5,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/bcm958305k_defconfig b/configs/bcm958305k_defconfig
index ba430e6..8fcde6c 100644
--- a/configs/bcm958305k_defconfig
+++ b/configs/bcm958305k_defconfig
@@ -5,3 +5,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/bcm958622hr_defconfig b/configs/bcm958622hr_defconfig
index 3bf0b0e..4a24da2 100644
--- a/configs/bcm958622hr_defconfig
+++ b/configs/bcm958622hr_defconfig
@@ -5,3 +5,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index 8add08d..fcfbf65 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TEGRA30=y
 CONFIG_TARGET_BEAVER=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-beaver"
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Tegra30 (Beaver) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig
index 620d621..c11617a 100644
--- a/configs/bg0900_defconfig
+++ b/configs/bg0900_defconfig
@@ -7,3 +7,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
index d807ea5..6d7c20d 100644
--- a/configs/birdland_bav335a_defconfig
+++ b/configs/birdland_bav335a_defconfig
@@ -2,6 +2,7 @@
 CONFIG_TARGET_BAV335X=y
 CONFIG_BAV_VERSION=1
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -10,3 +11,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
index 2ed64f6..910ddc7 100644
--- a/configs/birdland_bav335b_defconfig
+++ b/configs/birdland_bav335b_defconfig
@@ -2,6 +2,7 @@
 CONFIG_TARGET_BAV335X=y
 CONFIG_BAV_VERSION=2
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -10,3 +11,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/bubinga_defconfig b/configs/bubinga_defconfig
index 1423dc5..5316aa2 100644
--- a/configs/bubinga_defconfig
+++ b/configs/bubinga_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_BUBINGA=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig
index a353aa1..db05c09 100644
--- a/configs/caddy2_defconfig
+++ b/configs/caddy2_defconfig
@@ -1,8 +1,11 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_VME8349=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="CADDY2"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/cairo_defconfig b/configs/cairo_defconfig
index 3844bd4..e421fe1 100644
--- a/configs/cairo_defconfig
+++ b/configs/cairo_defconfig
@@ -10,3 +10,4 @@
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_NET is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/cam5200_defconfig b/configs/cam5200_defconfig
index eda131a..8815005 100644
--- a/configs/cam5200_defconfig
+++ b/configs/cam5200_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/cam5200_niosflash_defconfig b/configs/cam5200_niosflash_defconfig
index aa7c70a..8c5c9cd 100644
--- a/configs/cam5200_niosflash_defconfig
+++ b/configs/cam5200_niosflash_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/canyonlands_defconfig b/configs/canyonlands_defconfig
index ad7e927..360ee6e 100644
--- a/configs/canyonlands_defconfig
+++ b/configs/canyonlands_defconfig
@@ -3,6 +3,7 @@
 CONFIG_TARGET_CANYONLANDS=y
 CONFIG_CANYONLANDS=y
 CONFIG_DEFAULT_DEVICE_TREE="canyonlands"
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index c9f565a..808e0e2 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TEGRA30=y
 CONFIG_TARGET_CARDHU=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-cardhu"
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Tegra30 (Cardhu) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig
index 02008ea..8fc8e64 100644
--- a/configs/cgtqmx6eval_defconfig
+++ b/configs/cgtqmx6eval_defconfig
@@ -3,10 +3,9 @@
 CONFIG_TARGET_CGTQMX6EVAL=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6QDL"
+CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > "
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_DM=y
-CONFIG_DM_THERMAL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/charon_defconfig b/configs/charon_defconfig
index d67cc55..7732c29 100644
--- a/configs/charon_defconfig
+++ b/configs/charon_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_CHARON=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 390b2ec..4c72035 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -56,6 +56,7 @@
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_DM_VIDEO=y
 CONFIG_I2C_EDID=y
+CONFIG_VIDEO_ROTATION=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index 1cee7d4..8a39740 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -8,14 +8,15 @@
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
+CONFIG_FIT=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
-CONFIG_BOOTSTAGE=y
-CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig
new file mode 100644
index 0000000..448446d
--- /dev/null
+++ b/configs/chromebook_samus_defconfig
@@ -0,0 +1,51 @@
+CONFIG_X86=y
+CONFIG_SYS_MALLOC_F_LEN=0x1800
+CONFIG_VENDOR_GOOGLE=y
+CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
+CONFIG_TARGET_CHROMEBOOK_SAMUS=y
+CONFIG_ENABLE_MRC_CACHE=y
+CONFIG_HAVE_MRC=y
+CONFIG_HAVE_REFCODE=y
+CONFIG_SMP=y
+CONFIG_HAVE_VGA_BIOS=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_TPM_TEST=y
+CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CPU=y
+CONFIG_INTEL_BROADWELL_GPIO=y
+CONFIG_CMD_CROS_EC=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_LPC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0x3f8
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
+CONFIG_TIMER=y
+CONFIG_TPM_TIS_LPC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_VIDEO=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_VIDEO_BROADWELL_IGD=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_TPM=y
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index 6e851cc..3b32e51 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -5,13 +5,14 @@
 CONFIG_HAVE_MRC=y
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_HAVE_VGA_BIOS=y
+CONFIG_FIT=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
-CONFIG_BOOTSTAGE=y
-CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
diff --git a/configs/cm5200_defconfig b/configs/cm5200_defconfig
index 76c7b06..171ed47 100644
--- a/configs/cm5200_defconfig
+++ b/configs/cm5200_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_CM5200=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index 528251c..c37442d 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_CM_FX6=y
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL"
 CONFIG_SYS_PROMPT="CM-FX6 # "
 # CONFIG_CMD_IMLS is not set
@@ -31,3 +32,4 @@
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig
index df16a61..1cabf0e 100644
--- a/configs/cm_t335_defconfig
+++ b/configs/cm_t335_defconfig
@@ -7,3 +7,4 @@
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig
index 1d9af56..054a1c9 100644
--- a/configs/cm_t3517_defconfig
+++ b/configs/cm_t3517_defconfig
@@ -8,3 +8,4 @@
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig
index 1e1591f..71a9005 100644
--- a/configs/cm_t35_defconfig
+++ b/configs/cm_t35_defconfig
@@ -9,3 +9,4 @@
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index d1da759..28a96fb 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -11,6 +11,7 @@
 # CONFIG_CMD_NFS is not set
 CONFIG_DM=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
 CONFIG_DM_SERIAL=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig
index ccf3807..439302c 100644
--- a/configs/cm_t54_defconfig
+++ b/configs/cm_t54_defconfig
@@ -2,6 +2,7 @@
 CONFIG_OMAP54XX=y
 CONFIG_TARGET_CM_T54=y
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_PROMPT="CM-T54 # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -9,3 +10,4 @@
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig
index 3963a50..d1de116 100644
--- a/configs/colibri_pxa270_defconfig
+++ b/configs/colibri_pxa270_defconfig
@@ -4,3 +4,5 @@
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index e8b3e0c..778aae7 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TEGRA20=y
 CONFIG_TARGET_COLIBRI_T20=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri"
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Colibri T20 # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index 6dda271..35b29f9 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TEGRA30=y
 CONFIG_TARGET_COLIBRI_T30=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri"
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Colibri T30 # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index 27a41e7..7356b77 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -17,3 +17,4 @@
 CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
 CONFIG_FSL_LPUART=y
 CONFIG_FSL_DSPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig
new file mode 100644
index 0000000..24a927d
--- /dev/null
+++ b/configs/conga-qeval20-qa3-e3845_defconfig
@@ -0,0 +1,47 @@
+CONFIG_X86=y
+CONFIG_VENDOR_CONGATEC=y
+CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y
+CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845"
+CONFIG_HAVE_INTEL_ME=y
+CONFIG_ENABLE_MRC_CACHE=y
+CONFIG_SMP=y
+CONFIG_HAVE_VGA_BIOS=y
+CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_MP_TABLE=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CPU=y
+CONFIG_WINBOND_W83627=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_E1000=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0x3f8
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
+CONFIG_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO_VESA=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_114=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
index 3df602f..b46f4cc 100644
--- a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_CONTROLCENTERD=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD,DEVELOP"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -12,3 +16,4 @@
 CONFIG_FSL_ESPI=y
 CONFIG_TPM_AUTH_SESSIONS=y
 CONFIG_TPM=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/controlcenterd_36BIT_SDCARD_defconfig b/configs/controlcenterd_36BIT_SDCARD_defconfig
index c30dfae..25eb520 100644
--- a/configs/controlcenterd_36BIT_SDCARD_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_CONTROLCENTERD=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -12,3 +16,4 @@
 CONFIG_FSL_ESPI=y
 CONFIG_TPM_AUTH_SESSIONS=y
 CONFIG_TPM=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig
index fda0db2..a1c7df7 100644
--- a/configs/coreboot-x86_defconfig
+++ b/configs/coreboot-x86_defconfig
@@ -1,12 +1,13 @@
 CONFIG_X86=y
 CONFIG_VENDOR_COREBOOT=y
 CONFIG_TARGET_COREBOOT=y
+CONFIG_FIT=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
-CONFIG_BOOTSTAGE=y
-CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index c9410db..1aabf26 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
index 09306bb..71028cf 100644
--- a/configs/cougarcanyon2_defconfig
+++ b/configs/cougarcanyon2_defconfig
@@ -8,6 +8,8 @@
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_PCI=y
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index 6bc4b8d..b4e1876 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -7,16 +7,19 @@
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_FIT=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
-CONFIG_BOOTSTAGE=y
-CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig
index c962a61..b2d2aeb 100644
--- a/configs/d2net_v2_defconfig
+++ b/configs/d2net_v2_defconfig
@@ -8,3 +8,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig
index c253c38..870186c 100644
--- a/configs/da850_am18xxevm_defconfig
+++ b/configs/da850_am18xxevm_defconfig
@@ -10,3 +10,4 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index 75f4eb6..6d7f984 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -11,3 +11,4 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig
index d8c002f..7aba5c4 100644
--- a/configs/da850evm_direct_nor_defconfig
+++ b/configs/da850evm_direct_nor_defconfig
@@ -8,3 +8,4 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index dc5077d..15bd9f1 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TEGRA114=y
 CONFIG_TARGET_DALMORE=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore"
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Tegra114 (Dalmore) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/devconcenter_defconfig b/configs/devconcenter_defconfig
index f75bb62..ffdf8d7 100644
--- a/configs/devconcenter_defconfig
+++ b/configs/devconcenter_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_INTIP=y
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="DEVCONCENTER"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index ddf09fe..dbb447d 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_DM=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig
index d782f45..57894da 100644
--- a/configs/devkit8000_defconfig
+++ b/configs/devkit8000_defconfig
@@ -8,3 +8,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/digsy_mtc_RAMBOOT_defconfig b/configs/digsy_mtc_RAMBOOT_defconfig
index 17ac961..ad424dd 100644
--- a/configs/digsy_mtc_RAMBOOT_defconfig
+++ b/configs/digsy_mtc_RAMBOOT_defconfig
@@ -1,9 +1,11 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_DIGSY_MTC=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000"
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR="d"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/digsy_mtc_defconfig b/configs/digsy_mtc_defconfig
index 913ba7e..ce9cbf0 100644
--- a/configs/digsy_mtc_defconfig
+++ b/configs/digsy_mtc_defconfig
@@ -1,7 +1,9 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_DIGSY_MTC=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR=" "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/digsy_mtc_rev5_RAMBOOT_defconfig b/configs/digsy_mtc_rev5_RAMBOOT_defconfig
index 408cff5..0fc08d8 100644
--- a/configs/digsy_mtc_rev5_RAMBOOT_defconfig
+++ b/configs/digsy_mtc_rev5_RAMBOOT_defconfig
@@ -1,9 +1,11 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_DIGSY_MTC=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000,DIGSY_REV5"
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR="d"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/digsy_mtc_rev5_defconfig b/configs/digsy_mtc_rev5_defconfig
index e950eb3..9a9d215 100644
--- a/configs/digsy_mtc_rev5_defconfig
+++ b/configs/digsy_mtc_rev5_defconfig
@@ -1,9 +1,11 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_DIGSY_MTC=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="DIGSY_REV5"
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR="d"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/dlvision-10g_defconfig b/configs/dlvision-10g_defconfig
index fe15a4a..dd98059 100644
--- a/configs/dlvision-10g_defconfig
+++ b/configs/dlvision-10g_defconfig
@@ -1,8 +1,12 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_DLVISION_10G=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/dlvision_defconfig b/configs/dlvision_defconfig
index b011cb1..c6fee13 100644
--- a/configs/dlvision_defconfig
+++ b/configs/dlvision_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_DLVISION=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig
index 1c4e502..ed83019 100644
--- a/configs/dns325_defconfig
+++ b/configs/dns325_defconfig
@@ -5,3 +5,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig
index 43e6423..757043b 100644
--- a/configs/dockstar_defconfig
+++ b/configs/dockstar_defconfig
@@ -6,3 +6,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig
index 32d1dc1..0a5f70b 100644
--- a/configs/dra72_evm_defconfig
+++ b/configs/dra72_evm_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_DRA7XX_EVM=y
 CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="dra72-evm"
@@ -12,7 +14,6 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
@@ -20,7 +21,5 @@
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig
index 9946261..916016d 100644
--- a/configs/dra74_evm_defconfig
+++ b/configs/dra74_evm_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_OMAP54XX=y
 CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
@@ -10,16 +13,12 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 1be2f5b..7aaef1b 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -8,9 +8,9 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/dra7xx_evm_qspiboot_defconfig b/configs/dra7xx_evm_qspiboot_defconfig
index 4370b96..0789cff 100644
--- a/configs/dra7xx_evm_qspiboot_defconfig
+++ b/configs/dra7xx_evm_qspiboot_defconfig
@@ -9,8 +9,8 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/dra7xx_evm_uart3_defconfig b/configs/dra7xx_evm_uart3_defconfig
index 204483a..768920b 100644
--- a/configs/dra7xx_evm_uart3_defconfig
+++ b/configs/dra7xx_evm_uart3_defconfig
@@ -10,8 +10,8 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index f7174e6..967f2ff 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -12,3 +12,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig
index 966fa9e..c6b3b53 100644
--- a/configs/dreamplug_defconfig
+++ b/configs/dreamplug_defconfig
@@ -12,3 +12,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/duovero_defconfig b/configs/duovero_defconfig
index 81d089e..30e5255 100644
--- a/configs/duovero_defconfig
+++ b/configs/duovero_defconfig
@@ -9,3 +9,4 @@
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig
index db2d159..1a7b07d 100644
--- a/configs/e2220-1170_defconfig
+++ b/configs/e2220-1170_defconfig
@@ -2,6 +2,7 @@
 CONFIG_TEGRA=y
 CONFIG_TEGRA210=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra210-e2220-1170"
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Tegra210 (E2220-1170) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig
index 9ca47e6..27535df 100644
--- a/configs/eco5pk_defconfig
+++ b/configs/eco5pk_defconfig
@@ -2,9 +2,11 @@
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_ECO5PK=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_PROMPT="ECO5-PK # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig
index b4cbd5f..7d83445 100644
--- a/configs/efi-x86_defconfig
+++ b/configs/efi-x86_defconfig
@@ -2,6 +2,7 @@
 CONFIG_VENDOR_EFI=y
 CONFIG_DEFAULT_DEVICE_TREE="efi"
 CONFIG_TARGET_EFI=y
+CONFIG_FIT=y
 # CONFIG_CMD_BOOTM is not set
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index c196bd6..0689e97 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -2,31 +2,28 @@
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_ROCKCHIP_RK3036=y
 CONFIG_TARGET_EVB_RK3036=y
+CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
 CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_ADDR=0x80000
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_REGULATOR=y
-CONFIG_CLK=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
-CONFIG_RESET=y
-CONFIG_LED=y
+CONFIG_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_PINCTRL=y
+CONFIG_LED=y
+CONFIG_RESET=y
+CONFIG_DM_MMC=y
 CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_PINCTRL=y
 CONFIG_ROCKCHIP_3036_PINCTRL=y
-CONFIG_ROCKCHIP_GPIO=y
 CONFIG_RAM=y
-CONFIG_DM_MMC=y
-CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_CMD_DHRYSTONE=y
-CONFIG_ERRNO_STR=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_NS16550=y
 CONFIG_DEBUG_UART_BASE=0x20068000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 5aa4166..d27e4a5 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -35,8 +35,8 @@
 # CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_PMIC_ACT8846=y
 CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_REGULATOR_ACT8846=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_PWM=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM=y
@@ -48,6 +48,7 @@
 CONFIG_SYS_NS16550=y
 CONFIG_DM_VIDEO=y
 CONFIG_I2C_EDID=y
+CONFIG_VIDEO_ROTATION=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/flea3_defconfig b/configs/flea3_defconfig
index 05bb8b4..5e35601 100644
--- a/configs/flea3_defconfig
+++ b/configs/flea3_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
 CONFIG_TARGET_FLEA3=y
+CONFIG_FIT=y
 CONFIG_SYS_PROMPT="flea3 U-Boot > "
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/fo300_defconfig b/configs/fo300_defconfig
index b8e5c80..db979ec 100644
--- a/configs/fo300_defconfig
+++ b/configs/fo300_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="FO300"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig
index 09ad330..d700760 100644
--- a/configs/ga10h_v1_1_defconfig
+++ b/configs/ga10h_v1_1_defconfig
@@ -17,6 +17,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ga10h-v1.1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index 925d3ee..832ac4d 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -4,15 +4,18 @@
 CONFIG_TARGET_GALILEO=y
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_FIT=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
-CONFIG_BOOTSTAGE=y
-CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/gdppc440etx_defconfig b/configs/gdppc440etx_defconfig
index 9b06cb6..695d860 100644
--- a/configs/gdppc440etx_defconfig
+++ b/configs/gdppc440etx_defconfig
@@ -1,6 +1,8 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_GDPPC440ETX=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/glacier_defconfig b/configs/glacier_defconfig
index 61444ff..1943882 100644
--- a/configs/glacier_defconfig
+++ b/configs/glacier_defconfig
@@ -3,6 +3,7 @@
 CONFIG_TARGET_CANYONLANDS=y
 CONFIG_GLACIER=y
 CONFIG_DEFAULT_DEVICE_TREE="glacier"
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/glacier_ramboot_defconfig b/configs/glacier_ramboot_defconfig
index 11d7da2..c7b5b76 100644
--- a/configs/glacier_ramboot_defconfig
+++ b/configs/glacier_ramboot_defconfig
@@ -3,6 +3,7 @@
 CONFIG_TARGET_CANYONLANDS=y
 CONFIG_GLACIER=y
 CONFIG_DEFAULT_DEVICE_TREE="glacier"
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/canyonlands/u-boot-ram.lds"
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig
index 779daf6..ece39de 100644
--- a/configs/goflexhome_defconfig
+++ b/configs/goflexhome_defconfig
@@ -6,3 +6,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/gose_defconfig b/configs/gose_defconfig
index 01aa817..475bdd1 100644
--- a/configs/gose_defconfig
+++ b/configs/gose_defconfig
@@ -20,3 +20,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/gplugd_defconfig b/configs/gplugd_defconfig
index d2c5e6a..b7ef262 100644
--- a/configs/gplugd_defconfig
+++ b/configs/gplugd_defconfig
@@ -8,3 +8,4 @@
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig
index a8d339c..a78d3b6 100644
--- a/configs/gt90h_v4_defconfig
+++ b/configs/gt90h_v4_defconfig
@@ -16,6 +16,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-gt90h-v4"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig
index 7e20dbb..453afb0 100644
--- a/configs/guruplug_defconfig
+++ b/configs/guruplug_defconfig
@@ -10,3 +10,4 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig
index 547e7f6..686bed6 100644
--- a/configs/gwventana_defconfig
+++ b/configs/gwventana_defconfig
@@ -5,6 +5,9 @@
 CONFIG_SPL_STACK_R_ADDR=0x18000000
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
 CONFIG_SYS_PROMPT="Ventana > "
 # CONFIG_CMD_IMLS is not set
@@ -13,3 +16,4 @@
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/h2200_defconfig b/configs/h2200_defconfig
index d112cf1..0fadc90 100644
--- a/configs/h2200_defconfig
+++ b/configs/h2200_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_H2200=y
+CONFIG_FIT=y
 CONFIG_SYS_PROMPT="> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig
index ecd04a6..4742aaf6 100644
--- a/configs/h8_homlet_v2_defconfig
+++ b/configs/h8_homlet_v2_defconfig
@@ -4,10 +4,7 @@
 CONFIG_DRAM_CLK=480
 CONFIG_DRAM_ZQ=15355
 CONFIG_DRAM_ODT_EN=y
-#CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
-#CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_AXP_GPIO=y
-#CONFIG_USB_MUSB_HOST=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-allwinner-h8homlet-v2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
@@ -15,7 +12,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_AXP_DCDC1_VOLT=3000
-CONFIG_AXP_DCDC2_VOLT=900
-CONFIG_AXP_DCDC3_VOLT=900
-CONFIG_AXP_DCDC4_VOLT=0
 CONFIG_AXP_DCDC5_VOLT=1500
diff --git a/configs/haleakala_defconfig b/configs/haleakala_defconfig
index 234bbea..77de58a 100644
--- a/configs/haleakala_defconfig
+++ b/configs/haleakala_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_KILAUEA=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="HALEAKALA"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index 14125b4..561b27b 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TEGRA20=y
 CONFIG_TARGET_HARMONY=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-harmony"
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Tegra20 (Harmony) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig
index f7042e2..b44763e 100644
--- a/configs/highbank_defconfig
+++ b/configs/highbank_defconfig
@@ -1,8 +1,11 @@
 CONFIG_ARM=y
 CONFIG_ARCH_HIGHBANK=y
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds...\nPress <s> to stop or <d> to delay\n"
 CONFIG_AUTOBOOT_KEYED_CTRLC=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig
index fd94bf5..8b75642 100644
--- a/configs/hikey_defconfig
+++ b/configs/hikey_defconfig
@@ -2,3 +2,4 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig
index f6c531f..b7ef33b 100644
--- a/configs/hrcon_defconfig
+++ b/configs/hrcon_defconfig
@@ -1,7 +1,12 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_HRCON=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig
index aad015a..13cf81d 100644
--- a/configs/hrcon_dh_defconfig
+++ b/configs/hrcon_dh_defconfig
@@ -1,5 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_HRCON=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig
index a15a15a..daa4e9d 100644
--- a/configs/i12-tvbox_defconfig
+++ b/configs/i12-tvbox_defconfig
@@ -6,6 +6,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,MACPWR=SUNXI_GPH(21)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig
index 3f1624c..1fbf66a 100644
--- a/configs/iNet_3F_defconfig
+++ b/configs/iNet_3F_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3f"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig
index 6c4cd56..7d91aec 100644
--- a/configs/iNet_3W_defconfig
+++ b/configs/iNet_3W_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3w"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig
index 00e1458..ba04b60 100644
--- a/configs/iNet_86VS_defconfig
+++ b/configs/iNet_86VS_defconfig
@@ -13,6 +13,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig
index a229f46..22ef1a6 100644
--- a/configs/ib62x0_defconfig
+++ b/configs/ib62x0_defconfig
@@ -11,3 +11,4 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/icon_defconfig b/configs/icon_defconfig
index 36fd884..39b5185 100644
--- a/configs/icon_defconfig
+++ b/configs/icon_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_ICON=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig
index 3b4d37e..cdb21b7 100644
--- a/configs/iconnect_defconfig
+++ b/configs/iconnect_defconfig
@@ -6,3 +6,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig
index deafa38..f962d7d 100644
--- a/configs/ids8313_defconfig
+++ b/configs/ids8313_defconfig
@@ -3,9 +3,12 @@
 CONFIG_TARGET_IDS8313=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000"
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Enter password - autoboot in %d seconds...\n"
 CONFIG_AUTOBOOT_DELAY_STR="ids"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/igep0020_defconfig b/configs/igep0020_defconfig
index a96c130..2731e94 100644
--- a/configs/igep0020_defconfig
+++ b/configs/igep0020_defconfig
@@ -7,5 +7,6 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_NS16550=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/igep0020_nand_defconfig b/configs/igep0020_nand_defconfig
index cf3ee79..dec1f8d 100644
--- a/configs/igep0020_nand_defconfig
+++ b/configs/igep0020_nand_defconfig
@@ -7,5 +7,6 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_NS16550=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/igep0030_defconfig b/configs/igep0030_defconfig
index 63ce633..73b02e9 100644
--- a/configs/igep0030_defconfig
+++ b/configs/igep0030_defconfig
@@ -8,3 +8,4 @@
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/igep0030_nand_defconfig b/configs/igep0030_nand_defconfig
index dce7e06..ab65213 100644
--- a/configs/igep0030_nand_defconfig
+++ b/configs/igep0030_nand_defconfig
@@ -8,3 +8,4 @@
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig
index b7f1d61..a779d47 100644
--- a/configs/igep0032_defconfig
+++ b/configs/igep0032_defconfig
@@ -7,5 +7,6 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_NS16550=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig
index 1c68293..0b9c604 100644
--- a/configs/inet1_defconfig
+++ b/configs/inet1_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig
index a7b3a9f..744051a 100644
--- a/configs/inet97fv2_defconfig
+++ b/configs/inet97fv2_defconfig
@@ -13,6 +13,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet97fv2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig
index c0c6cb2..1897daa 100644
--- a/configs/inet98v_rev2_defconfig
+++ b/configs/inet98v_rev2_defconfig
@@ -15,6 +15,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-98v-rev2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig
index 0a17cf7..662f2e2 100644
--- a/configs/inet9f_rev03_defconfig
+++ b/configs/inet9f_rev03_defconfig
@@ -13,6 +13,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet9f-rev03"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig
index 2d03974..6e49081 100644
--- a/configs/inetspace_v2_defconfig
+++ b/configs/inetspace_v2_defconfig
@@ -8,3 +8,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorap_cm720t_defconfig b/configs/integratorap_cm720t_defconfig
index 5541f8e..6291139 100644
--- a/configs/integratorap_cm720t_defconfig
+++ b/configs/integratorap_cm720t_defconfig
@@ -4,3 +4,4 @@
 CONFIG_CM720T=y
 CONFIG_SYS_PROMPT="Integrator-AP # "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorap_cm920t_defconfig b/configs/integratorap_cm920t_defconfig
index de094b1..7132607 100644
--- a/configs/integratorap_cm920t_defconfig
+++ b/configs/integratorap_cm920t_defconfig
@@ -4,3 +4,4 @@
 CONFIG_CM920T=y
 CONFIG_SYS_PROMPT="Integrator-AP # "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorap_cm926ejs_defconfig b/configs/integratorap_cm926ejs_defconfig
index cf75425..f58e256 100644
--- a/configs/integratorap_cm926ejs_defconfig
+++ b/configs/integratorap_cm926ejs_defconfig
@@ -4,3 +4,4 @@
 CONFIG_CM926EJ_S=y
 CONFIG_SYS_PROMPT="Integrator-AP # "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorap_cm946es_defconfig b/configs/integratorap_cm946es_defconfig
index cd1b1c3..b32512d 100644
--- a/configs/integratorap_cm946es_defconfig
+++ b/configs/integratorap_cm946es_defconfig
@@ -4,3 +4,4 @@
 CONFIG_CM946ES=y
 CONFIG_SYS_PROMPT="Integrator-AP # "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorcp_cm1136_defconfig b/configs/integratorcp_cm1136_defconfig
index 292a0fb..76c8998 100644
--- a/configs/integratorcp_cm1136_defconfig
+++ b/configs/integratorcp_cm1136_defconfig
@@ -4,3 +4,4 @@
 CONFIG_CM1136=y
 CONFIG_SYS_PROMPT="Integrator-CP # "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorcp_cm920t_defconfig b/configs/integratorcp_cm920t_defconfig
index 20cd404..ca7beb3 100644
--- a/configs/integratorcp_cm920t_defconfig
+++ b/configs/integratorcp_cm920t_defconfig
@@ -4,3 +4,4 @@
 CONFIG_CM920T=y
 CONFIG_SYS_PROMPT="Integrator-CP # "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorcp_cm926ejs_defconfig b/configs/integratorcp_cm926ejs_defconfig
index 1091be3..71ca032 100644
--- a/configs/integratorcp_cm926ejs_defconfig
+++ b/configs/integratorcp_cm926ejs_defconfig
@@ -4,3 +4,4 @@
 CONFIG_CM926EJ_S=y
 CONFIG_SYS_PROMPT="Integrator-CP # "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorcp_cm946es_defconfig b/configs/integratorcp_cm946es_defconfig
index a4aeba4..d4d11b8 100644
--- a/configs/integratorcp_cm946es_defconfig
+++ b/configs/integratorcp_cm946es_defconfig
@@ -4,3 +4,4 @@
 CONFIG_CM946ES=y
 CONFIG_SYS_PROMPT="Integrator-CP # "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/intip_defconfig b/configs/intip_defconfig
index 7893f64..48f1bdb 100644
--- a/configs/intip_defconfig
+++ b/configs/intip_defconfig
@@ -1,7 +1,10 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_INTIP=y
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="INTIB"
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/io64_defconfig b/configs/io64_defconfig
index b433cdd..083d94a 100644
--- a/configs/io64_defconfig
+++ b/configs/io64_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_IO64=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/io_defconfig b/configs/io_defconfig
index 17c9c9d..de2749e 100644
--- a/configs/io_defconfig
+++ b/configs/io_defconfig
@@ -1,8 +1,12 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_IO=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/iocon_defconfig b/configs/iocon_defconfig
index a6532d1..069db16 100644
--- a/configs/iocon_defconfig
+++ b/configs/iocon_defconfig
@@ -2,8 +2,10 @@
 CONFIG_4xx=y
 CONFIG_TARGET_IOCON=y
 CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ipek01_defconfig b/configs/ipek01_defconfig
index c8ddbc5..a8e5174 100644
--- a/configs/ipek01_defconfig
+++ b/configs/ipek01_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_IPEK01=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
index 443a1c7..1a165f0 100644
--- a/configs/jesurun_q5_defconfig
+++ b/configs/jesurun_q5_defconfig
@@ -7,6 +7,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(19)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index efc4aee..c07b278 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TEGRA124=y
 CONFIG_TARGET_JETSON_TK1=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1"
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Tegra124 (Jetson TK1) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 5616be9..0949468 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -4,6 +4,7 @@
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="k2e-evm"
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_PROMPT="K2E EVM # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 7cebacd..b721a1c 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -4,6 +4,9 @@
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="k2g-evm"
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_REMOTEPROC_TI_POWER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index f49d820..579c6b8 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -4,6 +4,7 @@
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="k2hk-evm"
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_PROMPT="K2HK EVM # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 6f5ac18..af1dc2c 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -4,6 +4,7 @@
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="k2l-evm"
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_PROMPT="K2L EVM # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/katmai_defconfig b/configs/katmai_defconfig
index a2c4294..b242d81 100644
--- a/configs/katmai_defconfig
+++ b/configs/katmai_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_KATMAI=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/kc1_defconfig b/configs/kc1_defconfig
new file mode 100644
index 0000000..1e5c918
--- /dev/null
+++ b/configs/kc1_defconfig
@@ -0,0 +1,14 @@
+CONFIG_ARM=y
+CONFIG_OMAP44XX=y
+CONFIG_TARGET_KC1=y
+CONFIG_SPL=y
+CONFIG_SYS_PROMPT="kc1 # "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/kilauea_defconfig b/configs/kilauea_defconfig
index 5c77b0c..e6e6e0a 100644
--- a/configs/kilauea_defconfig
+++ b/configs/kilauea_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_KILAUEA=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="KILAUEA"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig
index d2625e5..349651d 100644
--- a/configs/km_kirkwood_128m16_defconfig
+++ b/configs/km_kirkwood_128m16_defconfig
@@ -7,3 +7,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig
index 4db809e..9a0d85c 100644
--- a/configs/km_kirkwood_defconfig
+++ b/configs/km_kirkwood_defconfig
@@ -7,3 +7,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig
index 98b1c10..d2c488e 100644
--- a/configs/km_kirkwood_pci_defconfig
+++ b/configs/km_kirkwood_pci_defconfig
@@ -7,3 +7,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/kmcoge4_defconfig b/configs/kmcoge4_defconfig
index b4371ff..49e1c9b 100644
--- a/configs/kmcoge4_defconfig
+++ b/configs/kmcoge4_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_KMP204X=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMCOGE4"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -11,3 +15,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig
index 6623162..6d9a6fa 100644
--- a/configs/kmcoge5ne_defconfig
+++ b/configs/kmcoge5ne_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_KM8360=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMCOGE5NE"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig
index 0b4fee1..b390e3e 100644
--- a/configs/kmcoge5un_defconfig
+++ b/configs/kmcoge5un_defconfig
@@ -7,3 +7,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig
index 98c4cc9..03cfffb 100644
--- a/configs/kmeter1_defconfig
+++ b/configs/kmeter1_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_KM8360=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMETER1"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/kmlion1_defconfig b/configs/kmlion1_defconfig
index bf55746..12d0131 100644
--- a/configs/kmlion1_defconfig
+++ b/configs/kmlion1_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_KMP204X=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMLION1"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -11,3 +15,4 @@
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig
index 13a3187..3a1aa69 100644
--- a/configs/kmnusa_defconfig
+++ b/configs/kmnusa_defconfig
@@ -7,3 +7,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig
index 6d7896e..1d29c87 100644
--- a/configs/kmopti2_defconfig
+++ b/configs/kmopti2_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_TUXX1=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMOPTI2"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/kmsugp1_defconfig b/configs/kmsugp1_defconfig
index 0f4c51b..bc9aaec 100644
--- a/configs/kmsugp1_defconfig
+++ b/configs/kmsugp1_defconfig
@@ -7,3 +7,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig
index 6cc721b..dda73be 100644
--- a/configs/kmsupx5_defconfig
+++ b/configs/kmsupx5_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_TUXX1=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMSUPX5"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/kmsuv31_defconfig b/configs/kmsuv31_defconfig
index 0c27f17..0a16c04 100644
--- a/configs/kmsuv31_defconfig
+++ b/configs/kmsuv31_defconfig
@@ -7,3 +7,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig
index 6acf420..b28070b 100644
--- a/configs/kmtegr1_defconfig
+++ b/configs/kmtegr1_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_SUVD3=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig
index a4427ac..dbe0d22 100644
--- a/configs/kmtepr2_defconfig
+++ b/configs/kmtepr2_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_TUXX1=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMTEPR2"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig
index c2ee6be..9dd6894 100644
--- a/configs/kmvect1_defconfig
+++ b/configs/kmvect1_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_SUVD3=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMVECT1"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig
index fc8a567..24ea181 100644
--- a/configs/koelsch_defconfig
+++ b/configs/koelsch_defconfig
@@ -20,3 +20,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/kwb_defconfig b/configs/kwb_defconfig
index 4d2aa6c..a5602a0 100644
--- a/configs/kwb_defconfig
+++ b/configs/kwb_defconfig
@@ -26,6 +26,8 @@
 CONFIG_CMD_TIME=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_STORAGE=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 60cdebf..2cc9de4 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -2,25 +2,23 @@
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_ROCKCHIP_RK3036=y
 CONFIG_TARGET_KYLIN_RK3036=y
+CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
 CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_ADDR=0x80000
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_REGULATOR=y
-CONFIG_CLK=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
-CONFIG_RESET=y
-CONFIG_LED=y
+CONFIG_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_PINCTRL=y
+CONFIG_LED=y
+CONFIG_RESET=y
+CONFIG_DM_MMC=y
 CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_PINCTRL=y
 CONFIG_ROCKCHIP_3036_PINCTRL=y
-CONFIG_ROCKCHIP_GPIO=y
 CONFIG_RAM=y
-CONFIG_DM_MMC=y
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/kzm9g_defconfig b/configs/kzm9g_defconfig
index 476f5f0..ac7690d 100644
--- a/configs/kzm9g_defconfig
+++ b/configs/kzm9g_defconfig
@@ -3,3 +3,4 @@
 CONFIG_TARGET_KZM9G=y
 CONFIG_SYS_PROMPT="KZM-A9-GT# "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/lager_defconfig b/configs/lager_defconfig
index 77f1fb3..f042ff7 100644
--- a/configs/lager_defconfig
+++ b/configs/lager_defconfig
@@ -20,3 +20,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/legoev3_defconfig b/configs/legoev3_defconfig
new file mode 100644
index 0000000..d838baa
--- /dev/null
+++ b/configs/legoev3_defconfig
@@ -0,0 +1,12 @@
+CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
+CONFIG_TARGET_LEGOEV3=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds - press 'l' to stop...\n"
+CONFIG_AUTOBOOT_STOP_STR="l"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index 842f645..96576ce 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -1,5 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
@@ -9,3 +11,4 @@
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index 0e1a59d..86a27c6 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -1,5 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
@@ -9,3 +11,4 @@
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_FSL_LPUART=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index fe84419..a24923e 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -1,8 +1,11 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index 025a8f2..b7e3cd7 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -1,7 +1,13 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index f4c81e2..f357383 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -1,5 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 # CONFIG_CMD_SETEXPR is not set
@@ -8,3 +10,4 @@
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index e81448d..202c865 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -1,5 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
 CONFIG_SYS_EXTRA_OPTIONS="LPUART"
@@ -9,3 +11,4 @@
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_FSL_LPUART=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index 2e98d6c..025fd4e 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -2,6 +2,8 @@
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index bf19c33..eff4966 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -1,7 +1,13 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_RSA=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index b7b3a8d..f25e6e2 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -2,6 +2,8 @@
 CONFIG_TARGET_LS1021ATWR=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index 599342f..74f0445 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -2,6 +2,8 @@
 CONFIG_TARGET_LS1021ATWR=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart"
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LPUART"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index d7c7e4c..c94581e 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -2,6 +2,8 @@
 CONFIG_TARGET_LS1021ATWR=y
 CONFIG_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index f6d4b4a..03363a7 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -1,7 +1,10 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 453a3bb..a44988a 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -3,6 +3,8 @@
 CONFIG_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index f7113c5..c1a6736 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -1,9 +1,12 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043AQDS=y
-CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI=y
+CONFIG_SYS_NS16550=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index 21d6407..7468c1b 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -3,6 +3,9 @@
 CONFIG_DM_SERIAL=y
 CONFIG_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index 8d4370f..4ba0cef 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -1,10 +1,14 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
 CONFIG_SYS_NS16550=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_DM_SPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index bc76996..0a79e98 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -1,8 +1,12 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043AQDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_NS16550=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_DM_SPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index cb076c9..3864dd6 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -2,6 +2,9 @@
 CONFIG_TARGET_LS1043AQDS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT"
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index 0409e33..622d26e 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -1,10 +1,14 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
 CONFIG_SYS_NS16550=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_DM_SPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index 09fb1ed..02597f2 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -3,6 +3,9 @@
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index d9d6c97..c25c3c1 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -1,9 +1,13 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043ARDB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, SECURE_BOOT"
-CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, SECURE_BOOT"
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI=y
\ No newline at end of file
+CONFIG_SYS_NS16550=y
+CONFIG_RSA=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 8622ce7..97f224d 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -1,9 +1,12 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043ARDB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
-CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI=y
+CONFIG_SYS_NS16550=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index c4f5f60..a273331 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -1,10 +1,13 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043ARDB=y
+CONFIG_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
-CONFIG_SYS_NS16550=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI=y
+CONFIG_SYS_NS16550=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index 6c7eda3..50f4955 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -1,10 +1,13 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043ARDB=y
+CONFIG_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
-CONFIG_SYS_NS16550=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI=y
+CONFIG_SYS_NS16550=y
diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2080a_emu_defconfig
index d58d2d0..eca5265 100644
--- a/configs/ls2080a_emu_defconfig
+++ b/configs/ls2080a_emu_defconfig
@@ -1,5 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS2080A_EMU=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2080A"
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_IMLS is not set
@@ -13,3 +17,4 @@
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2080a_simu_defconfig
index 4c19b89..7540c4b 100644
--- a/configs/ls2080a_simu_defconfig
+++ b/configs/ls2080a_simu_defconfig
@@ -1,5 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS2080A_SIMU=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2080A"
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_IMLS is not set
@@ -14,3 +18,4 @@
 # CONFIG_CMD_MISC is not set
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index 6ac09ce..a16a6d5 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -4,6 +4,10 @@
 CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index b7d64f6..b5a64f0 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -1,9 +1,14 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS2080AQDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index 1b30114..f8f54e7 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -4,6 +4,10 @@
 CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index daed2e3..0c90869 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -1,9 +1,14 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS2080ARDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ls2085a_emu_defconfig b/configs/ls2085a_emu_defconfig
index 1c20a27..036bb6f 100644
--- a/configs/ls2085a_emu_defconfig
+++ b/configs/ls2085a_emu_defconfig
@@ -1,5 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS2080A_EMU=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2085A"
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_IMLS is not set
@@ -13,3 +17,4 @@
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ls2085a_simu_defconfig b/configs/ls2085a_simu_defconfig
index 38905ce..0702bab 100644
--- a/configs/ls2085a_simu_defconfig
+++ b/configs/ls2085a_simu_defconfig
@@ -1,5 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS2080A_SIMU=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2085A"
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_IMLS is not set
@@ -14,3 +18,4 @@
 # CONFIG_CMD_MISC is not set
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ls2085aqds_defconfig b/configs/ls2085aqds_defconfig
index b4a1d8c..a5c8388 100644
--- a/configs/ls2085aqds_defconfig
+++ b/configs/ls2085aqds_defconfig
@@ -4,6 +4,10 @@
 CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
diff --git a/configs/ls2085aqds_nand_defconfig b/configs/ls2085aqds_nand_defconfig
index b6bc7c6..d355c9a 100644
--- a/configs/ls2085aqds_nand_defconfig
+++ b/configs/ls2085aqds_nand_defconfig
@@ -1,9 +1,14 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS2080AQDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ls2085ardb_defconfig b/configs/ls2085ardb_defconfig
index 0f514ca..fe46dbc 100644
--- a/configs/ls2085ardb_defconfig
+++ b/configs/ls2085ardb_defconfig
@@ -4,6 +4,10 @@
 CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
diff --git a/configs/ls2085ardb_nand_defconfig b/configs/ls2085ardb_nand_defconfig
index 593b8ca..5fb0cf6 100644
--- a/configs/ls2085ardb_nand_defconfig
+++ b/configs/ls2085ardb_nand_defconfig
@@ -1,9 +1,14 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS2080ARDB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig
index 7264c2d..f33cda6 100644
--- a/configs/lschlv2_defconfig
+++ b/configs/lschlv2_defconfig
@@ -9,3 +9,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig
index 62acb40..9f3fde5 100644
--- a/configs/lsxhl_defconfig
+++ b/configs/lsxhl_defconfig
@@ -9,3 +9,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/luan_defconfig b/configs/luan_defconfig
index 7babe26..6995819 100644
--- a/configs/luan_defconfig
+++ b/configs/luan_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_LUAN=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/lwmon5_defconfig b/configs/lwmon5_defconfig
index 5cbca3b..b317937 100644
--- a/configs/lwmon5_defconfig
+++ b/configs/lwmon5_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_LWMON5=y
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/m28evk_defconfig b/configs/m28evk_defconfig
index 9da42eb..b587617 100644
--- a/configs/m28evk_defconfig
+++ b/configs/m28evk_defconfig
@@ -1,8 +1,10 @@
 CONFIG_ARM=y
 CONFIG_TARGET_M28EVK=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/m53evk_defconfig b/configs/m53evk_defconfig
index b5e72ef..4e0368b 100644
--- a/configs/m53evk_defconfig
+++ b/configs/m53evk_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_M53EVK=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/denx/m53evk/imximage.cfg"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ma5d4evk_defconfig b/configs/ma5d4evk_defconfig
index 88102d9..378dc30 100644
--- a/configs/ma5d4evk_defconfig
+++ b/configs/ma5d4evk_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_MA5D4EVK=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4"
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/makalu_defconfig b/configs/makalu_defconfig
index 1b71638..79c13cf 100644
--- a/configs/makalu_defconfig
+++ b/configs/makalu_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_MAKALU=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
index 8495800..4bdbb6d 100644
--- a/configs/marsboard_defconfig
+++ b/configs/marsboard_defconfig
@@ -9,3 +9,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_DM_THERMAL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig
index 1e204d5..a25ffcf 100644
--- a/configs/mcx_defconfig
+++ b/configs/mcx_defconfig
@@ -2,6 +2,7 @@
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_MCX=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_PROMPT="mcx # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
@@ -10,3 +11,4 @@
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mecp5123_defconfig b/configs/mecp5123_defconfig
index 1957f0b..86d7c3f 100644
--- a/configs/mecp5123_defconfig
+++ b/configs/mecp5123_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_MPC512X=y
 CONFIG_TARGET_MECP5123=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig
index 49687cf..631ed18 100644
--- a/configs/medcom-wide_defconfig
+++ b/configs/medcom-wide_defconfig
@@ -4,6 +4,8 @@
 CONFIG_TEGRA20=y
 CONFIG_TARGET_MEDCOM_WIDE=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-medcom-wide"
+CONFIG_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Tegra20 (Medcom-Wide) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig
index e4f7cce..f207428 100644
--- a/configs/meesc_dataflash_defconfig
+++ b/configs/meesc_dataflash_defconfig
@@ -1,9 +1,11 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_MEESC=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig
index 7d1fe7b..8931357 100644
--- a/configs/meesc_defconfig
+++ b/configs/meesc_defconfig
@@ -1,9 +1,11 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_MEESC=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mgcoge3ne_defconfig b/configs/mgcoge3ne_defconfig
index 7b795f5..dc91157 100644
--- a/configs/mgcoge3ne_defconfig
+++ b/configs/mgcoge3ne_defconfig
@@ -1,4 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC8260=y
 CONFIG_TARGET_KM82XX=y
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="MGCOGE3NE"
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mgcoge3un_defconfig b/configs/mgcoge3un_defconfig
index 965972a..f1e8fd7 100644
--- a/configs/mgcoge3un_defconfig
+++ b/configs/mgcoge3un_defconfig
@@ -7,3 +7,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mgcoge_defconfig b/configs/mgcoge_defconfig
index 1fb8dfd..86200fa 100644
--- a/configs/mgcoge_defconfig
+++ b/configs/mgcoge_defconfig
@@ -1,4 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC8260=y
 CONFIG_TARGET_KM82XX=y
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="MGCOGE"
+CONFIG_OF_LIBFDT=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index af6a8ec..ea39e6a 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -8,16 +8,20 @@
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
-CONFIG_BOOTSTAGE=y
-CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig
index 07865d8..a5722e7 100644
--- a/configs/mixtile_loftq_defconfig
+++ b/configs/mixtile_loftq_defconfig
@@ -8,6 +8,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig
index 03e58cd..316b7e8 100644
--- a/configs/mk802_a10s_defconfig
+++ b/configs/mk802_a10s_defconfig
@@ -7,6 +7,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-mk802"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig
index 922f8c3..bc24b4c 100644
--- a/configs/mk802_defconfig
+++ b/configs/mk802_defconfig
@@ -5,6 +5,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig
index 2a359be..6636e7f 100644
--- a/configs/mk802ii_defconfig
+++ b/configs/mk802ii_defconfig
@@ -4,6 +4,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/motionpro_defconfig b/configs/motionpro_defconfig
index 4d3f909..ea2b28a 100644
--- a/configs/motionpro_defconfig
+++ b/configs/motionpro_defconfig
@@ -1,7 +1,9 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_MOTIONPRO=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mpc5121ads_defconfig b/configs/mpc5121ads_defconfig
index e5fe27f..865b97b 100644
--- a/configs/mpc5121ads_defconfig
+++ b/configs/mpc5121ads_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_MPC512X=y
 CONFIG_TARGET_MPC5121ADS=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mpc5121ads_rev2_defconfig b/configs/mpc5121ads_rev2_defconfig
index 3562353..6fe22b3 100644
--- a/configs/mpc5121ads_rev2_defconfig
+++ b/configs/mpc5121ads_rev2_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC512X=y
 CONFIG_TARGET_MPC5121ADS=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC5121ADS_REV2"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig
index c31d948..af76130 100644
--- a/configs/mpc8308_p1m_defconfig
+++ b/configs/mpc8308_p1m_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8308_P1M=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig
index a0153e4..c537440 100644
--- a/configs/mt_ventoux_defconfig
+++ b/configs/mt_ventoux_defconfig
@@ -2,9 +2,11 @@
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_MT_VENTOUX=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_PROMPT="mt_ventoux => "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/munices_defconfig b/configs/munices_defconfig
index 1c0309a..f490eab 100644
--- a/configs/munices_defconfig
+++ b/configs/munices_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_MUNICES=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig
index 22c46f8..4582cce 100644
--- a/configs/mx23_olinuxino_defconfig
+++ b/configs/mx23_olinuxino_defconfig
@@ -5,3 +5,4 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig
index 55e8915..43e3d0a 100644
--- a/configs/mx23evk_defconfig
+++ b/configs/mx23evk_defconfig
@@ -7,3 +7,4 @@
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx25pdk_defconfig b/configs/mx25pdk_defconfig
index 79edf33..5a4bd57 100644
--- a/configs/mx25pdk_defconfig
+++ b/configs/mx25pdk_defconfig
@@ -4,3 +4,4 @@
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig
index dcabd7b..f4c934f 100644
--- a/configs/mx28evk_auart_console_defconfig
+++ b/configs/mx28evk_auart_console_defconfig
@@ -7,3 +7,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index d7f0706..d0e413d 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig
@@ -7,3 +7,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig
index f4ace44..0f76bde 100644
--- a/configs/mx28evk_nand_defconfig
+++ b/configs/mx28evk_nand_defconfig
@@ -7,3 +7,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig
index 976ebc2..ad939ca 100644
--- a/configs/mx28evk_spi_defconfig
+++ b/configs/mx28evk_spi_defconfig
@@ -7,3 +7,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx35pdk_defconfig b/configs/mx35pdk_defconfig
index c13e9f2..699d929 100644
--- a/configs/mx35pdk_defconfig
+++ b/configs/mx35pdk_defconfig
@@ -1,3 +1,4 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX35PDK=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig
index f2c3743..0bb0c61 100644
--- a/configs/mx51evk_defconfig
+++ b/configs/mx51evk_defconfig
@@ -3,3 +3,4 @@
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53ard_defconfig b/configs/mx53ard_defconfig
index 8f233c9..e8a211a 100644
--- a/configs/mx53ard_defconfig
+++ b/configs/mx53ard_defconfig
@@ -2,3 +2,4 @@
 CONFIG_TARGET_MX53ARD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg"
 # CONFIG_CMD_IMLS is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53evk_defconfig b/configs/mx53evk_defconfig
index 958a7d8..1c4da22 100644
--- a/configs/mx53evk_defconfig
+++ b/configs/mx53evk_defconfig
@@ -3,3 +3,4 @@
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53evk/imximage.cfg"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig
index 1badd4e..273ce16 100644
--- a/configs/mx53loco_defconfig
+++ b/configs/mx53loco_defconfig
@@ -3,3 +3,4 @@
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53smd_defconfig b/configs/mx53smd_defconfig
index 2fdd374..92e9f63 100644
--- a/configs/mx53smd_defconfig
+++ b/configs/mx53smd_defconfig
@@ -3,3 +3,4 @@
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53smd/imximage.cfg"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index e8964d9..58e297a 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -8,3 +8,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_DM=y
 CONFIG_DM_THERMAL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6dlarm2_defconfig b/configs/mx6dlarm2_defconfig
index de96d35..60e5dd6 100644
--- a/configs/mx6dlarm2_defconfig
+++ b/configs/mx6dlarm2_defconfig
@@ -6,3 +6,4 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6dlarm2_lpddr2_defconfig b/configs/mx6dlarm2_lpddr2_defconfig
index 9ee4ee7..01a682f 100644
--- a/configs/mx6dlarm2_lpddr2_defconfig
+++ b/configs/mx6dlarm2_lpddr2_defconfig
@@ -6,3 +6,4 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig
index 40d82ca..46b8a9f 100644
--- a/configs/mx6dlsabreauto_defconfig
+++ b/configs/mx6dlsabreauto_defconfig
@@ -7,3 +7,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig
index b2cf924..45a7ec3 100644
--- a/configs/mx6dlsabresd_defconfig
+++ b/configs/mx6dlsabresd_defconfig
@@ -7,3 +7,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qarm2_defconfig b/configs/mx6qarm2_defconfig
index 7f08d86..7aa7916 100644
--- a/configs/mx6qarm2_defconfig
+++ b/configs/mx6qarm2_defconfig
@@ -6,3 +6,4 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qarm2_lpddr2_defconfig b/configs/mx6qarm2_lpddr2_defconfig
index 7186799..5920430 100644
--- a/configs/mx6qarm2_lpddr2_defconfig
+++ b/configs/mx6qarm2_lpddr2_defconfig
@@ -6,3 +6,4 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig
index c44cd8f..0877c41 100644
--- a/configs/mx6qpsabreauto_defconfig
+++ b/configs/mx6qpsabreauto_defconfig
@@ -5,3 +5,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig
index 67b9e10..36ebc89 100644
--- a/configs/mx6qsabreauto_defconfig
+++ b/configs/mx6qsabreauto_defconfig
@@ -7,3 +7,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index 8736e31..fc8323c 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -9,3 +9,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_DM_THERMAL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig
index 63187b3..224e6ed 100644
--- a/configs/mx6qsabresd_defconfig
+++ b/configs/mx6qsabresd_defconfig
@@ -7,3 +7,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig
index d047309..406777c 100644
--- a/configs/mx6sabresd_spl_defconfig
+++ b/configs/mx6sabresd_spl_defconfig
@@ -8,3 +8,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig
index 5eca5e9..2d24622 100644
--- a/configs/mx6slevk_defconfig
+++ b/configs/mx6slevk_defconfig
@@ -10,3 +10,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_THERMAL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig
index caf0335..65b5e9d 100644
--- a/configs/mx6slevk_spinor_defconfig
+++ b/configs/mx6slevk_spinor_defconfig
@@ -10,3 +10,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_THERMAL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index 2603927..fee352c 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -8,3 +8,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_THERMAL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index 953a246..f4e88f2 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -8,3 +8,4 @@
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6sxsabresd_spl_defconfig b/configs/mx6sxsabresd_spl_defconfig
index 3843f99..2713a4b 100644
--- a/configs/mx6sxsabresd_spl_defconfig
+++ b/configs/mx6sxsabresd_spl_defconfig
@@ -8,3 +8,4 @@
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SPI_FLASH=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index 835285f..77d78e7 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -6,3 +6,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index efbffe3..a6dd96b 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -6,3 +6,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index 1d262c1..40b0e7e 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -12,3 +12,4 @@
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig
index eae74a0..ab9ebba 100644
--- a/configs/nas220_defconfig
+++ b/configs/nas220_defconfig
@@ -6,3 +6,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/neo_defconfig b/configs/neo_defconfig
index a500b5f..0366da1 100644
--- a/configs/neo_defconfig
+++ b/configs/neo_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_NEO=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig
index 87f4f92..c0aee31 100644
--- a/configs/net2big_v2_defconfig
+++ b/configs/net2big_v2_defconfig
@@ -8,3 +8,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig
index 2e2ee35..eb26f88 100644
--- a/configs/netspace_lite_v2_defconfig
+++ b/configs/netspace_lite_v2_defconfig
@@ -8,3 +8,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig
index d336ef3..e37523e 100644
--- a/configs/netspace_max_v2_defconfig
+++ b/configs/netspace_max_v2_defconfig
@@ -8,3 +8,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig
index 667da1b..e847123 100644
--- a/configs/netspace_mini_v2_defconfig
+++ b/configs/netspace_mini_v2_defconfig
@@ -8,3 +8,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig
index 949f680..01a6f7e 100644
--- a/configs/netspace_v2_defconfig
+++ b/configs/netspace_v2_defconfig
@@ -8,3 +8,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index 281292d..40da15c 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -7,3 +7,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index 5ae77e3..5f7c17a 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -7,3 +7,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index e5c7824..8707d7e 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -7,3 +7,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index e2a12422..fbe9b6f 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -7,3 +7,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index 3d38c08..078fc20 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -7,3 +7,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index 9b44758..707fb58 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -7,3 +7,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index 889aac2..9217823 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -2,7 +2,9 @@
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_KOSAGI_NOVENA=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig
index 6b3f28a..ddd9004 100644
--- a/configs/nsa310s_defconfig
+++ b/configs/nsa310s_defconfig
@@ -1,13 +1,14 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NSA310S=y
-CONFIG_SYS_NS16550=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="nsa310s => "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_HUSH_PARSER=y
 CONFIG_CMD_DHCP=y
-CONFIG_CMD_NAND=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_USB=y
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 1243006..604aacf 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -4,6 +4,9 @@
 CONFIG_TEGRA124=y
 CONFIG_TARGET_NYAN_BIG=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big"
+CONFIG_FIT=y
+CONFIG_FIT_BEST_MATCH=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Tegra124 (Nyan-big) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index e563843..3b543e8 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -4,6 +4,8 @@
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_FIT=y
+CONFIG_FIT_BEST_MATCH=y
 CONFIG_SYS_PROMPT="ODROID-XU3 # "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index 2c4959b..1f4016b 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -4,6 +4,8 @@
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_PROMPT="Odroid # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
index 988f99d..1fb1f71 100644
--- a/configs/omap3_beagle_defconfig
+++ b/configs/omap3_beagle_defconfig
@@ -7,3 +7,4 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig
index 04b3215..5fc4bfc 100644
--- a/configs/omap3_ha_defconfig
+++ b/configs/omap3_ha_defconfig
@@ -9,3 +9,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index 53c6913..a58b85a 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -11,3 +11,4 @@
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig
index 4c2a17d..2958e24 100644
--- a/configs/omap3_overo_defconfig
+++ b/configs/omap3_overo_defconfig
@@ -11,3 +11,4 @@
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/omap3_pandora_defconfig b/configs/omap3_pandora_defconfig
index badfde6..e565d65 100644
--- a/configs/omap3_pandora_defconfig
+++ b/configs/omap3_pandora_defconfig
@@ -11,3 +11,4 @@
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/omap3_zoom1_defconfig b/configs/omap3_zoom1_defconfig
index 639000c..70f0fdb 100644
--- a/configs/omap3_zoom1_defconfig
+++ b/configs/omap3_zoom1_defconfig
@@ -8,3 +8,4 @@
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig
index 332ed66..c6ff836 100644
--- a/configs/omap4_panda_defconfig
+++ b/configs/omap4_panda_defconfig
@@ -8,3 +8,4 @@
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig
index 023ee41..d42fc47 100644
--- a/configs/omap4_sdp4430_defconfig
+++ b/configs/omap4_sdp4430_defconfig
@@ -9,3 +9,4 @@
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig
index ba5d9ca..cdd80cc 100644
--- a/configs/omap5_uevm_defconfig
+++ b/configs/omap5_uevm_defconfig
@@ -7,3 +7,4 @@
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index 7c2d6c8..8b97508 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -10,3 +10,4 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig
index ea7861d..26dc87e 100644
--- a/configs/openrd_base_defconfig
+++ b/configs/openrd_base_defconfig
@@ -6,3 +6,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig
index 886698b..2e0606d 100644
--- a/configs/openrd_client_defconfig
+++ b/configs/openrd_client_defconfig
@@ -6,3 +6,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig
index 4989319..451c8ab 100644
--- a/configs/openrd_ultimate_defconfig
+++ b/configs/openrd_ultimate_defconfig
@@ -6,3 +6,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig
index a1ecf06..5e8671f 100644
--- a/configs/ot1200_defconfig
+++ b/configs/ot1200_defconfig
@@ -10,3 +10,4 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig
index 5d44d7d..2d37d8b 100644
--- a/configs/ot1200_spl_defconfig
+++ b/configs/ot1200_spl_defconfig
@@ -11,3 +11,4 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
index a7315ce..6282acf 100644
--- a/configs/p2371-0000_defconfig
+++ b/configs/p2371-0000_defconfig
@@ -3,6 +3,7 @@
 CONFIG_TEGRA210=y
 CONFIG_TARGET_P2371_0000=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-0000"
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Tegra210 (P2371-0000) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig
index c41f322..392c539 100644
--- a/configs/p2371-2180_defconfig
+++ b/configs/p2371-2180_defconfig
@@ -3,6 +3,7 @@
 CONFIG_TEGRA210=y
 CONFIG_TARGET_P2371_2180=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-2180"
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Tegra210 (P2371-2180) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
@@ -13,8 +14,8 @@
 # CONFIG_CMD_NFS is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PCI_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_TEGRA114_SPI=y
-CONFIG_PCI_TEGRA=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig
index e6de2da..04df7e9 100644
--- a/configs/p2571_defconfig
+++ b/configs/p2571_defconfig
@@ -3,6 +3,7 @@
 CONFIG_TEGRA210=y
 CONFIG_TARGET_P2571=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2571"
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Tegra210 (P2571) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig
index 5469331..f044551 100644
--- a/configs/paz00_defconfig
+++ b/configs/paz00_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TEGRA20=y
 CONFIG_TARGET_PAZ00=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-paz00"
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/pcm030_LOWBOOT_defconfig b/configs/pcm030_LOWBOOT_defconfig
index 42389bb..6b66d4c 100644
--- a/configs/pcm030_LOWBOOT_defconfig
+++ b/configs/pcm030_LOWBOOT_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_PCM030=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/pcm030_defconfig b/configs/pcm030_defconfig
index 9da4bb0..7ee7658 100644
--- a/configs/pcm030_defconfig
+++ b/configs/pcm030_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_PCM030=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_PROMPT="uboot> "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig
index ce7c4bb..b74b372 100644
--- a/configs/pcm051_rev1_defconfig
+++ b/configs/pcm051_rev1_defconfig
@@ -9,3 +9,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index 7c2dee4..18be2a0 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -9,3 +9,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig
index 49159ce..f97f110 100644
--- a/configs/pcm052_defconfig
+++ b/configs/pcm052_defconfig
@@ -11,3 +11,4 @@
 CONFIG_NAND_VF610_NFC=y
 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
 CONFIG_FSL_LPUART=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/pdm360ng_defconfig b/configs/pdm360ng_defconfig
index 3997f59..1b9de3d 100644
--- a/configs/pdm360ng_defconfig
+++ b/configs/pdm360ng_defconfig
@@ -1,4 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC512X=y
 CONFIG_TARGET_PDM360NG=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index 65c6044..23b9762 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -4,6 +4,8 @@
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi"
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_BEST_MATCH=y
 CONFIG_SYS_PROMPT="Peach-Pi # "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index 272988f..adde56f 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -4,6 +4,8 @@
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit"
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_BEST_MATCH=y
 CONFIG_SYS_PROMPT="Peach-Pit # "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig
index 00a3dac..97ee71d 100644
--- a/configs/pengwyn_defconfig
+++ b/configs/pengwyn_defconfig
@@ -6,3 +6,4 @@
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig
index 62bb80a..7073739 100644
--- a/configs/pepper_defconfig
+++ b/configs/pepper_defconfig
@@ -7,3 +7,4 @@
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 169a2ac..4017983 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -29,6 +29,6 @@
 CONFIG_PIC32_ETH=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_FULL is not set
-CONFIG_SYS_VSNPRINTF=y
+CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig
index ccca1ca..687e69b 100644
--- a/configs/picosam9g45_defconfig
+++ b/configs/picosam9g45_defconfig
@@ -11,3 +11,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig
index c4a82d7..b7e5d7c 100644
--- a/configs/platinum_picon_defconfig
+++ b/configs/platinum_picon_defconfig
@@ -8,3 +8,4 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig
index f824bae..cb38895 100644
--- a/configs/platinum_titanium_defconfig
+++ b/configs/platinum_titanium_defconfig
@@ -8,3 +8,4 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig
index c2c4638..85fe61d 100644
--- a/configs/plutux_defconfig
+++ b/configs/plutux_defconfig
@@ -4,6 +4,8 @@
 CONFIG_TEGRA20=y
 CONFIG_TARGET_PLUTUX=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-plutux"
+CONFIG_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Tegra20 (Plutux) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig
index 1a31256..53ee15c 100644
--- a/configs/pogo_e02_defconfig
+++ b/configs/pogo_e02_defconfig
@@ -6,3 +6,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/porter_defconfig b/configs/porter_defconfig
index 44f2387..5899f73 100644
--- a/configs/porter_defconfig
+++ b/configs/porter_defconfig
@@ -20,3 +20,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/portl2_defconfig b/configs/portl2_defconfig
index 0efc4c6..37c9ddb 100644
--- a/configs/portl2_defconfig
+++ b/configs/portl2_defconfig
@@ -7,3 +7,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig
index d9b3b45..99884ed 100644
--- a/configs/pov_protab2_ips9_defconfig
+++ b/configs/pov_protab2_ips9_defconfig
@@ -14,6 +14,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pov-protab2-ips9"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 02984ed..5b32bb1 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_PXM2=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
@@ -12,3 +13,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig
index 205359e..b6ff528 100644
--- a/configs/q8_a13_tablet_defconfig
+++ b/configs/q8_a13_tablet_defconfig
@@ -15,6 +15,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-q8-tablet"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig
index 927ab2a..398546a 100644
--- a/configs/q8_a23_tablet_800x480_defconfig
+++ b/configs/q8_a23_tablet_800x480_defconfig
@@ -16,6 +16,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-q8-tablet"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig
index 755f4ee..3c32387 100644
--- a/configs/q8_a33_tablet_1024x600_defconfig
+++ b/configs/q8_a33_tablet_1024x600_defconfig
@@ -16,6 +16,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig
index a8dfa0d..aed4fba 100644
--- a/configs/q8_a33_tablet_800x480_defconfig
+++ b/configs/q8_a33_tablet_800x480_defconfig
@@ -16,6 +16,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig
index d28532c..21493aa 100644
--- a/configs/qemu-ppce500_defconfig
+++ b/configs/qemu-ppce500_defconfig
@@ -1,8 +1,13 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_QEMU_PPCE500=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index b0c935c..bb9c6cd 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -4,13 +4,15 @@
 CONFIG_MAX_CPUS=2
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_FIT=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
-CONFIG_BOOTSTAGE=y
-CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
 CONFIG_CPU=y
diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig
index d6387fc..edbf2ea 100644
--- a/configs/r7-tv-dongle_defconfig
+++ b/configs/r7-tv-dongle_defconfig
@@ -6,6 +6,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-r7-tv-dongle"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/rainier_defconfig b/configs/rainier_defconfig
index cffc355..abbd67f 100644
--- a/configs/rainier_defconfig
+++ b/configs/rainier_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_SEQUOIA=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAINIER"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/rainier_ramboot_defconfig b/configs/rainier_ramboot_defconfig
index 9766835..519e796 100644
--- a/configs/rainier_ramboot_defconfig
+++ b/configs/rainier_ramboot_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_SEQUOIA=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index a1403fb..6e7d0d2 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -12,3 +12,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/redwood_defconfig b/configs/redwood_defconfig
index 3b7cebb..ef83153 100644
--- a/configs/redwood_defconfig
+++ b/configs/redwood_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_REDWOOD=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index 3cf82c3..35b96a3 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -9,3 +9,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_DM_THERMAL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index f33daf1..68e674d 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -33,8 +33,8 @@
 # CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_PMIC_ACT8846=y
 CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_REGULATOR_ACT8846=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_PWM=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM=y
@@ -46,6 +46,7 @@
 CONFIG_SYS_NS16550=y
 CONFIG_DM_VIDEO=y
 CONFIG_I2C_EDID=y
+CONFIG_VIDEO_ROTATION=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
index bd81ee6..ff515fd 100644
--- a/configs/rpi_2_defconfig
+++ b/configs/rpi_2_defconfig
@@ -1,9 +1,11 @@
 CONFIG_ARM=y
 CONFIG_ARCH_BCM283X=y
 CONFIG_TARGET_RPI_2=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_PHYS_TO_BUS=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
index 5d27909..e343c66 100644
--- a/configs/rpi_defconfig
+++ b/configs/rpi_defconfig
@@ -1,9 +1,11 @@
 CONFIG_ARM=y
 CONFIG_ARCH_BCM283X=y
 CONFIG_TARGET_RPI=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_PHYS_TO_BUS=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index 4c1fd4b..7a4011e 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_RUT=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
@@ -12,3 +13,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index 75b1713..d6bc70e 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -10,3 +10,4 @@
 CONFIG_CMD_SF=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_SPI_FLASH=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index 6d61a7e..eb2f1f0 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -10,3 +10,4 @@
 CONFIG_CMD_SF=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_SPI_FLASH=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index 36f8254..1133892 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -8,3 +8,4 @@
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig
index 2de83d4..e4f577b 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -8,3 +8,4 @@
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index 644b150..4a97da1 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -8,3 +8,4 @@
 # CONFIG_CMD_FPGA is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index 1e42880..968cd66 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -8,3 +8,4 @@
 # CONFIG_CMD_FPGA is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index 724b55b..bc98e6b 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -8,3 +8,4 @@
 # CONFIG_CMD_FPGA is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index 3daac36..f1261ab 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index e3517e8..0e53b32 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index 1cdb9bc..a1b2c53 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index a75705a..bf81f9b 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index 346a890..c78266e 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index efba861..7c10aab 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -10,3 +10,4 @@
 # CONFIG_CMD_FPGA is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 02534bf..d69c9fc 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -28,6 +28,7 @@
 CONFIG_DEVRES=y
 CONFIG_ADC=y
 CONFIG_ADC_SANDBOX=y
+CONFIG_BLK=y
 CONFIG_CLK=y
 CONFIG_SANDBOX_GPIO=y
 CONFIG_SYS_I2C_SANDBOX=y
diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig
index 0d41602..b8949aa 100644
--- a/configs/sansa_fuze_plus_defconfig
+++ b/configs/sansa_fuze_plus_defconfig
@@ -5,3 +5,4 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig
index 068b1b6..3e23852 100644
--- a/configs/sbc8349_PCI_33_defconfig
+++ b/configs/sbc8349_PCI_33_defconfig
@@ -1,6 +1,9 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_SBC8349=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig
index 9939155..255d598 100644
--- a/configs/sbc8349_PCI_66_defconfig
+++ b/configs/sbc8349_PCI_66_defconfig
@@ -1,6 +1,9 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_SBC8349=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig
index f1e356d..f97d5ca 100644
--- a/configs/sbc8349_defconfig
+++ b/configs/sbc8349_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_SBC8349=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_33_PCIE_defconfig b/configs/sbc8548_PCI_33_PCIE_defconfig
index bf1f0a5..b6f3968 100644
--- a/configs/sbc8548_PCI_33_PCIE_defconfig
+++ b/configs/sbc8548_PCI_33_PCIE_defconfig
@@ -1,6 +1,9 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_SBC8548=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,33,PCIE"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_33_defconfig b/configs/sbc8548_PCI_33_defconfig
index 789333e..63f4943 100644
--- a/configs/sbc8548_PCI_33_defconfig
+++ b/configs/sbc8548_PCI_33_defconfig
@@ -1,6 +1,9 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_SBC8548=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,33"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_66_PCIE_defconfig b/configs/sbc8548_PCI_66_PCIE_defconfig
index e0f3752..367711b 100644
--- a/configs/sbc8548_PCI_66_PCIE_defconfig
+++ b/configs/sbc8548_PCI_66_PCIE_defconfig
@@ -1,6 +1,9 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_SBC8548=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,66,PCIE"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_66_defconfig b/configs/sbc8548_PCI_66_defconfig
index 132e66d..a682da2 100644
--- a/configs/sbc8548_PCI_66_defconfig
+++ b/configs/sbc8548_PCI_66_defconfig
@@ -1,6 +1,9 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_SBC8548=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,66"
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_defconfig b/configs/sbc8548_defconfig
index b8d9d5a..dede802 100644
--- a/configs/sbc8548_defconfig
+++ b/configs/sbc8548_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_SBC8548=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8641d_defconfig b/configs/sbc8641d_defconfig
index a37b18e..b61913e 100644
--- a/configs/sbc8641d_defconfig
+++ b/configs/sbc8641d_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC86xx=y
 CONFIG_TARGET_SBC8641D=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sc_sps_1_defconfig b/configs/sc_sps_1_defconfig
index a9aec82..06f2322 100644
--- a/configs/sc_sps_1_defconfig
+++ b/configs/sc_sps_1_defconfig
@@ -4,3 +4,4 @@
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig
index 7956670..cd3820d 100644
--- a/configs/seaboard_defconfig
+++ b/configs/seaboard_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TEGRA20=y
 CONFIG_TARGET_SEABOARD=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-seaboard"
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/secomx6quq7_defconfig b/configs/secomx6quq7_defconfig
index 5291881..0980e68 100644
--- a/configs/secomx6quq7_defconfig
+++ b/configs/secomx6quq7_defconfig
@@ -9,3 +9,4 @@
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sequoia_defconfig b/configs/sequoia_defconfig
index 39190a3..6f6007c 100644
--- a/configs/sequoia_defconfig
+++ b/configs/sequoia_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_SEQUOIA=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sequoia_ramboot_defconfig b/configs/sequoia_ramboot_defconfig
index b86b230..f805238 100644
--- a/configs/sequoia_ramboot_defconfig
+++ b/configs/sequoia_ramboot_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_SEQUOIA=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig
index 9b41460..a51abc7 100644
--- a/configs/sheevaplug_defconfig
+++ b/configs/sheevaplug_defconfig
@@ -10,3 +10,4 @@
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/silk_defconfig b/configs/silk_defconfig
index 836beff..67fca2a 100644
--- a/configs/silk_defconfig
+++ b/configs/silk_defconfig
@@ -20,3 +20,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 654bb4b..2cb9c71 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -2,8 +2,10 @@
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SMARTWEB=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
+CONFIG_OF_LIBFDT=y
diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig
index b0dec29..b3d16ab 100644
--- a/configs/smdk5250_defconfig
+++ b/configs/smdk5250_defconfig
@@ -4,6 +4,8 @@
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250"
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_BEST_MATCH=y
 CONFIG_SYS_PROMPT="SMDK5250 # "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig
index 50148fc..a84d159 100644
--- a/configs/smdk5420_defconfig
+++ b/configs/smdk5420_defconfig
@@ -4,6 +4,8 @@
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420"
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_BEST_MATCH=y
 CONFIG_SYS_PROMPT="SMDK5420 # "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig
index 83b52cf..9315b03 100644
--- a/configs/snapper9260_defconfig
+++ b/configs/snapper9260_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SNAPPER9260=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
 CONFIG_SYS_PROMPT="Snapper> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig
index 37a3e64..9c24d79 100644
--- a/configs/snapper9g20_defconfig
+++ b/configs/snapper9g20_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SNAPPER9260=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20"
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
index 0335795..370c5fd 100644
--- a/configs/sniper_defconfig
+++ b/configs/sniper_defconfig
@@ -12,3 +12,4 @@
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index 3d8081b..5dbd18a 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -4,6 +4,8 @@
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow"
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_BEST_MATCH=y
 CONFIG_SYS_PROMPT="snow # "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 6e8976f..7b60d95 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -7,22 +7,22 @@
 CONFIG_SPL_STACK_R_ADDR=0x00800000
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
 CONFIG_SPL=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
-CONFIG_DM_MMC=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index e31aa71..6a487f4 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -7,22 +7,22 @@
 CONFIG_SPL_STACK_R_ADDR=0x00800000
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
 CONFIG_SPL=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
-CONFIG_DM_MMC=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index 65c1197..cfcae5d 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -8,16 +8,16 @@
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SPL_SIMPLE_BUS=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_DM_MMC=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
-CONFIG_DM_MMC=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index c98d4a1..b6f6a65 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -8,16 +8,16 @@
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SPL_SIMPLE_BUS=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_DM_MMC=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
-CONFIG_DM_MMC=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 59fbb2c..f45c3ed 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -7,13 +7,14 @@
 CONFIG_SPL_STACK_R_ADDR=0x00800000
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
 CONFIG_SPL=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -23,6 +24,5 @@
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
-CONFIG_DM_MMC=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index aaba8cb..e25d09b 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -7,13 +7,14 @@
 CONFIG_SPL_STACK_R_ADDR=0x00800000
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
 CONFIG_SPL=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
-CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -22,6 +23,5 @@
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
-CONFIG_DM_MMC=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index a4f0835..59a6be4 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -4,18 +4,18 @@
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_SR1500=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
 CONFIG_SPL=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
+CONFIG_FIT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
-CONFIG_DM_MMC=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index 19cc388..3b73dbd 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig
@@ -1,6 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_SOCRATES=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/spring_defconfig b/configs/spring_defconfig
index 11cb6e3..352bd1a 100644
--- a/configs/spring_defconfig
+++ b/configs/spring_defconfig
@@ -4,6 +4,8 @@
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5250-spring"
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_BEST_MATCH=y
 CONFIG_SYS_PROMPT="spring # "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig
index fb330e2..00d105b 100644
--- a/configs/stm32f429-discovery_defconfig
+++ b/configs/stm32f429-discovery_defconfig
@@ -4,3 +4,4 @@
 CONFIG_TARGET_STM32F429_DISCOVERY=y
 CONFIG_SYS_PROMPT="U-Boot > "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/stout_defconfig b/configs/stout_defconfig
index d353495..c5af189 100644
--- a/configs/stout_defconfig
+++ b/configs/stout_defconfig
@@ -20,3 +20,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig
index 59fdc7b..704ad89 100644
--- a/configs/strider_con_defconfig
+++ b/configs/strider_con_defconfig
@@ -1,8 +1,13 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_STRIDER=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON"
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig
index a0584b8..81b706f 100644
--- a/configs/strider_cpu_defconfig
+++ b/configs/strider_cpu_defconfig
@@ -1,8 +1,13 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_STRIDER=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU"
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig
index d3de194..7f737f2 100644
--- a/configs/sunxi_Gemei_G9_defconfig
+++ b/configs/sunxi_Gemei_G9_defconfig
@@ -11,6 +11,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-gemei-g9"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig
index b0b8390..79a0ca6 100644
--- a/configs/suvd3_defconfig
+++ b/configs/suvd3_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_SUVD3=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SUVD3"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/sycamore_defconfig b/configs/sycamore_defconfig
index 29b3d2b..fa495ba 100644
--- a/configs/sycamore_defconfig
+++ b/configs/sycamore_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_WALNUT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/t3corp_defconfig b/configs/t3corp_defconfig
index 75eeda6..e9fe84d 100644
--- a/configs/t3corp_defconfig
+++ b/configs/t3corp_defconfig
@@ -1,4 +1,7 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_T3CORP=y
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig
index af4292b..c1eb34c 100644
--- a/configs/tao3530_defconfig
+++ b/configs/tao3530_defconfig
@@ -9,3 +9,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index 3f08cc1..0af7f2d 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -14,3 +14,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USE_TINY_PRINTF=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index c56c412..3cfa09a 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -1,9 +1,11 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TBS2910=y
+CONFIG_FIT=y
 CONFIG_SYS_PROMPT="Matrix U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_DM=y
 CONFIG_DM_THERMAL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig
index 3d10fd0..389603c 100644
--- a/configs/tec-ng_defconfig
+++ b/configs/tec-ng_defconfig
@@ -4,6 +4,8 @@
 CONFIG_TEGRA30=y
 CONFIG_TARGET_TEC_NG=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-tec-ng"
+CONFIG_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Tegra30 (TEC-NG) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/tec_defconfig b/configs/tec_defconfig
index 274fc9d..9b1d2fc 100644
--- a/configs/tec_defconfig
+++ b/configs/tec_defconfig
@@ -4,6 +4,8 @@
 CONFIG_TEGRA20=y
 CONFIG_TARGET_TEC=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-tec"
+CONFIG_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Tegra20 (TEC) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig
index fbed23c..62a6ee6 100644
--- a/configs/theadorable_debug_defconfig
+++ b/configs/theadorable_debug_defconfig
@@ -5,6 +5,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_FIT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
diff --git a/configs/theadorable_defconfig b/configs/theadorable_defconfig
index cce4669..4d5f3b0 100644
--- a/configs/theadorable_defconfig
+++ b/configs/theadorable_defconfig
@@ -5,6 +5,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_FIT=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index 13aade6..666cf5e 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -12,3 +12,4 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig
index 0c9a9d1..52d3a65 100644
--- a/configs/ti814x_evm_defconfig
+++ b/configs/ti814x_evm_defconfig
@@ -6,3 +6,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig
index 78f11f5..13a2c6e 100644
--- a/configs/ti816x_evm_defconfig
+++ b/configs/ti816x_evm_defconfig
@@ -6,3 +6,4 @@
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/titanium_defconfig b/configs/titanium_defconfig
index e7f594c..6c93616 100644
--- a/configs/titanium_defconfig
+++ b/configs/titanium_defconfig
@@ -7,3 +7,4 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig
index cdc51c0..6c52fff 100644
--- a/configs/tqma6q_mba6_mmc_defconfig
+++ b/configs/tqma6q_mba6_mmc_defconfig
@@ -1,8 +1,12 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TQMA6=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig
index 1408be3..85b239b 100644
--- a/configs/tqma6q_mba6_spi_defconfig
+++ b/configs/tqma6q_mba6_spi_defconfig
@@ -2,8 +2,12 @@
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TQMA6=y
 CONFIG_TQMA6X_SPI_BOOT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig
index 4e5428b..977f98a 100644
--- a/configs/tqma6s_mba6_mmc_defconfig
+++ b/configs/tqma6s_mba6_mmc_defconfig
@@ -2,8 +2,12 @@
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TQMA6=y
 CONFIG_TQMA6S=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig
index 04740ec..c6dac61 100644
--- a/configs/tqma6s_mba6_spi_defconfig
+++ b/configs/tqma6s_mba6_spi_defconfig
@@ -3,8 +3,12 @@
 CONFIG_TARGET_TQMA6=y
 CONFIG_TQMA6S=y
 CONFIG_TQMA6X_SPI_BOOT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig
index 1d47006..a7068e5 100644
--- a/configs/tqma6s_wru4_mmc_defconfig
+++ b/configs/tqma6s_wru4_mmc_defconfig
@@ -3,9 +3,13 @@
 CONFIG_TARGET_TQMA6=y
 CONFIG_TQMA6S=y
 CONFIG_WRU4=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Enter password in %d seconds to stop autoboot\n"
 CONFIG_AUTOBOOT_ENCRYPTION=y
 CONFIG_AUTOBOOT_STOP_STR_SHA256="36a9e7f1c95b82ffb99743e0c5c4ce95d83c9a430aac59f84ef3cbfab6145068"
 CONFIG_CMD_GPIO=y
 CONFIG_PCA9551_LED=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index e6b9381..9c281f8 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -3,6 +3,8 @@
 CONFIG_TARGET_TRATS2=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_PROMPT="Trats2 # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index 8234046..eef22a6 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -2,6 +2,8 @@
 CONFIG_ARCH_EXYNOS=y
 CONFIG_TARGET_TRATS=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_PROMPT="Trats # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/tricorder_defconfig b/configs/tricorder_defconfig
index c32ef86..bdd9c89 100644
--- a/configs/tricorder_defconfig
+++ b/configs/tricorder_defconfig
@@ -11,3 +11,4 @@
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/tricorder_flash_defconfig b/configs/tricorder_flash_defconfig
index 1cf3928..3bac8e3 100644
--- a/configs/tricorder_flash_defconfig
+++ b/configs/tricorder_flash_defconfig
@@ -11,3 +11,4 @@
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index e34faa3..a0b3a3e 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TEGRA20=y
 CONFIG_TARGET_TRIMSLICE=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-trimslice"
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Tegra20 (TrimSlice) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/ts4800_defconfig b/configs/ts4800_defconfig
index a2fa541..1b30033 100644
--- a/configs/ts4800_defconfig
+++ b/configs/ts4800_defconfig
@@ -2,3 +2,4 @@
 CONFIG_TARGET_TS4800=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/tseries_mmc_defconfig b/configs/tseries_mmc_defconfig
index 168e379..3fe06eb 100644
--- a/configs/tseries_mmc_defconfig
+++ b/configs/tseries_mmc_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_TSERIES=y
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
@@ -23,6 +24,7 @@
 CONFIG_CMD_TIME=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/tseries_nand_defconfig b/configs/tseries_nand_defconfig
index 8151caf..2993537 100644
--- a/configs/tseries_nand_defconfig
+++ b/configs/tseries_nand_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_TSERIES=y
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
@@ -24,6 +25,7 @@
 CONFIG_CMD_TIME=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/tseries_spi_defconfig b/configs/tseries_spi_defconfig
index 901c55e..4c6d544 100644
--- a/configs/tseries_spi_defconfig
+++ b/configs/tseries_spi_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_TSERIES=y
 CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
@@ -28,6 +29,7 @@
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig
index 1030dc7..b144575 100644
--- a/configs/tuge1_defconfig
+++ b/configs/tuge1_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_TUXX1=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="TUGE1"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig
index 7675fb3..7563336 100644
--- a/configs/tuxx1_defconfig
+++ b/configs/tuxx1_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_TUXX1=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="TUXX1"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/twister_defconfig b/configs/twister_defconfig
index e721edb..06c98eb 100644
--- a/configs/twister_defconfig
+++ b/configs/twister_defconfig
@@ -2,9 +2,11 @@
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_TWISTER=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_PROMPT="twister => "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
index 0a7f70a..3f53749 100644
--- a/configs/udoo_defconfig
+++ b/configs/udoo_defconfig
@@ -6,3 +6,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_DM=y
 CONFIG_DM_THERMAL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig
index 4d7afb8..a6862db 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -18,7 +18,6 @@
 CONFIG_CMD_TIME=y
 # CONFIG_CMD_MISC is not set
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_SIMPLE_BUS=y
 CONFIG_GPIO_UNIPHIER=y
 CONFIG_MMC_UNIPHIER=y
 CONFIG_NAND_DENALI=y
diff --git a/configs/uniphier_pro4_defconfig b/configs/uniphier_pro4_defconfig
index 45ef883..989f614 100644
--- a/configs/uniphier_pro4_defconfig
+++ b/configs/uniphier_pro4_defconfig
@@ -18,7 +18,6 @@
 CONFIG_CMD_TIME=y
 # CONFIG_CMD_MISC is not set
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_SIMPLE_BUS=y
 CONFIG_GPIO_UNIPHIER=y
 CONFIG_MMC_UNIPHIER=y
 CONFIG_NAND_DENALI=y
diff --git a/configs/uniphier_pxs2_ld6b_defconfig b/configs/uniphier_pxs2_ld6b_defconfig
index 4a8d70b..747aeb8 100644
--- a/configs/uniphier_pxs2_ld6b_defconfig
+++ b/configs/uniphier_pxs2_ld6b_defconfig
@@ -18,7 +18,6 @@
 CONFIG_CMD_TIME=y
 # CONFIG_CMD_MISC is not set
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_SIMPLE_BUS=y
 CONFIG_GPIO_UNIPHIER=y
 CONFIG_MMC_UNIPHIER=y
 CONFIG_NAND_DENALI=y
diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig
index edf2b83..e90dd66 100644
--- a/configs/usb_a9263_dataflash_defconfig
+++ b/configs/usb_a9263_dataflash_defconfig
@@ -11,3 +11,4 @@
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig
index c25d103..68f78b3 100644
--- a/configs/usbarmory_defconfig
+++ b/configs/usbarmory_defconfig
@@ -3,3 +3,4 @@
 CONFIG_TARGET_USBARMORY=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig
index 5a8ba8e..8624695 100644
--- a/configs/ve8313_defconfig
+++ b/configs/ve8313_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_VE8313=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index 05f6bc4..954c1de 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TEGRA124=y
 CONFIG_TARGET_VENICE2=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2"
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Tegra124 (Venice2) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig
index 66c9e26..9e4e7f6 100644
--- a/configs/ventana_defconfig
+++ b/configs/ventana_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TEGRA20=y
 CONFIG_TARGET_VENTANA=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-ventana"
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Tegra20 (Ventana) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/vexpress_aemv8a_dram_defconfig b/configs/vexpress_aemv8a_dram_defconfig
index cad4466..0b5799a 100644
--- a/configs/vexpress_aemv8a_dram_defconfig
+++ b/configs/vexpress_aemv8a_dram_defconfig
@@ -16,3 +16,4 @@
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_DM=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig
index bc3e05a..07036cc 100644
--- a/configs/vexpress_aemv8a_juno_defconfig
+++ b/configs/vexpress_aemv8a_juno_defconfig
@@ -16,3 +16,4 @@
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_DM=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig
index e899b90..16d6796 100644
--- a/configs/vexpress_aemv8a_semi_defconfig
+++ b/configs/vexpress_aemv8a_semi_defconfig
@@ -16,3 +16,4 @@
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_DM=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_ca15_tc2_defconfig b/configs/vexpress_ca15_tc2_defconfig
index a3ff78a..0016030 100644
--- a/configs/vexpress_ca15_tc2_defconfig
+++ b/configs/vexpress_ca15_tc2_defconfig
@@ -14,3 +14,4 @@
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_ca5x2_defconfig b/configs/vexpress_ca5x2_defconfig
index ce5da91..b260401 100644
--- a/configs/vexpress_ca5x2_defconfig
+++ b/configs/vexpress_ca5x2_defconfig
@@ -14,3 +14,4 @@
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig
index 2947fc1..4a64339 100644
--- a/configs/vexpress_ca9x4_defconfig
+++ b/configs/vexpress_ca9x4_defconfig
@@ -14,3 +14,4 @@
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig
index d959293..7c83887 100644
--- a/configs/vf610twr_defconfig
+++ b/configs/vf610twr_defconfig
@@ -14,3 +14,4 @@
 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
 CONFIG_SPI_FLASH=y
 CONFIG_FSL_LPUART=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig
index b6a96f2..4591526 100644
--- a/configs/vf610twr_nand_defconfig
+++ b/configs/vf610twr_nand_defconfig
@@ -14,3 +14,4 @@
 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
 CONFIG_SPI_FLASH=y
 CONFIG_FSL_LPUART=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig
index 7a91da3..e21d4ff 100644
--- a/configs/vme8349_defconfig
+++ b/configs/vme8349_defconfig
@@ -1,5 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC83xx=y
 CONFIG_TARGET_VME8349=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/walnut_defconfig b/configs/walnut_defconfig
index 29b3d2b..fa495ba 100644
--- a/configs/walnut_defconfig
+++ b/configs/walnut_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_WALNUT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index f2c9cd2..f6bd308 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -8,3 +8,4 @@
 CONFIG_CMD_GPIO=y
 CONFIG_DM=y
 CONFIG_DM_THERMAL=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/warp_defconfig b/configs/warp_defconfig
index f112d33..959e29c 100644
--- a/configs/warp_defconfig
+++ b/configs/warp_defconfig
@@ -8,3 +8,4 @@
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/whistler_defconfig b/configs/whistler_defconfig
index 9fa9664..a818a0f 100644
--- a/configs/whistler_defconfig
+++ b/configs/whistler_defconfig
@@ -4,6 +4,7 @@
 CONFIG_TEGRA20=y
 CONFIG_TARGET_WHISTLER=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-whistler"
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_PROMPT="Tegra20 (Whistler) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/wtk_defconfig b/configs/wtk_defconfig
index 7d4f754..3d046cd 100644
--- a/configs/wtk_defconfig
+++ b/configs/wtk_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM823L=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ065T9DR51U"
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/x600_defconfig b/configs/x600_defconfig
index 71dc7dc..881c080 100644
--- a/configs/x600_defconfig
+++ b/configs/x600_defconfig
@@ -10,3 +10,4 @@
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USE_TINY_PRINTF=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/xfi3_defconfig b/configs/xfi3_defconfig
index 3c7cb0d..437e018 100644
--- a/configs/xfi3_defconfig
+++ b/configs/xfi3_defconfig
@@ -5,3 +5,4 @@
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/xpedite1000_defconfig b/configs/xpedite1000_defconfig
index 3bccacb..45cd821 100644
--- a/configs/xpedite1000_defconfig
+++ b/configs/xpedite1000_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_XPEDITE1000=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/xpedite517x_defconfig b/configs/xpedite517x_defconfig
index 07c4642..38f6290 100644
--- a/configs/xpedite517x_defconfig
+++ b/configs/xpedite517x_defconfig
@@ -1,5 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC86xx=y
 CONFIG_TARGET_XPEDITE517X=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/xpedite520x_defconfig b/configs/xpedite520x_defconfig
index 6a25b47..d9957e0 100644
--- a/configs/xpedite520x_defconfig
+++ b/configs/xpedite520x_defconfig
@@ -1,5 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_XPEDITE520X=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/xpedite537x_defconfig b/configs/xpedite537x_defconfig
index 611f1b1..a4f648c 100644
--- a/configs/xpedite537x_defconfig
+++ b/configs/xpedite537x_defconfig
@@ -1,5 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_XPEDITE537X=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/xpedite550x_defconfig b/configs/xpedite550x_defconfig
index 8f6b433..10cf7e8 100644
--- a/configs/xpedite550x_defconfig
+++ b/configs/xpedite550x_defconfig
@@ -1,5 +1,10 @@
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_XPEDITE550X=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/yellowstone_defconfig b/configs/yellowstone_defconfig
index 7f4144c..773e93b 100644
--- a/configs/yellowstone_defconfig
+++ b/configs/yellowstone_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_YOSEMITE=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="YELLOWSTONE"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/yosemite_defconfig b/configs/yosemite_defconfig
index cd852c2..bad6df2 100644
--- a/configs/yosemite_defconfig
+++ b/configs/yosemite_defconfig
@@ -1,5 +1,7 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_YOSEMITE=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="YOSEMITE"
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/yucca_defconfig b/configs/yucca_defconfig
index c3e7a7a..5dbbaba 100644
--- a/configs/yucca_defconfig
+++ b/configs/yucca_defconfig
@@ -1,4 +1,6 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_YUCCA=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/disk/part.c b/disk/part.c
index 1935b28..67d98fe 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -7,6 +7,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <errno.h>
 #include <ide.h>
 #include <malloc.h>
 #include <part.h>
@@ -20,13 +21,7 @@
 #define PRINTF(fmt,args...)
 #endif
 
-struct block_drvr {
-	char *name;
-	block_dev_desc_t* (*get_dev)(int dev);
-	int (*select_hwpart)(int dev_num, int hwpart);
-};
-
-static const struct block_drvr block_drvr[] = {
+const struct block_drvr block_drvr[] = {
 #if defined(CONFIG_CMD_IDE)
 	{ .name = "ide", .get_dev = ide_get_dev, },
 #endif
@@ -58,10 +53,26 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef HAVE_BLOCK_DEVICE
-static block_dev_desc_t *get_dev_hwpart(const char *ifname, int dev, int hwpart)
+static struct part_driver *part_driver_lookup_type(int part_type)
+{
+	struct part_driver *drv =
+		ll_entry_start(struct part_driver, part_driver);
+	const int n_ents = ll_entry_count(struct part_driver, part_driver);
+	struct part_driver *entry;
+
+	for (entry = drv; entry != drv + n_ents; entry++) {
+		if (part_type == entry->part_type)
+			return entry;
+	}
+
+	/* Not found */
+	return NULL;
+}
+
+static struct blk_desc *get_dev_hwpart(const char *ifname, int dev, int hwpart)
 {
 	const struct block_drvr *drvr = block_drvr;
-	block_dev_desc_t* (*reloc_get_dev)(int dev);
+	struct blk_desc* (*reloc_get_dev)(int dev);
 	int (*select_hwpart)(int dev_num, int hwpart);
 	char *name;
 	int ret;
@@ -84,14 +95,14 @@
 			select_hwpart += gd->reloc_off;
 #endif
 		if (strncmp(ifname, name, strlen(name)) == 0) {
-			block_dev_desc_t *dev_desc = reloc_get_dev(dev);
+			struct blk_desc *dev_desc = reloc_get_dev(dev);
 			if (!dev_desc)
 				return NULL;
 			if (hwpart == 0 && !select_hwpart)
 				return dev_desc;
 			if (!select_hwpart)
 				return NULL;
-			ret = select_hwpart(dev_desc->dev, hwpart);
+			ret = select_hwpart(dev_desc->devnum, hwpart);
 			if (ret < 0)
 				return NULL;
 			return dev_desc;
@@ -101,17 +112,17 @@
 	return NULL;
 }
 
-block_dev_desc_t *get_dev(const char *ifname, int dev)
+struct blk_desc *blk_get_dev(const char *ifname, int dev)
 {
 	return get_dev_hwpart(ifname, dev, 0);
 }
 #else
-block_dev_desc_t *get_dev_hwpart(const char *ifname, int dev, int hwpart)
+struct blk_desc *get_dev_hwpart(const char *ifname, int dev, int hwpart)
 {
 	return NULL;
 }
 
-block_dev_desc_t *get_dev(const char *ifname, int dev)
+struct blk_desc *blk_get_dev(const char *ifname, int dev)
 {
 	return NULL;
 }
@@ -144,7 +155,7 @@
 	return bc_quot * mul_by + (bc_rem * mul_by) / div_by;
 }
 
-void dev_print (block_dev_desc_t *dev_desc)
+void dev_print (struct blk_desc *dev_desc)
 {
 	lba512_t lba512; /* number of blocks if 512bytes block size */
 
@@ -250,55 +261,33 @@
 
 #ifdef HAVE_BLOCK_DEVICE
 
-void init_part(block_dev_desc_t *dev_desc)
+void part_init(struct blk_desc *dev_desc)
 {
-#ifdef CONFIG_ISO_PARTITION
-	if (test_part_iso(dev_desc) == 0) {
-		dev_desc->part_type = PART_TYPE_ISO;
-		return;
-	}
-#endif
+	struct part_driver *drv =
+		ll_entry_start(struct part_driver, part_driver);
+	const int n_ents = ll_entry_count(struct part_driver, part_driver);
+	struct part_driver *entry;
 
-#ifdef CONFIG_MAC_PARTITION
-	if (test_part_mac(dev_desc) == 0) {
-		dev_desc->part_type = PART_TYPE_MAC;
-		return;
-	}
-#endif
-
-/* must be placed before DOS partition detection */
-#ifdef CONFIG_EFI_PARTITION
-	if (test_part_efi(dev_desc) == 0) {
-		dev_desc->part_type = PART_TYPE_EFI;
-		return;
-	}
-#endif
-
-#ifdef CONFIG_DOS_PARTITION
-	if (test_part_dos(dev_desc) == 0) {
-		dev_desc->part_type = PART_TYPE_DOS;
-		return;
-	}
-#endif
+	dev_desc->part_type = PART_TYPE_UNKNOWN;
+	for (entry = drv; entry != drv + n_ents; entry++) {
+		int ret;
 
-#ifdef CONFIG_AMIGA_PARTITION
-	if (test_part_amiga(dev_desc) == 0) {
-	    dev_desc->part_type = PART_TYPE_AMIGA;
-	    return;
+		ret = entry->test(dev_desc);
+		debug("%s: try '%s': ret=%d\n", __func__, entry->name, ret);
+		if (!ret) {
+			dev_desc->part_type = entry->part_type;
+			break;
+		}
 	}
-#endif
-	dev_desc->part_type = PART_TYPE_UNKNOWN;
 }
 
-
+static void print_part_header(const char *type, struct blk_desc *dev_desc)
+{
 #if defined(CONFIG_MAC_PARTITION) || \
 	defined(CONFIG_DOS_PARTITION) || \
 	defined(CONFIG_ISO_PARTITION) || \
 	defined(CONFIG_AMIGA_PARTITION) || \
 	defined(CONFIG_EFI_PARTITION)
-
-static void print_part_header(const char *type, block_dev_desc_t *dev_desc)
-{
 	puts ("\nPartition Map for ");
 	switch (dev_desc->if_type) {
 	case IF_TYPE_IDE:
@@ -330,63 +319,34 @@
 		break;
 	}
 	printf (" device %d  --   Partition Type: %s\n\n",
-			dev_desc->dev, type);
-}
-
+			dev_desc->devnum, type);
 #endif /* any CONFIG_..._PARTITION */
+}
 
-void print_part(block_dev_desc_t * dev_desc)
+void part_print(struct blk_desc *dev_desc)
 {
-
-		switch (dev_desc->part_type) {
-#ifdef CONFIG_MAC_PARTITION
-	case PART_TYPE_MAC:
-		PRINTF ("## Testing for valid MAC partition ##\n");
-		print_part_header ("MAC", dev_desc);
-		print_part_mac (dev_desc);
-		return;
-#endif
-#ifdef CONFIG_DOS_PARTITION
-	case PART_TYPE_DOS:
-		PRINTF ("## Testing for valid DOS partition ##\n");
-		print_part_header ("DOS", dev_desc);
-		print_part_dos (dev_desc);
-		return;
-#endif
-
-#ifdef CONFIG_ISO_PARTITION
-	case PART_TYPE_ISO:
-		PRINTF ("## Testing for valid ISO Boot partition ##\n");
-		print_part_header ("ISO", dev_desc);
-		print_part_iso (dev_desc);
-		return;
-#endif
+	struct part_driver *drv;
 
-#ifdef CONFIG_AMIGA_PARTITION
-	case PART_TYPE_AMIGA:
-	    PRINTF ("## Testing for a valid Amiga partition ##\n");
-	    print_part_header ("AMIGA", dev_desc);
-	    print_part_amiga (dev_desc);
-	    return;
-#endif
-
-#ifdef CONFIG_EFI_PARTITION
-	case PART_TYPE_EFI:
-		PRINTF ("## Testing for valid EFI partition ##\n");
-		print_part_header ("EFI", dev_desc);
-		print_part_efi (dev_desc);
+	drv = part_driver_lookup_type(dev_desc->part_type);
+	if (!drv) {
+		printf("## Unknown partition table type %x\n",
+		       dev_desc->part_type);
 		return;
-#endif
 	}
-	puts ("## Unknown partition table\n");
+
+	PRINTF("## Testing for valid %s partition ##\n", drv->name);
+	print_part_header(drv->name, dev_desc);
+	if (drv->print)
+		drv->print(dev_desc);
 }
 
 #endif /* HAVE_BLOCK_DEVICE */
 
-int get_partition_info(block_dev_desc_t *dev_desc, int part,
+int part_get_info(struct blk_desc *dev_desc, int part,
 		       disk_partition_t *info)
 {
 #ifdef HAVE_BLOCK_DEVICE
+	struct part_driver *drv;
 
 #ifdef CONFIG_PARTITION_UUIDS
 	/* The common case is no UUID support */
@@ -396,61 +356,27 @@
 	info->type_guid[0] = 0;
 #endif
 
-	switch (dev_desc->part_type) {
-#ifdef CONFIG_MAC_PARTITION
-	case PART_TYPE_MAC:
-		if (get_partition_info_mac(dev_desc, part, info) == 0) {
-			PRINTF("## Valid MAC partition found ##\n");
-			return 0;
-		}
-		break;
-#endif
-
-#ifdef CONFIG_DOS_PARTITION
-	case PART_TYPE_DOS:
-		if (get_partition_info_dos(dev_desc, part, info) == 0) {
-			PRINTF("## Valid DOS partition found ##\n");
-			return 0;
-		}
-		break;
-#endif
-
-#ifdef CONFIG_ISO_PARTITION
-	case PART_TYPE_ISO:
-		if (get_partition_info_iso(dev_desc, part, info) == 0) {
-			PRINTF("## Valid ISO boot partition found ##\n");
-			return 0;
-		}
-		break;
-#endif
-
-#ifdef CONFIG_AMIGA_PARTITION
-	case PART_TYPE_AMIGA:
-		if (get_partition_info_amiga(dev_desc, part, info) == 0) {
-			PRINTF("## Valid Amiga partition found ##\n");
-			return 0;
-		}
-		break;
-#endif
-
-#ifdef CONFIG_EFI_PARTITION
-	case PART_TYPE_EFI:
-		if (get_partition_info_efi(dev_desc, part, info) == 0) {
-			PRINTF("## Valid EFI partition found ##\n");
-			return 0;
-		}
-		break;
-#endif
-	default:
-		break;
+	drv = part_driver_lookup_type(dev_desc->part_type);
+	if (!drv) {
+		debug("## Unknown partition table type %x\n",
+		      dev_desc->part_type);
+		return -EPROTONOSUPPORT;
+	}
+	if (!drv->get_info) {
+		PRINTF("## Driver %s does not have the get_info() method\n");
+		return -ENOSYS;
+	}
+	if (drv->get_info(dev_desc, part, info) == 0) {
+		PRINTF("## Valid %s partition found ##\n", drv->name);
+		return 0;
 	}
 #endif /* HAVE_BLOCK_DEVICE */
 
 	return -1;
 }
 
-int get_device(const char *ifname, const char *dev_hwpart_str,
-	       block_dev_desc_t **dev_desc)
+int blk_get_device_by_str(const char *ifname, const char *dev_hwpart_str,
+			  struct blk_desc **dev_desc)
 {
 	char *ep;
 	char *dup_str = NULL;
@@ -500,7 +426,7 @@
 	 * already loaded.
 	 */
 	if(hwpart != 0)
-		init_part(*dev_desc);
+		part_init(*dev_desc);
 #endif
 
 cleanup:
@@ -511,8 +437,8 @@
 #define PART_UNSPECIFIED -2
 #define PART_AUTO -1
 #define MAX_SEARCH_PARTITIONS 16
-int get_device_and_partition(const char *ifname, const char *dev_part_str,
-			     block_dev_desc_t **dev_desc,
+int blk_get_device_part_str(const char *ifname, const char *dev_part_str,
+			     struct blk_desc **dev_desc,
 			     disk_partition_t *info, int allow_whole_dev)
 {
 	int ret = -1;
@@ -525,10 +451,6 @@
 	int part;
 	disk_partition_t tmpinfo;
 
-#if defined CONFIG_SANDBOX && defined CONFIG_CMD_UBIFS
-#error Only one of CONFIG_SANDBOX and CONFIG_CMD_UBIFS may be selected
-#endif
-
 #ifdef CONFIG_SANDBOX
 	/*
 	 * Special-case a pseudo block device "hostfs", to allow access to the
@@ -598,7 +520,7 @@
 	}
 
 	/* Look up the device */
-	dev = get_device(ifname, dev_str, dev_desc);
+	dev = blk_get_device_by_str(ifname, dev_str, dev_desc);
 	if (dev < 0)
 		goto cleanup;
 
@@ -675,7 +597,7 @@
 	 * other than "auto", use that partition number directly.
 	 */
 	if (part != PART_AUTO) {
-		ret = get_partition_info(*dev_desc, part, info);
+		ret = part_get_info(*dev_desc, part, info);
 		if (ret) {
 			printf("** Invalid partition %d **\n", part);
 			goto cleanup;
@@ -687,7 +609,7 @@
 		 */
 		part = 0;
 		for (p = 1; p <= MAX_SEARCH_PARTITIONS; p++) {
-			ret = get_partition_info(*dev_desc, p, info);
+			ret = part_get_info(*dev_desc, p, info);
 			if (ret)
 				continue;
 
diff --git a/disk/part_amiga.c b/disk/part_amiga.c
index 57c1b9d..d4316b8 100644
--- a/disk/part_amiga.c
+++ b/disk/part_amiga.c
@@ -126,7 +126,7 @@
  * the ID AMIGA_ID_RDISK ('RDSK') and needs to have a valid
  * sum-to-zero checksum
  */
-struct rigid_disk_block *get_rdisk(block_dev_desc_t *dev_desc)
+struct rigid_disk_block *get_rdisk(struct blk_desc *dev_desc)
 {
     int i;
     int limit;
@@ -140,7 +140,7 @@
 
     for (i=0; i<limit; i++)
     {
-	ulong res = dev_desc->block_read(dev_desc, i, 1, (ulong *)block_buffer);
+	ulong res = blk_dread(dev_desc, i, 1, (ulong *)block_buffer);
 	if (res == 1)
 	{
 	    struct rigid_disk_block *trdb = (struct rigid_disk_block *)block_buffer;
@@ -166,7 +166,7 @@
  * Ridgid disk block
  */
 
-struct bootcode_block *get_bootcode(block_dev_desc_t *dev_desc)
+struct bootcode_block *get_bootcode(struct blk_desc *dev_desc)
 {
     int i;
     int limit;
@@ -182,7 +182,7 @@
 
     for (i = 0; i < limit; i++)
     {
-	ulong res = dev_desc->block_read(dev_desc, i, 1, (ulong *)block_buffer);
+	ulong res = blk_dread(dev_desc, i, 1, (ulong *)block_buffer);
 	if (res == 1)
 	{
 	    struct bootcode_block *boot = (struct bootcode_block *)block_buffer;
@@ -207,27 +207,27 @@
  * Test if the given partition has an Amiga partition table/Rigid
  * Disk block
  */
-int test_part_amiga(block_dev_desc_t *dev_desc)
+static int part_test_amiga(struct blk_desc *dev_desc)
 {
     struct rigid_disk_block *rdb;
     struct bootcode_block *bootcode;
 
-    PRINTF("test_part_amiga: Testing for an Amiga RDB partition\n");
+    PRINTF("part_test_amiga: Testing for an Amiga RDB partition\n");
 
     rdb = get_rdisk(dev_desc);
     if (rdb)
     {
 	bootcode = get_bootcode(dev_desc);
 	if (bootcode)
-	    PRINTF("test_part_amiga: bootable Amiga disk\n");
+	    PRINTF("part_test_amiga: bootable Amiga disk\n");
 	else
-	    PRINTF("test_part_amiga: non-bootable Amiga disk\n");
+	    PRINTF("part_test_amiga: non-bootable Amiga disk\n");
 
 	return 0;
     }
     else
     {
-	PRINTF("test_part_amiga: no RDB found\n");
+	PRINTF("part_test_amiga: no RDB found\n");
 	return -1;
     }
 
@@ -236,7 +236,8 @@
 /*
  * Find partition number partnum on the given drive.
  */
-static struct partition_block *find_partition(block_dev_desc_t *dev_desc, int partnum)
+static struct partition_block *find_partition(struct blk_desc *dev_desc,
+					      int partnum)
 {
     struct rigid_disk_block *rdb;
     struct partition_block *p;
@@ -257,8 +258,7 @@
 
     while (block != 0xFFFFFFFF)
     {
-	ulong res = dev_desc->block_read(dev_desc, block, 1,
-					 (ulong *)block_buffer);
+	ulong res = blk_dread(dev_desc, block, 1, (ulong *)block_buffer);
 	if (res == 1)
 	{
 	    p = (struct partition_block *)block_buffer;
@@ -290,7 +290,8 @@
 /*
  * Get info about a partition
  */
-int get_partition_info_amiga (block_dev_desc_t *dev_desc, int part, disk_partition_t *info)
+static int part_get_info_amiga(struct blk_desc *dev_desc, int part,
+				    disk_partition_t *info)
 {
     struct partition_block *p = find_partition(dev_desc, part-1);
     struct amiga_part_geometry *g;
@@ -302,7 +303,7 @@
     info->start = g->low_cyl  * g->block_per_track * g->surfaces;
     info->size  = (g->high_cyl - g->low_cyl + 1) * g->block_per_track * g->surfaces - 1;
     info->blksz = rdb.block_bytes;
-    bcpl_strcpy(info->name, p->drive_name);
+    bcpl_strcpy((char *)info->name, p->drive_name);
 
 
     disk_type = g->dos_type;
@@ -317,7 +318,7 @@
     return 0;
 }
 
-void print_part_amiga (block_dev_desc_t *dev_desc)
+static void part_print_amiga(struct blk_desc *dev_desc)
 {
     struct rigid_disk_block *rdb;
     struct bootcode_block *boot;
@@ -328,14 +329,14 @@
     rdb = get_rdisk(dev_desc);
     if (!rdb)
     {
-	PRINTF("print_part_amiga: no rdb found\n");
+	PRINTF("part_print_amiga: no rdb found\n");
 	return;
     }
 
-    PRINTF("print_part_amiga: Scanning partition list\n");
+    PRINTF("part_print_amiga: Scanning partition list\n");
 
     block = rdb->partition_list;
-    PRINTF("print_part_amiga: partition list at 0x%x\n", block);
+    PRINTF("part_print_amiga: partition list at 0x%x\n", block);
 
     printf("Summary:  DiskBlockSize: %d\n"
 	   "          Cylinders    : %d\n"
@@ -353,7 +354,7 @@
 
 	PRINTF("Trying to load block #0x%X\n", block);
 
-	res = dev_desc->block_read(dev_desc, block, 1, (ulong *)block_buffer);
+	res = blk_dread(dev_desc, block, 1, (ulong *)block_buffer);
 	if (res == 1)
 	{
 	    p = (struct partition_block *)block_buffer;
@@ -377,4 +378,12 @@
     }
 }
 
+U_BOOT_PART_TYPE(amiga) = {
+	.name		= "AMIGA",
+	.part_type	= PART_TYPE_AMIGA,
+	.get_info	= part_get_info_amiga,
+	.print		= part_print_amiga,
+	.test		= part_test_amiga,
+};
+
 #endif
diff --git a/disk/part_dos.c b/disk/part_dos.c
index 08872d6..511917a 100644
--- a/disk/part_dos.c
+++ b/disk/part_dos.c
@@ -87,11 +87,11 @@
 }
 
 
-int test_part_dos (block_dev_desc_t *dev_desc)
+static int part_test_dos(struct blk_desc *dev_desc)
 {
 	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
 
-	if (dev_desc->block_read(dev_desc, 0, 1, (ulong *)buffer) != 1)
+	if (blk_dread(dev_desc, 0, 1, (ulong *)buffer) != 1)
 		return -1;
 
 	if (test_block_type(buffer) != DOS_MBR)
@@ -102,7 +102,7 @@
 
 /*  Print a partition that is relative to its Extended partition table
  */
-static void print_partition_extended(block_dev_desc_t *dev_desc,
+static void print_partition_extended(struct blk_desc *dev_desc,
 				     lbaint_t ext_part_sector,
 				     lbaint_t relative,
 				     int part_num, unsigned int disksig)
@@ -111,10 +111,9 @@
 	dos_partition_t *pt;
 	int i;
 
-	if (dev_desc->block_read(dev_desc, ext_part_sector, 1,
-				 (ulong *)buffer) != 1) {
+	if (blk_dread(dev_desc, ext_part_sector, 1, (ulong *)buffer) != 1) {
 		printf ("** Can't read partition table on %d:" LBAFU " **\n",
-			dev_desc->dev, ext_part_sector);
+			dev_desc->devnum, ext_part_sector);
 		return;
 	}
 	i=test_block_type(buffer);
@@ -167,21 +166,19 @@
 
 /*  Print a partition that is relative to its Extended partition table
  */
-static int get_partition_info_extended (block_dev_desc_t *dev_desc,
-				 lbaint_t ext_part_sector,
-				 lbaint_t relative, int part_num,
-				 int which_part, disk_partition_t *info,
-				 unsigned int disksig)
+static int part_get_info_extended(struct blk_desc *dev_desc,
+				  lbaint_t ext_part_sector, lbaint_t relative,
+				  int part_num, int which_part,
+				  disk_partition_t *info, unsigned int disksig)
 {
 	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
 	dos_partition_t *pt;
 	int i;
 	int dos_type;
 
-	if (dev_desc->block_read(dev_desc, ext_part_sector, 1,
-				 (ulong *)buffer) != 1) {
+	if (blk_dread(dev_desc, ext_part_sector, 1, (ulong *)buffer) != 1) {
 		printf ("** Can't read partition table on %d:" LBAFU " **\n",
-			dev_desc->dev, ext_part_sector);
+			dev_desc->devnum, ext_part_sector);
 		return -1;
 	}
 	if (buffer[DOS_PART_MAGIC_OFFSET] != 0x55 ||
@@ -216,24 +213,29 @@
 				case IF_TYPE_IDE:
 				case IF_TYPE_SATA:
 				case IF_TYPE_ATAPI:
-					sprintf ((char *)info->name, "hd%c%d",
-						'a' + dev_desc->dev, part_num);
+					sprintf((char *)info->name, "hd%c%d",
+						'a' + dev_desc->devnum,
+						part_num);
 					break;
 				case IF_TYPE_SCSI:
-					sprintf ((char *)info->name, "sd%c%d",
-						'a' + dev_desc->dev, part_num);
+					sprintf((char *)info->name, "sd%c%d",
+						'a' + dev_desc->devnum,
+						part_num);
 					break;
 				case IF_TYPE_USB:
-					sprintf ((char *)info->name, "usbd%c%d",
-						'a' + dev_desc->dev, part_num);
+					sprintf((char *)info->name, "usbd%c%d",
+						'a' + dev_desc->devnum,
+						part_num);
 					break;
 				case IF_TYPE_DOC:
-					sprintf ((char *)info->name, "docd%c%d",
-						'a' + dev_desc->dev, part_num);
+					sprintf((char *)info->name, "docd%c%d",
+						'a' + dev_desc->devnum,
+						part_num);
 					break;
 				default:
-					sprintf ((char *)info->name, "xx%c%d",
-						'a' + dev_desc->dev, part_num);
+					sprintf((char *)info->name, "xx%c%d",
+						'a' + dev_desc->devnum,
+						part_num);
 					break;
 			}
 			/* sprintf(info->type, "%d, pt->sys_ind); */
@@ -259,7 +261,7 @@
 			lbaint_t lba_start
 				= le32_to_int (pt->start4) + relative;
 
-			return get_partition_info_extended (dev_desc, lba_start,
+			return part_get_info_extended(dev_desc, lba_start,
 				 ext_part_sector == 0 ? lba_start : relative,
 				 part_num, which_part, info, disksig);
 		}
@@ -283,16 +285,24 @@
 	return -1;
 }
 
-void print_part_dos (block_dev_desc_t *dev_desc)
+void part_print_dos(struct blk_desc *dev_desc)
 {
 	printf("Part\tStart Sector\tNum Sectors\tUUID\t\tType\n");
 	print_partition_extended(dev_desc, 0, 0, 1, 0);
 }
 
-int get_partition_info_dos (block_dev_desc_t *dev_desc, int part, disk_partition_t * info)
+int part_get_info_dos(struct blk_desc *dev_desc, int part,
+		      disk_partition_t *info)
 {
-	return get_partition_info_extended(dev_desc, 0, 0, 1, part, info, 0);
+	return part_get_info_extended(dev_desc, 0, 0, 1, part, info, 0);
 }
 
+U_BOOT_PART_TYPE(dos) = {
+	.name		= "DOS",
+	.part_type	= PART_TYPE_DOS,
+	.get_info	= part_get_info_ptr(part_get_info_dos),
+	.print		= part_print_ptr(part_print_dos),
+	.test		= part_test_dos,
+};
 
 #endif
diff --git a/disk/part_efi.c b/disk/part_efi.c
index e1b58c5..77bdfcb 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -41,10 +41,10 @@
 
 static int pmbr_part_valid(struct partition *part);
 static int is_pmbr_valid(legacy_mbr * mbr);
-static int is_gpt_valid(block_dev_desc_t *dev_desc, u64 lba,
+static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba,
 				gpt_header *pgpt_head, gpt_entry **pgpt_pte);
-static gpt_entry *alloc_read_gpt_entries(block_dev_desc_t * dev_desc,
-				gpt_header * pgpt_head);
+static gpt_entry *alloc_read_gpt_entries(struct blk_desc *dev_desc,
+					 gpt_header *pgpt_head);
 static int is_pte_valid(gpt_entry * pte);
 
 static char *print_efiname(gpt_entry *pte)
@@ -176,7 +176,7 @@
  * Public Functions (include/part.h)
  */
 
-void print_part_efi(block_dev_desc_t * dev_desc)
+void part_print_efi(struct blk_desc *dev_desc)
 {
 	ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz);
 	gpt_entry *gpt_pte = NULL;
@@ -237,8 +237,8 @@
 	return;
 }
 
-int get_partition_info_efi(block_dev_desc_t * dev_desc, int part,
-				disk_partition_t * info)
+int part_get_info_efi(struct blk_desc *dev_desc, int part,
+		      disk_partition_t *info)
 {
 	ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz);
 	gpt_entry *gpt_pte = NULL;
@@ -300,13 +300,13 @@
 	return 0;
 }
 
-int get_partition_info_efi_by_name(block_dev_desc_t *dev_desc,
+int part_get_info_efi_by_name(struct blk_desc *dev_desc,
 	const char *name, disk_partition_t *info)
 {
 	int ret;
 	int i;
 	for (i = 1; i < GPT_ENTRY_NUMBERS; i++) {
-		ret = get_partition_info_efi(dev_desc, i, info);
+		ret = part_get_info_efi(dev_desc, i, info);
 		if (ret != 0) {
 			/* no more entries in table */
 			return -1;
@@ -319,12 +319,12 @@
 	return -2;
 }
 
-int test_part_efi(block_dev_desc_t * dev_desc)
+static int part_test_efi(struct blk_desc *dev_desc)
 {
 	ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, legacymbr, 1, dev_desc->blksz);
 
 	/* Read legacy MBR from block 0 and validate it */
-	if ((dev_desc->block_read(dev_desc, 0, 1, (ulong *)legacymbr) != 1)
+	if ((blk_dread(dev_desc, 0, 1, (ulong *)legacymbr) != 1)
 		|| (is_pmbr_valid(legacymbr) != 1)) {
 		return -1;
 	}
@@ -337,7 +337,7 @@
  *
  * @return - zero on success, otherwise error
  */
-static int set_protective_mbr(block_dev_desc_t *dev_desc)
+static int set_protective_mbr(struct blk_desc *dev_desc)
 {
 	/* Setup the Protective MBR */
 	ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, p_mbr, 1);
@@ -354,16 +354,16 @@
 	p_mbr->partition_record[0].nr_sects = (u32) dev_desc->lba - 1;
 
 	/* Write MBR sector to the MMC device */
-	if (dev_desc->block_write(dev_desc, 0, 1, p_mbr) != 1) {
+	if (blk_dwrite(dev_desc, 0, 1, p_mbr) != 1) {
 		printf("** Can't write to device %d **\n",
-			dev_desc->dev);
+			dev_desc->devnum);
 		return -1;
 	}
 
 	return 0;
 }
 
-int write_gpt_table(block_dev_desc_t *dev_desc,
+int write_gpt_table(struct blk_desc *dev_desc,
 		gpt_header *gpt_h, gpt_entry *gpt_e)
 {
 	const int pte_blk_cnt = BLOCK_CNT((gpt_h->num_partition_entries
@@ -386,31 +386,28 @@
 	gpt_h->header_crc32 = cpu_to_le32(calc_crc32);
 
 	/* Write the First GPT to the block right after the Legacy MBR */
-	if (dev_desc->block_write(dev_desc, 1, 1, gpt_h) != 1)
+	if (blk_dwrite(dev_desc, 1, 1, gpt_h) != 1)
 		goto err;
 
-	if (dev_desc->block_write(dev_desc, 2, pte_blk_cnt, gpt_e)
+	if (blk_dwrite(dev_desc, 2, pte_blk_cnt, gpt_e)
 	    != pte_blk_cnt)
 		goto err;
 
 	prepare_backup_gpt_header(gpt_h);
 
-	if (dev_desc->block_write(dev_desc,
-				  (lbaint_t)le64_to_cpu(gpt_h->last_usable_lba)
-				  + 1,
-				  pte_blk_cnt, gpt_e) != pte_blk_cnt)
+	if (blk_dwrite(dev_desc, (lbaint_t)le64_to_cpu(gpt_h->last_usable_lba)
+		       + 1, pte_blk_cnt, gpt_e) != pte_blk_cnt)
 		goto err;
 
-	if (dev_desc->block_write(dev_desc,
-				  (lbaint_t)le64_to_cpu(gpt_h->my_lba), 1,
-				  gpt_h) != 1)
+	if (blk_dwrite(dev_desc, (lbaint_t)le64_to_cpu(gpt_h->my_lba), 1,
+		       gpt_h) != 1)
 		goto err;
 
 	debug("GPT successfully written to block device!\n");
 	return 0;
 
  err:
-	printf("** Can't write to device %d **\n", dev_desc->dev);
+	printf("** Can't write to device %d **\n", dev_desc->devnum);
 	return -1;
 }
 
@@ -517,7 +514,7 @@
 	return 0;
 }
 
-int gpt_fill_header(block_dev_desc_t *dev_desc, gpt_header *gpt_h,
+int gpt_fill_header(struct blk_desc *dev_desc, gpt_header *gpt_h,
 		char *str_guid, int parts_count)
 {
 	gpt_h->signature = cpu_to_le64(GPT_HEADER_SIGNATURE);
@@ -539,7 +536,7 @@
 	return 0;
 }
 
-int gpt_restore(block_dev_desc_t *dev_desc, char *str_disk_guid,
+int gpt_restore(struct blk_desc *dev_desc, char *str_disk_guid,
 		disk_partition_t *partitions, int parts_count)
 {
 	int ret;
@@ -595,7 +592,7 @@
 	}
 }
 
-int gpt_verify_headers(block_dev_desc_t *dev_desc, gpt_header *gpt_head,
+int gpt_verify_headers(struct blk_desc *dev_desc, gpt_header *gpt_head,
 		       gpt_entry **gpt_pte)
 {
 	/*
@@ -619,7 +616,7 @@
 	return 0;
 }
 
-int gpt_verify_partitions(block_dev_desc_t *dev_desc,
+int gpt_verify_partitions(struct blk_desc *dev_desc,
 			  disk_partition_t *partitions, int parts,
 			  gpt_header *gpt_head, gpt_entry **gpt_pte)
 {
@@ -658,11 +655,13 @@
 		gpt_part_size = le64_to_cpu(gpt_e[i].ending_lba) -
 			le64_to_cpu(gpt_e[i].starting_lba) + 1;
 		debug("size(LBA) - GPT: %8llu, ENV: %8llu ",
-		      gpt_part_size, (u64) partitions[i].size);
+		      (unsigned long long)gpt_part_size,
+		      (unsigned long long)partitions[i].size);
 
 		if (le64_to_cpu(gpt_part_size) != partitions[i].size) {
 			error("Partition %s size: %llu does not match %llu!\n",
-			      efi_str, gpt_part_size, (u64) partitions[i].size);
+			      efi_str, (unsigned long long)gpt_part_size,
+			      (unsigned long long)partitions[i].size);
 			return -1;
 		}
 
@@ -678,12 +677,12 @@
 		/* Check if GPT and ENV start LBAs match */
 		debug("start LBA - GPT: %8llu, ENV: %8llu\n",
 		      le64_to_cpu(gpt_e[i].starting_lba),
-		      (u64) partitions[i].start);
+		      (unsigned long long)partitions[i].start);
 
 		if (le64_to_cpu(gpt_e[i].starting_lba) != partitions[i].start) {
 			error("Partition %s start: %llu does not match %llu!\n",
 			      efi_str, le64_to_cpu(gpt_e[i].starting_lba),
-			      (u64) partitions[i].start);
+			      (unsigned long long)partitions[i].start);
 			return -1;
 		}
 	}
@@ -691,7 +690,7 @@
 	return 0;
 }
 
-int is_valid_gpt_buf(block_dev_desc_t *dev_desc, void *buf)
+int is_valid_gpt_buf(struct blk_desc *dev_desc, void *buf)
 {
 	gpt_header *gpt_h;
 	gpt_entry *gpt_e;
@@ -712,7 +711,7 @@
 	return 0;
 }
 
-int write_mbr_and_gpt_partitions(block_dev_desc_t *dev_desc, void *buf)
+int write_mbr_and_gpt_partitions(struct blk_desc *dev_desc, void *buf)
 {
 	gpt_header *gpt_h;
 	gpt_entry *gpt_e;
@@ -737,7 +736,7 @@
 	/* write MBR */
 	lba = 0;	/* MBR is always at 0 */
 	cnt = 1;	/* MBR (1 block) */
-	if (dev_desc->block_write(dev_desc, lba, cnt, buf) != cnt) {
+	if (blk_dwrite(dev_desc, lba, cnt, buf) != cnt) {
 		printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
 		       __func__, "MBR", cnt, lba);
 		return 1;
@@ -746,7 +745,7 @@
 	/* write Primary GPT */
 	lba = GPT_PRIMARY_PARTITION_TABLE_LBA;
 	cnt = 1;	/* GPT Header (1 block) */
-	if (dev_desc->block_write(dev_desc, lba, cnt, gpt_h) != cnt) {
+	if (blk_dwrite(dev_desc, lba, cnt, gpt_h) != cnt) {
 		printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
 		       __func__, "Primary GPT Header", cnt, lba);
 		return 1;
@@ -754,7 +753,7 @@
 
 	lba = le64_to_cpu(gpt_h->partition_entry_lba);
 	cnt = gpt_e_blk_cnt;
-	if (dev_desc->block_write(dev_desc, lba, cnt, gpt_e) != cnt) {
+	if (blk_dwrite(dev_desc, lba, cnt, gpt_e) != cnt) {
 		printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
 		       __func__, "Primary GPT Entries", cnt, lba);
 		return 1;
@@ -765,7 +764,7 @@
 	/* write Backup GPT */
 	lba = le64_to_cpu(gpt_h->partition_entry_lba);
 	cnt = gpt_e_blk_cnt;
-	if (dev_desc->block_write(dev_desc, lba, cnt, gpt_e) != cnt) {
+	if (blk_dwrite(dev_desc, lba, cnt, gpt_e) != cnt) {
 		printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
 		       __func__, "Backup GPT Entries", cnt, lba);
 		return 1;
@@ -773,7 +772,7 @@
 
 	lba = le64_to_cpu(gpt_h->my_lba);
 	cnt = 1;	/* GPT Header (1 block) */
-	if (dev_desc->block_write(dev_desc, lba, cnt, gpt_h) != cnt) {
+	if (blk_dwrite(dev_desc, lba, cnt, gpt_h) != cnt) {
 		printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
 		       __func__, "Backup GPT Header", cnt, lba);
 		return 1;
@@ -834,7 +833,7 @@
  * Description: returns 1 if valid,  0 on error.
  * If valid, returns pointers to PTEs.
  */
-static int is_gpt_valid(block_dev_desc_t *dev_desc, u64 lba,
+static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba,
 			gpt_header *pgpt_head, gpt_entry **pgpt_pte)
 {
 	if (!dev_desc || !pgpt_head) {
@@ -843,7 +842,7 @@
 	}
 
 	/* Read GPT Header from device */
-	if (dev_desc->block_read(dev_desc, (lbaint_t)lba, 1, pgpt_head) != 1) {
+	if (blk_dread(dev_desc, (lbaint_t)lba, 1, pgpt_head) != 1) {
 		printf("*** ERROR: Can't read GPT header ***\n");
 		return 0;
 	}
@@ -876,8 +875,8 @@
  * Allocates space for PTEs based on information found in @gpt.
  * Notes: remember to free pte when you're done!
  */
-static gpt_entry *alloc_read_gpt_entries(block_dev_desc_t * dev_desc,
-					 gpt_header * pgpt_head)
+static gpt_entry *alloc_read_gpt_entries(struct blk_desc *dev_desc,
+					 gpt_header *pgpt_head)
 {
 	size_t count = 0, blk_cnt;
 	lbaint_t blk;
@@ -911,8 +910,7 @@
 	/* Read GPT Entries from device */
 	blk = le64_to_cpu(pgpt_head->partition_entry_lba);
 	blk_cnt = BLOCK_CNT(count, dev_desc);
-	if (dev_desc->block_read(dev_desc, blk, (lbaint_t)blk_cnt, pte)
-	    != blk_cnt) {
+	if (blk_dread(dev_desc, blk, (lbaint_t)blk_cnt, pte) != blk_cnt) {
 		printf("*** ERROR: Can't read GPT Entries ***\n");
 		free(pte);
 		return NULL;
@@ -951,4 +949,17 @@
 		return 1;
 	}
 }
+
+/*
+ * Add an 'a_' prefix so it comes before 'dos' in the linker list. We need to
+ * check EFI first, since a DOS partition is often used as a 'protective MBR'
+ * with EFI.
+ */
+U_BOOT_PART_TYPE(a_efi) = {
+	.name		= "EFI",
+	.part_type	= PART_TYPE_EFI,
+	.get_info	= part_get_info_ptr(part_get_info_efi),
+	.print		= part_print_ptr(part_print_efi),
+	.test		= part_test_efi,
+};
 #endif
diff --git a/disk/part_iso.c b/disk/part_iso.c
index 5f4bb18..b83983b 100644
--- a/disk/part_iso.c
+++ b/disk/part_iso.c
@@ -46,7 +46,8 @@
 
 
 /* only boot records will be listed as valid partitions */
-int get_partition_info_iso_verb(block_dev_desc_t * dev_desc, int part_num, disk_partition_t * info, int verb)
+int part_get_info_iso_verb(struct blk_desc *dev_desc, int part_num,
+			   disk_partition_t *info, int verb)
 {
 	int i,offset,entry_num;
 	unsigned short *chksumbuf;
@@ -62,18 +63,18 @@
 
 	/* the first sector (sector 0x10) must be a primary volume desc */
 	blkaddr=PVD_OFFSET;
-	if (dev_desc->block_read(dev_desc, PVD_OFFSET, 1, (ulong *)tmpbuf) != 1)
+	if (blk_dread(dev_desc, PVD_OFFSET, 1, (ulong *)tmpbuf) != 1)
 		return -1;
 	if(ppr->desctype!=0x01) {
 		if(verb)
 			printf ("** First descriptor is NOT a primary desc on %d:%d **\n",
-				dev_desc->dev, part_num);
+				dev_desc->devnum, part_num);
 		return (-1);
 	}
 	if(strncmp((char *)ppr->stand_ident,"CD001",5)!=0) {
 		if(verb)
 			printf ("** Wrong ISO Ident: %s on %d:%d **\n",
-				ppr->stand_ident,dev_desc->dev, part_num);
+				ppr->stand_ident, dev_desc->devnum, part_num);
 		return (-1);
 	}
 	lastsect= ((ppr->firstsek_LEpathtab1_LE & 0x000000ff)<<24) +
@@ -84,14 +85,14 @@
 	PRINTF(" Lastsect:%08lx\n",lastsect);
 	for(i=blkaddr;i<lastsect;i++) {
 		PRINTF("Reading block %d\n", i);
-		if (dev_desc->block_read(dev_desc, i, 1, (ulong *)tmpbuf) != 1)
+		if (blk_dread(dev_desc, i, 1, (ulong *)tmpbuf) != 1)
 			return -1;
 		if(ppr->desctype==0x00)
 			break; /* boot entry found */
 		if(ppr->desctype==0xff) {
 			if(verb)
 				printf ("** No valid boot catalog found on %d:%d **\n",
-					dev_desc->dev, part_num);
+					dev_desc->devnum, part_num);
 			return (-1);
 		}
 	}
@@ -99,15 +100,15 @@
 	if(strncmp(pbr->ident_str,"EL TORITO SPECIFICATION",23)!=0) {
 		if(verb)
 			printf ("** Wrong El Torito ident: %s on %d:%d **\n",
-				pbr->ident_str,dev_desc->dev, part_num);
+				pbr->ident_str, dev_desc->devnum, part_num);
 		return (-1);
 	}
 	bootaddr=le32_to_int(pbr->pointer);
 	PRINTF(" Boot Entry at: %08lX\n",bootaddr);
-	if (dev_desc->block_read(dev_desc, bootaddr, 1, (ulong *)tmpbuf) != 1) {
+	if (blk_dread(dev_desc, bootaddr, 1, (ulong *)tmpbuf) != 1) {
 		if(verb)
 			printf ("** Can't read Boot Entry at %lX on %d:%d **\n",
-				bootaddr,dev_desc->dev, part_num);
+				bootaddr, dev_desc->devnum, part_num);
 		return (-1);
 	}
 	chksum=0;
@@ -116,21 +117,21 @@
 		chksum+=((chksumbuf[i] &0xff)<<8)+((chksumbuf[i] &0xff00)>>8);
 	if(chksum!=0) {
 		if(verb)
-			printf ("** Checksum Error in booting catalog validation entry on %d:%d **\n",
-				dev_desc->dev, part_num);
+			printf("** Checksum Error in booting catalog validation entry on %d:%d **\n",
+			       dev_desc->devnum, part_num);
 		return (-1);
 	}
 	if((pve->key[0]!=0x55)||(pve->key[1]!=0xAA)) {
 		if(verb)
 			printf ("** Key 0x55 0xAA error on %d:%d **\n",
-				dev_desc->dev, part_num);
+				dev_desc->devnum, part_num);
 		return(-1);
 	}
 #ifdef CHECK_FOR_POWERPC_PLATTFORM
 	if(pve->platform!=0x01) {
 		if(verb)
 			printf ("** No PowerPC platform CD on %d:%d **\n",
-				dev_desc->dev, part_num);
+				dev_desc->devnum, part_num);
 		return(-1);
 	}
 #endif
@@ -143,23 +144,23 @@
 		case IF_TYPE_SATA:
 		case IF_TYPE_ATAPI:
 			sprintf ((char *)info->name, "hd%c%d",
-				'a' + dev_desc->dev, part_num);
+				'a' + dev_desc->devnum, part_num);
 			break;
 		case IF_TYPE_SCSI:
 			sprintf ((char *)info->name, "sd%c%d",
-				'a' + dev_desc->dev, part_num);
+				'a' + dev_desc->devnum, part_num);
 			break;
 		case IF_TYPE_USB:
 			sprintf ((char *)info->name, "usbd%c%d",
-				'a' + dev_desc->dev, part_num);
+				'a' + dev_desc->devnum, part_num);
 			break;
 		case IF_TYPE_DOC:
 			sprintf ((char *)info->name, "docd%c%d",
-				'a' + dev_desc->dev, part_num);
+				'a' + dev_desc->devnum, part_num);
 			break;
 		default:
 			sprintf ((char *)info->name, "xx%c%d",
-				'a' + dev_desc->dev, part_num);
+				'a' + dev_desc->devnum, part_num);
 			break;
 	}
 	/* the bootcatalog (including validation Entry) is limited to 2048Bytes
@@ -183,7 +184,7 @@
 		else {
 			if(verb)
 				printf ("** Partition %d not found on device %d **\n",
-					part_num,dev_desc->dev);
+					part_num, dev_desc->devnum);
 			return(-1);
 		}
 	}
@@ -191,13 +192,13 @@
 	 * searched w/o succsess */
 	if(verb)
 		printf ("** Partition %d not found on device %d **\n",
-			part_num,dev_desc->dev);
+			part_num, dev_desc->devnum);
 	return(-1);
 found:
 	if(pide->boot_ind!=0x88) {
 		if(verb)
-			printf ("** Partition %d is not bootable on device %d **\n",
-				part_num,dev_desc->dev);
+			printf("** Partition %d is not bootable on device %d **\n",
+			       part_num, dev_desc->devnum);
 		return (-1);
 	}
 	switch(pide->boot_media) {
@@ -216,18 +217,20 @@
 	return 0;
 }
 
-int get_partition_info_iso(block_dev_desc_t * dev_desc, int part_num, disk_partition_t * info)
+static int part_get_info_iso(struct blk_desc *dev_desc, int part_num,
+				  disk_partition_t *info)
 {
-	return(get_partition_info_iso_verb(dev_desc, part_num, info, 1));
+	return part_get_info_iso_verb(dev_desc, part_num, info, 1);
 }
 
-
-void print_part_iso(block_dev_desc_t * dev_desc)
+static void part_print_iso(struct blk_desc *dev_desc)
 {
 	disk_partition_t info;
 	int i;
-	if(get_partition_info_iso_verb(dev_desc,0,&info,0)==-1) {
-		printf("** No boot partition found on device %d **\n",dev_desc->dev);
+
+	if (part_get_info_iso_verb(dev_desc, 0, &info, 0) == -1) {
+		printf("** No boot partition found on device %d **\n",
+		       dev_desc->devnum);
 		return;
 	}
 	printf("Part   Start     Sect x Size Type\n");
@@ -236,14 +239,21 @@
 		printf(" %2d " LBAFU " " LBAFU " %6ld %.32s\n",
 		       i, info.start, info.size, info.blksz, info.type);
 		i++;
-	} while (get_partition_info_iso_verb(dev_desc,i,&info,0)!=-1);
+	} while (part_get_info_iso_verb(dev_desc, i, &info, 0) != -1);
 }
 
-int test_part_iso (block_dev_desc_t *dev_desc)
+static int part_test_iso(struct blk_desc *dev_desc)
 {
 	disk_partition_t info;
 
-	return(get_partition_info_iso_verb(dev_desc,0,&info,0));
+	return part_get_info_iso_verb(dev_desc, 0, &info, 0);
 }
 
+U_BOOT_PART_TYPE(iso) = {
+	.name		= "ISO",
+	.part_type	= PART_TYPE_ISO,
+	.get_info	= part_get_info_iso,
+	.print		= part_print_iso,
+	.test		= part_test_iso,
+};
 #endif
diff --git a/disk/part_mac.c b/disk/part_mac.c
index f3bc8dd..3952b8d 100644
--- a/disk/part_mac.c
+++ b/disk/part_mac.c
@@ -32,13 +32,15 @@
 #endif
 
 
-static int part_mac_read_ddb (block_dev_desc_t *dev_desc, mac_driver_desc_t *ddb_p);
-static int part_mac_read_pdb (block_dev_desc_t *dev_desc, int part, mac_partition_t *pdb_p);
+static int part_mac_read_ddb(struct blk_desc *dev_desc,
+			     mac_driver_desc_t *ddb_p);
+static int part_mac_read_pdb(struct blk_desc *dev_desc, int part,
+			     mac_partition_t *pdb_p);
 
 /*
  * Test for a valid MAC partition
  */
-int test_part_mac (block_dev_desc_t *dev_desc)
+static int part_test_mac(struct blk_desc *dev_desc)
 {
 	ALLOC_CACHE_ALIGN_BUFFER(mac_driver_desc_t, ddesc, 1);
 	ALLOC_CACHE_ALIGN_BUFFER(mac_partition_t, mpart, 1);
@@ -51,8 +53,7 @@
 
 	n = 1;	/* assuming at least one partition */
 	for (i=1; i<=n; ++i) {
-		if ((dev_desc->block_read(dev_desc, i, 1,
-					  (ulong *)mpart) != 1) ||
+		if ((blk_dread(dev_desc, i, 1, (ulong *)mpart) != 1) ||
 		    (mpart->signature != MAC_PARTITION_MAGIC) ) {
 			return (-1);
 		}
@@ -62,8 +63,7 @@
 	return (0);
 }
 
-
-void print_part_mac (block_dev_desc_t *dev_desc)
+static void part_print_mac(struct blk_desc *dev_desc)
 {
 	ulong i, n;
 	ALLOC_CACHE_ALIGN_BUFFER(mac_driver_desc_t, ddesc, 1);
@@ -105,16 +105,16 @@
 		char c;
 
 		printf ("%4ld: ", i);
-		if (dev_desc->block_read(dev_desc, i, 1, (ulong *)mpart) != 1) {
+		if (blk_dread(dev_desc, i, 1, (ulong *)mpart) != 1) {
 			printf ("** Can't read Partition Map on %d:%ld **\n",
-				dev_desc->dev, i);
+				dev_desc->devnum, i);
 			return;
 		}
 
 		if (mpart->signature != MAC_PARTITION_MAGIC) {
-			printf ("** Bad Signature on %d:%ld - "
-				"expected 0x%04x, got 0x%04x\n",
-				dev_desc->dev, i, MAC_PARTITION_MAGIC, mpart->signature);
+			printf("** Bad Signature on %d:%ld - expected 0x%04x, got 0x%04x\n",
+			       dev_desc->devnum, i, MAC_PARTITION_MAGIC,
+			       mpart->signature);
 			return;
 		}
 
@@ -149,9 +149,10 @@
 /*
  * Read Device Descriptor Block
  */
-static int part_mac_read_ddb (block_dev_desc_t *dev_desc, mac_driver_desc_t *ddb_p)
+static int part_mac_read_ddb(struct blk_desc *dev_desc,
+			     mac_driver_desc_t *ddb_p)
 {
-	if (dev_desc->block_read(dev_desc, 0, 1, (ulong *)ddb_p) != 1) {
+	if (blk_dread(dev_desc, 0, 1, (ulong *)ddb_p) != 1) {
 		printf ("** Can't read Driver Desriptor Block **\n");
 		return (-1);
 	}
@@ -169,7 +170,8 @@
 /*
  * Read Partition Descriptor Block
  */
-static int part_mac_read_pdb (block_dev_desc_t *dev_desc, int part, mac_partition_t *pdb_p)
+static int part_mac_read_pdb(struct blk_desc *dev_desc, int part,
+			     mac_partition_t *pdb_p)
 {
 	int n = 1;
 
@@ -179,16 +181,16 @@
 		 * partition 1 first since this is the only way to
 		 * know how many partitions we have.
 		 */
-		if (dev_desc->block_read(dev_desc, n, 1, (ulong *)pdb_p) != 1) {
+		if (blk_dread(dev_desc, n, 1, (ulong *)pdb_p) != 1) {
 			printf ("** Can't read Partition Map on %d:%d **\n",
-				dev_desc->dev, n);
+				dev_desc->devnum, n);
 			return (-1);
 		}
 
 		if (pdb_p->signature != MAC_PARTITION_MAGIC) {
-			printf ("** Bad Signature on %d:%d: "
-				"expected 0x%04x, got 0x%04x\n",
-				dev_desc->dev, n, MAC_PARTITION_MAGIC, pdb_p->signature);
+			printf("** Bad Signature on %d:%d: expected 0x%04x, got 0x%04x\n",
+			       dev_desc->devnum, n, MAC_PARTITION_MAGIC,
+			       pdb_p->signature);
 			return (-1);
 		}
 
@@ -197,9 +199,9 @@
 
 		if ((part < 1) || (part > pdb_p->map_count)) {
 			printf ("** Invalid partition %d:%d [%d:1...%d:%d only]\n",
-				dev_desc->dev, part,
-				dev_desc->dev,
-				dev_desc->dev, pdb_p->map_count);
+				dev_desc->devnum, part,
+				dev_desc->devnum,
+				dev_desc->devnum, pdb_p->map_count);
 			return (-1);
 		}
 
@@ -210,7 +212,8 @@
 	/* NOTREACHED */
 }
 
-int get_partition_info_mac (block_dev_desc_t *dev_desc, int part, disk_partition_t *info)
+static int part_get_info_mac(struct blk_desc *dev_desc, int part,
+				  disk_partition_t *info)
 {
 	ALLOC_CACHE_ALIGN_BUFFER(mac_driver_desc_t, ddesc, 1);
 	ALLOC_CACHE_ALIGN_BUFFER(mac_partition_t, mpart, 1);
@@ -233,4 +236,11 @@
 	return (0);
 }
 
+U_BOOT_PART_TYPE(mac) = {
+	.name		= "MAC",
+	.part_type	= PART_TYPE_MAC,
+	.get_info	= part_get_info_mac,
+	.print		= part_print_mac,
+	.test		= part_test_mac,
+};
 #endif
diff --git a/doc/README.arm64 b/doc/README.arm64
index de669cb..f658fa2 100644
--- a/doc/README.arm64
+++ b/doc/README.arm64
@@ -36,26 +36,6 @@
 6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and
    aarch32 specific codes.
 
-7. CONFIG_SYS_FULL_VA is used to enable 2-level page tables. For cores
-   supporting 64k pages it allows usage of full 48+ virtual/physical addresses
-
-   Enabling this option requires the following ones to be defined:
-       - CONFIG_SYS_MEM_MAP - an array of 'struct mm_region' describing the
-         system memory map (start, length, attributes)
-       - CONFIG_SYS_MEM_MAP_SIZE - number of entries in CONFIG_SYS_MEM_MAP
-       - CONFIG_SYS_PTL1_ENTRIES - number of 1st level page table entries
-       - CONFIG_SYS_PTL2_ENTRIES - number of 1nd level page table entries
-         for the largest CONFIG_SYS_MEM_MAP entry
-       - CONFIG_COREID_MASK - the mask value used to get the core from the
-         MPIDR_EL1 register
-       - CONFIG_SYS_PTL2_BITS - number of bits addressed by the 2nd level
-         page tables
-       - CONFIG_SYS_BLOCK_SHIFT - number of bits addressed by a single block
-         entry from L2 page tables
-       - CONFIG_SYS_PGTABLE_SIZE - total size of the page table
-       - CONFIG_SYS_TCR_EL{1,2,3}_IPS_BITS - the IPS field of the TCR_EL{1,2,3}
-
-
 
 
 Contributor
diff --git a/doc/README.efi b/doc/README.efi
index 23a3cdd..1fd3f00 100644
--- a/doc/README.efi
+++ b/doc/README.efi
@@ -4,6 +4,28 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+=========== Table of Contents ===========
+
+  1  U-Boot on EFI
+  1.1  In God's Name, Why?
+  1.2  Status
+  1.3  Build Instructions
+  1.4  Trying it out
+  1.5  Inner workings
+  1.6  EFI Application
+  1.7  EFI Payload
+  1.8  Tables
+  1.9  Interrupts
+  1.10 32/64-bit
+  1.11 Future work
+  1.12 Where is the code?
+
+  2  EFI on U-Boot
+  2.1  In God's Name, Why?
+  2.2  How do I get it?
+  2.3  Status
+  2.4  Future work
+
 U-Boot on EFI
 =============
 This document provides information about U-Boot running on top of EFI, either
@@ -234,7 +256,6 @@
 common/cmd_efi.c
 	the 'efi' command
 
-
 --
 Ben Stoltz, Simon Glass
 Google, Inc
@@ -242,3 +263,63 @@
 
 [1] http://www.qemu.org
 [2] http://www.tianocore.org/ovmf/
+
+-------------------------------------------------------------------------------
+
+EFI on U-Boot
+=============
+
+In addition to support for running U-Boot as a UEFI application, U-Boot itself
+can also expose the UEFI interfaces and thus allow UEFI payloads to run under
+it.
+
+In God's Name, Why?
+-------------------
+
+With this support in place, you can run any UEFI payload (such as the Linux
+kernel, grub2 or gummiboot) on U-Boot. This dramatically simplifies boot loader
+configuration, as U-Boot based systems now look and feel (almost) the same way
+as TianoCore based systems.
+
+How do I get it?
+----------------
+
+EFI support for 32bit ARM and AArch64 is already included in U-Boot. All you
+need to do is enable
+
+  CONFIG_CMD_BOOTEFI=y
+  CONFIG_EFI_LOADER=y
+
+in your .config file and you will automatically get a bootefi command to run
+an efi application as well as snippet in the default distro boot script that
+scans for removable media efi binaries as fallback.
+
+Status
+------
+
+I am successfully able to run grub2 and Linux EFI binaries with this code on
+ARMv7 as well as AArch64 systems.
+
+When enabled, the resulting U-Boot binary only grows by ~10KB, so it's very
+light weight.
+
+All storage devices are directly accessible from the uEFI payload
+
+Removable media booting (search for /efi/boot/boota{a64,arm}.efi) is supported.
+
+Simple use cases like "Plug this SD card into my ARM device and it just
+boots into grub which boots into Linux", work very well.
+
+Future work
+-----------
+
+Of course, there are still a few things one could do on top:
+
+   - Improve disk media detection (don't scan, use what information we
+have)
+   - Add EFI variable support using NVRAM
+   - Add GFX support
+   - Make EFI Shell work
+   - Network device support
+   - Support for payload exit
+   - Payload Watchdog support
diff --git a/doc/README.x86 b/doc/README.x86
index d3fea5d..c5c3010 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -20,8 +20,17 @@
 
 U-Boot also supports booting directly from x86 reset vector, without coreboot.
 In this case, known as bare mode, from the fact that it runs on the
-'bare metal', U-Boot acts like a BIOS replacement. Currently Link, QEMU x86
-targets and all Intel boards support running U-Boot 'bare metal'.
+'bare metal', U-Boot acts like a BIOS replacement. The following platforms
+are supported:
+
+   - Bayley Bay
+   - Cougar Canyon 2 CRB
+   - Crown Bay CRB
+   - Galileo
+   - Link (Chromebook Pixel)
+   - Minnowboard MAX
+   - Samus (Chromebook Pixel 2015)
+   - QEMU x86
 
 As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
 Linux kernel as part of a FIT image. It also supports a compressed zImage.
@@ -94,6 +103,87 @@
 $ make chromebook_link_defconfig
 $ make all
 
+---
+
+Chromebook Samus (2015 Pixel) instructions for bare mode:
+
+First, you need the following binary blobs:
+
+* descriptor.bin - Intel flash descriptor
+* me.bin - Intel Management Engine
+* mrc.bin - Memory Reference Code, which sets up SDRAM
+* refcode.elf - Additional Reference code
+* vga.bin - video ROM, which sets up the display
+
+If you have a samus you can obtain them from your flash, for example, in
+developer mode on the Chromebook (use Ctrl-Alt-F2 to obtain a terminal and
+log in as 'root'):
+
+   cd /tmp
+   flashrom -w samus.bin
+   scp samus.bin username@ip_address:/path/to/somewhere
+
+If not see the coreboot tree [4] where you can use:
+
+   bash crosfirmware.sh samus
+
+to get the image. There is also an 'extract_blobs.sh' scripts that you can use
+on the 'coreboot-Google_Samus.*' file to short-circuit some of the below.
+
+Then 'ifdtool -x samus.bin' on your development machine will produce:
+
+   flashregion_0_flashdescriptor.bin
+   flashregion_1_bios.bin
+   flashregion_2_intel_me.bin
+
+Rename flashregion_0_flashdescriptor.bin to descriptor.bin
+Rename flashregion_2_intel_me.bin to me.bin
+You can ignore flashregion_1_bios.bin - it is not used.
+
+To get the rest, use 'cbfstool samus.bin print':
+
+samus.bin: 8192 kB, bootblocksize 2864, romsize 8388608, offset 0x700000
+alignment: 64 bytes, architecture: x86
+
+Name                           Offset     Type         Size
+cmos_layout.bin                0x700000   cmos_layout  1164
+pci8086,0406.rom               0x7004c0   optionrom    65536
+spd.bin                        0x710500   (unknown)    4096
+cpu_microcode_blob.bin         0x711540   microcode    70720
+fallback/romstage              0x722a00   stage        54210
+fallback/ramstage              0x72fe00   stage        96382
+config                         0x7476c0   raw          6075
+fallback/vboot                 0x748ec0   stage        15980
+fallback/refcode               0x74cd80   stage        75578
+fallback/payload               0x75f500   payload      62878
+u-boot.dtb                     0x76eb00   (unknown)    5318
+(empty)                        0x770000   null         196504
+mrc.bin                        0x79ffc0   (unknown)    222876
+(empty)                        0x7d66c0   null         167320
+
+You can extract what you need:
+
+   cbfstool samus.bin extract -n pci8086,0406.rom -f vga.bin
+   cbfstool samus.bin extract -n fallback/refcode -f refcode.rmod
+   cbfstool samus.bin extract -n mrc.bin -f mrc.bin
+   cbfstool samus.bin extract -n fallback/refcode -f refcode.bin -U
+
+Note that the -U flag is only supported by the latest cbfstool. It unpacks
+and decompresses the stage to produce a coreboot rmodule. This is a simple
+representation of an ELF file. You need the patch "Support decoding a stage
+with compression".
+
+Put all 5 files into board/google/chromebook_samus.
+
+Now you can build U-Boot and obtain u-boot.rom:
+
+$ make chromebook_link_defconfig
+$ make all
+
+If you are using em100, then this command will flash write -Boot:
+
+   em100 -s -d filename.rom -c W25Q64CV -r
+
 ---
 
 Intel Crown Bay specific instructions for bare mode:
@@ -371,7 +461,8 @@
 
 Driver Model
 ------------
-x86 has been converted to use driver model for serial and GPIO.
+x86 has been converted to use driver model for serial, GPIO, SPI, SPI flash,
+keyboard, real-time clock, USB. Video is in progress.
 
 Device Tree
 -----------
@@ -669,6 +760,58 @@
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS "boot=zboot 03000000 0 04000000 ${filesize}"
 
+Test with SeaBIOS
+-----------------
+SeaBIOS [14] is an open source implementation of a 16-bit x86 BIOS. It can run
+in an emulator or natively on x86 hardware with the use of U-Boot. With its
+help, we can boot some OSes that require 16-bit BIOS services like Windows/DOS.
+
+As U-Boot, we have to manually create a table where SeaBIOS gets various system
+information (eg: E820) from. The table unfortunately has to follow the coreboot
+table format as SeaBIOS currently supports booting as a coreboot payload.
+
+To support loading SeaBIOS, U-Boot should be built with CONFIG_SEABIOS on.
+Booting SeaBIOS is done via U-Boot's bootelf command, like below:
+
+   => tftp bios.bin.elf;bootelf
+   Using e1000#0 device
+   TFTP from server 10.10.0.100; our IP address is 10.10.0.108
+   ...
+   Bytes transferred = 122124 (1dd0c hex)
+   ## Starting application at 0x000ff06e ...
+   SeaBIOS (version rel-1.9.0)
+   ...
+
+bios.bin.elf is the SeaBIOS image built from SeaBIOS source tree.
+Make sure it is built as follows:
+
+   $ make menuconfig
+
+Inside the "General Features" menu, select "Build for coreboot" as the
+"Build Target". Inside the "Debugging" menu, turn on "Serial port debugging"
+so that we can see something as soon as SeaBIOS boots. Leave other options
+as in their default state. Then,
+
+   $ make
+   ...
+   Total size: 121888  Fixed: 66496  Free: 9184 (used 93.0% of 128KiB rom)
+   Creating out/bios.bin.elf
+
+Currently this is tested on QEMU x86 target with U-Boot chain-loading SeaBIOS
+to install/boot a Windows XP OS (below for example command to install Windows).
+
+   # Create a 10G disk.img as the virtual hard disk
+   $ qemu-img create -f qcow2 disk.img 10G
+
+   # Install a Windows XP OS from an ISO image 'winxp.iso'
+   $ qemu-system-i386 -serial stdio -bios u-boot.rom -hda disk.img -cdrom winxp.iso -smp 2 -m 512
+
+   # Boot a Windows XP OS installed on the virutal hard disk
+   $ qemu-system-i386 -serial stdio -bios u-boot.rom -hda disk.img -smp 2 -m 512
+
+This is also tested on Intel Crown Bay board with a PCIe graphics card, booting
+SeaBIOS then chain-loading a GRUB on a USB drive, then Linux kernel finally.
+
 
 Development Flow
 ----------------
@@ -736,7 +879,7 @@
 During the U-Boot porting, one of the important steps is to write correct PIRQ
 routing information in the board device tree. Without it, device drivers in the
 Linux kernel won't function correctly due to interrupt is not working. Please
-refer to U-Boot doc [14] for the device tree bindings of Intel interrupt router.
+refer to U-Boot doc [15] for the device tree bindings of Intel interrupt router.
 Here we have more details on the intel,pirq-routing property below.
 
 	intel,pirq-routing = <
@@ -812,6 +955,15 @@
 held in reset. For more details, check how they are implemented by the Intel
 Galileo board support codes in board/intel/galileo/galileo.c.
 
+coreboot:
+
+See scripts/coreboot.sed which can assist with porting coreboot code into
+U-Boot drivers. It will not resolve all build errors, but will perform common
+transformations. Remember to add attribution to coreboot for new files added
+to U-Boot. This should go at the top of each file and list the coreboot
+filename where the code originated.
+
+
 TODO List
 ---------
 - Audio
@@ -833,4 +985,5 @@
 [11] https://en.wikipedia.org/wiki/GUID_Partition_Table
 [12] http://events.linuxfoundation.org/sites/events/files/slides/chromeos_and_diy_vboot_0.pdf
 [13] http://events.linuxfoundation.org/sites/events/files/slides/elce-2014.pdf
-[14] doc/device-tree-bindings/misc/intel,irq-router.txt
+[14] http://www.seabios.org/SeaBIOS
+[15] doc/device-tree-bindings/misc/intel,irq-router.txt
diff --git a/doc/device-tree-bindings/gpio/intel,x86-broadwell-pinctrl.txt b/doc/device-tree-bindings/gpio/intel,x86-broadwell-pinctrl.txt
new file mode 100644
index 0000000..a644381
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/intel,x86-broadwell-pinctrl.txt
@@ -0,0 +1,208 @@
+Intel x86 PINCTRL/GPIO controller
+
+Pin-muxing on broadwell devices can be described with a node for the PINCTRL
+master node and a set of child nodes for each required pin state on the SoC.
+These pin states use phandles and are referred to but a configuration section
+which lists all pins in the device.
+
+The PINCTRL master node requires the following properties:
+- compatible : "intel,x86-broadwell-pinctrl"
+
+Pin state nodes must be sub-nodes of the pinctrl master node. The must have
+a phandle. They can contain the following optional properties:
+- mode-gpio	- forces the pin into GPIO mode
+- output-value	- sets the default output value of the GPIO, 0 (low, default)
+			or 1 (high)
+- direction	- sets the direction of the gpio, either PIN_INPUT (default)
+			or PIN_OUTPUT
+- invert	- the input pin is inverted
+- trigger	- sets the trigger type, either TRIGGER_EDGE (default) or
+			TRIGGER_LEVEL
+- sense-disable - the input state sense is disabled
+- owner		0 sets the owner of the pin, either OWNER_ACPI (default) or
+			ONWER_GPIO
+- route		- sets whether the pin is routed, either PIRQ_APIC_MASK or
+			PIRQ_APIC_ROUTE
+- irq-enable	- the interrupt is enabled
+- reset-rsmrst	- the pin will only be reset by RSMRST
+- pirq-apic	- the pin will be routed to the IOxAPIC
+
+The first pin state will be the default, so pins without a configuration will
+use that.
+
+The pin configuration node is also a sub-node of the pinctrl master node, but
+does not have a phandle. It has a single property:
+
+- config	- configuration to use for each pin. Each entry has of 3 cells:
+			- GPIO number (0..94)
+			- phandle of configuration (above)
+			- interrupt number (0..15)
+
+		  There should be one entry for each pin (i.e. 95 entries).
+		  But missing pins will receive the default configuration.
+
+Example:
+
+pch_pinctrl {
+	compatible = "intel,x86-broadwell-pinctrl";
+
+	/* Put this first: it is the default */
+	gpio_unused: gpio-unused {
+		mode-gpio;
+		direction = <PIN_INPUT>;
+		owner = <OWNER_GPIO>;
+		sense-disable;
+	};
+
+	gpio_acpi_sci: acpi-sci {
+		mode-gpio;
+		direction = <PIN_INPUT>;
+		invert;
+		route = <ROUTE_SCI>;
+	};
+
+	gpio_acpi_smi: acpi-smi {
+		mode-gpio;
+		direction = <PIN_INPUT>;
+		invert;
+		route = <ROUTE_SMI>;
+	};
+
+	gpio_input: gpio-input {
+		mode-gpio;
+		direction = <PIN_INPUT>;
+		owner = <OWNER_GPIO>;
+	};
+
+	gpio_input_invert: gpio-input-invert {
+		mode-gpio;
+		direction = <PIN_INPUT>;
+		owner = <OWNER_GPIO>;
+		invert;
+	};
+
+	gpio_native: gpio-native {
+	};
+
+	gpio_out_high: gpio-out-high {
+		mode-gpio;
+		direction = <PIN_OUTPUT>;
+		output-value = <1>;
+		owner = <OWNER_GPIO>;
+		sense-disable;
+	};
+
+	gpio_out_low: gpio-out-low {
+		mode-gpio;
+		direction = <PIN_OUTPUT>;
+		output-value = <0>;
+		owner = <OWNER_GPIO>;
+		sense-disable;
+	};
+
+	gpio_pirq: gpio-pirq {
+		mode-gpio;
+		direction = <PIN_INPUT>;
+		owner = <OWNER_GPIO>;
+		pirq-apic = <PIRQ_APIC_ROUTE>;
+	};
+
+	soc_gpio@0 {
+		config =
+			<0 &gpio_unused 0>,	/* unused */
+			<1 &gpio_unused 0>,	/* unused */
+			<2 &gpio_unused 0>,	/* unused */
+			<3 &gpio_unused 0>,	/* unused */
+			<4 &gpio_native 0>,	/* native: i2c0_sda_gpio4 */
+			<5 &gpio_native 0>,	/* native: i2c0_scl_gpio5 */
+			<6 &gpio_native 0>,	/* native: i2c1_sda_gpio6 */
+			<7 &gpio_native 0>,	/* native: i2c1_scl_gpio7 */
+			<8 &gpio_acpi_sci 0>,	/* pch_lte_wake_l */
+			<9 &gpio_input_invert 0>,/* trackpad_int_l (wake) */
+			<10 &gpio_acpi_sci 0>,	/* pch_wlan_wake_l */
+			<11 &gpio_unused 0>,	/* unused */
+			<12 &gpio_unused 0>,	/* unused */
+			<13 &gpio_pirq 3>,	/* trackpad_int_l (pirql) */
+			<14 &gpio_pirq 4>,	/* touch_int_l (pirqm) */
+			<15 &gpio_unused 0>,	/* unused (strap) */
+			<16 &gpio_input 0>,	/* pch_wp */
+			<17 &gpio_unused 0>,	/* unused */
+			<18 &gpio_unused 0>,	/* unused */
+			<19 &gpio_unused 0>,	/* unused */
+			<20 &gpio_native 0>,	/* pcie_wlan_clkreq_l */
+			<21 &gpio_out_high 0>,	/* pp3300_ssd_en */
+			<22 &gpio_unused 0>,	/* unused */
+			<23 &gpio_out_low 0>,	/* pp3300_autobahn_en */
+			<24 &gpio_unused 0>,	/* unused */
+			<25 &gpio_input 0>,	/* ec_in_rw */
+			<26 &gpio_unused 0>,	/* unused */
+			<27 &gpio_acpi_sci 0>,	/* pch_wake_l */
+			<28 &gpio_unused 0>,	/* unused */
+			<29 &gpio_unused 0>,	/* unused */
+			<30 &gpio_native 0>,	/* native: pch_suswarn_l */
+			<31 &gpio_native 0>,	/* native: acok_buf */
+			<32 &gpio_native 0>,	/* native: lpc_clkrun_l */
+			<33 &gpio_native 0>,	/* native: ssd_devslp */
+			<34 &gpio_acpi_smi 0>,	/* ec_smi_l */
+			<35 &gpio_acpi_smi 0>,	/* pch_nmi_dbg_l (route in nmi_en) */
+			<36 &gpio_acpi_sci 0>,	/* ec_sci_l */
+			<37 &gpio_unused 0>,	/* unused */
+			<38 &gpio_unused 0>,	/* unused */
+			<39 &gpio_unused 0>,	/* unused */
+			<40 &gpio_native 0>,	/* native: pch_usb1_oc_l */
+			<41 &gpio_native 0>,	/* native: pch_usb2_oc_l */
+			<42 &gpio_unused 0>,	/* wlan_disable_l */
+			<43 &gpio_out_high 0>,	/* pp1800_codec_en */
+			<44 &gpio_unused 0>,	/* unused */
+			<45 &gpio_acpi_sci 0>,	/* dsp_int - codec wake */
+			<46 &gpio_pirq 6>,	/* hotword_det_l_3v3 (pirqo) - codec irq */
+			<47 &gpio_out_low 0>,	/* ssd_reset_l */
+			<48 &gpio_unused 0>,	/* unused */
+			<49 &gpio_unused 0>,	/* unused */
+			<50 &gpio_unused 0>,	/* unused */
+			<51 &gpio_unused 0>,	/* unused */
+			<52 &gpio_input 0>,	/* sim_det */
+			<53 &gpio_unused 0>,	/* unused */
+			<54 &gpio_unused 0>,	/* unused */
+			<55 &gpio_unused 0>,	/* unused */
+			<56 &gpio_unused 0>,	/* unused */
+			<57 &gpio_out_high 0>,	/* codec_reset_l */
+			<58 &gpio_unused 0>,	/* unused */
+			<59 &gpio_out_high 0>,	/* lte_disable_l */
+			<60 &gpio_unused 0>,	/* unused */
+			<61 &gpio_native 0>,	/* native: pch_sus_stat */
+			<62 &gpio_native 0>,	/* native: pch_susclk */
+			<63 &gpio_native 0>,	/* native: pch_slp_s5_l */
+			<64 &gpio_unused 0>,	/* unused */
+			<65 &gpio_input 0>,	/* ram_id3 */
+			<66 &gpio_input 0>,	/* ram_id3_old (strap) */
+			<67 &gpio_input 0>,	/* ram_id0 */
+			<68 &gpio_input 0>,	/* ram_id1 */
+			<69 &gpio_input 0>,	/* ram_id2 */
+			<70 &gpio_unused 0>,	/* unused */
+			<71 &gpio_native 0>,	/* native: modphy_en */
+			<72 &gpio_unused 0>,	/* unused */
+			<73 &gpio_unused 0>,	/* unused */
+			<74 &gpio_unused 0>,	/* unused */
+			<75 &gpio_unused 0>,	/* unused */
+			<76 &gpio_unused 0>,	/* unused */
+			<77 &gpio_unused 0>,	/* unused */
+			<78 &gpio_unused 0>,	/* unused */
+			<79 &gpio_unused 0>,	/* unused */
+			<80 &gpio_unused 0>,	/* unused */
+			<81 &gpio_unused 0>,	/* unused */
+			<82 &gpio_native 0>,	/* native: ec_rcin_l */
+			<83 &gpio_native 0>,	/* gspi0_cs */
+			<84 &gpio_native 0>,	/* gspi0_clk */
+			<85 &gpio_native 0>,	/* gspi0_miso */
+			<86 &gpio_native 0>,	/* gspi0_mosi (strap) */
+			<87 &gpio_unused 0>,	/* unused */
+			<88 &gpio_unused 0>,	/* unused */
+			<89 &gpio_out_high 0>,	/* pp3300_sd_en */
+			<90 &gpio_unused 0>,	/* unused */
+			<91 &gpio_unused 0>,	/* unused */
+			<92 &gpio_unused 0>,	/* unused */
+			<93 &gpio_unused 0>,	/* unused */
+			<94 &gpio_unused 0 >;	/* unused */
+	};
+};
diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
index 45ab1af..22d3bec 100644
--- a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
+++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
@@ -8,17 +8,19 @@
 
 Pin nodes must be children of the pinctrl master node and can
 contain the following properties:
-- pad-offset        - (required) offset in the IOBASE for the pin to configured.
-- gpio-offset       - (required) offset in the GPIOBASE for the pin to configured and
-					also the bit shift in this register.
-- mode-gpio			- (optional) standalone property to force the pin into GPIO mode.
-- mode-func			- (optional) function number to assign to the pin. if 'mode-gpio'
-					is set, this property will be ignored.
+- pad-offset	- (required) offset in the IOBASE for the pin to configure
+- gpio-offset	- (required) 2 cells
+			- offset in the GPIOBASE for the pin to configure
+			- the bit shift in this register (4 = bit 4)
+- mode-gpio	- (optional) standalone property to force the pin into GPIO mode
+- mode-func	- (optional) function number to assign to the pin. If
+			'mode-gpio' is set, this property will be ignored.
 in case of 'mode-gpio' property set:
-- output-value		- (optional) this set the default output value of the GPIO.
-- direction         - (optional) this set the direction of the gpio.
-- pull-str          - (optional) this set the pull strength of the pin.
-- pull-assign       - (optional) this set the pull assignement (up/down) of the pin.
+- output-value	- (optional) this set the default output value of the GPIO
+- direction	- (optional) this set the direction of the gpio
+- pull-str	- (optional) this set the pull strength of the pin
+- pull-assign	- (optional) this set the pull assignement (up/down) of the pin
+- invert            - (optional) this input pin is inverted
 
 Example:
 
diff --git a/doc/device-tree-bindings/video/rockchip-lvds.txt b/doc/device-tree-bindings/video/rockchip-lvds.txt
new file mode 100644
index 0000000..07e3d3f
--- /dev/null
+++ b/doc/device-tree-bindings/video/rockchip-lvds.txt
@@ -0,0 +1,77 @@
+Rockchip LVDS interface
+------------------
+
+Required properties:
+- compatible: "rockchip,rk3288-lvds";
+
+- reg: physical base address of the controller and length
+	of memory mapped region.
+- clocks: must include clock specifiers corresponding to entries in the
+	clock-names property.
+- clock-names: must contain "pclk_lvds"
+
+- rockchip,grf: phandle to the general register files syscon
+
+- rockchip,data-mapping: should be <LVDS_FORMAT_VESA> or  <LVDS_FORMAT_JEIDA>,
+	This describes how the color bits are laid out in the
+	serialized LVDS signal.
+- rockchip,data-width : should be <18> or <24>;
+- rockchip,output: should be <LVDS_OUTPUT_RGB>, <LVDS_OUTPUT_SINGLE> or
+	<LVDS_OUTPUT_DUAL>, This describes the output face.
+
+- display-timings : described by
+	doc/devicetree/device-tree-bindings/video/display-timing.txt.
+
+Example:
+	lvds: lvds@ff96c000 {
+		compatible = "rockchip,rk3288-lvds";
+		reg = <0xff96c000 0x4000>;
+		clocks = <&cru PCLK_LVDS_PHY>;
+		clock-names = "pclk_lvds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&lcdc0_ctl>;
+		rockchip,grf = <&grf>;
+		status = "disabled";
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			lvds_in: port@0 {
+				reg = <0>;
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				lvds_in_vopb: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_lvds>;
+				};
+				lvds_in_vopl: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_lvds>;
+				};
+			};
+		};
+	};
+
+	&lvds {
+		rockchip,data-mapping = <LVDS_FORMAT_VESA>;
+		rockchip,data-width = <24>;
+		rockchip,output = <LVDS_OUTPUT_DUAL>;
+		rockchip,panel = <&panel>;
+		status = "okay";
+
+		display-timings {
+			timing@0 {
+				clock-frequency = <40000000>;
+				hactive = <1920>;
+				vactive = <1080>;
+				hsync-len = <44>;
+				hfront-porch = <88>;
+				hback-porch = <148>;
+				vfront-porch = <4>;
+				vback-porch = <36>;
+				vsync-len = <5>;
+			};
+		};
+	};
diff --git a/doc/mkimage.1 b/doc/mkimage.1
index b48f70b..e0f210a 100644
--- a/doc/mkimage.1
+++ b/doc/mkimage.1
@@ -97,6 +97,10 @@
 .B Create FIT image:
 
 .TP
+.BI "\-b
+Specifies that the following arguments are device tree binary files (.dtb).
+
+.TP
 .BI "\-c [" "comment" "]"
 Specifies a comment to be added when signing. This is typically a useful
 message which describes how the image was signed or some other useful
@@ -108,10 +112,24 @@
 create the image.
 
 .TP
-.BI "\-f [" "image tree source file" "]"
+.BI "\-E
+After processing, move the image data outside the FIT and store a data offset
+in the FIT. Images will be placed one after the other immediately after the
+FIT, with each one aligned to a 4-byte boundary. The existing 'data' property
+in each image will be replaced with 'data-offset' and 'data-size' properties.
+A 'data-offset' of 0 indicates that it starts in the first (4-byte aligned)
+byte after the FIT.
+
+.TP
+.BI "\-f [" "image tree source file" " | " "auto" "]"
 Image tree source file that describes the structure and contents of the
 FIT image.
 
+This can be automatically generated for some simple cases.
+Use "-f auto" for this. In that case the arguments -d, -A, -O, -T, -C, -a
+and -e are used to specify the image to include in the FIT and its attributes.
+No .its file is required.
+
 .TP
 .BI "\-F"
 Indicates that an existing FIT image should be modified. No dtc
@@ -164,7 +182,7 @@
 .nf
 .B mkimage -f kernel.its -k /public/signing-keys -K u-boot.dtb \\\\
 .br
-.B -c "Kernel 3.8 image for production devices" kernel.itb
+.B -c """Kernel 3.8 image for production devices""" kernel.itb
 .fi
 
 .P
@@ -175,7 +193,25 @@
 .nf
 .B mkimage -F -k /secret/signing-keys -K u-boot.dtb \\\\
 .br
+.B -c """Kernel 3.8 image for production devices""" kernel.itb
+.fi
+
+.P
+Create a FIT image containing a kernel, using automatic mode. No .its file
+is required.
+.nf
+.B mkimage -f auto -A arm -O linux -T kernel -C none -a 43e00000 -e 0 \\\\
+.br
+.B -c """Kernel 4.4 image for production devices""" -d vmlinuz kernel.itb
+.fi
+.P
+Create a FIT image containing a kernel and some device tree files, using
+automatic mode. No .its file is required.
+.nf
+.B mkimage -f auto -A arm -O linux -T kernel -C none -a 43e00000 -e 0 \\\\
+.br
-.B -c "Kernel 3.8 image for production devices" kernel.itb
+.B -c """Kernel 4.4 image for production devices""" -d vmlinuz \\\\
+.B -b /path/to/rk3288-firefly.dtb /path/to/rk3288-jerry.dtb kernel.itb
 .fi
 
 .SH HOMEPAGE
diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt
index 3175c9f..3db068d 100644
--- a/doc/uImage.FIT/source_file_format.txt
+++ b/doc/uImage.FIT/source_file_format.txt
@@ -2,6 +2,7 @@
 ==========================================================
 
 Author: Marian Balakowicz <m8@semihalf.com>
+External data additions, 25/1/16 Simon Glass <sjg@chromium.org>
 
 1) Introduction
 ---------------
@@ -262,7 +263,24 @@
 not* be specified in a configuration node.
 
 
-8) Examples
+8) External data
+----------------
+
+The above format shows a 'data' property which holds the data for each image.
+It is also possible for this data to reside outside the FIT itself. This
+allows the FIT to be quite small, so that it can be loaded and scanned
+without loading a large amount of data. Then when an image is needed it can
+be loaded from an external source.
+
+In this case the 'data' property is omitted. Instead you can use:
+
+  - data-offset : offset of the data in a separate image store. The image
+    store is placed immediately after the last byte of the device tree binary,
+    aligned to a 4-byte boundary.
+  - data-size : size of the data in bytes
+
+
+9) Examples
 -----------
 
 Please see doc/uImage.FIT/*.its for actual image source files.
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index 990f768..f35c4d4 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -1,3 +1,14 @@
+config BLK
+	bool "Support block devices"
+	depends on DM
+	help
+	  Enable support for block devices, such as SCSI, MMC and USB
+	  flash sticks. These provide a block-level interface which permits
+	  reading, writing and (in some cases) erasing blocks. Block
+	  devices often have a partition table which allows the device to
+	  be partitioned into several areas, called 'partitions' in U-Boot.
+	  A filesystem can be placed in each partition.
+
 config DISK
 	bool "Support disk controllers with driver model"
 	depends on DM
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index 5eb87e0..b5c7ae1 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -5,6 +5,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+obj-$(CONFIG_BLK) += blk-uclass.o
+
 obj-$(CONFIG_DISK) += disk-uclass.o
 obj-$(CONFIG_SCSI_AHCI) += ahci.o
 obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
new file mode 100644
index 0000000..49df2a6
--- /dev/null
+++ b/drivers/block/blk-uclass.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <blk.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+
+int blk_first_device(int if_type, struct udevice **devp)
+{
+	struct blk_desc *desc;
+	int ret;
+
+	ret = uclass_first_device(UCLASS_BLK, devp);
+	if (ret)
+		return ret;
+	if (!*devp)
+		return -ENODEV;
+	do {
+		desc = dev_get_uclass_platdata(*devp);
+		if (desc->if_type == if_type)
+			return 0;
+		ret = uclass_next_device(devp);
+		if (ret)
+			return ret;
+	} while (*devp);
+
+	return -ENODEV;
+}
+
+int blk_next_device(struct udevice **devp)
+{
+	struct blk_desc *desc;
+	int ret, if_type;
+
+	desc = dev_get_uclass_platdata(*devp);
+	if_type = desc->if_type;
+	do {
+		ret = uclass_next_device(devp);
+		if (ret)
+			return ret;
+		if (!*devp)
+			return -ENODEV;
+		desc = dev_get_uclass_platdata(*devp);
+		if (desc->if_type == if_type)
+			return 0;
+	} while (1);
+}
+
+int blk_get_device(int if_type, int devnum, struct udevice **devp)
+{
+	struct uclass *uc;
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get(UCLASS_BLK, &uc);
+	if (ret)
+		return ret;
+	uclass_foreach_dev(dev, uc) {
+		struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+		debug("%s: if_type=%d, devnum=%d: %s, %d, %d\n", __func__,
+		      if_type, devnum, dev->name, desc->if_type, desc->devnum);
+		if (desc->if_type == if_type && desc->devnum == devnum) {
+			*devp = dev;
+			return device_probe(dev);
+		}
+	}
+
+	return -ENODEV;
+}
+
+unsigned long blk_dread(struct blk_desc *block_dev, lbaint_t start,
+			lbaint_t blkcnt, void *buffer)
+{
+	struct udevice *dev = block_dev->bdev;
+	const struct blk_ops *ops = blk_get_ops(dev);
+
+	if (!ops->read)
+		return -ENOSYS;
+
+	return ops->read(dev, start, blkcnt, buffer);
+}
+
+unsigned long blk_dwrite(struct blk_desc *block_dev, lbaint_t start,
+			 lbaint_t blkcnt, const void *buffer)
+{
+	struct udevice *dev = block_dev->bdev;
+	const struct blk_ops *ops = blk_get_ops(dev);
+
+	if (!ops->write)
+		return -ENOSYS;
+
+	return ops->write(dev, start, blkcnt, buffer);
+}
+
+unsigned long blk_derase(struct blk_desc *block_dev, lbaint_t start,
+			 lbaint_t blkcnt)
+{
+	struct udevice *dev = block_dev->bdev;
+	const struct blk_ops *ops = blk_get_ops(dev);
+
+	if (!ops->erase)
+		return -ENOSYS;
+
+	return ops->erase(dev, start, blkcnt);
+}
+
+int blk_prepare_device(struct udevice *dev)
+{
+	struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+	part_init(desc);
+
+	return 0;
+}
+
+int blk_create_device(struct udevice *parent, const char *drv_name,
+		      const char *name, int if_type, int devnum, int blksz,
+		      lbaint_t size, struct udevice **devp)
+{
+	struct blk_desc *desc;
+	struct udevice *dev;
+	int ret;
+
+	ret = device_bind_driver(parent, drv_name, name, &dev);
+	if (ret)
+		return ret;
+	desc = dev_get_uclass_platdata(dev);
+	desc->if_type = if_type;
+	desc->blksz = blksz;
+	desc->lba = size / blksz;
+	desc->part_type = PART_TYPE_UNKNOWN;
+	desc->bdev = dev;
+	desc->devnum = devnum;
+	*devp = dev;
+
+	return 0;
+}
+
+int blk_unbind_all(int if_type)
+{
+	struct uclass *uc;
+	struct udevice *dev, *next;
+	int ret;
+
+	ret = uclass_get(UCLASS_BLK, &uc);
+	if (ret)
+		return ret;
+	uclass_foreach_dev_safe(dev, next, uc) {
+		struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+		if (desc->if_type == if_type) {
+			ret = device_remove(dev);
+			if (ret)
+				return ret;
+			ret = device_unbind(dev);
+			if (ret)
+				return ret;
+		}
+	}
+
+	return 0;
+}
+
+UCLASS_DRIVER(blk) = {
+	.id		= UCLASS_BLK,
+	.name		= "blk",
+	.per_device_platdata_auto_alloc_size = sizeof(struct blk_desc),
+};
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index bc072f3..6ec52a9 100644
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -620,7 +620,7 @@
 
 static void dwc_ahsata_print_info(int dev)
 {
-	block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
+	struct blk_desc *pdev = &(sata_dev_desc[dev]);
 
 	printf("SATA Device Info:\n\r");
 #ifdef CONFIG_SYS_64BIT_LBA
@@ -956,7 +956,7 @@
 	struct ahci_probe_ent *probe_ent =
 		(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
 	u8 port = probe_ent->hard_port_no;
-	block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
+	struct blk_desc *pdev = &(sata_dev_desc[dev]);
 
 	id = (u16 *)memalign(ARCH_DMA_MINALIGN,
 				roundup(ARCH_DMA_MINALIGN,
diff --git a/drivers/block/pata_bfin.c b/drivers/block/pata_bfin.c
index c2673bd..26569d7 100644
--- a/drivers/block/pata_bfin.c
+++ b/drivers/block/pata_bfin.c
@@ -965,7 +965,7 @@
 		/* Probe device and set xfer mode */
 		bfin_ata_identify(ap, dev%PATA_DEV_NUM_PER_PORT);
 		bfin_ata_set_Feature_cmd(ap, dev%PATA_DEV_NUM_PER_PORT);
-		init_part(&sata_dev_desc[dev]);
+		part_init(&sata_dev_desc[dev]);
 		return 0;
 	}
 
diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c
index 170f0fa..2d340ef 100644
--- a/drivers/block/sandbox.c
+++ b/drivers/block/sandbox.c
@@ -4,125 +4,149 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <config.h>
 #include <common.h>
+#include <blk.h>
+#include <dm.h>
+#include <fdtdec.h>
 #include <part.h>
 #include <os.h>
 #include <malloc.h>
 #include <sandboxblockdev.h>
 #include <asm/errno.h>
+#include <dm/device-internal.h>
 
-static struct host_block_dev host_devices[CONFIG_HOST_MAX_DEVICES];
+DECLARE_GLOBAL_DATA_PTR;
 
-static struct host_block_dev *find_host_device(int dev)
-{
-	if (dev >= 0 && dev < CONFIG_HOST_MAX_DEVICES)
-		return &host_devices[dev];
-
-	return NULL;
-}
-
-static unsigned long host_block_read(block_dev_desc_t *block_dev,
+static unsigned long host_block_read(struct udevice *dev,
 				     unsigned long start, lbaint_t blkcnt,
 				     void *buffer)
 {
-	int dev = block_dev->dev;
-	struct host_block_dev *host_dev = find_host_device(dev);
+	struct host_block_dev *host_dev = dev_get_priv(dev);
+	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
 
-	if (!host_dev)
-		return -1;
-	if (os_lseek(host_dev->fd,
-		     start * host_dev->blk_dev.blksz,
-		     OS_SEEK_SET) == -1) {
-		printf("ERROR: Invalid position\n");
+	if (os_lseek(host_dev->fd, start * block_dev->blksz, OS_SEEK_SET) ==
+			-1) {
+		printf("ERROR: Invalid block %lx\n", start);
 		return -1;
 	}
-	ssize_t len = os_read(host_dev->fd, buffer,
-			      blkcnt * host_dev->blk_dev.blksz);
+	ssize_t len = os_read(host_dev->fd, buffer, blkcnt * block_dev->blksz);
 	if (len >= 0)
-		return len / host_dev->blk_dev.blksz;
+		return len / block_dev->blksz;
 	return -1;
 }
 
-static unsigned long host_block_write(block_dev_desc_t *block_dev,
+static unsigned long host_block_write(struct udevice *dev,
 				      unsigned long start, lbaint_t blkcnt,
 				      const void *buffer)
 {
-	int dev = block_dev->dev;
-	struct host_block_dev *host_dev = find_host_device(dev);
-	if (os_lseek(host_dev->fd,
-		     start * host_dev->blk_dev.blksz,
-		     OS_SEEK_SET) == -1) {
-		printf("ERROR: Invalid position\n");
+	struct host_block_dev *host_dev = dev_get_priv(dev);
+	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+
+	if (os_lseek(host_dev->fd, start * block_dev->blksz, OS_SEEK_SET) ==
+			-1) {
+		printf("ERROR: Invalid block %lx\n", start);
 		return -1;
 	}
-	ssize_t len = os_write(host_dev->fd, buffer, blkcnt *
-			       host_dev->blk_dev.blksz);
+	ssize_t len = os_write(host_dev->fd, buffer, blkcnt * block_dev->blksz);
 	if (len >= 0)
-		return len / host_dev->blk_dev.blksz;
+		return len / block_dev->blksz;
 	return -1;
 }
 
-int host_dev_bind(int dev, char *filename)
+int host_dev_bind(int devnum, char *filename)
 {
-	struct host_block_dev *host_dev = find_host_device(dev);
+	struct host_block_dev *host_dev;
+	struct udevice *dev;
+	char dev_name[20], *str, *fname;
+	int ret, fd;
 
-	if (!host_dev)
-		return -1;
-	if (host_dev->blk_dev.priv) {
-		os_close(host_dev->fd);
-		host_dev->blk_dev.priv = NULL;
+	/* Remove and unbind the old device, if any */
+	ret = blk_get_device(IF_TYPE_HOST, devnum, &dev);
+	if (ret == 0) {
+		ret = device_remove(dev);
+		if (ret)
+			return ret;
+		ret = device_unbind(dev);
+		if (ret)
+			return ret;
+	} else if (ret != -ENODEV) {
+		return ret;
 	}
-	if (host_dev->filename)
-		free(host_dev->filename);
-	if (filename && *filename) {
-		host_dev->filename = strdup(filename);
-	} else {
-		host_dev->filename = NULL;
+
+	if (!filename)
 		return 0;
+
+	snprintf(dev_name, sizeof(dev_name), "host%d", devnum);
+	str = strdup(dev_name);
+	if (!str)
+		return -ENOMEM;
+	fname = strdup(filename);
+	if (!fname) {
+		free(str);
+		return -ENOMEM;
 	}
 
-	host_dev->fd = os_open(host_dev->filename, OS_O_RDWR);
-	if (host_dev->fd == -1) {
-		printf("Failed to access host backing file '%s'\n",
-		       host_dev->filename);
-		return 1;
+	fd = os_open(filename, OS_O_RDWR);
+	if (fd == -1) {
+		printf("Failed to access host backing file '%s'\n", filename);
+		ret = -ENOENT;
+		goto err;
+	}
+	ret = blk_create_device(gd->dm_root, "sandbox_host_blk", str,
+				IF_TYPE_HOST, devnum, 512,
+				os_lseek(fd, 0, OS_SEEK_END), &dev);
+	if (ret)
+		goto err_file;
+	ret = device_probe(dev);
+	if (ret) {
+		device_unbind(dev);
+		goto err_file;
 	}
 
-	block_dev_desc_t *blk_dev = &host_dev->blk_dev;
-	blk_dev->if_type = IF_TYPE_HOST;
-	blk_dev->priv = host_dev;
-	blk_dev->blksz = 512;
-	blk_dev->lba = os_lseek(host_dev->fd, 0, OS_SEEK_END) / blk_dev->blksz;
-	blk_dev->block_read = host_block_read;
-	blk_dev->block_write = host_block_write;
-	blk_dev->dev = dev;
-	blk_dev->part_type = PART_TYPE_UNKNOWN;
-	init_part(blk_dev);
+	host_dev = dev_get_priv(dev);
+	host_dev->fd = fd;
+	host_dev->filename = fname;
 
-	return 0;
+	return blk_prepare_device(dev);
+err_file:
+	os_close(fd);
+err:
+	free(fname);
+	free(str);
+	return ret;
 }
 
-int host_get_dev_err(int dev, block_dev_desc_t **blk_devp)
+int host_get_dev_err(int devnum, struct blk_desc **blk_devp)
 {
-	struct host_block_dev *host_dev = find_host_device(dev);
+	struct udevice *dev;
+	int ret;
 
-	if (!host_dev)
-		return -ENODEV;
+	ret = blk_get_device(IF_TYPE_HOST, devnum, &dev);
+	if (ret)
+		return ret;
+	*blk_devp = dev_get_uclass_platdata(dev);
 
-	if (!host_dev->blk_dev.priv)
-		return -ENOENT;
-
-	*blk_devp = &host_dev->blk_dev;
 	return 0;
 }
 
-block_dev_desc_t *host_get_dev(int dev)
+struct blk_desc *host_get_dev(int dev)
 {
-	block_dev_desc_t *blk_dev;
+	struct blk_desc *blk_dev;
 
 	if (host_get_dev_err(dev, &blk_dev))
 		return NULL;
 
 	return blk_dev;
 }
+
+static const struct blk_ops sandbox_host_blk_ops = {
+	.read	= host_block_read,
+	.write	= host_block_write,
+};
+
+U_BOOT_DRIVER(sandbox_host_blk) = {
+	.name		= "sandbox_host_blk",
+	.id		= UCLASS_BLK,
+	.ops		= &sandbox_host_blk_ops,
+	.priv_auto_alloc_size	= sizeof(struct host_block_dev),
+};
diff --git a/drivers/block/systemace.c b/drivers/block/systemace.c
index b974e80..09fe834 100644
--- a/drivers/block/systemace.c
+++ b/drivers/block/systemace.c
@@ -69,11 +69,11 @@
 	return in16(base + off);
 }
 
-static unsigned long systemace_read(block_dev_desc_t *block_dev,
+static unsigned long systemace_read(struct blk_desc *block_dev,
 				    unsigned long start, lbaint_t blkcnt,
 				    void *buffer);
 
-static block_dev_desc_t systemace_dev = { 0 };
+static struct blk_desc systemace_dev = { 0 };
 
 static int get_cf_lock(void)
 {
@@ -105,13 +105,13 @@
 }
 
 #ifdef CONFIG_PARTITIONS
-block_dev_desc_t *systemace_get_dev(int dev)
+struct blk_desc *systemace_get_dev(int dev)
 {
 	/* The first time through this, the systemace_dev object is
 	   not yet initialized. In that case, fill it in. */
 	if (systemace_dev.blksz == 0) {
 		systemace_dev.if_type = IF_TYPE_UNKNOWN;
-		systemace_dev.dev = 0;
+		systemace_dev.devnum = 0;
 		systemace_dev.part_type = PART_TYPE_UNKNOWN;
 		systemace_dev.type = DEV_TYPE_HARDDISK;
 		systemace_dev.blksz = 512;
@@ -124,7 +124,7 @@
 		 */
 		ace_writew(width == 8 ? 0 : 0x0001, 0);
 
-		init_part(&systemace_dev);
+		part_init(&systemace_dev);
 
 	}
 
@@ -137,7 +137,7 @@
  * the dev_desc) to read blocks of data. The return value is the
  * number of blocks read. A zero return indicates an error.
  */
-static unsigned long systemace_read(block_dev_desc_t *block_dev,
+static unsigned long systemace_read(struct blk_desc *block_dev,
 				    unsigned long start, lbaint_t blkcnt,
 				    void *buffer)
 {
diff --git a/drivers/core/simple-bus.c b/drivers/core/simple-bus.c
index 913c3cc..1a9c864 100644
--- a/drivers/core/simple-bus.c
+++ b/drivers/core/simple-bus.c
@@ -53,6 +53,7 @@
 
 static const struct udevice_id generic_simple_bus_ids[] = {
 	{ .compatible = "simple-bus" },
+	{ .compatible = "simple-mfd" },
 	{ }
 };
 
diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c
index a0666d0..e03f46a 100644
--- a/drivers/core/syscon-uclass.c
+++ b/drivers/core/syscon-uclass.c
@@ -38,6 +38,7 @@
 	struct uclass *uc;
 	int ret;
 
+	*devp = NULL;
 	ret = uclass_get(UCLASS_SYSCON, &uc);
 	if (ret)
 		return ret;
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 12095e7..1141ce1 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -401,6 +401,19 @@
 	return uclass_get_device_tail(dev, ret, devp);
 }
 
+int uclass_first_device_err(enum uclass_id id, struct udevice **devp)
+{
+	int ret;
+
+	ret = uclass_first_device(id, devp);
+	if (ret)
+		return ret;
+	else if (!*devp)
+		return -ENODEV;
+
+	return 0;
+}
+
 int uclass_next_device(struct udevice **devp)
 {
 	struct udevice *dev = *devp;
diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c
index 395d472..faece88 100644
--- a/drivers/dfu/dfu_mmc.c
+++ b/drivers/dfu/dfu_mmc.c
@@ -351,11 +351,11 @@
 
 	} else if (!strcmp(entity_type, "part")) {
 		disk_partition_t partinfo;
-		block_dev_desc_t *blk_dev = &mmc->block_dev;
+		struct blk_desc *blk_dev = &mmc->block_dev;
 		int mmcdev = second_arg;
 		int mmcpart = third_arg;
 
-		if (get_partition_info(blk_dev, mmcpart, &partinfo) != 0) {
+		if (part_get_info(blk_dev, mmcpart, &partinfo) != 0) {
 			error("Couldn't find part #%d on mmc device #%d\n",
 			      mmcpart, mmcdev);
 			return -ENODEV;
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 94fabb9..a5da5e7 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -39,6 +39,15 @@
 	  may be dedicated as a general purpose I/O or be assigned to
 	  a function of an embedded peripheral.
 
+config INTEL_BROADWELL_GPIO
+	bool "Intel Broadwell GPIO driver"
+	depends on DM
+	help
+	  This driver supports Broadwell U devices which have an expanded
+	  GPIO feature set. The difference is large enough to merit a separate
+	  driver from the common Intel ICH6 driver. It supports a total of
+	  95 GPIOs which can be configured from the device tree.
+
 config LPC32XX_GPIO
 	bool "LPC32XX GPIO driver"
 	depends on DM
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ca8c487..e7b7ec4 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -14,6 +14,7 @@
 obj-$(CONFIG_AT91_GPIO)	+= at91_gpio.o
 obj-$(CONFIG_ATMEL_PIO4)	+= atmel_pio4.o
 obj-$(CONFIG_INTEL_ICH6_GPIO)	+= intel_ich6_gpio.o
+obj-$(CONFIG_INTEL_BROADWELL_GPIO)	+= intel_broadwell_gpio.o
 obj-$(CONFIG_KIRKWOOD_GPIO)	+= kw_gpio.o
 obj-$(CONFIG_KONA_GPIO)	+= kona_gpio.o
 obj-$(CONFIG_MARVELL_GPIO)	+= mvgpio.o
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index d603b55..b58d4e6 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -257,7 +257,7 @@
 	return _dm_gpio_free(desc.dev, desc.offset);
 }
 
-static int check_reserved(struct gpio_desc *desc, const char *func)
+static int check_reserved(const struct gpio_desc *desc, const char *func)
 {
 	struct gpio_dev_priv *uc_priv;
 
@@ -324,7 +324,7 @@
 							desc.offset, value);
 }
 
-int dm_gpio_get_value(struct gpio_desc *desc)
+int dm_gpio_get_value(const struct gpio_desc *desc)
 {
 	int value;
 	int ret;
@@ -338,7 +338,7 @@
 	return desc->flags & GPIOD_ACTIVE_LOW ? !value : value;
 }
 
-int dm_gpio_set_value(struct gpio_desc *desc, int value)
+int dm_gpio_set_value(const struct gpio_desc *desc, int value)
 {
 	int ret;
 
@@ -577,6 +577,24 @@
 	return vector;
 }
 
+int dm_gpio_get_values_as_int(const struct gpio_desc *desc_list, int count)
+{
+	unsigned bitmask = 1;
+	unsigned vector = 0;
+	int ret, i;
+
+	for (i = 0; i < count; i++) {
+		ret = dm_gpio_get_value(&desc_list[i]);
+		if (ret < 0)
+			return ret;
+		else if (ret)
+			vector |= bitmask;
+		bitmask <<= 1;
+	}
+
+	return vector;
+}
+
 static int _gpio_request_by_name_nodev(const void *blob, int node,
 				       const char *list_name, int index,
 				       struct gpio_desc *desc, int flags,
@@ -748,7 +766,7 @@
 	return 0;
 }
 
-int gpio_get_number(struct gpio_desc *desc)
+int gpio_get_number(const struct gpio_desc *desc)
 {
 	struct udevice *dev = desc->dev;
 	struct gpio_dev_priv *uc_priv;
diff --git a/drivers/gpio/intel_broadwell_gpio.c b/drivers/gpio/intel_broadwell_gpio.c
new file mode 100644
index 0000000..8cf76f9
--- /dev/null
+++ b/drivers/gpio/intel_broadwell_gpio.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <pch.h>
+#include <pci.h>
+#include <syscon.h>
+#include <asm/cpu.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/gpio.h>
+#include <dt-bindings/gpio/x86-gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * struct broadwell_bank_priv - Private driver data
+ *
+ * @regs:	Pointer to GPIO registers
+ * @bank:	Bank number for this bank (0, 1 or 2)
+ * @offset:	GPIO offset for this bank (0, 32 or 64)
+ */
+struct broadwell_bank_priv {
+	struct pch_lp_gpio_regs *regs;
+	int bank;
+	int offset;
+};
+
+static int broadwell_gpio_request(struct udevice *dev, unsigned offset,
+			     const char *label)
+{
+	struct broadwell_bank_priv *priv = dev_get_priv(dev);
+	struct pch_lp_gpio_regs *regs = priv->regs;
+	u32 val;
+
+	/*
+	 * Make sure that the GPIO pin we want isn't already in use for some
+	 * built-in hardware function. We have to check this for every
+	 * requested pin.
+	 */
+	debug("%s: request bank %d offset %d: ", __func__, priv->bank, offset);
+	val = inl(&regs->own[priv->bank]);
+	if (!(val & (1UL << offset))) {
+		debug("gpio is reserved for internal use\n");
+		return -EPERM;
+	}
+	debug("ok\n");
+
+	return 0;
+}
+
+static int broadwell_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+	struct broadwell_bank_priv *priv = dev_get_priv(dev);
+	struct pch_lp_gpio_regs *regs = priv->regs;
+
+	setio_32(&regs->config[priv->offset + offset], CONFA_DIR_INPUT);
+
+	return 0;
+}
+
+static int broadwell_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+	struct broadwell_bank_priv *priv = dev_get_priv(dev);
+	struct pch_lp_gpio_regs *regs = priv->regs;
+
+	return inl(&regs->config[priv->offset + offset]) & CONFA_LEVEL_HIGH ?
+		1 : 0;
+}
+
+static int broadwell_gpio_set_value(struct udevice *dev, unsigned offset,
+				    int value)
+{
+	struct broadwell_bank_priv *priv = dev_get_priv(dev);
+	struct pch_lp_gpio_regs *regs = priv->regs;
+
+	debug("%s: dev=%s, offset=%d, value=%d\n", __func__, dev->name, offset,
+	      value);
+	clrsetio_32(&regs->config[priv->offset + offset], CONFA_OUTPUT_HIGH,
+		      value ? CONFA_OUTPUT_HIGH : 0);
+
+	return 0;
+}
+
+static int broadwell_gpio_direction_output(struct udevice *dev, unsigned offset,
+					   int value)
+{
+	struct broadwell_bank_priv *priv = dev_get_priv(dev);
+	struct pch_lp_gpio_regs *regs = priv->regs;
+
+	broadwell_gpio_set_value(dev, offset, value);
+	clrio_32(&regs->config[priv->offset + offset], CONFA_DIR_INPUT);
+
+	return 0;
+}
+
+static int broadwell_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+	struct broadwell_bank_priv *priv = dev_get_priv(dev);
+	struct pch_lp_gpio_regs *regs = priv->regs;
+	u32 mask = 1UL << offset;
+
+	if (!(inl(&regs->own[priv->bank]) & mask))
+		return GPIOF_FUNC;
+	if (inl(&regs->config[priv->offset + offset]) & CONFA_DIR_INPUT)
+		return GPIOF_INPUT;
+	else
+		return GPIOF_OUTPUT;
+}
+
+static int broadwell_gpio_probe(struct udevice *dev)
+{
+	struct broadwell_bank_platdata *plat = dev_get_platdata(dev);
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct broadwell_bank_priv *priv = dev_get_priv(dev);
+	struct udevice *pinctrl;
+	int ret;
+
+	/* Set up pin control if available */
+	ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
+	debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret);
+
+	uc_priv->gpio_count = GPIO_PER_BANK;
+	uc_priv->bank_name = plat->bank_name;
+
+	priv->regs = (struct pch_lp_gpio_regs *)(uintptr_t)plat->base_addr;
+	priv->bank = plat->bank;
+	priv->offset = priv->bank * 32;
+	debug("%s: probe done, regs %p, bank %d\n", __func__, priv->regs,
+	      priv->bank);
+
+	return 0;
+}
+
+static int broadwell_gpio_ofdata_to_platdata(struct udevice *dev)
+{
+	struct broadwell_bank_platdata *plat = dev_get_platdata(dev);
+	u32 gpiobase;
+	int bank;
+	int ret;
+
+	ret = pch_get_gpio_base(dev->parent, &gpiobase);
+	if (ret)
+		return ret;
+
+	bank = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
+	if (bank == -1) {
+		debug("%s: Invalid bank number %d\n", __func__, bank);
+		return -EINVAL;
+	}
+	plat->bank = bank;
+	plat->base_addr = gpiobase;
+	plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+				      "bank-name", NULL);
+
+	return 0;
+}
+
+static int broadwell_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+				struct fdtdec_phandle_args *args)
+{
+	desc->offset = args->args[0];
+	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+	return 0;
+}
+
+static const struct dm_gpio_ops gpio_broadwell_ops = {
+	.request		= broadwell_gpio_request,
+	.direction_input	= broadwell_gpio_direction_input,
+	.direction_output	= broadwell_gpio_direction_output,
+	.get_value		= broadwell_gpio_get_value,
+	.set_value		= broadwell_gpio_set_value,
+	.get_function		= broadwell_gpio_get_function,
+	.xlate			= broadwell_gpio_xlate,
+};
+
+static const struct udevice_id intel_broadwell_gpio_ids[] = {
+	{ .compatible = "intel,broadwell-gpio" },
+	{ }
+};
+
+U_BOOT_DRIVER(gpio_broadwell) = {
+	.name	= "gpio_broadwell",
+	.id	= UCLASS_GPIO,
+	.of_match = intel_broadwell_gpio_ids,
+	.ops	= &gpio_broadwell_ops,
+	.ofdata_to_platdata	= broadwell_gpio_ofdata_to_platdata,
+	.probe	= broadwell_gpio_probe,
+	.priv_auto_alloc_size = sizeof(struct broadwell_bank_priv),
+	.platdata_auto_alloc_size = sizeof(struct broadwell_bank_platdata),
+};
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 527ed6d..b7e379a 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -32,6 +32,8 @@
 #include <fdtdec.h>
 #include <pch.h>
 #include <pci.h>
+#include <syscon.h>
+#include <asm/cpu.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/pci.h>
@@ -51,18 +53,6 @@
 #define GPIO_IOSEL_OFFSET(x)	(x + 4)
 #define GPIO_LVL_OFFSET(x)	(x + 8)
 
-#define IOPAD_MODE_MASK				0x7
-#define IOPAD_PULL_ASSIGN_SHIFT		7
-#define IOPAD_PULL_ASSIGN_MASK		(0x3 << IOPAD_PULL_ASSIGN_SHIFT)
-#define IOPAD_PULL_STRENGTH_SHIFT	9
-#define IOPAD_PULL_STRENGTH_MASK	(0x3 << IOPAD_PULL_STRENGTH_SHIFT)
-
-/* TODO: Move this to device tree, or platform data */
-void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
-{
-	gd->arch.gpio_map = map;
-}
-
 static int _ich6_gpio_set_value(uint16_t base, unsigned offset, int value)
 {
 	u32 val;
@@ -77,23 +67,6 @@
 	return 0;
 }
 
-static int _ich6_gpio_set_function(uint16_t base, unsigned offset, int func)
-{
-	u32 val;
-
-	if (func) {
-		val = inl(base);
-		val |= (1UL << offset);
-		outl(val, base);
-	} else {
-		val = inl(base);
-		val &= ~(1UL << offset);
-		outl(val, base);
-	}
-
-	return 0;
-}
-
 static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir)
 {
 	u32 val;
@@ -108,161 +81,9 @@
 		outl(val, base);
 	}
 
-	return 0;
-}
-
-static int _gpio_ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node)
-{
-	u32 gpio_offset[2];
-	int pad_offset;
-	int val;
-	int ret;
-	const void *prop;
-
-	/*
-	 * GPIO node is not mandatory, so we only do the
-	 * pinmuxing if the node exist.
-	 */
-	ret = fdtdec_get_int_array(gd->fdt_blob, pin_node, "gpio-offset",
-			     gpio_offset, 2);
-	if (!ret) {
-		/* Do we want to force the GPIO mode? */
-		prop = fdt_getprop(gd->fdt_blob, pin_node, "mode-gpio",
-				      NULL);
-		if (prop)
-			_ich6_gpio_set_function(GPIO_USESEL_OFFSET
-						(gpiobase) +
-						gpio_offset[0],
-						gpio_offset[1], 1);
-
-		val =
-		    fdtdec_get_int(gd->fdt_blob, pin_node, "direction", -1);
-		if (val != -1)
-			_ich6_gpio_set_direction(GPIO_IOSEL_OFFSET
-						 (gpiobase) +
-						 gpio_offset[0],
-						 gpio_offset[1], val);
-
-		val =
-		    fdtdec_get_int(gd->fdt_blob, pin_node, "output-value", -1);
-		if (val != -1)
-			_ich6_gpio_set_value(GPIO_LVL_OFFSET(gpiobase)
-					     + gpio_offset[0],
-					     gpio_offset[1], val);
-	}
-
-	/* if iobase is present, let's configure the pad */
-	if (iobase != -1) {
-		int iobase_addr;
-
-		/*
-		 * The offset for the same pin for the IOBASE and GPIOBASE are
-		 * different, so instead of maintaining a lookup table,
-		 * the device tree should provide directly the correct
-		 * value for both mapping.
-		 */
-		pad_offset =
-		    fdtdec_get_int(gd->fdt_blob, pin_node, "pad-offset", -1);
-		if (pad_offset == -1) {
-			debug("%s: Invalid register io offset %d\n",
-			      __func__, pad_offset);
-			return -EINVAL;
-		}
-
-		/* compute the absolute pad address */
-		iobase_addr = iobase + pad_offset;
-
-		/*
-		 * Do we need to set a specific function mode?
-		 * If someone put also 'mode-gpio', this option will
-		 * be just ignored by the controller
-		 */
-		val = fdtdec_get_int(gd->fdt_blob, pin_node, "mode-func", -1);
-		if (val != -1)
-			clrsetbits_le32(iobase_addr, IOPAD_MODE_MASK, val);
-
-		/* Configure the pull-up/down if needed */
-		val = fdtdec_get_int(gd->fdt_blob, pin_node, "pull-assign", -1);
-		if (val != -1)
-			clrsetbits_le32(iobase_addr,
-					IOPAD_PULL_ASSIGN_MASK,
-					val << IOPAD_PULL_ASSIGN_SHIFT);
-
-		val =
-		    fdtdec_get_int(gd->fdt_blob, pin_node, "pull-strength", -1);
-		if (val != -1)
-			clrsetbits_le32(iobase_addr,
-					IOPAD_PULL_STRENGTH_MASK,
-					val << IOPAD_PULL_STRENGTH_SHIFT);
-
-		debug("%s: pad cfg [0x%x]: %08x\n", __func__, pad_offset,
-		      readl(iobase_addr));
-	}
-
 	return 0;
 }
 
-int gpio_ich6_pinctrl_init(void)
-{
-	struct udevice *pch;
-	int pin_node;
-	int node;
-	int ret;
-	u32 gpiobase;
-	u32 iobase = -1;
-
-	ret = uclass_first_device(UCLASS_PCH, &pch);
-	if (ret)
-		return ret;
-	if (!pch)
-		return -ENODEV;
-
-	/*
-	 * Get the memory/io base address to configure every pins.
-	 * IOBASE is used to configure the mode/pads
-	 * GPIOBASE is used to configure the direction and default value
-	 */
-	ret = pch_get_gpio_base(pch, &gpiobase);
-	if (ret) {
-		debug("%s: invalid GPIOBASE address (%08x)\n", __func__,
-		      gpiobase);
-		return -EINVAL;
-	}
-
-	/* This is not an error to not have a pinctrl node */
-	node =
-	    fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_X86_PINCTRL);
-	if (node <= 0) {
-		debug("%s: no pinctrl node\n", __func__);
-		return 0;
-	}
-
-	/*
-	 * Get the IOBASE, this is not mandatory as this is not
-	 * supported by all the CPU
-	 */
-	ret = pch_get_io_base(pch, &iobase);
-	if (ret && ret != -ENOSYS) {
-		debug("%s: invalid IOBASE address (%08x)\n", __func__,
-		      iobase);
-		return -EINVAL;
-	}
-
-	for (pin_node = fdt_first_subnode(gd->fdt_blob, node);
-	     pin_node > 0;
-	     pin_node = fdt_next_subnode(gd->fdt_blob, pin_node)) {
-		/* Configure the pin */
-		ret = _gpio_ich6_pinctrl_cfg_pin(gpiobase, iobase, pin_node);
-		if (ret != 0) {
-			debug("%s: invalid configuration for the pin %d\n",
-			      __func__, pin_node);
-			return ret;
-		}
-	}
-
-	return 0;
-}
-
 static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
 {
 	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
@@ -279,6 +100,7 @@
 		debug("%s: Invalid register offset %d\n", __func__, offset);
 		return -EINVAL;
 	}
+	plat->offset = offset;
 	plat->base_addr = gpiobase + offset;
 	plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
 				      "bank-name", NULL);
@@ -291,11 +113,10 @@
 	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 	struct ich6_bank_priv *bank = dev_get_priv(dev);
+	struct udevice *pinctrl;
 
-	if (gd->arch.gpio_map) {
-		setup_pch_gpios(plat->base_addr, gd->arch.gpio_map);
-		gd->arch.gpio_map = NULL;
-	}
+	/* Set up pin control if available */
+	syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
 
 	uc_priv->gpio_count = GPIO_PER_BANK;
 	uc_priv->bank_name = plat->bank_name;
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index c62f025..40e87bd 100644
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -116,11 +116,9 @@
 
 	/* This only supports RK3288 at present */
 	priv->regs = (struct rockchip_gpio_regs *)dev_get_addr(dev);
-	ret = uclass_first_device(UCLASS_PINCTRL, &priv->pinctrl);
+	ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl);
 	if (ret)
 		return ret;
-	if (!priv->pinctrl)
-		return -ENODEV;
 
 	uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
 	end = strrchr(dev->name, '@');
diff --git a/drivers/input/Makefile b/drivers/input/Makefile
index 5f15265..9109ac6 100644
--- a/drivers/input/Makefile
+++ b/drivers/input/Makefile
@@ -10,6 +10,7 @@
 obj-$(CONFIG_I8042_KEYB) += i8042.o
 obj-$(CONFIG_TEGRA_KEYBOARD) += tegra-kbc.o
 obj-$(CONFIG_TWL4030_INPUT) += twl4030.o
+obj-$(CONFIG_TWL6030_INPUT) += twl6030.o
 obj-$(CONFIG_CROS_EC_KEYB) += cros_ec_keyb.o
 ifdef CONFIG_PS2KBD
 obj-y += keyboard.o pc_keyb.o
diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c
index 661d7fd..03d4840 100644
--- a/drivers/input/i8042.c
+++ b/drivers/input/i8042.c
@@ -134,6 +134,10 @@
 	    kbd_read(I8042_DATA_REG) != KBD_POR)
 		goto err;
 
+	if (kbd_write(I8042_DATA_REG, CMD_DRAIN_OUTPUT) ||
+	    kbd_read(I8042_DATA_REG) != KBD_ACK)
+		goto err;
+
 	/* set AT translation and disable irq */
 	config = kbd_cmd_read(CMD_RD_CONFIG);
 	if (config == -1)
diff --git a/drivers/input/twl6030.c b/drivers/input/twl6030.c
new file mode 100644
index 0000000..8de032a
--- /dev/null
+++ b/drivers/input/twl6030.c
@@ -0,0 +1,48 @@
+/*
+ * TWL6030 input
+ *
+ * Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <twl6030.h>
+
+int twl6030_input_power_button(void)
+{
+	u8 value;
+
+	twl6030_i2c_read_u8(TWL6030_CHIP_PM, TWL6030_STS_HW_CONDITIONS, &value);
+
+	/* Power button is active low. */
+	if (value & TWL6030_STS_HW_CONDITIONS_PWRON)
+		return 0;
+
+	return 1;
+}
+
+int twl6030_input_charger(void)
+{
+	u8 value;
+
+	twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, TWL6030_CONTROLLER_STAT1,
+		&value);
+
+	if (value & TWL6030_CONTROLLER_STAT1_VAC_DET)
+		return 1;
+
+	return 0;
+}
+
+int twl6030_input_usb(void)
+{
+	u8 value;
+
+	twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, TWL6030_CONTROLLER_STAT1,
+		&value);
+
+	if (value & TWL6030_CONTROLLER_STAT1_VBUS_DET)
+		return 1;
+
+	return 0;
+}
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index f2b08ab..5969d34 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -16,8 +16,8 @@
 obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
 obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o
 obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
-endif
 obj-$(CONFIG_FSL_DEBUG_SERVER) += fsl_debug_server.o
+endif
 obj-$(CONFIG_FSL_IIM) += fsl_iim.o
 obj-$(CONFIG_GPIO_LED) += gpio_led.o
 obj-$(CONFIG_I2C_EEPROM) += i2c_eeprom.o
diff --git a/drivers/misc/altera_sysid.c b/drivers/misc/altera_sysid.c
index 2d0fa2a..ed6d462 100644
--- a/drivers/misc/altera_sysid.c
+++ b/drivers/misc/altera_sysid.c
@@ -32,11 +32,9 @@
 	int ret;
 
 	/* the first misc device will be used */
-	ret = uclass_first_device(UCLASS_MISC, &dev);
+	ret = uclass_first_device_err(UCLASS_MISC, &dev);
 	if (ret)
 		return;
-	if (!dev)
-		return;
 	ret = misc_read(dev, 0, &sysid, sizeof(sysid));
 	if (ret)
 		return;
diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c
index 5ef7ff7..8f2694f 100644
--- a/drivers/mmc/arm_pl180_mmci.c
+++ b/drivers/mmc/arm_pl180_mmci.c
@@ -375,7 +375,7 @@
 	if (mmc == NULL)
 		return -1;
 
-	debug("registered mmc interface number is:%d\n", mmc->block_dev.dev);
+	debug("registered mmc interface number is:%d\n", mmc->block_dev.devnum);
 
 	return 0;
 }
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 909e3ca..7329f40 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -189,7 +189,7 @@
 				 data ? DIV_ROUND_UP(data->blocks, 8) : 0);
 	int ret = 0, flags = 0, i;
 	unsigned int timeout = 100000;
-	u32 retry = 10000;
+	u32 retry = 100000;
 	u32 mask, ctrl;
 	ulong start = get_timer(0);
 	struct bounce_buffer bbstate;
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index ede5d6e..8b2e606 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -182,7 +182,7 @@
 	list_for_each(entry, &mmc_devices) {
 		m = list_entry(entry, struct mmc, link);
 
-		if (m->block_dev.dev == dev_num)
+		if (m->block_dev.devnum == dev_num)
 			return m;
 	}
 
@@ -234,10 +234,10 @@
 	return blkcnt;
 }
 
-static ulong mmc_bread(block_dev_desc_t *block_dev, lbaint_t start,
+static ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start,
 		       lbaint_t blkcnt, void *dst)
 {
-	int dev_num = block_dev->dev;
+	int dev_num = block_dev->devnum;
 	int err;
 	lbaint_t cur, blocks_todo = blkcnt;
 
@@ -1495,7 +1495,7 @@
 	mmc->block_dev.revision[0] = 0;
 #endif
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
-	init_part(&mmc->block_dev);
+	part_init(&mmc->block_dev);
 #endif
 
 	return 0;
@@ -1556,7 +1556,7 @@
 	mmc->dsr = 0xffffffff;
 	/* Setup the universal parts of the block interface just once */
 	mmc->block_dev.if_type = IF_TYPE_MMC;
-	mmc->block_dev.dev = cur_dev_num++;
+	mmc->block_dev.devnum = cur_dev_num++;
 	mmc->block_dev.removable = 1;
 	mmc->block_dev.block_read = mmc_bread;
 	mmc->block_dev.block_write = mmc_bwrite;
@@ -1579,7 +1579,7 @@
 }
 
 #ifdef CONFIG_PARTITIONS
-block_dev_desc_t *mmc_get_dev(int dev)
+struct blk_desc *mmc_get_dev(int dev)
 {
 	struct mmc *mmc = find_mmc_device(dev);
 	if (!mmc || mmc_init(mmc))
@@ -1728,7 +1728,7 @@
 		else
 			mmc_type = NULL;
 
-		printf("%s: %d", m->cfg->name, m->block_dev.dev);
+		printf("%s: %d", m->cfg->name, m->block_dev.devnum);
 		if (mmc_type)
 			printf(" (%s)", mmc_type);
 
diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h
index 6a70639..d3f6bfe 100644
--- a/drivers/mmc/mmc_private.h
+++ b/drivers/mmc/mmc_private.h
@@ -22,23 +22,23 @@
 
 #ifndef CONFIG_SPL_BUILD
 
-unsigned long mmc_berase(block_dev_desc_t *block_dev, lbaint_t start,
+unsigned long mmc_berase(struct blk_desc *block_dev, lbaint_t start,
 			 lbaint_t blkcnt);
 
-unsigned long mmc_bwrite(block_dev_desc_t *block_dev, lbaint_t start,
+unsigned long mmc_bwrite(struct blk_desc *block_dev, lbaint_t start,
 			 lbaint_t blkcnt, const void *src);
 
 #else /* CONFIG_SPL_BUILD */
 
 /* SPL will never write or erase, declare dummies to reduce code size. */
 
-static inline unsigned long mmc_berase(block_dev_desc_t *block_dev,
+static inline unsigned long mmc_berase(struct blk_desc *block_dev,
 				       lbaint_t start, lbaint_t blkcnt)
 {
 	return 0;
 }
 
-static inline ulong mmc_bwrite(block_dev_desc_t *block_dev, lbaint_t start,
+static inline ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start,
 			       lbaint_t blkcnt, const void *src)
 {
 	return 0;
diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c
index 9032a73..7547e1a 100644
--- a/drivers/mmc/mmc_spi.c
+++ b/drivers/mmc/mmc_spi.c
@@ -91,7 +91,7 @@
 			spi_xfer(spi, bsize * 8, NULL, buf, 0);
 			spi_xfer(spi, 2 * 8, NULL, &crc, 0);
 #ifdef CONFIG_MMC_SPI_CRC_ON
-			if (be_to_cpu16(cyg_crc16(buf, bsize)) != crc) {
+			if (be_to_cpu16(crc16_ccitt(0, buf, bsize)) != crc) {
 				debug("%s: CRC error\n", mmc->cfg->name);
 				r1 = R1_SPI_COM_CRC;
 				break;
@@ -120,7 +120,7 @@
 	tok[1] = multi ? SPI_TOKEN_MULTI_WRITE : SPI_TOKEN_SINGLE;
 	while (bcnt--) {
 #ifdef CONFIG_MMC_SPI_CRC_ON
-		crc = cpu_to_be16(cyg_crc16((u8 *)buf, bsize));
+		crc = cpu_to_be16(crc16_ccitt(0, (u8 *)buf, bsize));
 #endif
 		spi_xfer(spi, 2 * 8, tok, NULL, 0);
 		spi_xfer(spi, bsize * 8, buf, NULL, 0);
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index 79b8c4d..7b186f8 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -65,10 +65,10 @@
 	return err;
 }
 
-unsigned long mmc_berase(block_dev_desc_t *block_dev, lbaint_t start,
+unsigned long mmc_berase(struct blk_desc *block_dev, lbaint_t start,
 			 lbaint_t blkcnt)
 {
-	int dev_num = block_dev->dev;
+	int dev_num = block_dev->devnum;
 	int err = 0;
 	u32 start_rem, blkcnt_rem;
 	struct mmc *mmc = find_mmc_device(dev_num);
@@ -171,10 +171,10 @@
 	return blkcnt;
 }
 
-ulong mmc_bwrite(block_dev_desc_t *block_dev, lbaint_t start, lbaint_t blkcnt,
+ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
 		 const void *src)
 {
-	int dev_num = block_dev->dev;
+	int dev_num = block_dev->devnum;
 	lbaint_t cur, blocks_todo = blkcnt;
 	int err;
 
diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
index 31fb3ab..9fa87d5 100644
--- a/drivers/mmc/mxsmmc.c
+++ b/drivers/mmc/mxsmmc.c
@@ -142,7 +142,7 @@
 	uint32_t ctrl0;
 	int ret;
 
-	debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
+	debug("MMC%d: CMD%d\n", mmc->block_dev.devnum, cmd->cmdidx);
 
 	/* Check bus busy */
 	timeout = MXSMMC_MAX_TIMEOUT;
@@ -157,13 +157,13 @@
 	}
 
 	if (!timeout) {
-		printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
+		printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.devnum);
 		return TIMEOUT;
 	}
 
 	/* See if card is present */
 	if (!mxsmmc_cd(priv)) {
-		printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
+		printf("MMC%d: No card detected!\n", mmc->block_dev.devnum);
 		return NO_CARD_ERR;
 	}
 
@@ -200,9 +200,9 @@
 		if (data->flags & MMC_DATA_READ) {
 			ctrl0 |= SSP_CTRL0_READ;
 		} else if (priv->mmc_is_wp &&
-			priv->mmc_is_wp(mmc->block_dev.dev)) {
+			priv->mmc_is_wp(mmc->block_dev.devnum)) {
 			printf("MMC%d: Can not write a locked card!\n",
-				mmc->block_dev.dev);
+				mmc->block_dev.devnum);
 			return UNUSABLE_ERR;
 		}
 
@@ -243,21 +243,21 @@
 
 	if (!timeout) {
 		printf("MMC%d: Command %d busy\n",
-			mmc->block_dev.dev, cmd->cmdidx);
+			mmc->block_dev.devnum, cmd->cmdidx);
 		return TIMEOUT;
 	}
 
 	/* Check command timeout */
 	if (reg & SSP_STATUS_RESP_TIMEOUT) {
 		printf("MMC%d: Command %d timeout (status 0x%08x)\n",
-			mmc->block_dev.dev, cmd->cmdidx, reg);
+			mmc->block_dev.devnum, cmd->cmdidx, reg);
 		return TIMEOUT;
 	}
 
 	/* Check command errors */
 	if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
 		printf("MMC%d: Command %d error (status 0x%08x)!\n",
-			mmc->block_dev.dev, cmd->cmdidx, reg);
+			mmc->block_dev.devnum, cmd->cmdidx, reg);
 		return COMM_ERR;
 	}
 
@@ -279,14 +279,14 @@
 		if (ret) {
 			printf("MMC%d: Data timeout with command %d "
 				"(status 0x%08x)!\n",
-				mmc->block_dev.dev, cmd->cmdidx, reg);
+				mmc->block_dev.devnum, cmd->cmdidx, reg);
 			return ret;
 		}
 	} else {
 		ret = mxsmmc_send_cmd_dma(priv, data);
 		if (ret) {
 			printf("MMC%d: DMA transfer failed\n",
-				mmc->block_dev.dev);
+				mmc->block_dev.devnum);
 			return ret;
 		}
 	}
@@ -297,7 +297,7 @@
 		(SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
 		SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
 		printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
-			mmc->block_dev.dev, cmd->cmdidx, reg);
+			mmc->block_dev.devnum, cmd->cmdidx, reg);
 		return COMM_ERR;
 	}
 
@@ -330,7 +330,7 @@
 			SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
 
 	debug("MMC%d: Set %d bits bus width\n",
-		mmc->block_dev.dev, mmc->bus_width);
+		mmc->block_dev.devnum, mmc->bus_width);
 }
 
 static int mxsmmc_init(struct mmc *mmc)
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 5038a9f..afe0b06 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -96,7 +96,7 @@
 }
 #endif
 
-#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
+#if defined(CONFIG_OMAP44XX)
 static void omap4_vmmc_pbias_config(struct mmc *mmc)
 {
 	u32 value = 0;
@@ -104,8 +104,6 @@
 	value = readl((*ctrl)->control_pbiaslite);
 	value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
 	writel(value, (*ctrl)->control_pbiaslite);
-	/* set VMMC to 3V */
-	twl6030_power_mmc_init();
 	value = readl((*ctrl)->control_pbiaslite);
 	value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
 	writel(value, (*ctrl)->control_pbiaslite);
@@ -175,13 +173,13 @@
 		&prcm_base->iclken1_core);
 #endif
 
-#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
+#if defined(CONFIG_OMAP44XX)
 	/* PBIAS config needed for MMC1 only */
-	if (mmc->block_dev.dev == 0)
+	if (mmc->block_dev.devnum == 0)
 		omap4_vmmc_pbias_config(mmc);
 #endif
 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
-	if (mmc->block_dev.dev == 0)
+	if (mmc->block_dev.devnum == 0)
 		omap5_pbias_config(mmc);
 #endif
 
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 8586d89..ef7e615 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -137,7 +137,7 @@
 	int trans_bytes = 0, is_aligned = 1;
 	u32 mask, flags, mode;
 	unsigned int time = 0, start_addr = 0;
-	int mmc_dev = mmc->block_dev.dev;
+	int mmc_dev = mmc->block_dev.devnum;
 	unsigned start = get_timer(0);
 
 	/* Timeout unit - ms */
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 2ae2e3c..44d9e9b 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -665,7 +665,7 @@
 
 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
 static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs,
-				 u32 *len)
+				 u64 *len)
 {
 	u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
 	int shift = ffs(mask) - 1;
@@ -685,11 +685,11 @@
 /*
  * Return 1 if the entire region is locked, 0 otherwise
  */
-static int stm_is_locked_sr(struct spi_flash *flash, u32 ofs, u32 len,
+static int stm_is_locked_sr(struct spi_flash *flash, loff_t ofs, u64 len,
 			    u8 sr)
 {
 	loff_t lock_offs;
-	u32 lock_len;
+	u64 lock_len;
 
 	stm_get_locked_range(flash, sr, &lock_offs, &lock_len);
 
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 7e312f1..71c3abe 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -6,6 +6,7 @@
 #include <errno.h>
 #include <common.h>
 #include <asm/io.h>
+#include <fdt_support.h>
 #include <fsl_mdio.h>
 #ifdef CONFIG_FSL_LAYERSCAPE
 #include <asm/arch/fsl_serdes.h>
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index d01bfc1..c7fbf7b 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -30,11 +30,9 @@
 
 	/* Since buses may not be numbered yet try a little harder with bus 0 */
 	if (ret == -ENODEV) {
-		ret = uclass_first_device(UCLASS_PCI, busp);
+		ret = uclass_first_device_err(UCLASS_PCI, busp);
 		if (ret)
 			return ret;
-		else if (!*busp)
-			return -ENODEV;
 		ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
 	}
 
@@ -252,6 +250,21 @@
 	return ops->write_config(bus, bdf, offset, value, size);
 }
 
+int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
+			    u32 clr, u32 set)
+{
+	ulong val;
+	int ret;
+
+	ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
+	if (ret)
+		return ret;
+	val &= ~clr;
+	val |= set;
+
+	return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
+}
+
 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
 		     enum pci_size_t size)
 {
@@ -276,7 +289,6 @@
 				    size);
 }
 
-
 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
 {
 	return pci_write_config(bdf, offset, value, PCI_SIZE_32);
@@ -420,6 +432,48 @@
 	return 0;
 }
 
+int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
+{
+	u8 val;
+	int ret;
+
+	ret = dm_pci_read_config8(dev, offset, &val);
+	if (ret)
+		return ret;
+	val &= ~clr;
+	val |= set;
+
+	return dm_pci_write_config8(dev, offset, val);
+}
+
+int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
+{
+	u16 val;
+	int ret;
+
+	ret = dm_pci_read_config16(dev, offset, &val);
+	if (ret)
+		return ret;
+	val &= ~clr;
+	val |= set;
+
+	return dm_pci_write_config16(dev, offset, val);
+}
+
+int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
+{
+	u32 val;
+	int ret;
+
+	ret = dm_pci_read_config32(dev, offset, &val);
+	if (ret)
+		return ret;
+	val &= ~clr;
+	val |= set;
+
+	return dm_pci_write_config32(dev, offset, val);
+}
+
 static void set_vga_bridge_bits(struct udevice *dev)
 {
 	struct udevice *parent = dev->parent;
diff --git a/drivers/pci/pci_auto_common.c b/drivers/pci/pci_auto_common.c
index 85c419e..677f094 100644
--- a/drivers/pci/pci_auto_common.c
+++ b/drivers/pci/pci_auto_common.c
@@ -62,6 +62,17 @@
 	return -1;
 }
 
+static void pciauto_show_region(const char *name, struct pci_region *region)
+{
+	pciauto_region_init(region);
+	debug("PCI Autoconfig: Bus %s region: [%llx-%llx],\n"
+	      "\t\tPhysical Memory [%llx-%llxx]\n", name,
+	      (unsigned long long)region->bus_start,
+	      (unsigned long long)(region->bus_start + region->size - 1),
+	      (unsigned long long)region->phys_start,
+	      (unsigned long long)(region->phys_start + region->size - 1));
+}
+
 void pciauto_config_init(struct pci_controller *hose)
 {
 	int i;
@@ -90,39 +101,11 @@
 		}
 	}
 
-
-	if (hose->pci_mem) {
-		pciauto_region_init(hose->pci_mem);
-
-		debug("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
-		       "\t\tPhysical Memory [%llx-%llxx]\n",
-		    (u64)hose->pci_mem->bus_start,
-		    (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
-		    (u64)hose->pci_mem->phys_start,
-		    (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
-	}
-
-	if (hose->pci_prefetch) {
-		pciauto_region_init(hose->pci_prefetch);
-
-		debug("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
-		       "\t\tPhysical Memory [%llx-%llx]\n",
-		    (u64)hose->pci_prefetch->bus_start,
-		    (u64)(hose->pci_prefetch->bus_start +
-			    hose->pci_prefetch->size - 1),
-		    (u64)hose->pci_prefetch->phys_start,
-		    (u64)(hose->pci_prefetch->phys_start +
-			    hose->pci_prefetch->size - 1));
-	}
 
-	if (hose->pci_io) {
-		pciauto_region_init(hose->pci_io);
-
-		debug("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
-		       "\t\tPhysical Memory: [%llx-%llx]\n",
-		    (u64)hose->pci_io->bus_start,
-		    (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
-		    (u64)hose->pci_io->phys_start,
-		    (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
-	}
+	if (hose->pci_mem)
+		pciauto_show_region("Memory", hose->pci_mem);
+	if (hose->pci_prefetch)
+		pciauto_show_region("Prefetchable Mem", hose->pci_prefetch);
+	if (hose->pci_io)
+		pciauto_show_region("I/O", hose->pci_io);
 }
diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c
index 9fe07f2..4434e36 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -325,7 +325,7 @@
 	if (ret)
 		return ret;
 	for (uclass_first_device(UCLASS_REGULATOR, &dev);
-	     dev && !ret;
+	     dev;
 	     uclass_next_device(&dev)) {
 		ret = regulator_autoset(dev);
 		if (ret == -EMEDIUMTYPE) {
diff --git a/drivers/power/twl6030.c b/drivers/power/twl6030.c
index a1c6663..05c79be 100644
--- a/drivers/power/twl6030.c
+++ b/drivers/power/twl6030.c
@@ -5,7 +5,6 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <config.h>
-#ifdef CONFIG_TWL6030_POWER
 
 #include <twl6030.h>
 
@@ -29,6 +28,7 @@
 	.vbat_shift	= TWL6032_VBAT_SHIFT,
 };
 
+
 static int twl6030_gpadc_read_channel(u8 channel_no)
 {
 	u8 lsb = 0;
@@ -72,6 +72,13 @@
 	return 0;
 }
 
+void twl6030_power_off(void)
+{
+	twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_PHOENIX_DEV_ON,
+		TWL6030_PHOENIX_APP_DEVOFF | TWL6030_PHOENIX_CON_DEVOFF |
+		TWL6030_PHOENIX_MOD_DEVOFF);
+}
+
 void twl6030_stop_usb_charging(void)
 {
 	twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CONTROLLER_CTRL1, 0);
@@ -212,24 +219,53 @@
 	return;
 }
 
-void twl6030_power_mmc_init()
+void twl6030_power_mmc_init(int dev_index)
 {
-	/* set voltage to 3.0 and turnon for APP */
-	twl6030_i2c_write_u8(TWL6030_CHIP_PM, VMMC_CFG_VOLTATE, 0x15);
-	twl6030_i2c_write_u8(TWL6030_CHIP_PM, VMMC_CFG_STATE, 0x21);
+	u8 value = 0;
+
+	if (dev_index == 0) {
+		/* 3.0V voltage output for VMMC */
+		twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_VMMC_CFG_VOLTAGE,
+			TWL6030_CFG_VOLTAGE_30);
+
+		/* Enable P1 output for VMMC */
+		twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_VMMC_CFG_STATE,
+			TWL6030_CFG_STATE_P1 | TWL6030_CFG_STATE_ON);
+
+		twl6030_i2c_read_u8(TWL6030_CHIP_PM, TWL6030_PH_STS_BOOT, &value);
+	} else if (dev_index == 1) {
+		/* BOOT2 indicates 1.8V/2.8V VAUX1 for eMMC */
+		if (value & TWL6030_PH_STS_BOOT2) {
+			/* 1.8V voltage output for VAUX1 */
+			twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_VAUX1_CFG_VOLTAGE,
+				TWL6030_CFG_VOLTAGE_18);
+		} else {
+			/* 2.8V voltage output for VAUX1 */
+			twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_VAUX1_CFG_VOLTAGE,
+				TWL6030_CFG_VOLTAGE_28);
+		}
+
+		/* Enable P1 output for VAUX */
+		twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_VAUX1_CFG_STATE,
+			TWL6030_CFG_STATE_P1 | TWL6030_CFG_STATE_ON);
+	}
 }
 
 void twl6030_usb_device_settings()
 {
-	u8 data = 0;
+	u8 value = 0;
 
-	/* Select APP Group and set state to ON */
-	twl6030_i2c_write_u8(TWL6030_CHIP_PM, VUSB_CFG_STATE, 0x21);
+	/* 3.3V voltage output for VUSB */
+	twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_VUSB_CFG_VOLTAGE,
+		TWL6030_CFG_VOLTAGE_33);
 
-	twl6030_i2c_read_u8(TWL6030_CHIP_PM, MISC2, &data);
-	data |= 0x10;
+	/* Enable P1 output for VUSB */
+	twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_VUSB_CFG_STATE,
+		TWL6030_CFG_STATE_P1 | TWL6030_CFG_STATE_ON);
 
-	/* Select the input supply for VBUS regulator */
-	twl6030_i2c_write_u8(TWL6030_CHIP_PM, MISC2, data);
+	/* Select the input supply for VUSB regulator */
+	twl6030_i2c_read_u8(TWL6030_CHIP_PM, TWL6030_MISC2, &value);
+	value |= TWL6030_MISC2_VUSB_IN_VSYS;
+	value &= ~TWL6030_MISC2_VUSB_IN_PMID;
+	twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_MISC2, value);
 }
-#endif
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index 437224b..d0b76be 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -21,4 +21,14 @@
 	help
 	  Say 'y' here to add support for test processor which does dummy
 	  operations for sandbox platform.
+
+config REMOTEPROC_TI_POWER
+	bool "Support for TI Power processor"
+	select REMOTEPROC
+	depends on DM
+	depends on ARCH_KEYSTONE
+	depends on OF_CONTROL
+	help
+	  Say 'y' here to add support for TI power processors such as those
+	  found on certain TI keystone and OMAP generation SoCs.
 endmenu
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index 720aa6e..65fc061 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -8,3 +8,4 @@
 
 # Remote proc drivers - Please keep this list alphabetically sorted.
 obj-$(CONFIG_REMOTEPROC_SANDBOX) += sandbox_testproc.o
+obj-$(CONFIG_REMOTEPROC_TI_POWER) += ti_power_proc.o
diff --git a/drivers/remoteproc/ti_power_proc.c b/drivers/remoteproc/ti_power_proc.c
new file mode 100644
index 0000000..76ac3be
--- /dev/null
+++ b/drivers/remoteproc/ti_power_proc.c
@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2015-2016
+ * Texas Instruments Incorporated - http://www.ti.com/
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#define pr_fmt(fmt) "%s: " fmt, __func__
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <remoteproc.h>
+#include <mach/psc_defs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * struct ti_powerproc_privdata - power processor private data
+ * @loadaddr:	base address for loading the power processor
+ * @psc_module:	psc module address.
+ */
+struct ti_powerproc_privdata {
+	phys_addr_t loadaddr;
+	u32 psc_module;
+};
+
+/**
+ * ti_of_to_priv() - generate private data from device tree
+ * @dev:	corresponding ti remote processor device
+ * @priv:	pointer to driver specific private data
+ *
+ * Return: 0 if all went ok, else corresponding -ve error
+ */
+static int ti_of_to_priv(struct udevice *dev,
+			 struct ti_powerproc_privdata *priv)
+{
+	int node = dev->of_offset;
+	const void *blob = gd->fdt_blob;
+	int tmp;
+
+	if (!blob) {
+		debug("'%s' no dt?\n", dev->name);
+		return -EINVAL;
+	}
+
+	priv->loadaddr = fdtdec_get_addr(blob, node, "reg");
+	if (priv->loadaddr == FDT_ADDR_T_NONE) {
+		debug("'%s': no 'reg' property\n", dev->name);
+		return -EINVAL;
+	}
+
+	tmp = fdtdec_get_int(blob, node, "ti,lpsc_module", -EINVAL);
+	if (tmp < 0) {
+		debug("'%s': no 'ti,lpsc_module' property\n", dev->name);
+		return tmp;
+	}
+	priv->psc_module = tmp;
+
+	return 0;
+}
+
+/**
+ * ti_powerproc_probe() - Basic probe
+ * @dev:	corresponding ti remote processor device
+ *
+ * Return: 0 if all went ok, else corresponding -ve error
+ */
+static int ti_powerproc_probe(struct udevice *dev)
+{
+	struct dm_rproc_uclass_pdata *uc_pdata;
+	struct ti_powerproc_privdata *priv;
+	int ret;
+
+	uc_pdata = dev_get_uclass_platdata(dev);
+	priv = dev_get_priv(dev);
+
+	ret = ti_of_to_priv(dev, priv);
+
+	debug("%s probed with slave_addr=0x%08lX module=%d(%d)\n",
+	      uc_pdata->name, priv->loadaddr, priv->psc_module, ret);
+
+	return ret;
+}
+
+/**
+ * ti_powerproc_load() - Loadup the TI remote processor
+ * @dev:	corresponding ti remote processor device
+ * @addr:	Address in memory where image binary is stored
+ * @size:	Size in bytes of the image binary
+ *
+ * Return: 0 if all went ok, else corresponding -ve error
+ */
+static int ti_powerproc_load(struct udevice *dev, ulong addr, ulong size)
+{
+	struct dm_rproc_uclass_pdata *uc_pdata;
+	struct ti_powerproc_privdata *priv;
+	int ret;
+
+	uc_pdata = dev_get_uclass_platdata(dev);
+	if (!uc_pdata) {
+		debug("%s: no uc pdata!\n", dev->name);
+		return -EINVAL;
+	}
+
+	priv = dev_get_priv(dev);
+	ret = psc_module_keep_in_reset_enabled(priv->psc_module, false);
+	if (ret) {
+		debug("%s Unable to disable module '%d'(ret=%d)\n",
+		      uc_pdata->name, priv->psc_module, ret);
+		return ret;
+	}
+
+	debug("%s: Loading binary from 0x%08lX, size 0x%08lX to 0x%08lX\n",
+	      uc_pdata->name, addr, size, priv->loadaddr);
+
+	memcpy((void *)priv->loadaddr, (void *)addr, size);
+
+	debug("%s: Complete!\n", uc_pdata->name);
+	return 0;
+}
+
+/**
+ * ti_powerproc_start() - (replace: short desc)
+ * @dev:	corresponding ti remote processor device
+ *
+ * Return: 0 if all went ok, else corresponding -ve error
+ */
+static int ti_powerproc_start(struct udevice *dev)
+{
+	struct dm_rproc_uclass_pdata *uc_pdata;
+	struct ti_powerproc_privdata *priv;
+	int ret;
+
+	uc_pdata = dev_get_uclass_platdata(dev);
+	if (!uc_pdata) {
+		debug("%s: no uc pdata!\n", dev->name);
+		return -EINVAL;
+	}
+
+	priv = dev_get_priv(dev);
+	ret = psc_disable_module(priv->psc_module);
+	if (ret) {
+		debug("%s Unable to disable module '%d'(ret=%d)\n",
+		      uc_pdata->name, priv->psc_module, ret);
+		return ret;
+	}
+
+	ret = psc_module_release_from_reset(priv->psc_module);
+	if (ret) {
+		debug("%s Failed to wait for module '%d'(ret=%d)\n",
+		      uc_pdata->name, priv->psc_module, ret);
+		return ret;
+	}
+	ret = psc_enable_module(priv->psc_module);
+	if (ret) {
+		debug("%s Unable to disable module '%d'(ret=%d)\n",
+		      uc_pdata->name, priv->psc_module, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct dm_rproc_ops ti_powerproc_ops = {
+	.load = ti_powerproc_load,
+	.start = ti_powerproc_start,
+};
+
+static const struct udevice_id ti_powerproc_ids[] = {
+	{.compatible = "ti,power-processor"},
+	{}
+};
+
+U_BOOT_DRIVER(ti_powerproc) = {
+	.name = "ti_power_proc",
+	.of_match = ti_powerproc_ids,
+	.id = UCLASS_REMOTEPROC,
+	.ops = &ti_powerproc_ops,
+	.probe = ti_powerproc_probe,
+	.priv_auto_alloc_size = sizeof(struct ti_powerproc_privdata),
+};
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 93dad33..28da9dd 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -105,7 +105,7 @@
 	 * As far as we know it doesn't make sense to support selection of
 	 * these options at run-time, so use the existing CONFIG options.
 	 */
-	serial_out_shift(addr, plat->reg_shift, value);
+	serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value);
 }
 
 static int ns16550_readb(NS16550_t port, int offset)
@@ -116,7 +116,7 @@
 	offset *= 1 << plat->reg_shift;
 	addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset;
 
-	return serial_in_shift(addr, plat->reg_shift);
+	return serial_in_shift(addr + plat->reg_offset, plat->reg_shift);
 }
 
 /* We can clean these up once everything is moved to driver model */
@@ -401,6 +401,8 @@
 		return -EINVAL;
 
 	plat->base = addr;
+	plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+				     "reg-offset", 0);
 	plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
 					 "reg-shift", 0);
 	plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 1c447ff..0ce5c44 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -115,7 +115,7 @@
 /* Called after relocation */
 void serial_initialize(void)
 {
-	serial_find_console_or_panic();
+	serial_init();
 }
 
 static void _serial_putc(struct udevice *dev, char ch)
@@ -123,11 +123,12 @@
 	struct dm_serial_ops *ops = serial_get_ops(dev);
 	int err;
 
+	if (ch == '\n')
+		_serial_putc(dev, '\r');
+
 	do {
 		err = ops->putc(dev, ch);
 	} while (err == -EAGAIN);
-	if (ch == '\n')
-		_serial_putc(dev, '\r');
 }
 
 static void _serial_puts(struct udevice *dev, const char *str)
diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c
index 7dbb49f..6292eb1 100644
--- a/drivers/serial/serial_arc.c
+++ b/drivers/serial/serial_arc.c
@@ -68,9 +68,6 @@
 	struct arc_serial_platdata *plat = dev->platdata;
 	struct arc_serial_regs *const regs = plat->reg;
 
-	if (c == '\n')
-		arc_serial_putc(dev, '\r');
-
 	while (!(readb(&regs->status) & UART_TXEMPTY))
 		;
 
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index fc3321f..042e9a2 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -77,9 +77,6 @@
 
 static void _lpuart_serial_putc(struct lpuart_fsl *base, const char c)
 {
-	if (c == '\n')
-		_lpuart_serial_putc(base, '\r');
-
 	while (!(__raw_readb(&base->us1) & US1_TDRE))
 		WATCHDOG_RESET();
 
@@ -198,9 +195,6 @@
 
 static void _lpuart32_serial_putc(struct lpuart_fsl *base, const char c)
 {
-	if (c == '\n')
-		_lpuart32_serial_putc(base, '\r');
-
 	while (!(in_be32(&base->stat) & STAT_TDRE))
 		WATCHDOG_RESET();
 
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 51485c0..1563bb3 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -164,15 +164,15 @@
 
 static void mxc_serial_putc(const char c)
 {
+	/* If \n, also do \r */
+	if (c == '\n')
+		serial_putc('\r');
+
 	__REG(UART_PHYS + UTXD) = c;
 
 	/* wait for transmitter to be ready */
 	while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
 		WATCHDOG_RESET();
-
-	/* If \n, also do \r */
-	if (c == '\n')
-		serial_putc ('\r');
 }
 
 /*
diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c
index 8fbcc10..1eb19ec 100644
--- a/drivers/serial/serial_pxa.c
+++ b/drivers/serial/serial_pxa.c
@@ -156,6 +156,10 @@
 {
 	struct pxa_uart_regs *uart_regs;
 
+	/* If \n, also do \r */
+	if (c == '\n')
+		pxa_putc_dev(uart_index, '\r');
+
 	uart_regs = pxa_uart_index_to_regs(uart_index);
 	if (!uart_regs)
 		hang();
@@ -163,10 +167,6 @@
 	while (!(readl(&uart_regs->lsr) & LSR_TEMT))
 		WATCHDOG_RESET();
 	writel(c, &uart_regs->thr);
-
-	/* If \n, also do \r */
-	if (c == '\n')
-		pxa_putc_dev (uart_index,'\r');
 }
 
 /*
diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c
index d4e7df2..0f0878a 100644
--- a/drivers/serial/serial_s3c24x0.c
+++ b/drivers/serial/serial_s3c24x0.c
@@ -135,14 +135,14 @@
 {
 	struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
 
+	/* If \n, also do \r */
+	if (c == '\n')
+		serial_putc('\r');
+
 	while (!(readl(&uart->utrstat) & 0x2))
 		/* wait for room in the tx FIFO */ ;
 
 	writeb(c, &uart->utxh);
-
-	/* If \n, also do \r */
-	if (c == '\n')
-		serial_putc('\r');
 }
 
 static inline void serial_putc_dev(unsigned int dev_index, const char c)
diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c
index 75f0ec3..2e19813 100644
--- a/drivers/serial/usbtty.c
+++ b/drivers/serial/usbtty.c
@@ -434,11 +434,12 @@
 	if (!usbtty_configured ())
 		return;
 
-	buf_push (&usbtty_output, &c, 1);
 	/* If \n, also do \r */
 	if (c == '\n')
 		buf_push (&usbtty_output, "\r", 1);
 
+	buf_push(&usbtty_output, &c, 1);
+
 	/* Poll at end to handle new data... */
 	if ((usbtty_output.size + 2) >= usbtty_output.totalsize) {
 		usbtty_poll ();
@@ -498,8 +499,8 @@
 		n = next_nl_pos (str);
 
 		if (str[n] == '\n') {
-			__usbtty_puts (str, n + 1);
-			__usbtty_puts ("\r", 1);
+			__usbtty_puts("\r", 1);
+			__usbtty_puts(str, n + 1);
 			str += (n + 1);
 			len -= (n + 1);
 		} else {
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2cdb110..f0258f8 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -155,6 +155,13 @@
 	  Zynq QSPI IP core. This IP is used to connect the flash in
 	  4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
 
+config OMAP3_SPI
+	bool "McSPI driver for OMAP"
+	help
+	  SPI master controller for OMAP24XX and later Multichannel SPI
+	  (McSPI). This driver be used to access SPI chips on platforms
+	  embedding this OMAP3 McSPI IP core.
+
 endif # if DM_SPI
 
 config FSL_ESPI
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 95cdfa3..2fe34c9 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -1,4 +1,7 @@
 /*
+ * Copyright (C) 2016 Jagan Teki <jteki@openedev.com>
+ *		      Christophe Ricard <christophe.ricard@gmail.com>
+ *
  * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
  *
  * Driver for McSPI controller on OMAP3. Based on davinci_spi.c
@@ -15,307 +18,211 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <spi.h>
 #include <malloc.h>
 #include <asm/io.h>
-#include "omap3_spi.h"
-
-#define SPI_WAIT_TIMEOUT 10
-
-static void spi_reset(struct omap3_spi_slave *ds)
-{
-	unsigned int tmp;
 
-	writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &ds->regs->sysconfig);
-	do {
-		tmp = readl(&ds->regs->sysstatus);
-	} while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE));
-
-	writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE |
-				 OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP |
-				 OMAP3_MCSPI_SYSCONFIG_SMARTIDLE,
-				 &ds->regs->sysconfig);
-
-	writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &ds->regs->wakeupenable);
-}
-
-static void omap3_spi_write_chconf(struct omap3_spi_slave *ds, int val)
-{
-	writel(val, &ds->regs->channel[ds->slave.cs].chconf);
-	/* Flash post writes to make immediate effect */
-	readl(&ds->regs->channel[ds->slave.cs].chconf);
-}
-
-static void omap3_spi_set_enable(struct omap3_spi_slave *ds, int enable)
-{
-	writel(enable, &ds->regs->channel[ds->slave.cs].chctrl);
-	/* Flash post writes to make immediate effect */
-	readl(&ds->regs->channel[ds->slave.cs].chctrl);
-}
+DECLARE_GLOBAL_DATA_PTR;
 
-void spi_init()
-{
-	/* do nothing */
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-				  unsigned int max_hz, unsigned int mode)
-{
-	struct omap3_spi_slave	*ds;
-	struct mcspi *regs;
-
-	/*
-	 * OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules)
-	 * with different number of chip selects (CS, channels):
-	 * McSPI1 has 4 CS (bus 0, cs 0 - 3)
-	 * McSPI2 has 2 CS (bus 1, cs 0 - 1)
-	 * McSPI3 has 2 CS (bus 2, cs 0 - 1)
-	 * McSPI4 has 1 CS (bus 3, cs 0)
-	 */
-
-	switch (bus) {
-	case 0:
-		regs = (struct mcspi *)OMAP3_MCSPI1_BASE;
-		break;
-#ifdef OMAP3_MCSPI2_BASE
-	case 1:
-		regs = (struct mcspi *)OMAP3_MCSPI2_BASE;
-		break;
-#endif
-#ifdef OMAP3_MCSPI3_BASE
-	case 2:
-		regs = (struct mcspi *)OMAP3_MCSPI3_BASE;
-		break;
-#endif
-#ifdef OMAP3_MCSPI4_BASE
-	case 3:
-		regs = (struct mcspi *)OMAP3_MCSPI4_BASE;
-		break;
+#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
+#define OMAP3_MCSPI1_BASE	0x48030100
+#define OMAP3_MCSPI2_BASE	0x481A0100
+#else
+#define OMAP3_MCSPI1_BASE	0x48098000
+#define OMAP3_MCSPI2_BASE	0x4809A000
+#define OMAP3_MCSPI3_BASE	0x480B8000
+#define OMAP3_MCSPI4_BASE	0x480BA000
 #endif
-	default:
-		printf("SPI error: unsupported bus %i. \
-			Supported busses 0 - 3\n", bus);
-		return NULL;
-	}
 
-	if (((bus == 0) && (cs > 3)) ||
-			((bus == 1) && (cs > 1)) ||
-			((bus == 2) && (cs > 1)) ||
-			((bus == 3) && (cs > 0))) {
-		printf("SPI error: unsupported chip select %i \
-			on bus %i\n", cs, bus);
-		return NULL;
-	}
+/* per-register bitmasks */
+#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
+#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
+#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE	BIT(0)
+#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
 
-	if (max_hz > OMAP3_MCSPI_MAX_FREQ) {
-		printf("SPI error: unsupported frequency %i Hz. \
-			Max frequency is 48 Mhz\n", max_hz);
-		return NULL;
-	}
+#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
 
-	if (mode > SPI_MODE_3) {
-		printf("SPI error: unsupported SPI mode %i\n", mode);
-		return NULL;
-	}
+#define OMAP3_MCSPI_MODULCTRL_SINGLE	BIT(0)
+#define OMAP3_MCSPI_MODULCTRL_MS	BIT(2)
+#define OMAP3_MCSPI_MODULCTRL_STEST	BIT(3)
 
-	ds = spi_alloc_slave(struct omap3_spi_slave, bus, cs);
-	if (!ds) {
-		printf("SPI error: malloc of SPI structure failed\n");
-		return NULL;
-	}
+#define OMAP3_MCSPI_CHCONF_PHA		BIT(0)
+#define OMAP3_MCSPI_CHCONF_POL		BIT(1)
+#define OMAP3_MCSPI_CHCONF_CLKD_MASK	GENMASK(5, 2)
+#define OMAP3_MCSPI_CHCONF_EPOL		BIT(6)
+#define OMAP3_MCSPI_CHCONF_WL_MASK	GENMASK(11, 7)
+#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY	BIT(12)
+#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY	BIT(13)
+#define OMAP3_MCSPI_CHCONF_TRM_MASK	GENMASK(13, 12)
+#define OMAP3_MCSPI_CHCONF_DMAW		BIT(14)
+#define OMAP3_MCSPI_CHCONF_DMAR		BIT(15)
+#define OMAP3_MCSPI_CHCONF_DPE0		BIT(16)
+#define OMAP3_MCSPI_CHCONF_DPE1		BIT(17)
+#define OMAP3_MCSPI_CHCONF_IS		BIT(18)
+#define OMAP3_MCSPI_CHCONF_TURBO	BIT(19)
+#define OMAP3_MCSPI_CHCONF_FORCE	BIT(20)
 
-	ds->regs = regs;
-	ds->freq = max_hz;
-	ds->mode = mode;
+#define OMAP3_MCSPI_CHSTAT_RXS		BIT(0)
+#define OMAP3_MCSPI_CHSTAT_TXS		BIT(1)
+#define OMAP3_MCSPI_CHSTAT_EOT		BIT(2)
 
-	return &ds->slave;
-}
+#define OMAP3_MCSPI_CHCTRL_EN		BIT(0)
+#define OMAP3_MCSPI_CHCTRL_DIS		(0 << 0)
 
-void spi_free_slave(struct spi_slave *slave)
-{
-	struct omap3_spi_slave *ds = to_omap3_spi(slave);
+#define OMAP3_MCSPI_WAKEUPENABLE_WKEN	BIT(0)
+#define MCSPI_PINDIR_D0_IN_D1_OUT	0
+#define MCSPI_PINDIR_D0_OUT_D1_IN	1
 
-	free(ds);
-}
+#define OMAP3_MCSPI_MAX_FREQ		48000000
+#define SPI_WAIT_TIMEOUT		10
 
-int spi_claim_bus(struct spi_slave *slave)
-{
-	struct omap3_spi_slave *ds = to_omap3_spi(slave);
-	unsigned int conf, div = 0;
+/* OMAP3 McSPI registers */
+struct mcspi_channel {
+	unsigned int chconf;		/* 0x2C, 0x40, 0x54, 0x68 */
+	unsigned int chstat;		/* 0x30, 0x44, 0x58, 0x6C */
+	unsigned int chctrl;		/* 0x34, 0x48, 0x5C, 0x70 */
+	unsigned int tx;		/* 0x38, 0x4C, 0x60, 0x74 */
+	unsigned int rx;		/* 0x3C, 0x50, 0x64, 0x78 */
+};
 
-	/* McSPI global module configuration */
+struct mcspi {
+	unsigned char res1[0x10];
+	unsigned int sysconfig;		/* 0x10 */
+	unsigned int sysstatus;		/* 0x14 */
+	unsigned int irqstatus;		/* 0x18 */
+	unsigned int irqenable;		/* 0x1C */
+	unsigned int wakeupenable;	/* 0x20 */
+	unsigned int syst;		/* 0x24 */
+	unsigned int modulctrl;		/* 0x28 */
+	struct mcspi_channel channel[4];
+	/* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
+	/* channel1: 0x40 - 0x50, bus 0 & 1 */
+	/* channel2: 0x54 - 0x64, bus 0 & 1 */
+	/* channel3: 0x68 - 0x78, bus 0 */
+};
 
-	/*
-	 * setup when switching from (reset default) slave mode
-	 * to single-channel master mode
-	 */
-	spi_reset(ds);
-	conf = readl(&ds->regs->modulctrl);
-	conf &= ~(OMAP3_MCSPI_MODULCTRL_STEST | OMAP3_MCSPI_MODULCTRL_MS);
-	conf |= OMAP3_MCSPI_MODULCTRL_SINGLE;
-	writel(conf, &ds->regs->modulctrl);
-
-	/* McSPI individual channel configuration */
-
-	/* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
-	if (ds->freq) {
-		while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
-					 > ds->freq)
-			div++;
-	} else
-		div = 0xC;
-
-	conf = readl(&ds->regs->channel[ds->slave.cs].chconf);
-
-	/* standard 4-wire master mode:	SCK, MOSI/out, MISO/in, nCS
-	 * REVISIT: this controller could support SPI_3WIRE mode.
-	 */
-#ifdef CONFIG_OMAP3_SPI_D0_D1_SWAPPED
-	/*
-	 * Some boards have D0 wired as MOSI / D1 as MISO instead of
-	 * The normal D0 as MISO / D1 as MOSI.
-	 */
-	conf &= ~OMAP3_MCSPI_CHCONF_DPE0;
-	conf |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
-#else
-	conf &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
-	conf |= OMAP3_MCSPI_CHCONF_DPE0;
+struct omap3_spi_priv {
+#ifndef CONFIG_DM_SPI
+	struct spi_slave slave;
 #endif
-
-	/* wordlength */
-	conf &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
-	conf |= (ds->slave.wordlen - 1) << 7;
-
-	/* set chipselect polarity; manage with FORCE */
-	if (!(ds->mode & SPI_CS_HIGH))
-		conf |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */
-	else
-		conf &= ~OMAP3_MCSPI_CHCONF_EPOL;
-
-	/* set clock divisor */
-	conf &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
-	conf |= div << 2;
-
-	/* set SPI mode 0..3 */
-	if (ds->mode & SPI_CPOL)
-		conf |= OMAP3_MCSPI_CHCONF_POL;
-	else
-		conf &= ~OMAP3_MCSPI_CHCONF_POL;
-	if (ds->mode & SPI_CPHA)
-		conf |= OMAP3_MCSPI_CHCONF_PHA;
-	else
-		conf &= ~OMAP3_MCSPI_CHCONF_PHA;
-
-	/* Transmit & receive mode */
-	conf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
-
-	omap3_spi_write_chconf(ds,conf);
+	struct mcspi *regs;
+	unsigned int cs;
+	unsigned int freq;
+	unsigned int mode;
+	unsigned int wordlen;
+	unsigned int pin_dir:1;
+};
 
-	return 0;
+static void omap3_spi_write_chconf(struct omap3_spi_priv *priv, int val)
+{
+	writel(val, &priv->regs->channel[priv->cs].chconf);
+	/* Flash post writes to make immediate effect */
+	readl(&priv->regs->channel[priv->cs].chconf);
 }
 
-void spi_release_bus(struct spi_slave *slave)
+static void omap3_spi_set_enable(struct omap3_spi_priv *priv, int enable)
 {
-	struct omap3_spi_slave *ds = to_omap3_spi(slave);
-
-	/* Reset the SPI hardware */
-	spi_reset(ds);
+	writel(enable, &priv->regs->channel[priv->cs].chctrl);
+	/* Flash post writes to make immediate effect */
+	readl(&priv->regs->channel[priv->cs].chctrl);
 }
 
-int omap3_spi_write(struct spi_slave *slave, unsigned int len, const void *txp,
-		    unsigned long flags)
+static int omap3_spi_write(struct omap3_spi_priv *priv, unsigned int len,
+			   const void *txp, unsigned long flags)
 {
-	struct omap3_spi_slave *ds = to_omap3_spi(slave);
-	int i;
 	ulong start;
-	int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
+	int i, chconf;
+
+	chconf = readl(&priv->regs->channel[priv->cs].chconf);
 
 	/* Enable the channel */
-	omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
+	omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
 
 	chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
-	chconf |= (ds->slave.wordlen - 1) << 7;
+	chconf |= (priv->wordlen - 1) << 7;
 	chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY;
 	chconf |= OMAP3_MCSPI_CHCONF_FORCE;
-	omap3_spi_write_chconf(ds,chconf);
+	omap3_spi_write_chconf(priv, chconf);
 
 	for (i = 0; i < len; i++) {
 		/* wait till TX register is empty (TXS == 1) */
 		start = get_timer(0);
-		while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
+		while (!(readl(&priv->regs->channel[priv->cs].chstat) &
 			 OMAP3_MCSPI_CHSTAT_TXS)) {
 			if (get_timer(start) > SPI_WAIT_TIMEOUT) {
 				printf("SPI TXS timed out, status=0x%08x\n",
-				       readl(&ds->regs->channel[ds->slave.cs].chstat));
+					readl(&priv->regs->channel[priv->cs].chstat));
 				return -1;
 			}
 		}
 		/* Write the data */
-		unsigned int *tx = &ds->regs->channel[ds->slave.cs].tx;
-		if (ds->slave.wordlen > 16)
+		unsigned int *tx = &priv->regs->channel[priv->cs].tx;
+		if (priv->wordlen > 16)
 			writel(((u32 *)txp)[i], tx);
-		else if (ds->slave.wordlen > 8)
+		else if (priv->wordlen > 8)
 			writel(((u16 *)txp)[i], tx);
 		else
 			writel(((u8 *)txp)[i], tx);
 	}
 
 	/* wait to finish of transfer */
-	while ((readl(&ds->regs->channel[ds->slave.cs].chstat) &
-			 (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) !=
-			 (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS));
+	while ((readl(&priv->regs->channel[priv->cs].chstat) &
+			(OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) !=
+			(OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS))
+		;
 
 	/* Disable the channel otherwise the next immediate RX will get affected */
-	omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
+	omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
 
 	if (flags & SPI_XFER_END) {
 
 		chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
-		omap3_spi_write_chconf(ds,chconf);
+		omap3_spi_write_chconf(priv, chconf);
 	}
 	return 0;
 }
 
-int omap3_spi_read(struct spi_slave *slave, unsigned int len, void *rxp,
-		   unsigned long flags)
+static int omap3_spi_read(struct omap3_spi_priv *priv, unsigned int len,
+			  void *rxp, unsigned long flags)
 {
-	struct omap3_spi_slave *ds = to_omap3_spi(slave);
-	int i;
+	int i, chconf;
 	ulong start;
-	int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
+
+	chconf = readl(&priv->regs->channel[priv->cs].chconf);
 
 	/* Enable the channel */
-	omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
+	omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
 
 	chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
-	chconf |= (ds->slave.wordlen - 1) << 7;
+	chconf |= (priv->wordlen - 1) << 7;
 	chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY;
 	chconf |= OMAP3_MCSPI_CHCONF_FORCE;
-	omap3_spi_write_chconf(ds,chconf);
+	omap3_spi_write_chconf(priv, chconf);
 
-	writel(0, &ds->regs->channel[ds->slave.cs].tx);
+	writel(0, &priv->regs->channel[priv->cs].tx);
 
 	for (i = 0; i < len; i++) {
 		start = get_timer(0);
 		/* Wait till RX register contains data (RXS == 1) */
-		while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
+		while (!(readl(&priv->regs->channel[priv->cs].chstat) &
 			 OMAP3_MCSPI_CHSTAT_RXS)) {
 			if (get_timer(start) > SPI_WAIT_TIMEOUT) {
 				printf("SPI RXS timed out, status=0x%08x\n",
-				       readl(&ds->regs->channel[ds->slave.cs].chstat));
+					readl(&priv->regs->channel[priv->cs].chstat));
 				return -1;
 			}
 		}
 
 		/* Disable the channel to prevent furher receiving */
-		if(i == (len - 1))
-			omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
+		if (i == (len - 1))
+			omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
 
 		/* Read the data */
-		unsigned int *rx = &ds->regs->channel[ds->slave.cs].rx;
-		if (ds->slave.wordlen > 16)
+		unsigned int *rx = &priv->regs->channel[priv->cs].rx;
+		if (priv->wordlen > 16)
 			((u32 *)rxp)[i] = readl(rx);
-		else if (ds->slave.wordlen > 8)
+		else if (priv->wordlen > 8)
 			((u16 *)rxp)[i] = (u16)readl(rx);
 		else
 			((u8 *)rxp)[i] = (u8)readl(rx);
@@ -323,133 +230,451 @@
 
 	if (flags & SPI_XFER_END) {
 		chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
-		omap3_spi_write_chconf(ds,chconf);
+		omap3_spi_write_chconf(priv, chconf);
 	}
 
 	return 0;
 }
 
 /*McSPI Transmit Receive Mode*/
-int omap3_spi_txrx(struct spi_slave *slave, unsigned int len,
-		   const void *txp, void *rxp, unsigned long flags)
+static int omap3_spi_txrx(struct omap3_spi_priv *priv, unsigned int len,
+			  const void *txp, void *rxp, unsigned long flags)
 {
-	struct omap3_spi_slave *ds = to_omap3_spi(slave);
 	ulong start;
-	int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
-	int i=0;
+	int chconf, i = 0;
+
+	chconf = readl(&priv->regs->channel[priv->cs].chconf);
 
 	/*Enable SPI channel*/
-	omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
+	omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
 
 	/*set TRANSMIT-RECEIVE Mode*/
 	chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
-	chconf |= (ds->slave.wordlen - 1) << 7;
+	chconf |= (priv->wordlen - 1) << 7;
 	chconf |= OMAP3_MCSPI_CHCONF_FORCE;
-	omap3_spi_write_chconf(ds,chconf);
+	omap3_spi_write_chconf(priv, chconf);
 
 	/*Shift in and out 1 byte at time*/
 	for (i=0; i < len; i++){
 		/* Write: wait for TX empty (TXS == 1)*/
 		start = get_timer(0);
-		while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
+		while (!(readl(&priv->regs->channel[priv->cs].chstat) &
 			 OMAP3_MCSPI_CHSTAT_TXS)) {
 			if (get_timer(start) > SPI_WAIT_TIMEOUT) {
 				printf("SPI TXS timed out, status=0x%08x\n",
-				       readl(&ds->regs->channel[ds->slave.cs].chstat));
+					readl(&priv->regs->channel[priv->cs].chstat));
 				return -1;
 			}
 		}
 		/* Write the data */
-		unsigned int *tx = &ds->regs->channel[ds->slave.cs].tx;
-		if (ds->slave.wordlen > 16)
+		unsigned int *tx = &priv->regs->channel[priv->cs].tx;
+		if (priv->wordlen > 16)
 			writel(((u32 *)txp)[i], tx);
-		else if (ds->slave.wordlen > 8)
+		else if (priv->wordlen > 8)
 			writel(((u16 *)txp)[i], tx);
 		else
 			writel(((u8 *)txp)[i], tx);
 
 		/*Read: wait for RX containing data (RXS == 1)*/
 		start = get_timer(0);
-		while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
+		while (!(readl(&priv->regs->channel[priv->cs].chstat) &
 			 OMAP3_MCSPI_CHSTAT_RXS)) {
 			if (get_timer(start) > SPI_WAIT_TIMEOUT) {
 				printf("SPI RXS timed out, status=0x%08x\n",
-				       readl(&ds->regs->channel[ds->slave.cs].chstat));
+					readl(&priv->regs->channel[priv->cs].chstat));
 				return -1;
 			}
 		}
 		/* Read the data */
-		unsigned int *rx = &ds->regs->channel[ds->slave.cs].rx;
-		if (ds->slave.wordlen > 16)
+		unsigned int *rx = &priv->regs->channel[priv->cs].rx;
+		if (priv->wordlen > 16)
 			((u32 *)rxp)[i] = readl(rx);
-		else if (ds->slave.wordlen > 8)
+		else if (priv->wordlen > 8)
 			((u16 *)rxp)[i] = (u16)readl(rx);
 		else
 			((u8 *)rxp)[i] = (u8)readl(rx);
 	}
 	/* Disable the channel */
-	omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
+	omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
 
 	/*if transfer must be terminated disable the channel*/
 	if (flags & SPI_XFER_END) {
 		chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
-		omap3_spi_write_chconf(ds,chconf);
+		omap3_spi_write_chconf(priv, chconf);
 	}
 
 	return 0;
 }
 
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-	     const void *dout, void *din, unsigned long flags)
+static int _spi_xfer(struct omap3_spi_priv *priv, unsigned int bitlen,
+		     const void *dout, void *din, unsigned long flags)
 {
-	struct omap3_spi_slave *ds = to_omap3_spi(slave);
 	unsigned int	len;
 	int ret = -1;
 
-	if (ds->slave.wordlen < 4 || ds->slave.wordlen > 32) {
-		printf("omap3_spi: invalid wordlen %d\n", ds->slave.wordlen);
+	if (priv->wordlen < 4 || priv->wordlen > 32) {
+		printf("omap3_spi: invalid wordlen %d\n", priv->wordlen);
 		return -1;
 	}
 
-	if (bitlen % ds->slave.wordlen)
+	if (bitlen % priv->wordlen)
 		return -1;
 
-	len = bitlen / ds->slave.wordlen;
+	len = bitlen / priv->wordlen;
 
 	if (bitlen == 0) {	 /* only change CS */
-		int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
+		int chconf = readl(&priv->regs->channel[priv->cs].chconf);
 
 		if (flags & SPI_XFER_BEGIN) {
-			omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
+			omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
 			chconf |= OMAP3_MCSPI_CHCONF_FORCE;
-			omap3_spi_write_chconf(ds,chconf);
+			omap3_spi_write_chconf(priv, chconf);
 		}
 		if (flags & SPI_XFER_END) {
 			chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
-			omap3_spi_write_chconf(ds,chconf);
-			omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
+			omap3_spi_write_chconf(priv, chconf);
+			omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
 		}
 		ret = 0;
 	} else {
 		if (dout != NULL && din != NULL)
-			ret = omap3_spi_txrx(slave, len, dout, din, flags);
+			ret = omap3_spi_txrx(priv, len, dout, din, flags);
 		else if (dout != NULL)
-			ret = omap3_spi_write(slave, len, dout, flags);
+			ret = omap3_spi_write(priv, len, dout, flags);
 		else if (din != NULL)
-			ret = omap3_spi_read(slave, len, din, flags);
+			ret = omap3_spi_read(priv, len, din, flags);
 	}
 	return ret;
 }
 
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+static void _omap3_spi_set_speed(struct omap3_spi_priv *priv)
 {
-	return 1;
+	uint32_t confr, div = 0;
+
+	confr = readl(&priv->regs->channel[priv->cs].chconf);
+
+	/* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
+	if (priv->freq) {
+		while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
+					> priv->freq)
+			div++;
+	} else {
+		 div = 0xC;
+	}
+
+	/* set clock divisor */
+	confr &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
+	confr |= div << 2;
+
+	omap3_spi_write_chconf(priv, confr);
 }
 
-void spi_cs_activate(struct spi_slave *slave)
+static void _omap3_spi_set_mode(struct omap3_spi_priv *priv)
 {
+	uint32_t confr;
+
+	confr = readl(&priv->regs->channel[priv->cs].chconf);
+
+	/* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
+	 * REVISIT: this controller could support SPI_3WIRE mode.
+	 */
+	if (priv->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
+		confr &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
+		confr |= OMAP3_MCSPI_CHCONF_DPE0;
+	} else {
+		confr &= ~OMAP3_MCSPI_CHCONF_DPE0;
+		confr |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
+	}
+
+	/* set SPI mode 0..3 */
+	confr &= ~(OMAP3_MCSPI_CHCONF_POL | OMAP3_MCSPI_CHCONF_PHA);
+	if (priv->mode & SPI_CPHA)
+		confr |= OMAP3_MCSPI_CHCONF_PHA;
+	if (priv->mode & SPI_CPOL)
+		confr |= OMAP3_MCSPI_CHCONF_POL;
+
+	/* set chipselect polarity; manage with FORCE */
+	if (!(priv->mode & SPI_CS_HIGH))
+		confr |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */
+	else
+		confr &= ~OMAP3_MCSPI_CHCONF_EPOL;
+
+	/* Transmit & receive mode */
+	confr &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
+
+	omap3_spi_write_chconf(priv, confr);
 }
 
-void spi_cs_deactivate(struct spi_slave *slave)
+static void _omap3_spi_set_wordlen(struct omap3_spi_priv *priv)
 {
+	unsigned int confr;
+
+	/* McSPI individual channel configuration */
+	confr = readl(&priv->regs->channel[priv->wordlen].chconf);
+
+	/* wordlength */
+	confr &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
+	confr |= (priv->wordlen - 1) << 7;
+
+	omap3_spi_write_chconf(priv, confr);
 }
+
+static void spi_reset(struct mcspi *regs)
+{
+	unsigned int tmp;
+
+	writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &regs->sysconfig);
+	do {
+		tmp = readl(&regs->sysstatus);
+	} while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE));
+
+	writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE |
+	       OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP |
+	       OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, &regs->sysconfig);
+
+	writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &regs->wakeupenable);
+}
+
+static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv)
+{
+	unsigned int conf;
+
+	spi_reset(priv->regs);
+
+	/*
+	 * setup when switching from (reset default) slave mode
+	 * to single-channel master mode
+	 */
+	conf = readl(&priv->regs->modulctrl);
+	conf &= ~(OMAP3_MCSPI_MODULCTRL_STEST | OMAP3_MCSPI_MODULCTRL_MS);
+	conf |= OMAP3_MCSPI_MODULCTRL_SINGLE;
+
+	writel(conf, &priv->regs->modulctrl);
+
+	_omap3_spi_set_mode(priv);
+	_omap3_spi_set_speed(priv);
+}
+
+#ifndef CONFIG_DM_SPI
+
+static inline struct omap3_spi_priv *to_omap3_spi(struct spi_slave *slave)
+{
+	return container_of(slave, struct omap3_spi_priv, slave);
+}
+
+void spi_init(void)
+{
+	/* do nothing */
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	struct omap3_spi_priv *priv = to_omap3_spi(slave);
+
+	free(priv);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	struct omap3_spi_priv *priv = to_omap3_spi(slave);
+
+	_omap3_spi_claim_bus(priv);
+	_omap3_spi_set_wordlen(priv);
+	_omap3_spi_set_mode(priv);
+	_omap3_spi_set_speed(priv);
+
+	return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+	struct omap3_spi_priv *priv = to_omap3_spi(slave);
+
+	/* Reset the SPI hardware */
+	spi_reset(priv->regs);
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+				     unsigned int max_hz, unsigned int mode)
+{
+	struct omap3_spi_priv *priv;
+	struct mcspi *regs;
+
+	/*
+	 * OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules)
+	 * with different number of chip selects (CS, channels):
+	 * McSPI1 has 4 CS (bus 0, cs 0 - 3)
+	 * McSPI2 has 2 CS (bus 1, cs 0 - 1)
+	 * McSPI3 has 2 CS (bus 2, cs 0 - 1)
+	 * McSPI4 has 1 CS (bus 3, cs 0)
+	 */
+
+	switch (bus) {
+	case 0:
+		 regs = (struct mcspi *)OMAP3_MCSPI1_BASE;
+		 break;
+#ifdef OMAP3_MCSPI2_BASE
+	case 1:
+		 regs = (struct mcspi *)OMAP3_MCSPI2_BASE;
+		 break;
+#endif
+#ifdef OMAP3_MCSPI3_BASE
+	case 2:
+		 regs = (struct mcspi *)OMAP3_MCSPI3_BASE;
+		 break;
+#endif
+#ifdef OMAP3_MCSPI4_BASE
+	case 3:
+		 regs = (struct mcspi *)OMAP3_MCSPI4_BASE;
+		 break;
+#endif
+	default:
+		 printf("SPI error: unsupported bus %i.  Supported busses 0 - 3\n", bus);
+		 return NULL;
+	}
+
+	if (((bus == 0) && (cs > 3)) ||
+	    ((bus == 1) && (cs > 1)) ||
+	    ((bus == 2) && (cs > 1)) ||
+	    ((bus == 3) && (cs > 0))) {
+		printf("SPI error: unsupported chip select %i on bus %i\n", cs, bus);
+		return NULL;
+	}
+
+	if (max_hz > OMAP3_MCSPI_MAX_FREQ) {
+		printf("SPI error: unsupported frequency %i Hz. Max frequency is 48 Mhz\n", max_hz);
+		return NULL;
+	}
+
+	if (mode > SPI_MODE_3) {
+		printf("SPI error: unsupported SPI mode %i\n", mode);
+		return NULL;
+	}
+
+	priv = spi_alloc_slave(struct omap3_spi_priv, bus, cs);
+	if (!priv) {
+		printf("SPI error: malloc of SPI structure failed\n");
+		return NULL;
+	}
+
+	priv->regs = regs;
+	priv->cs = cs;
+	priv->freq = max_hz;
+	priv->mode = mode;
+	priv->wordlen = priv->slave.wordlen;
+#ifdef CONFIG_OMAP3_SPI_D0_D1_SWAPPED
+	priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
+#endif
+
+	return &priv->slave;
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+	     const void *dout, void *din, unsigned long flags)
+{
+	struct omap3_spi_priv *priv = to_omap3_spi(slave);
+
+	return _spi_xfer(priv, bitlen, dout, din, flags);
+}
+
+#else
+
+static int omap3_spi_claim_bus(struct udevice *dev)
+{
+	struct udevice *bus = dev->parent;
+	struct omap3_spi_priv *priv = dev_get_priv(bus);
+	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+
+	priv->cs = slave_plat->cs;
+	priv->mode = slave_plat->mode;
+	priv->freq = slave_plat->max_hz;
+	_omap3_spi_claim_bus(priv);
+
+	return 0;
+}
+
+static int omap3_spi_release_bus(struct udevice *dev)
+{
+	struct udevice *bus = dev->parent;
+	struct omap3_spi_priv *priv = dev_get_priv(bus);
+
+	/* Reset the SPI hardware */
+	spi_reset(priv->regs);
+
+	return 0;
+}
+
+static int omap3_spi_set_wordlen(struct udevice *dev, unsigned int wordlen)
+{
+	struct udevice *bus = dev->parent;
+	struct omap3_spi_priv *priv = dev_get_priv(bus);
+	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+
+	priv->cs = slave_plat->cs;
+	priv->wordlen = wordlen;
+	_omap3_spi_set_wordlen(priv);
+
+	return 0;
+}
+
+static int omap3_spi_probe(struct udevice *dev)
+{
+	struct omap3_spi_priv *priv = dev_get_priv(dev);
+	const void *blob = gd->fdt_blob;
+	int node = dev->of_offset;
+
+	priv->regs = (struct mcspi *)dev_get_addr(dev);
+	priv->pin_dir = fdtdec_get_uint(blob, node, "ti,pindir-d0-out-d1-in",
+					    MCSPI_PINDIR_D0_IN_D1_OUT);
+	priv->wordlen = SPI_DEFAULT_WORDLEN;
+	return 0;
+}
+
+static int omap3_spi_xfer(struct udevice *dev, unsigned int bitlen,
+			    const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *bus = dev->parent;
+	struct omap3_spi_priv *priv = dev_get_priv(bus);
+
+	return _spi_xfer(priv, bitlen, dout, din, flags);
+}
+
+static int omap3_spi_set_speed(struct udevice *bus, unsigned int speed)
+{
+	return 0;
+}
+
+static int omap3_spi_set_mode(struct udevice *bus, uint mode)
+{
+	return 0;
+}
+
+static const struct dm_spi_ops omap3_spi_ops = {
+	.claim_bus      = omap3_spi_claim_bus,
+	.release_bus    = omap3_spi_release_bus,
+	.set_wordlen    = omap3_spi_set_wordlen,
+	.xfer	    = omap3_spi_xfer,
+	.set_speed      = omap3_spi_set_speed,
+	.set_mode	= omap3_spi_set_mode,
+	/*
+	 * cs_info is not needed, since we require all chip selects to be
+	 * in the device tree explicitly
+	 */
+};
+
+static const struct udevice_id omap3_spi_ids[] = {
+	{ .compatible = "ti,omap2-mcspi" },
+	{ .compatible = "ti,omap4-mcspi" },
+	{ }
+};
+
+U_BOOT_DRIVER(omap3_spi) = {
+	.name   = "omap3_spi",
+	.id     = UCLASS_SPI,
+	.of_match = omap3_spi_ids,
+	.probe = omap3_spi_probe,
+	.ops    = &omap3_spi_ops,
+	.priv_auto_alloc_size = sizeof(struct omap3_spi_priv),
+	.probe = omap3_spi_probe,
+};
+#endif
diff --git a/drivers/spi/omap3_spi.h b/drivers/spi/omap3_spi.h
deleted file mode 100644
index 6a07c6d..0000000
--- a/drivers/spi/omap3_spi.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Register definitions for the OMAP3 McSPI Controller
- *
- * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
- *
- * Parts taken from linux/drivers/spi/omap2_mcspi.c
- * Copyright (C) 2005, 2006 Nokia Corporation
- *
- * Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _OMAP3_SPI_H_
-#define _OMAP3_SPI_H_
-
-#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
-#define OMAP3_MCSPI1_BASE	0x48030100
-#define OMAP3_MCSPI2_BASE	0x481A0100
-#else
-#define OMAP3_MCSPI1_BASE	0x48098000
-#define OMAP3_MCSPI2_BASE	0x4809A000
-#define OMAP3_MCSPI3_BASE	0x480B8000
-#define OMAP3_MCSPI4_BASE	0x480BA000
-#endif
-
-#define OMAP3_MCSPI_MAX_FREQ	48000000
-
-/* OMAP3 McSPI registers */
-struct mcspi_channel {
-	unsigned int chconf;		/* 0x2C, 0x40, 0x54, 0x68 */
-	unsigned int chstat;		/* 0x30, 0x44, 0x58, 0x6C */
-	unsigned int chctrl;		/* 0x34, 0x48, 0x5C, 0x70 */
-	unsigned int tx;		/* 0x38, 0x4C, 0x60, 0x74 */
-	unsigned int rx;		/* 0x3C, 0x50, 0x64, 0x78 */
-};
-
-struct mcspi {
-	unsigned char res1[0x10];
-	unsigned int sysconfig;		/* 0x10 */
-	unsigned int sysstatus;		/* 0x14 */
-	unsigned int irqstatus;		/* 0x18 */
-	unsigned int irqenable;		/* 0x1C */
-	unsigned int wakeupenable;	/* 0x20 */
-	unsigned int syst;		/* 0x24 */
-	unsigned int modulctrl;		/* 0x28 */
-	struct mcspi_channel channel[4]; /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
-					/* channel1: 0x40 - 0x50, bus 0 & 1 */
-					/* channel2: 0x54 - 0x64, bus 0 & 1 */
-					/* channel3: 0x68 - 0x78, bus 0 */
-};
-
-/* per-register bitmasks */
-#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
-#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
-#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE	BIT(0)
-#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
-
-#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
-
-#define OMAP3_MCSPI_MODULCTRL_SINGLE	BIT(0)
-#define OMAP3_MCSPI_MODULCTRL_MS	BIT(2)
-#define OMAP3_MCSPI_MODULCTRL_STEST	BIT(3)
-
-#define OMAP3_MCSPI_CHCONF_PHA		BIT(0)
-#define OMAP3_MCSPI_CHCONF_POL		BIT(1)
-#define OMAP3_MCSPI_CHCONF_CLKD_MASK	GENMASK(5, 2)
-#define OMAP3_MCSPI_CHCONF_EPOL		BIT(6)
-#define OMAP3_MCSPI_CHCONF_WL_MASK	GENMASK(11, 7)
-#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY	BIT(12)
-#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY	BIT(13)
-#define OMAP3_MCSPI_CHCONF_TRM_MASK	GENMASK(13, 12)
-#define OMAP3_MCSPI_CHCONF_DMAW		BIT(14)
-#define OMAP3_MCSPI_CHCONF_DMAR		BIT(15)
-#define OMAP3_MCSPI_CHCONF_DPE0		BIT(16)
-#define OMAP3_MCSPI_CHCONF_DPE1		BIT(17)
-#define OMAP3_MCSPI_CHCONF_IS		BIT(18)
-#define OMAP3_MCSPI_CHCONF_TURBO	BIT(19)
-#define OMAP3_MCSPI_CHCONF_FORCE	BIT(20)
-
-#define OMAP3_MCSPI_CHSTAT_RXS		BIT(0)
-#define OMAP3_MCSPI_CHSTAT_TXS		BIT(1)
-#define OMAP3_MCSPI_CHSTAT_EOT		BIT(2)
-
-#define OMAP3_MCSPI_CHCTRL_EN		BIT(0)
-#define OMAP3_MCSPI_CHCTRL_DIS		(0 << 0)
-
-#define OMAP3_MCSPI_WAKEUPENABLE_WKEN	BIT(0)
-
-struct omap3_spi_slave {
-	struct spi_slave slave;
-	struct mcspi *regs;
-	unsigned int freq;
-	unsigned int mode;
-};
-
-static inline struct omap3_spi_slave *to_omap3_spi(struct spi_slave *slave)
-{
-	return container_of(slave, struct omap3_spi_slave, slave);
-}
-
-int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, const void *txp,
-			void *rxp, unsigned long flags);
-int omap3_spi_write(struct spi_slave *slave, unsigned int len, const void *txp,
-		    unsigned long flags);
-int omap3_spi_read(struct spi_slave *slave, unsigned int len, void *rxp,
-		   unsigned long flags);
-
-#endif /* _OMAP3_SPI_H_ */
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 409a5c4..e69ec0d 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -534,11 +534,15 @@
 	const void *blob = gd->fdt_blob;
 	int node = bus->of_offset;
 	fdt_addr_t addr;
+	void *mmap;
 
-	priv->base = (struct ti_qspi_regs *)dev_get_addr(bus);
-	priv->memory_map = (void *)dev_get_addr_index(bus, 1);
+	priv->base = map_physmem(dev_get_addr(bus), sizeof(struct ti_qspi_regs),
+				 MAP_NOCACHE);
+	priv->memory_map = map_physmem(dev_get_addr_index(bus, 1), 0,
+				       MAP_NOCACHE);
 	addr = dev_get_addr_index(bus, 2);
-	priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr;
+	mmap = map_physmem(dev_get_addr_index(bus, 2), 0, MAP_NOCACHE);
+	priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : mmap;
 
 	priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
 	if (priv->max_hz < 0) {
diff --git a/drivers/timer/omap-timer.c b/drivers/timer/omap-timer.c
index 3bb38c5..7422e0a 100644
--- a/drivers/timer/omap-timer.c
+++ b/drivers/timer/omap-timer.c
@@ -79,7 +79,8 @@
 {
 	struct omap_timer_priv *priv = dev_get_priv(dev);
 
-	priv->regs = (struct omap_gptimer_regs *)dev_get_addr(dev);
+	priv->regs = map_physmem(dev_get_addr(dev),
+				 sizeof(struct omap_gptimer_regs), MAP_NOCACHE);
 
 	return 0;
 }
diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index 382c0f2..f8ddf93 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c
@@ -82,11 +82,9 @@
 	node = fdtdec_get_chosen_node(blob, "tick-timer");
 	if (node < 0) {
 		/* No chosen timer, trying first available timer */
-		ret = uclass_first_device(UCLASS_TIMER, &dev);
+		ret = uclass_first_device_err(UCLASS_TIMER, &dev);
 		if (ret)
 			return ret;
-		if (!dev)
-			return -ENODEV;
 	} else {
 		if (uclass_get_device_by_of_offset(UCLASS_TIMER, node, &dev)) {
 			/*
diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c
index 50538e0..69c9a50 100644
--- a/drivers/usb/host/usb-uclass.c
+++ b/drivers/usb/host/usb-uclass.c
@@ -159,7 +159,11 @@
 		if (ret && !err)
 			err = ret;
 	}
-
+#ifdef CONFIG_BLK
+	ret = blk_unbind_all(IF_TYPE_USB);
+	if (ret && !err)
+		err = ret;
+#endif
 #ifdef CONFIG_SANDBOX
 	struct udevice *dev;
 
diff --git a/drivers/usb/musb-new/linux-compat.h b/drivers/usb/musb-new/linux-compat.h
index 46f83d9..1fc9391 100644
--- a/drivers/usb/musb-new/linux-compat.h
+++ b/drivers/usb/musb-new/linux-compat.h
@@ -37,4 +37,8 @@
 #define CONFIG_SOC_OMAP3430
 #endif
 
+#ifdef CONFIG_OMAP4430
+#define CONFIG_ARCH_OMAP4
+#endif
+
 #endif /* __LINUX_COMPAT_H__ */
diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c
index 9f307e9..684ad95 100644
--- a/drivers/usb/musb-new/omap2430.c
+++ b/drivers/usb/musb-new/omap2430.c
@@ -23,8 +23,10 @@
 #include <linux/usb/musb-omap.h>
 #else
 #include <common.h>
+#include <asm/omap_common.h>
 #include <asm/omap_musb.h>
 #include <twl4030.h>
+#include <twl6030.h>
 #include "linux-compat.h"
 #endif
 
@@ -434,6 +436,17 @@
 				__PRETTY_FUNCTION__);
 	}
 #endif
+
+#ifdef CONFIG_TWL6030_POWER
+	twl6030_usb_device_settings();
+#endif
+
+#ifdef CONFIG_OMAP4430
+	u32 *usbotghs_control = (u32 *)((*ctrl)->control_usbotghs_ctrl);
+	*usbotghs_control = USBOTGHS_CONTROL_AVALID |
+		USBOTGHS_CONTROL_VBUSVALID | USBOTGHS_CONTROL_IDDIG;
+#endif
+
 	return 0;
 #endif
 }
diff --git a/drivers/usb/musb-new/omap2430.h b/drivers/usb/musb-new/omap2430.h
index 56998c7..0c3dd8b 100644
--- a/drivers/usb/musb-new/omap2430.h
+++ b/drivers/usb/musb-new/omap2430.h
@@ -50,4 +50,12 @@
 #define OTG_FORCESTDBY		0x414
 #	define	ENABLEFORCE		(1 << 0)
 
+/*
+ * OMAP4-specific definitions
+ */
+
+#define USBOTGHS_CONTROL_AVALID		(1 << 0)
+#define USBOTGHS_CONTROL_VBUSVALID	(1 << 2)
+#define USBOTGHS_CONTROL_IDDIG		(1 << 4)
+
 #endif	/* __MUSB_OMAP243X_H__ */
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index ff4179f..8361a71 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -112,7 +112,7 @@
 
 config FRAMEBUFFER_SET_VESA_MODE
 	bool "Set framebuffer graphics resolution"
-	depends on VIDEO_VESA
+	depends on VIDEO_VESA || VIDEO_BROADWELL_IGD
 	help
 	  Set VESA/native framebuffer mode (needed for bootsplash and graphical
 	  framebuffer console)
@@ -362,6 +362,18 @@
 	   The devices provide a simple interface to start up the display,
 	   read display information and enable it.
 
+config VIDEO_BROADWELL_IGD
+	bool "Enable Intel Broadwell integrated graphics device"
+	depends on X86
+	help
+	  This enabled support for integrated graphics on Intel broadwell
+	  devices. Initialisation is mostly performed by a VGA boot ROM, with
+	  some setup handled by U-Boot itself. The graphics adaptor works as
+	  a VESA device and supports LCD panels, eDP and LVDS outputs.
+	  Configuration of most aspects of device operation is performed using
+	  a special tool which configures the VGA ROM, but the graphics
+	  resolution can be selected in U-Boot.
+
 config VIDEO_ROCKCHIP
 	bool "Enable Rockchip video support"
 	depends on DM_VIDEO
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 9b635fc..2fd0891 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -19,6 +19,8 @@
 obj-$(CONFIG_CONSOLE_TRUETYPE) += console_truetype.o fonts/
 endif
 
+obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o
+
 obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
 obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
 obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
diff --git a/drivers/video/broadwell_igd.c b/drivers/video/broadwell_igd.c
new file mode 100644
index 0000000..ce4f296
--- /dev/null
+++ b/drivers/video/broadwell_igd.c
@@ -0,0 +1,797 @@
+/*
+ * From coreboot src/soc/intel/broadwell/igd.c
+ *
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <bios_emul.h>
+#include <dm.h>
+#include <pci_rom.h>
+#include <vbe.h>
+#include <video.h>
+#include <video_fb.h>
+#include <asm/cpu.h>
+#include <asm/intel_regs.h>
+#include <asm/io.h>
+#include <asm/mtrr.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/iomap.h>
+#include <asm/arch/pch.h>
+#include <linux/log2.h>
+#include "i915_reg.h"
+
+struct broadwell_igd_priv {
+	GraphicDevice ctfb;
+	u8 *regs;
+};
+
+struct broadwell_igd_plat {
+	u32 dp_hotplug[3];
+
+	int port_select;
+	int power_up_delay;
+	int power_backlight_on_delay;
+	int power_down_delay;
+	int power_backlight_off_delay;
+	int power_cycle_delay;
+	int cpu_backlight;
+	int pch_backlight;
+	int cdclk;
+	int pre_graphics_delay;
+};
+
+#define GT_RETRY		1000
+#define GT_CDCLK_337		0
+#define GT_CDCLK_450		1
+#define GT_CDCLK_540		2
+#define GT_CDCLK_675		3
+
+u32 board_map_oprom_vendev(u32 vendev)
+{
+	return SA_IGD_OPROM_VENDEV;
+}
+
+static int poll32(u8 *addr, uint mask, uint value)
+{
+	ulong start;
+
+	start = get_timer(0);
+	debug("%s: addr %p = %x\n", __func__, addr, readl(addr));
+	while ((readl(addr) & mask) != value) {
+		if (get_timer(start) > GT_RETRY) {
+			debug("poll32: timeout: %x\n", readl(addr));
+			return -ETIMEDOUT;
+		}
+	}
+
+	return 0;
+}
+
+static int haswell_early_init(struct udevice *dev)
+{
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	u8 *regs = priv->regs;
+	int ret;
+
+	/* Enable Force Wake */
+	writel(0x00000020, regs + 0xa180);
+	writel(0x00010001, regs + 0xa188);
+	ret = poll32(regs + 0x130044, 1, 1);
+	if (ret)
+		goto err;
+
+	/* Enable Counters */
+	setbits_le32(regs + 0xa248, 0x00000016);
+
+	/* GFXPAUSE settings */
+	writel(0x00070020, regs + 0xa000);
+
+	/* ECO Settings */
+	clrsetbits_le32(regs + 0xa180, ~0xff3fffff, 0x15000000);
+
+	/* Enable DOP Clock Gating */
+	writel(0x000003fd, regs + 0x9424);
+
+	/* Enable Unit Level Clock Gating */
+	writel(0x00000080, regs + 0x9400);
+	writel(0x40401000, regs + 0x9404);
+	writel(0x00000000, regs + 0x9408);
+	writel(0x02000001, regs + 0x940c);
+
+	/*
+	 * RC6 Settings
+	 */
+
+	/* Wake Rate Limits */
+	setbits_le32(regs + 0xa090, 0x00000000);
+	setbits_le32(regs + 0xa098, 0x03e80000);
+	setbits_le32(regs + 0xa09c, 0x00280000);
+	setbits_le32(regs + 0xa0a8, 0x0001e848);
+	setbits_le32(regs + 0xa0ac, 0x00000019);
+
+	/* Render/Video/Blitter Idle Max Count */
+	writel(0x0000000a, regs + 0x02054);
+	writel(0x0000000a, regs + 0x12054);
+	writel(0x0000000a, regs + 0x22054);
+	writel(0x0000000a, regs + 0x1a054);
+
+	/* RC Sleep / RCx Thresholds */
+	setbits_le32(regs + 0xa0b0, 0x00000000);
+	setbits_le32(regs + 0xa0b4, 0x000003e8);
+	setbits_le32(regs + 0xa0b8, 0x0000c350);
+
+	/* RP Settings */
+	setbits_le32(regs + 0xa010, 0x000f4240);
+	setbits_le32(regs + 0xa014, 0x12060000);
+	setbits_le32(regs + 0xa02c, 0x0000e808);
+	setbits_le32(regs + 0xa030, 0x0003bd08);
+	setbits_le32(regs + 0xa068, 0x000101d0);
+	setbits_le32(regs + 0xa06c, 0x00055730);
+	setbits_le32(regs + 0xa070, 0x0000000a);
+
+	/* RP Control */
+	writel(0x00000b92, regs + 0xa024);
+
+	/* HW RC6 Control */
+	writel(0x88040000, regs + 0xa090);
+
+	/* Video Frequency Request */
+	writel(0x08000000, regs + 0xa00c);
+
+	/* Set RC6 VIDs */
+	ret = poll32(regs + 0x138124, (1 << 31), 0);
+	if (ret)
+		goto err;
+	writel(0, regs + 0x138128);
+	writel(0x80000004, regs + 0x138124);
+	ret = poll32(regs + 0x138124, (1 << 31), 0);
+	if (ret)
+		goto err;
+
+	/* Enable PM Interrupts */
+	writel(0x03000076, regs + 0x4402c);
+
+	/* Enable RC6 in idle */
+	writel(0x00040000, regs + 0xa094);
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+};
+
+static int haswell_late_init(struct udevice *dev)
+{
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	u8 *regs = priv->regs;
+	int ret;
+
+	/* Lock settings */
+	setbits_le32(regs + 0x0a248, (1 << 31));
+	setbits_le32(regs + 0x0a004, (1 << 4));
+	setbits_le32(regs + 0x0a080, (1 << 2));
+	setbits_le32(regs + 0x0a180, (1 << 31));
+
+	/* Disable Force Wake */
+	writel(0x00010000, regs + 0xa188);
+	ret = poll32(regs + 0x130044, 1, 0);
+	if (ret)
+		goto err;
+	writel(0x00000001, regs + 0xa188);
+
+	/* Enable power well for DP and Audio */
+	setbits_le32(regs + 0x45400, (1 << 31));
+	ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
+	if (ret)
+		goto err;
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+};
+
+static int broadwell_early_init(struct udevice *dev)
+{
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	u8 *regs = priv->regs;
+	int ret;
+
+	/* Enable Force Wake */
+	writel(0x00010001, regs + 0xa188);
+	ret = poll32(regs + 0x130044, 1, 1);
+	if (ret)
+		goto err;
+
+	/* Enable push bus metric control and shift */
+	writel(0x00000004, regs + 0xa248);
+	writel(0x000000ff, regs + 0xa250);
+	writel(0x00000010, regs + 0xa25c);
+
+	/* GFXPAUSE settings (set based on stepping) */
+
+	/* ECO Settings */
+	writel(0x45200000, regs + 0xa180);
+
+	/* Enable DOP Clock Gating */
+	writel(0x000000fd, regs + 0x9424);
+
+	/* Enable Unit Level Clock Gating */
+	writel(0x00000000, regs + 0x9400);
+	writel(0x40401000, regs + 0x9404);
+	writel(0x00000000, regs + 0x9408);
+	writel(0x02000001, regs + 0x940c);
+	writel(0x0000000a, regs + 0x1a054);
+
+	/* Video Frequency Request */
+	writel(0x08000000, regs + 0xa00c);
+
+	writel(0x00000009, regs + 0x138158);
+	writel(0x0000000d, regs + 0x13815c);
+
+	/*
+	 * RC6 Settings
+	 */
+
+	/* Wake Rate Limits */
+	clrsetbits_le32(regs + 0x0a090, ~0, 0);
+	setbits_le32(regs + 0x0a098, 0x03e80000);
+	setbits_le32(regs + 0x0a09c, 0x00280000);
+	setbits_le32(regs + 0x0a0a8, 0x0001e848);
+	setbits_le32(regs + 0x0a0ac, 0x00000019);
+
+	/* Render/Video/Blitter Idle Max Count */
+	writel(0x0000000a, regs + 0x02054);
+	writel(0x0000000a, regs + 0x12054);
+	writel(0x0000000a, regs + 0x22054);
+
+	/* RC Sleep / RCx Thresholds */
+	setbits_le32(regs + 0x0a0b0, 0x00000000);
+	setbits_le32(regs + 0x0a0b8, 0x00000271);
+
+	/* RP Settings */
+	setbits_le32(regs + 0x0a010, 0x000f4240);
+	setbits_le32(regs + 0x0a014, 0x12060000);
+	setbits_le32(regs + 0x0a02c, 0x0000e808);
+	setbits_le32(regs + 0x0a030, 0x0003bd08);
+	setbits_le32(regs + 0x0a068, 0x000101d0);
+	setbits_le32(regs + 0x0a06c, 0x00055730);
+	setbits_le32(regs + 0x0a070, 0x0000000a);
+	setbits_le32(regs + 0x0a168, 0x00000006);
+
+	/* RP Control */
+	writel(0x00000b92, regs + 0xa024);
+
+	/* HW RC6 Control */
+	writel(0x90040000, regs + 0xa090);
+
+	/* Set RC6 VIDs */
+	ret = poll32(regs + 0x138124, (1 << 31), 0);
+	if (ret)
+		goto err;
+	writel(0, regs + 0x138128);
+	writel(0x80000004, regs + 0x138124);
+	ret = poll32(regs + 0x138124, (1 << 31), 0);
+	if (ret)
+		goto err;
+
+	/* Enable PM Interrupts */
+	writel(0x03000076, regs + 0x4402c);
+
+	/* Enable RC6 in idle */
+	writel(0x00040000, regs + 0xa094);
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+}
+
+static int broadwell_late_init(struct udevice *dev)
+{
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	u8 *regs = priv->regs;
+	int ret;
+
+	/* Lock settings */
+	setbits_le32(regs + 0x0a248, 1 << 31);
+	setbits_le32(regs + 0x0a000, 1 << 18);
+	setbits_le32(regs + 0x0a180, 1 << 31);
+
+	/* Disable Force Wake */
+	writel(0x00010000, regs + 0xa188);
+	ret = poll32(regs + 0x130044, 1, 0);
+	if (ret)
+		goto err;
+
+	/* Enable power well for DP and Audio */
+	setbits_le32(regs + 0x45400, 1 << 31);
+	ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
+	if (ret)
+		goto err;
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+};
+
+
+static unsigned long gtt_read(struct broadwell_igd_priv *priv,
+			      unsigned long reg)
+{
+	u32 val;
+
+	val = readl(priv->regs + reg);
+	return val;
+}
+
+static void gtt_write(struct broadwell_igd_priv *priv, unsigned long reg,
+		      unsigned long data)
+{
+	writel(data, priv->regs + reg);
+}
+
+static inline void gtt_clrsetbits(struct broadwell_igd_priv *priv, u32 reg,
+				  u32 bic, u32 or)
+{
+	clrsetbits_le32(priv->regs + reg, bic, or);
+}
+
+static int gtt_poll(struct broadwell_igd_priv *priv, u32 reg, u32 mask,
+		    u32 value)
+{
+	unsigned try = GT_RETRY;
+	u32 data;
+
+	while (try--) {
+		data = gtt_read(priv, reg);
+		if ((data & mask) == value)
+			return 0;
+		udelay(10);
+	}
+
+	debug("GT init timeout\n");
+	return -ETIMEDOUT;
+}
+
+static void igd_setup_panel(struct udevice *dev)
+{
+	struct broadwell_igd_plat *plat = dev_get_platdata(dev);
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	u32 reg32;
+
+	/* Setup Digital Port Hotplug */
+	reg32 = (plat->dp_hotplug[0] & 0x7) << 2;
+	reg32 |= (plat->dp_hotplug[1] & 0x7) << 10;
+	reg32 |= (plat->dp_hotplug[2] & 0x7) << 18;
+	gtt_write(priv, PCH_PORT_HOTPLUG, reg32);
+
+	/* Setup Panel Power On Delays */
+	reg32 = (plat->port_select & 0x3) << 30;
+	reg32 |= (plat->power_up_delay & 0x1fff) << 16;
+	reg32 |= (plat->power_backlight_on_delay & 0x1fff);
+	gtt_write(priv, PCH_PP_ON_DELAYS, reg32);
+
+	/* Setup Panel Power Off Delays */
+	reg32 = (plat->power_down_delay & 0x1fff) << 16;
+	reg32 |= (plat->power_backlight_off_delay & 0x1fff);
+	gtt_write(priv, PCH_PP_OFF_DELAYS, reg32);
+
+	/* Setup Panel Power Cycle Delay */
+	if (plat->power_cycle_delay) {
+		reg32 = gtt_read(priv, PCH_PP_DIVISOR);
+		reg32 &= ~0xff;
+		reg32 |= plat->power_cycle_delay & 0xff;
+		gtt_write(priv, PCH_PP_DIVISOR, reg32);
+	}
+
+	/* Enable Backlight if needed */
+	if (plat->cpu_backlight) {
+		gtt_write(priv, BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE);
+		gtt_write(priv, BLC_PWM_CPU_CTL, plat->cpu_backlight);
+	}
+	if (plat->pch_backlight) {
+		gtt_write(priv, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE);
+		gtt_write(priv, BLC_PWM_PCH_CTL2, plat->pch_backlight);
+	}
+}
+
+static int igd_cdclk_init_haswell(struct udevice *dev)
+{
+	struct broadwell_igd_plat *plat = dev_get_platdata(dev);
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	int cdclk = plat->cdclk;
+	u16 devid;
+	int gpu_is_ulx = 0;
+	u32 dpdiv, lpcll;
+	int ret;
+
+	dm_pci_read_config16(dev, PCI_DEVICE_ID, &devid);
+
+	/* Check for ULX GT1 or GT2 */
+	if (devid == 0x0a0e || devid == 0x0a1e)
+		gpu_is_ulx = 1;
+
+	/* 675MHz is not supported on haswell */
+	if (cdclk == GT_CDCLK_675)
+		cdclk = GT_CDCLK_337;
+
+	/* If CD clock is fixed or ULT then set to 450MHz */
+	if ((gtt_read(priv, 0x42014) & 0x1000000) || cpu_is_ult())
+		cdclk = GT_CDCLK_450;
+
+	/* 540MHz is not supported on ULX */
+	if (gpu_is_ulx && cdclk == GT_CDCLK_540)
+		cdclk = GT_CDCLK_337;
+
+	/* 337.5MHz is not supported on non-ULT/ULX */
+	if (!gpu_is_ulx && !cpu_is_ult() && cdclk == GT_CDCLK_337)
+		cdclk = GT_CDCLK_450;
+
+	/* Set variables based on CD Clock setting */
+	switch (cdclk) {
+	case GT_CDCLK_337:
+		dpdiv = 169;
+		lpcll = (1 << 26);
+		break;
+	case GT_CDCLK_450:
+		dpdiv = 225;
+		lpcll = 0;
+		break;
+	case GT_CDCLK_540:
+		dpdiv = 270;
+		lpcll = (1 << 26);
+		break;
+	default:
+		ret = -EDOM;
+		goto err;
+	}
+
+	/* Set LPCLL_CTL CD Clock Frequency Select */
+	gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
+
+	/* ULX: Inform power controller of selected frequency */
+	if (gpu_is_ulx) {
+		if (cdclk == GT_CDCLK_450)
+			gtt_write(priv, 0x138128, 0x00000000); /* 450MHz */
+		else
+			gtt_write(priv, 0x138128, 0x00000001); /* 337.5MHz */
+		gtt_write(priv, 0x13812c, 0x00000000);
+		gtt_write(priv, 0x138124, 0x80000017);
+	}
+
+	/* Set CPU DP AUX 2X bit clock dividers */
+	gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
+	gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+}
+
+static int igd_cdclk_init_broadwell(struct udevice *dev)
+{
+	struct broadwell_igd_plat *plat = dev_get_platdata(dev);
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	int cdclk = plat->cdclk;
+	u32 dpdiv, lpcll, pwctl, cdset;
+	int ret;
+
+	/* Inform power controller of upcoming frequency change */
+	gtt_write(priv, 0x138128, 0);
+	gtt_write(priv, 0x13812c, 0);
+	gtt_write(priv, 0x138124, 0x80000018);
+
+	/* Poll GT driver mailbox for run/busy clear */
+	if (gtt_poll(priv, 0x138124, 1 << 31, 0 << 31))
+		cdclk = GT_CDCLK_450;
+
+	if (gtt_read(priv, 0x42014) & 0x1000000) {
+		/* If CD clock is fixed then set to 450MHz */
+		cdclk = GT_CDCLK_450;
+	} else {
+		/* Program CD clock to highest supported freq */
+		if (cpu_is_ult())
+			cdclk = GT_CDCLK_540;
+		else
+			cdclk = GT_CDCLK_675;
+	}
+
+	/* CD clock frequency 675MHz not supported on ULT */
+	if (cpu_is_ult() && cdclk == GT_CDCLK_675)
+		cdclk = GT_CDCLK_540;
+
+	/* Set variables based on CD Clock setting */
+	switch (cdclk) {
+	case GT_CDCLK_337:
+		cdset = 337;
+		lpcll = (1 << 27);
+		pwctl = 2;
+		dpdiv = 169;
+		break;
+	case GT_CDCLK_450:
+		cdset = 449;
+		lpcll = 0;
+		pwctl = 0;
+		dpdiv = 225;
+		break;
+	case GT_CDCLK_540:
+		cdset = 539;
+		lpcll = (1 << 26);
+		pwctl = 1;
+		dpdiv = 270;
+		break;
+	case GT_CDCLK_675:
+		cdset = 674;
+		lpcll = (1 << 26) | (1 << 27);
+		pwctl = 3;
+		dpdiv = 338;
+		break;
+	default:
+		ret = -EDOM;
+		goto err;
+	}
+	debug("%s: frequency = %d\n", __func__, cdclk);
+
+	/* Set LPCLL_CTL CD Clock Frequency Select */
+	gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
+
+	/* Inform power controller of selected frequency */
+	gtt_write(priv, 0x138128, pwctl);
+	gtt_write(priv, 0x13812c, 0);
+	gtt_write(priv, 0x138124, 0x80000017);
+
+	/* Program CD Clock Frequency */
+	gtt_clrsetbits(priv, 0x46200, ~0xfffffc00, cdset);
+
+	/* Set CPU DP AUX 2X bit clock dividers */
+	gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
+	gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+}
+
+u8 systemagent_revision(struct udevice *bus)
+{
+	ulong val;
+
+	pci_bus_read_config(bus, PCI_BDF(0, 0, 0), PCI_REVISION_ID, &val,
+			    PCI_SIZE_32);
+
+	return val;
+}
+
+static int igd_pre_init(struct udevice *dev, bool is_broadwell)
+{
+	struct broadwell_igd_plat *plat = dev_get_platdata(dev);
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	u32 rp1_gfx_freq;
+	int ret;
+
+	mdelay(plat->pre_graphics_delay);
+
+	/* Early init steps */
+	if (is_broadwell) {
+		ret = broadwell_early_init(dev);
+		if (ret)
+			goto err;
+
+		/* Set GFXPAUSE based on stepping */
+		if (cpu_get_stepping() <= (CPUID_BROADWELL_E0 & 0xf) &&
+		    systemagent_revision(pci_get_controller(dev)) <= 9) {
+			gtt_write(priv, 0xa000, 0x300ff);
+		} else {
+			gtt_write(priv, 0xa000, 0x30020);
+		}
+	} else {
+		ret = haswell_early_init(dev);
+		if (ret)
+			goto err;
+	}
+
+	/* Set RP1 graphics frequency */
+	rp1_gfx_freq = (readl(MCHBAR_REG(0x5998)) >> 8) & 0xff;
+	gtt_write(priv, 0xa008, rp1_gfx_freq << 24);
+
+	/* Post VBIOS panel setup */
+	igd_setup_panel(dev);
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+}
+
+static int igd_post_init(struct udevice *dev, bool is_broadwell)
+{
+	int ret;
+
+	/* Late init steps */
+	if (is_broadwell) {
+		ret = igd_cdclk_init_broadwell(dev);
+		if (ret)
+			return ret;
+		ret = broadwell_late_init(dev);
+		if (ret)
+			return ret;
+	} else {
+		igd_cdclk_init_haswell(dev);
+		ret = haswell_late_init(dev);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int broadwell_igd_int15_handler(void)
+{
+	int res = 0;
+
+	debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
+
+	switch (M.x86.R_AX) {
+	case 0x5f35:
+		/*
+		 * Boot Display Device Hook:
+		 *  bit 0 = CRT
+		 *  bit 1 = TV (eDP)
+		 *  bit 2 = EFP
+		 *  bit 3 = LFP
+		 *  bit 4 = CRT2
+		 *  bit 5 = TV2 (eDP)
+		 *  bit 6 = EFP2
+		 *  bit 7 = LFP2
+		 */
+		M.x86.R_AX = 0x005f;
+		M.x86.R_CX = 0x0000; /* Use video bios default */
+		res = 1;
+		break;
+	default:
+		debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
+		break;
+	}
+
+	return res;
+}
+
+static int broadwell_igd_probe(struct udevice *dev)
+{
+	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	bool is_broadwell;
+	GraphicDevice *gdev = &priv->ctfb;
+	int bits_per_pixel;
+	int ret;
+
+	if (!ll_boot_init()) {
+		/*
+		 * If we are running from EFI or coreboot, this driver can't
+		 * work.
+		 */
+		printf("Not available (previous bootloader prevents it)\n");
+		return -EPERM;
+	}
+	is_broadwell = cpu_get_family_model() == BROADWELL_FAMILY_ULT;
+	bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
+	debug("%s: is_broadwell=%d\n", __func__, is_broadwell);
+	ret = igd_pre_init(dev, is_broadwell);
+	if (!ret) {
+		ret = dm_pci_run_vga_bios(dev, broadwell_igd_int15_handler,
+					  PCI_ROM_USE_NATIVE |
+					  PCI_ROM_ALLOW_FALLBACK);
+		if (ret) {
+			printf("failed to run video BIOS: %d\n", ret);
+			ret = -EIO;
+		}
+	}
+	if (!ret)
+		ret = igd_post_init(dev, is_broadwell);
+	bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
+	if (ret)
+		return ret;
+
+	if (vbe_get_video_info(gdev)) {
+		printf("No video mode configured\n");
+		return -ENXIO;
+	}
+
+	/* Use write-through for the graphics memory, 256MB */
+	ret = mtrr_add_request(MTRR_TYPE_WRTHROUGH, gdev->pciBase, 256 << 20);
+	if (!ret)
+		ret = mtrr_commit(true);
+	if (ret && ret != -ENOSYS) {
+		printf("Failed to add MTRR: Display will be slow (err %d)\n",
+		       ret);
+	}
+
+	bits_per_pixel = gdev->gdfBytesPP * 8;
+	sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
+		bits_per_pixel);
+	printf("%s\n", gdev->modeIdent);
+	uc_priv->xsize = gdev->winSizeX;
+	uc_priv->ysize = gdev->winSizeY;
+	uc_priv->bpix = ilog2(bits_per_pixel);
+	plat->base = gdev->pciBase;
+	plat->size = gdev->memSize;
+	debug("fb=%x, size %x, display size=%d %d %d\n", gdev->pciBase,
+	      gdev->memSize, uc_priv->xsize, uc_priv->ysize, uc_priv->bpix);
+
+	return 0;
+}
+
+static int broadwell_igd_ofdata_to_platdata(struct udevice *dev)
+{
+	struct broadwell_igd_plat *plat = dev_get_platdata(dev);
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	int node = dev->of_offset;
+	const void *blob = gd->fdt_blob;
+
+	if (fdtdec_get_int_array(blob, node, "intel,dp-hotplug",
+				 plat->dp_hotplug,
+				 ARRAY_SIZE(plat->dp_hotplug)))
+		return -EINVAL;
+	plat->port_select = fdtdec_get_int(blob, node, "intel,port-select", 0);
+	plat->power_cycle_delay = fdtdec_get_int(blob, node,
+			"intel,power-cycle-delay", 0);
+	plat->power_up_delay = fdtdec_get_int(blob, node,
+			"intel,power-up-delay", 0);
+	plat->power_down_delay = fdtdec_get_int(blob, node,
+			"intel,power-down-delay", 0);
+	plat->power_backlight_on_delay = fdtdec_get_int(blob, node,
+			"intel,power-backlight-on-delay", 0);
+	plat->power_backlight_off_delay = fdtdec_get_int(blob, node,
+			"intel,power-backlight-off-delay", 0);
+	plat->cpu_backlight = fdtdec_get_int(blob, node,
+			"intel,cpu-backlight", 0);
+	plat->pch_backlight = fdtdec_get_int(blob, node,
+			"intel,pch-backlight", 0);
+	plat->pre_graphics_delay = fdtdec_get_int(blob, node,
+			"intel,pre-graphics-delay", 0);
+	priv->regs = (u8 *)dm_pci_read_bar32(dev, 0);
+	debug("%s: regs at %p\n", __func__, priv->regs);
+	debug("dp_hotplug %d %d %d\n", plat->dp_hotplug[0], plat->dp_hotplug[1],
+	      plat->dp_hotplug[2]);
+	debug("port_select = %d\n", plat->port_select);
+	debug("power_up_delay = %d\n", plat->power_up_delay);
+	debug("power_backlight_on_delay = %d\n",
+	      plat->power_backlight_on_delay);
+	debug("power_down_delay = %d\n", plat->power_down_delay);
+	debug("power_backlight_off_delay = %d\n",
+	      plat->power_backlight_off_delay);
+	debug("power_cycle_delay = %d\n", plat->power_cycle_delay);
+	debug("cpu_backlight = %x\n", plat->cpu_backlight);
+	debug("pch_backlight = %x\n", plat->pch_backlight);
+	debug("cdclk = %d\n", plat->cdclk);
+	debug("pre_graphics_delay = %d\n", plat->pre_graphics_delay);
+
+	return 0;
+}
+
+static const struct video_ops broadwell_igd_ops = {
+};
+
+static const struct udevice_id broadwell_igd_ids[] = {
+	{ .compatible = "intel,broadwell-igd" },
+	{ }
+};
+
+U_BOOT_DRIVER(broadwell_igd) = {
+	.name	= "broadwell_igd",
+	.id	= UCLASS_VIDEO,
+	.of_match = broadwell_igd_ids,
+	.ops	= &broadwell_igd_ops,
+	.ofdata_to_platdata = broadwell_igd_ofdata_to_platdata,
+	.probe	= broadwell_igd_probe,
+	.priv_auto_alloc_size	= sizeof(struct broadwell_igd_priv),
+	.platdata_auto_alloc_size	= sizeof(struct broadwell_igd_plat),
+};
diff --git a/drivers/video/coreboot_fb.c b/drivers/video/coreboot_fb.c
index 4790ef1..feb5463 100644
--- a/drivers/video/coreboot_fb.c
+++ b/drivers/video/coreboot_fb.c
@@ -7,7 +7,6 @@
  */
 
 #include <common.h>
-#include <asm/arch/tables.h>
 #include <asm/arch/sysinfo.h>
 #include <vbe.h>
 #include <video_fb.h>
diff --git a/drivers/video/display-uclass.c b/drivers/video/display-uclass.c
index 31522ea..e4763de 100644
--- a/drivers/video/display-uclass.c
+++ b/drivers/video/display-uclass.c
@@ -36,6 +36,9 @@
 	u8 buf[EDID_EXT_SIZE];
 	int ret;
 
+	if (ops && ops->read_timing)
+		return ops->read_timing(dev, timing);
+
 	if (!ops || !ops->read_edid)
 		return -ENOSYS;
 	ret = ops->read_edid(dev, buf, sizeof(buf));
diff --git a/drivers/video/i915_reg.h b/drivers/video/i915_reg.h
new file mode 100644
index 0000000..f540b15
--- /dev/null
+++ b/drivers/video/i915_reg.h
@@ -0,0 +1,362 @@
+/*
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef _I915_REG_H_
+#define _I915_REG_H_
+
+/* Hotplug control (945+ only) */
+#define PORT_HOTPLUG_EN		0x61110
+#define   HDMIB_HOTPLUG_INT_EN			(1 << 29)
+#define   DPB_HOTPLUG_INT_EN			(1 << 29)
+#define   HDMIC_HOTPLUG_INT_EN			(1 << 28)
+#define   DPC_HOTPLUG_INT_EN			(1 << 28)
+#define   HDMID_HOTPLUG_INT_EN			(1 << 27)
+#define   DPD_HOTPLUG_INT_EN			(1 << 27)
+#define   SDVOB_HOTPLUG_INT_EN			(1 << 26)
+#define   SDVOC_HOTPLUG_INT_EN			(1 << 25)
+#define   TV_HOTPLUG_INT_EN			(1 << 18)
+#define   CRT_HOTPLUG_INT_EN			(1 << 9)
+#define   CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
+#define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
+/* must use period 64 on GM45 according to docs */
+#define CRT_HOTPLUG_ACTIVATION_PERIOD_64	(1 << 8)
+#define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
+#define CRT_HOTPLUG_DAC_ON_TIME_4M		(1 << 7)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_50		(1 << 5)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_60		(2 << 5)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_70		(3 << 5)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK	(3 << 5)
+#define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
+#define CRT_HOTPLUG_DETECT_DELAY_2G		(1 << 4)
+#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
+#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
+
+/* Backlight control */
+#define BLC_PWM_CTL2		0x61250 /* 965+ only */
+#define   BLM_PWM_ENABLE		(1 << 31)
+#define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
+#define   BLM_PIPE_SELECT		(1 << 29)
+#define   BLM_PIPE_SELECT_IVB		(3 << 29)
+#define   BLM_PIPE_A			(0 << 29)
+#define   BLM_PIPE_B			(1 << 29)
+#define   BLM_PIPE_C			(2 << 29) /* ivb + */
+#define   BLM_PIPE(pipe)		((pipe) << 29)
+#define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */
+#define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)
+#define   BLM_PHASE_IN_ENABLE		(1 << 25)
+#define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)
+#define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)
+#define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
+#define   BLM_PHASE_IN_COUNT_SHIFT	(8)
+#define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
+#define   BLM_PHASE_IN_INCR_SHIFT	(0)
+#define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
+#define BLC_PWM_CTL		0x61254
+/*
+ * This is the most significant 15 bits of the number of backlight cycles in a
+ * complete cycle of the modulated backlight control.
+ *
+ * The actual value is this field multiplied by two.
+ */
+#define   BACKLIGHT_MODULATION_FREQ_SHIFT	(17)
+#define   BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)
+#define   BLM_LEGACY_MODE			(1 << 16) /* gen2 only */
+/*
+ * This is the number of cycles out of the backlight modulation cycle for which
+ * the backlight is on.
+ *
+ * This field must be no greater than the number of cycles in the complete
+ * backlight modulation cycle.
+ */
+#define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
+#define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
+#define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
+#define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
+
+#define BLC_HIST_CTL		0x61260
+
+/*
+ * New registers for PCH-split platforms. Safe where new bits show up, the
+ * register layout machtes with gen4 BLC_PWM_CTL[12]
+ */
+#define BLC_PWM_CPU_CTL2	0x48250
+#define  BLC_PWM2_ENABLE        (1<<31)
+#define BLC_PWM_CPU_CTL		0x48254
+
+#define BLM_HIST_CTL			0x48260
+#define  ENH_HIST_ENABLE		(1<<31)
+#define  ENH_MODIF_TBL_ENABLE		(1<<30)
+#define  ENH_PIPE_A_SELECT		(0<<29)
+#define  ENH_PIPE_B_SELECT		(1<<29)
+#define  ENH_PIPE(pipe) _PIPE(pipe, ENH_PIPE_A_SELECT, ENH_PIPE_B_SELECT)
+#define  HIST_MODE_YUV			(0<<24)
+#define  HIST_MODE_HSV			(1<<24)
+#define  ENH_MODE_DIRECT		(0<<13)
+#define  ENH_MODE_ADDITIVE		(1<<13)
+#define  ENH_MODE_MULTIPLICATIVE	(2<<13)
+#define  BIN_REGISTER_SET		(1<<11)
+#define  ENH_NUM_BINS			32
+
+#define BLM_HIST_ENH			0x48264
+
+#define BLM_HIST_GUARD_BAND		0x48268
+#define  BLM_HIST_INTR_ENABLE		(1<<31)
+#define  BLM_HIST_EVENT_STATUS		(1<<30)
+#define  BLM_HIST_INTR_DELAY_MASK	(0xFF<<22)
+#define  BLM_HIST_INTR_DELAY_SHIFT	22
+
+/*
+ * PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
+ * like the normal CTL from gen4 and earlier. Hooray for confusing naming.
+ */
+#define BLC_PWM_PCH_CTL1	0xc8250
+#define   BLM_PCH_PWM_ENABLE			(1 << 31)
+#define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
+#define   BLM_PCH_POLARITY			(1 << 29)
+#define BLC_PWM_PCH_CTL2	0xc8254
+
+/* digital port hotplug */
+#define PCH_PORT_HOTPLUG        0xc4030		/* SHOTPLUG_CTL */
+#define PORTD_HOTPLUG_ENABLE            (1 << 20)
+#define PORTD_PULSE_DURATION_2ms        (0)
+#define PORTD_PULSE_DURATION_4_5ms      (1 << 18)
+#define PORTD_PULSE_DURATION_6ms        (2 << 18)
+#define PORTD_PULSE_DURATION_100ms      (3 << 18)
+#define PORTD_PULSE_DURATION_MASK	(3 << 18)
+#define PORTD_HOTPLUG_NO_DETECT         (0)
+#define PORTD_HOTPLUG_SHORT_DETECT      (1 << 16)
+#define PORTD_HOTPLUG_LONG_DETECT       (1 << 17)
+#define PORTC_HOTPLUG_ENABLE            (1 << 12)
+#define PORTC_PULSE_DURATION_2ms        (0)
+#define PORTC_PULSE_DURATION_4_5ms      (1 << 10)
+#define PORTC_PULSE_DURATION_6ms        (2 << 10)
+#define PORTC_PULSE_DURATION_100ms      (3 << 10)
+#define PORTC_PULSE_DURATION_MASK	(3 << 10)
+#define PORTC_HOTPLUG_NO_DETECT         (0)
+#define PORTC_HOTPLUG_SHORT_DETECT      (1 << 8)
+#define PORTC_HOTPLUG_LONG_DETECT       (1 << 9)
+#define PORTB_HOTPLUG_ENABLE            (1 << 4)
+#define PORTB_PULSE_DURATION_2ms        (0)
+#define PORTB_PULSE_DURATION_4_5ms      (1 << 2)
+#define PORTB_PULSE_DURATION_6ms        (2 << 2)
+#define PORTB_PULSE_DURATION_100ms      (3 << 2)
+#define PORTB_PULSE_DURATION_MASK	(3 << 2)
+#define PORTB_HOTPLUG_NO_DETECT         (0)
+#define PORTB_HOTPLUG_SHORT_DETECT      (1 << 0)
+#define PORTB_HOTPLUG_LONG_DETECT       (1 << 1)
+
+#define PCH_GPIOA               0xc5010
+#define PCH_GPIOB               0xc5014
+#define PCH_GPIOC               0xc5018
+#define PCH_GPIOD               0xc501c
+#define PCH_GPIOE               0xc5020
+#define PCH_GPIOF               0xc5024
+
+#define PCH_GMBUS0		0xc5100
+#define PCH_GMBUS1		0xc5104
+#define PCH_GMBUS2		0xc5108
+#define PCH_GMBUS3		0xc510c
+#define PCH_GMBUS4		0xc5110
+#define PCH_GMBUS5		0xc5120
+
+#define _PCH_DPLL_A              0xc6014
+#define _PCH_DPLL_B              0xc6018
+#define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
+
+#define _PCH_FPA0                0xc6040
+#define  FP_CB_TUNE		(0x3<<22)
+#define _PCH_FPA1                0xc6044
+#define _PCH_FPB0                0xc6048
+#define _PCH_FPB1                0xc604c
+#define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
+#define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
+
+#define PCH_DPLL_TEST           0xc606c
+
+#define PCH_DREF_CONTROL        0xC6200
+#define  DREF_CONTROL_MASK      0x7fc3
+#define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0<<13)
+#define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2<<13)
+#define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3<<13)
+#define  DREF_CPU_SOURCE_OUTPUT_MASK		(3<<13)
+#define  DREF_SSC_SOURCE_DISABLE                (0<<11)
+#define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
+#define  DREF_SSC_SOURCE_MASK			(3<<11)
+#define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
+#define  DREF_NONSPREAD_CK505_ENABLE		(1<<9)
+#define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
+#define  DREF_NONSPREAD_SOURCE_MASK		(3<<9)
+#define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
+#define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
+#define  DREF_SUPERSPREAD_SOURCE_MASK		(3<<7)
+#define  DREF_SSC4_DOWNSPREAD                   (0<<6)
+#define  DREF_SSC4_CENTERSPREAD                 (1<<6)
+#define  DREF_SSC1_DISABLE                      (0<<1)
+#define  DREF_SSC1_ENABLE                       (1<<1)
+#define  DREF_SSC4_DISABLE                      (0)
+#define  DREF_SSC4_ENABLE                       (1)
+
+#define PCH_RAWCLK_FREQ         0xc6204
+#define  FDL_TP1_TIMER_SHIFT    12
+#define  FDL_TP1_TIMER_MASK     (3<<12)
+#define  FDL_TP2_TIMER_SHIFT    10
+#define  FDL_TP2_TIMER_MASK     (3<<10)
+#define  RAWCLK_FREQ_MASK       0x3ff
+
+#define PCH_DPLL_TMR_CFG        0xc6208
+
+#define PCH_SSC4_PARMS          0xc6210
+#define PCH_SSC4_AUX_PARMS      0xc6214
+
+#define PCH_DPLL_SEL		0xc7000
+#define  TRANSA_DPLL_ENABLE	(1<<3)
+#define	 TRANSA_DPLLB_SEL	(1<<0)
+#define	 TRANSA_DPLLA_SEL	0
+#define  TRANSB_DPLL_ENABLE	(1<<7)
+#define	 TRANSB_DPLLB_SEL	(1<<4)
+#define	 TRANSB_DPLLA_SEL	(0)
+#define  TRANSC_DPLL_ENABLE	(1<<11)
+#define	 TRANSC_DPLLB_SEL	(1<<8)
+#define	 TRANSC_DPLLA_SEL	(0)
+
+/* transcoder */
+
+#define _TRANS_HTOTAL_A          0xe0000
+#define  TRANS_HTOTAL_SHIFT     16
+#define  TRANS_HACTIVE_SHIFT    0
+#define _TRANS_HBLANK_A          0xe0004
+#define  TRANS_HBLANK_END_SHIFT 16
+#define  TRANS_HBLANK_START_SHIFT 0
+#define _TRANS_HSYNC_A           0xe0008
+#define  TRANS_HSYNC_END_SHIFT  16
+#define  TRANS_HSYNC_START_SHIFT 0
+#define _TRANS_VTOTAL_A          0xe000c
+#define  TRANS_VTOTAL_SHIFT     16
+#define  TRANS_VACTIVE_SHIFT    0
+#define _TRANS_VBLANK_A          0xe0010
+#define  TRANS_VBLANK_END_SHIFT 16
+#define  TRANS_VBLANK_START_SHIFT 0
+#define _TRANS_VSYNC_A           0xe0014
+#define  TRANS_VSYNC_END_SHIFT  16
+#define  TRANS_VSYNC_START_SHIFT 0
+#define _TRANS_VSYNCSHIFT_A	0xe0028
+
+#define _TRANSA_DATA_M1          0xe0030
+#define _TRANSA_DATA_N1          0xe0034
+#define _TRANSA_DATA_M2          0xe0038
+#define _TRANSA_DATA_N2          0xe003c
+#define _TRANSA_DP_LINK_M1       0xe0040
+#define _TRANSA_DP_LINK_N1       0xe0044
+#define _TRANSA_DP_LINK_M2       0xe0048
+#define _TRANSA_DP_LINK_N2       0xe004c
+
+/* Per-transcoder DIP controls */
+
+#define _VIDEO_DIP_CTL_A         0xe0200
+#define _VIDEO_DIP_DATA_A        0xe0208
+#define _VIDEO_DIP_GCP_A         0xe0210
+
+#define _VIDEO_DIP_CTL_B         0xe1200
+#define _VIDEO_DIP_DATA_B        0xe1208
+#define _VIDEO_DIP_GCP_B         0xe1210
+
+#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
+#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
+#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
+
+#define VLV_VIDEO_DIP_CTL_A		0x60200
+#define VLV_VIDEO_DIP_DATA_A		0x60208
+#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	0x60210
+
+#define VLV_VIDEO_DIP_CTL_B		0x61170
+#define VLV_VIDEO_DIP_DATA_B		0x61174
+#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B	0x61178
+
+#define VLV_TVIDEO_DIP_CTL(pipe) \
+	 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
+#define VLV_TVIDEO_DIP_DATA(pipe) \
+	 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
+#define VLV_TVIDEO_DIP_GCP(pipe) \
+	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
+
+/* vlv has 2 sets of panel control regs. */
+#define PIPEA_PP_STATUS         0x61200
+#define PIPEA_PP_CONTROL        0x61204
+#define PIPEA_PP_ON_DELAYS      0x61208
+#define PIPEA_PP_OFF_DELAYS     0x6120c
+#define PIPEA_PP_DIVISOR        0x61210
+
+#define PIPEB_PP_STATUS         0x61300
+#define PIPEB_PP_CONTROL        0x61304
+#define PIPEB_PP_ON_DELAYS      0x61308
+#define PIPEB_PP_OFF_DELAYS     0x6130c
+#define PIPEB_PP_DIVISOR        0x61310
+
+#define PCH_PP_STATUS		0xc7200
+#define PCH_PP_CONTROL		0xc7204
+#define  PANEL_UNLOCK_REGS	(0xabcd << 16)
+#define  PANEL_UNLOCK_MASK	(0xffff << 16)
+#define  EDP_FORCE_VDD		(1 << 3)
+#define  EDP_BLC_ENABLE		(1 << 2)
+#define  PANEL_POWER_RESET	(1 << 1)
+#define  PANEL_POWER_OFF	(0 << 0)
+#define  PANEL_POWER_ON		(1 << 0)
+#define PCH_PP_ON_DELAYS	0xc7208
+#define  PANEL_PORT_SELECT_MASK	(3 << 30)
+#define  PANEL_PORT_SELECT_LVDS	(0 << 30)
+#define  PANEL_PORT_SELECT_DPA	(1 << 30)
+#define  EDP_PANEL		(1 << 30)
+#define  PANEL_PORT_SELECT_DPC	(2 << 30)
+#define  PANEL_PORT_SELECT_DPD	(3 << 30)
+#define  PANEL_POWER_UP_DELAY_MASK	(0x1fff0000)
+#define  PANEL_POWER_UP_DELAY_SHIFT	16
+#define  PANEL_LIGHT_ON_DELAY_MASK	(0x1fff)
+#define  PANEL_LIGHT_ON_DELAY_SHIFT	0
+
+#define PCH_PP_OFF_DELAYS	0xc720c
+#define  PANEL_POWER_PORT_SELECT_MASK	(0x3 << 30)
+#define  PANEL_POWER_PORT_LVDS		(0 << 30)
+#define  PANEL_POWER_PORT_DP_A		(1 << 30)
+#define  PANEL_POWER_PORT_DP_C		(2 << 30)
+#define  PANEL_POWER_PORT_DP_D		(3 << 30)
+#define  PANEL_POWER_DOWN_DELAY_MASK	(0x1fff0000)
+#define  PANEL_POWER_DOWN_DELAY_SHIFT	16
+#define  PANEL_LIGHT_OFF_DELAY_MASK	(0x1fff)
+#define  PANEL_LIGHT_OFF_DELAY_SHIFT	0
+
+#define PCH_PP_DIVISOR		0xc7210
+#define  PP_REFERENCE_DIVIDER_MASK	(0xffffff00)
+#define  PP_REFERENCE_DIVIDER_SHIFT	8
+#define  PANEL_POWER_CYCLE_DELAY_MASK	(0x1f)
+#define  PANEL_POWER_CYCLE_DELAY_SHIFT	0
+
+#define PCH_DP_B		0xe4100
+#define PCH_DPB_AUX_CH_CTL	0xe4110
+#define PCH_DPB_AUX_CH_DATA1	0xe4114
+#define PCH_DPB_AUX_CH_DATA2	0xe4118
+#define PCH_DPB_AUX_CH_DATA3	0xe411c
+#define PCH_DPB_AUX_CH_DATA4	0xe4120
+#define PCH_DPB_AUX_CH_DATA5	0xe4124
+
+#define PCH_DP_C		0xe4200
+#define PCH_DPC_AUX_CH_CTL	0xe4210
+#define PCH_DPC_AUX_CH_DATA1	0xe4214
+#define PCH_DPC_AUX_CH_DATA2	0xe4218
+#define PCH_DPC_AUX_CH_DATA3	0xe421c
+#define PCH_DPC_AUX_CH_DATA4	0xe4220
+#define PCH_DPC_AUX_CH_DATA5	0xe4224
+
+#define PCH_DP_D		0xe4300
+#define PCH_DPD_AUX_CH_CTL	0xe4310
+#define PCH_DPD_AUX_CH_DATA1	0xe4314
+#define PCH_DPD_AUX_CH_DATA2	0xe4318
+#define PCH_DPD_AUX_CH_DATA3	0xe431c
+#define PCH_DPD_AUX_CH_DATA4	0xe4320
+#define PCH_DPD_AUX_CH_DATA5	0xe4324
+
+#endif /* _I915_REG_H_ */
diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c
index 9f85102..36d4b23 100644
--- a/drivers/video/ipu_common.c
+++ b/drivers/video/ipu_common.c
@@ -19,6 +19,7 @@
 #include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
+#include <div64.h>
 #include "ipu.h"
 #include "ipu_regs.h"
 
@@ -275,50 +276,84 @@
 
 static void ipu_pixel_clk_recalc(struct clk *clk)
 {
-	u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
-	if (div == 0)
-		clk->rate = 0;
-	else
-		clk->rate = (clk->parent->rate * 16) / div;
+	u32 div;
+	u64 final_rate = (unsigned long long)clk->parent->rate * 16;
+
+	div = __raw_readl(DI_BS_CLKGEN0(clk->id));
+	debug("read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\n",
+	      div, final_rate, clk->parent->rate);
+
+	clk->rate = 0;
+	if (div != 0) {
+		do_div(final_rate, div);
+		clk->rate = final_rate;
+	}
 }
 
 static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,
 	unsigned long rate)
 {
-	u32 div, div1;
-	u32 tmp;
+	u64 div, final_rate;
+	u32 remainder;
+	u64 parent_rate = (unsigned long long)clk->parent->rate * 16;
+
 	/*
 	 * Calculate divider
 	 * Fractional part is 4 bits,
 	 * so simply multiply by 2^4 to get fractional part.
 	 */
-	tmp = (clk->parent->rate * 16);
-	div = tmp / rate;
-
+	div = parent_rate;
+	remainder = do_div(div, rate);
+	/* Round the divider value */
+	if (remainder > (rate / 2))
+		div++;
 	if (div < 0x10)            /* Min DI disp clock divider is 1 */
 		div = 0x10;
 	if (div & ~0xFEF)
 		div &= 0xFF8;
 	else {
-		div1 = div & 0xFE0;
-		if ((tmp/div1 - tmp/div) < rate / 4)
-			div = div1;
-		else
-			div &= 0xFF8;
+		/* Round up divider if it gets us closer to desired pix clk */
+		if ((div & 0xC) == 0xC) {
+			div += 0x10;
+			div &= ~0xF;
+		}
 	}
-	return (clk->parent->rate * 16) / div;
+	final_rate = parent_rate;
+	do_div(final_rate, div);
+
+	return final_rate;
 }
 
 static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
 {
-	u32 div = (clk->parent->rate * 16) / rate;
+	u64 div, parent_rate;
+	u32 remainder;
+
+	parent_rate = (unsigned long long)clk->parent->rate * 16;
+	div = parent_rate;
+	remainder = do_div(div, rate);
+	/* Round the divider value */
+	if (remainder > (rate / 2))
+		div++;
+
+	/* Round up divider if it gets us closer to desired pix clk */
+	if ((div & 0xC) == 0xC) {
+		div += 0x10;
+		div &= ~0xF;
+	}
+	if (div > 0x1000)
+		debug("Overflow, DI_BS_CLKGEN0 div:0x%x\n", (u32)div);
 
 	__raw_writel(div, DI_BS_CLKGEN0(clk->id));
 
-	/* Setup pixel clock timing */
+	/*
+	 * Setup pixel clock timing
+	 * Down time is half of period
+	 */
 	__raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
 
-	clk->rate = (clk->parent->rate * 16) / div;
+	clk->rate = (u64)(clk->parent->rate * 16) / div;
+
 	return 0;
 }
 
diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile
index 0e9a8ac..7962f86 100644
--- a/drivers/video/rockchip/Makefile
+++ b/drivers/video/rockchip/Makefile
@@ -5,4 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += rk_edp.o rk_hdmi.o rk_vop.o
+obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o
diff --git a/drivers/video/rockchip/rk_lvds.c b/drivers/video/rockchip/rk_lvds.c
new file mode 100644
index 0000000..dc10b86
--- /dev/null
+++ b/drivers/video/rockchip/rk_lvds.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright 2016 Rockchip Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <display.h>
+#include <dm.h>
+#include <edid.h>
+#include <panel.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/lvds_rk3288.h>
+#include <asm/arch/grf_rk3288.h>
+#include <dt-bindings/clock/rk3288-cru.h>
+#include <dt-bindings/video/rk3288.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * struct rk_lvds_priv - private rockchip lvds display driver info
+ *
+ * @reg: LVDS register address
+ * @grf: GRF register
+ * @panel: Panel device that is used in driver
+ *
+ * @output: Output mode, decided single or double channel,
+ *		LVDS or LVTLL
+ * @format: Data format that RGB data will packing as
+ */
+struct rk_lvds_priv {
+	void __iomem *regs;
+	struct rk3288_grf *grf;
+	struct udevice *panel;
+
+	int output;
+	int format;
+};
+
+static inline void lvds_writel(struct rk_lvds_priv *lvds, u32 offset, u32 val)
+{
+	writel(val, lvds->regs + offset);
+
+	writel(val, lvds->regs + offset + 0x100);
+}
+
+int rk_lvds_enable(struct udevice *dev, int panel_bpp,
+		   const struct display_timing *edid)
+{
+	struct rk_lvds_priv *priv = dev_get_priv(dev);
+	struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
+	int ret = 0;
+	unsigned int val = 0;
+
+	ret = panel_enable_backlight(priv->panel);
+	if (ret) {
+		debug("%s: backlight error: %d\n", __func__, ret);
+		return ret;
+	}
+
+	/* Select the video source */
+	if (uc_plat->source_id)
+		val = RK3288_LVDS_SOC_CON6_SEL_VOP_LIT |
+		    (RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16);
+	else
+		val = RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16;
+	rk_setreg(&priv->grf->soc_con6, val);
+
+	/* Select data transfer format */
+	val = priv->format;
+	if (priv->output == LVDS_OUTPUT_DUAL)
+		val |= LVDS_DUAL | LVDS_CH0_EN | LVDS_CH1_EN;
+	else if (priv->output == LVDS_OUTPUT_SINGLE)
+		val |= LVDS_CH0_EN;
+	else if (priv->output == LVDS_OUTPUT_RGB)
+		val |= LVDS_TTL_EN | LVDS_CH0_EN | LVDS_CH1_EN;
+	val |= (0xffff << 16);
+	rk_setreg(&priv->grf->soc_con7, val);
+
+	/* Enable LVDS PHY */
+	if (priv->output == LVDS_OUTPUT_RGB) {
+		lvds_writel(priv, RK3288_LVDS_CH0_REG0,
+			    RK3288_LVDS_CH0_REG0_TTL_EN |
+			    RK3288_LVDS_CH0_REG0_LANECK_EN |
+			    RK3288_LVDS_CH0_REG0_LANE4_EN |
+			    RK3288_LVDS_CH0_REG0_LANE3_EN |
+			    RK3288_LVDS_CH0_REG0_LANE2_EN |
+			    RK3288_LVDS_CH0_REG0_LANE1_EN |
+			    RK3288_LVDS_CH0_REG0_LANE0_EN);
+		lvds_writel(priv, RK3288_LVDS_CH0_REG2,
+			    RK3288_LVDS_PLL_FBDIV_REG2(0x46));
+
+		lvds_writel(priv, RK3288_LVDS_CH0_REG3,
+			    RK3288_LVDS_PLL_FBDIV_REG3(0x46));
+		lvds_writel(priv, RK3288_LVDS_CH0_REG4,
+			    RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE |
+			    RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE |
+			    RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE |
+			    RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE |
+			    RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE |
+			    RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE);
+		lvds_writel(priv, RK3288_LVDS_CH0_REG5,
+			    RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA |
+			    RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA |
+			    RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA |
+			    RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA |
+			    RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA |
+			    RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA);
+		lvds_writel(priv, RK3288_LVDS_CH0_REGD,
+			    RK3288_LVDS_PLL_PREDIV_REGD(0x0a));
+		lvds_writel(priv, RK3288_LVDS_CH0_REG20,
+			    RK3288_LVDS_CH0_REG20_LSB);
+	} else {
+		lvds_writel(priv, RK3288_LVDS_CH0_REG0,
+			    RK3288_LVDS_CH0_REG0_LVDS_EN |
+			    RK3288_LVDS_CH0_REG0_LANECK_EN |
+			    RK3288_LVDS_CH0_REG0_LANE4_EN |
+			    RK3288_LVDS_CH0_REG0_LANE3_EN |
+			    RK3288_LVDS_CH0_REG0_LANE2_EN |
+			    RK3288_LVDS_CH0_REG0_LANE1_EN |
+			    RK3288_LVDS_CH0_REG0_LANE0_EN);
+		lvds_writel(priv, RK3288_LVDS_CH0_REG1,
+			    RK3288_LVDS_CH0_REG1_LANECK_BIAS |
+			    RK3288_LVDS_CH0_REG1_LANE4_BIAS |
+			    RK3288_LVDS_CH0_REG1_LANE3_BIAS |
+			    RK3288_LVDS_CH0_REG1_LANE2_BIAS |
+			    RK3288_LVDS_CH0_REG1_LANE1_BIAS |
+			    RK3288_LVDS_CH0_REG1_LANE0_BIAS);
+		lvds_writel(priv, RK3288_LVDS_CH0_REG2,
+			    RK3288_LVDS_CH0_REG2_RESERVE_ON |
+			    RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE |
+			    RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE |
+			    RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE |
+			    RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE |
+			    RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE |
+			    RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE |
+			    RK3288_LVDS_PLL_FBDIV_REG2(0x46));
+		lvds_writel(priv, RK3288_LVDS_CH0_REG3,
+			    RK3288_LVDS_PLL_FBDIV_REG3(0x46));
+		lvds_writel(priv, RK3288_LVDS_CH0_REG4, 0x00);
+		lvds_writel(priv, RK3288_LVDS_CH0_REG5, 0x00);
+		lvds_writel(priv, RK3288_LVDS_CH0_REGD,
+			    RK3288_LVDS_PLL_PREDIV_REGD(0x0a));
+		lvds_writel(priv, RK3288_LVDS_CH0_REG20,
+			    RK3288_LVDS_CH0_REG20_LSB);
+	}
+
+	/* Power on */
+	writel(RK3288_LVDS_CFG_REGC_PLL_ENABLE,
+	       priv->regs + RK3288_LVDS_CFG_REGC);
+
+	writel(RK3288_LVDS_CFG_REG21_TX_ENABLE,
+	       priv->regs + RK3288_LVDS_CFG_REG21);
+
+	return 0;
+}
+
+int rk_lvds_read_timing(struct udevice *dev, struct display_timing *timing)
+{
+	if (fdtdec_decode_display_timing
+	    (gd->fdt_blob, dev->of_offset, 0, timing)) {
+		debug("%s: Failed to decode display timing\n", __func__);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int rk_lvds_ofdata_to_platdata(struct udevice *dev)
+{
+	struct rk_lvds_priv *priv = dev_get_priv(dev);
+	const void *blob = gd->fdt_blob;
+	int node = dev->of_offset;
+	int ret;
+	priv->regs = (void *)dev_get_addr(dev);
+	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+	ret = fdtdec_get_int(blob, node, "rockchip,output", -1);
+	if (ret != -1) {
+		priv->output = ret;
+		debug("LVDS output : %d\n", ret);
+	} else {
+		/* default set it as output rgb */
+		priv->output = LVDS_OUTPUT_RGB;
+	}
+
+	ret = fdtdec_get_int(blob, node, "rockchip,data-mapping", -1);
+	if (ret != -1) {
+		priv->format = ret;
+		debug("LVDS data-mapping : %d\n", ret);
+	} else {
+		/* default set it as format jeida */
+		priv->format = LVDS_FORMAT_JEIDA;
+	}
+
+	ret = fdtdec_get_int(blob, node, "rockchip,data-width", -1);
+	if (ret != -1) {
+		debug("LVDS data-width : %d\n", ret);
+		if (ret == 24) {
+			priv->format |= LVDS_24BIT;
+		} else if (ret == 18) {
+			priv->format |= LVDS_18BIT;
+		} else {
+			debug("rockchip-lvds unsupport data-width[%d]\n", ret);
+			ret = -EINVAL;
+			return ret;
+		}
+	} else {
+		priv->format |= LVDS_24BIT;
+	}
+
+	return 0;
+}
+
+int rk_lvds_probe(struct udevice *dev)
+{
+	struct rk_lvds_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
+					   &priv->panel);
+	if (ret) {
+		debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
+		      dev->name, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct dm_display_ops lvds_rockchip_ops = {
+	.read_timing = rk_lvds_read_timing,
+	.enable = rk_lvds_enable,
+};
+
+static const struct udevice_id rockchip_lvds_ids[] = {
+	{.compatible = "rockchip,rk3288-lvds"},
+	{}
+};
+
+U_BOOT_DRIVER(lvds_rockchip) = {
+	.name	= "lvds_rockchip",
+	.id	= UCLASS_DISPLAY,
+	.of_match = rockchip_lvds_ids,
+	.ops	= &lvds_rockchip_ops,
+	.ofdata_to_platdata	= rk_lvds_ofdata_to_platdata,
+	.probe	= rk_lvds_probe,
+	.priv_auto_alloc_size	= sizeof(struct rk_lvds_priv),
+};
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index adbc68f..a54af17 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -102,6 +102,7 @@
 	u32 hfront_porch = edid->hfront_porch.typ;
 	u32 vfront_porch = edid->vfront_porch.typ;
 	uint flags;
+	int mode_flags;
 
 	switch (mode) {
 	case VOP_MODE_HDMI:
@@ -113,9 +114,20 @@
 		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
 				V_EDP_OUT_EN(1));
 		break;
+	case VOP_MODE_LVDS:
+		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
+				V_RGB_OUT_EN(1));
+		break;
 	}
 
-	flags = V_DSP_OUT_MODE(15) |
+	if (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP)
+		/* RGBaaa */
+		mode_flags = 15;
+	else
+		/* RGB888 */
+		mode_flags = 0;
+
+	flags = V_DSP_OUT_MODE(mode_flags) |
 		V_DSP_HSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)) |
 		V_DSP_VSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_VSYNC_HIGH));
 
@@ -227,7 +239,7 @@
 
 	ret = rkclk_get_clk(CLK_NEW, &clk);
 	if (!ret) {
-		ret = clk_set_periph_rate(clk, DCLK_VOP0 + vop_id,
+		ret = clk_set_periph_rate(clk, DCLK_VOP0 + remote_vop_id,
 					  timing.pixelclock.typ);
 	}
 	if (ret) {
diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c
index c73f242..6219300 100644
--- a/drivers/video/simple_panel.c
+++ b/drivers/video/simple_panel.c
@@ -38,13 +38,15 @@
 	struct simple_panel_priv *priv = dev_get_priv(dev);
 	int ret;
 
-	ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
-					   "power-supply", &priv->reg);
-	if (ret) {
-		debug("%s: Warning: cnnot get power supply: ret=%d\n",
-		      __func__, ret);
-		if (ret != -ENOENT)
-			return ret;
+	if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
+		ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
+						   "power-supply", &priv->reg);
+		if (ret) {
+			debug("%s: Warning: cnnot get power supply: ret=%d\n",
+			      __func__, ret);
+			if (ret != -ENOENT)
+				return ret;
+		}
 	}
 	ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
 					   "backlight", &priv->backlight);
@@ -69,7 +71,7 @@
 	struct simple_panel_priv *priv = dev_get_priv(dev);
 	int ret;
 
-	if (priv->reg) {
+	if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
 		debug("%s: Enable regulator '%s'\n", __func__, priv->reg->name);
 		ret = regulator_set_enable(priv->reg, true);
 		if (ret)
diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c
index 832e90a..c8cc05e 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -240,8 +240,7 @@
 	if (argc != 3)
 		return CMD_RET_USAGE;
 
-	uclass_first_device(UCLASS_VIDEO_CONSOLE, &dev);
-	if (!dev)
+	if (uclass_first_device_err(UCLASS_VIDEO_CONSOLE, &dev))
 		return CMD_RET_FAILURE;
 	col = simple_strtoul(argv[1], NULL, 10);
 	row = simple_strtoul(argv[2], NULL, 10);
@@ -259,8 +258,7 @@
 	if (argc != 2)
 		return CMD_RET_USAGE;
 
-	uclass_first_device(UCLASS_VIDEO_CONSOLE, &dev);
-	if (!dev)
+	if (uclass_first_device_err(UCLASS_VIDEO_CONSOLE, &dev))
 		return CMD_RET_FAILURE;
 	for (s = argv[1]; *s; s++)
 		vidconsole_put_char(dev, *s);
diff --git a/dts/Kconfig b/dts/Kconfig
index d639be9..d585009 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -53,11 +53,22 @@
 
 config DEFAULT_DEVICE_TREE
 	string "Default Device Tree for DT control"
+	depends on OF_CONTROL
 	help
 	  This option specifies the default Device Tree used for DT control.
 	  It can be overridden from the command line:
 	  $ make DEVICE_TREE=<device-tree-name>
 
+config OF_LIST
+	string "List of device tree files to include for DT control"
+	depends on SPL_LOAD_FIT
+	help
+	  This option specifies a list of device tree files to use for DT
+	  control. These will be packaged into a FIT. At run-time, SPL will
+	  select the correct DT to use by examining the hardware (e.g.
+	  reading a board ID value). This is a list of device tree files
+	  (without the directory or .dtb suffix) separated by <space>.
+
 config OF_SPL_REMOVE_PROPS
 	string "List of device tree properties to drop for SPL"
 	depends on SPL_OF_CONTROL
diff --git a/fs/ext4/dev.c b/fs/ext4/dev.c
index 9fd10de..ee84d3f 100644
--- a/fs/ext4/dev.c
+++ b/fs/ext4/dev.c
@@ -24,6 +24,7 @@
  */
 
 #include <common.h>
+#include <blk.h>
 #include <config.h>
 #include <memalign.h>
 #include <ext4fs.h>
@@ -32,13 +33,13 @@
 
 lbaint_t part_offset;
 
-static block_dev_desc_t *ext4fs_block_dev_desc;
+static struct blk_desc *ext4fs_blk_desc;
 static disk_partition_t *part_info;
 
-void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info)
+void ext4fs_set_blk_dev(struct blk_desc *rbdd, disk_partition_t *info)
 {
 	assert(rbdd->blksz == (1 << rbdd->log2blksz));
-	ext4fs_block_dev_desc = rbdd;
+	ext4fs_blk_desc = rbdd;
 	get_fs()->dev_desc = rbdd;
 	part_info = info;
 	part_offset = info->start;
@@ -49,11 +50,11 @@
 int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf)
 {
 	unsigned block_len;
-	int log2blksz = ext4fs_block_dev_desc->log2blksz;
-	ALLOC_CACHE_ALIGN_BUFFER(char, sec_buf, (ext4fs_block_dev_desc ?
-						 ext4fs_block_dev_desc->blksz :
+	int log2blksz = ext4fs_blk_desc->log2blksz;
+	ALLOC_CACHE_ALIGN_BUFFER(char, sec_buf, (ext4fs_blk_desc ?
+						 ext4fs_blk_desc->blksz :
 						 0));
-	if (ext4fs_block_dev_desc == NULL) {
+	if (ext4fs_blk_desc == NULL) {
 		printf("** Invalid Block Device Descriptor (NULL)\n");
 		return 0;
 	}
@@ -69,21 +70,19 @@
 
 	/* Get the read to the beginning of a partition */
 	sector += byte_offset >> log2blksz;
-	byte_offset &= ext4fs_block_dev_desc->blksz - 1;
+	byte_offset &= ext4fs_blk_desc->blksz - 1;
 
 	debug(" <" LBAFU ", %d, %d>\n", sector, byte_offset, byte_len);
 
 	if (byte_offset != 0) {
 		int readlen;
 		/* read first part which isn't aligned with start of sector */
-		if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc,
-						      part_info->start + sector,
-						      1, (void *)sec_buf)
-		    != 1) {
+		if (blk_dread(ext4fs_blk_desc, part_info->start + sector, 1,
+			      (void *)sec_buf) != 1) {
 			printf(" ** ext2fs_devread() read error **\n");
 			return 0;
 		}
-		readlen = min((int)ext4fs_block_dev_desc->blksz - byte_offset,
+		readlen = min((int)ext4fs_blk_desc->blksz - byte_offset,
 			      byte_len);
 		memcpy(buf, sec_buf + byte_offset, readlen);
 		buf += readlen;
@@ -95,38 +94,33 @@
 		return 1;
 
 	/* read sector aligned part */
-	block_len = byte_len & ~(ext4fs_block_dev_desc->blksz - 1);
+	block_len = byte_len & ~(ext4fs_blk_desc->blksz - 1);
 
 	if (block_len == 0) {
-		ALLOC_CACHE_ALIGN_BUFFER(u8, p, ext4fs_block_dev_desc->blksz);
+		ALLOC_CACHE_ALIGN_BUFFER(u8, p, ext4fs_blk_desc->blksz);
 
-		block_len = ext4fs_block_dev_desc->blksz;
-		ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc,
-						  part_info->start + sector,
-						  1, (void *)p);
+		block_len = ext4fs_blk_desc->blksz;
+		blk_dread(ext4fs_blk_desc, part_info->start + sector, 1,
+			  (void *)p);
 		memcpy(buf, p, byte_len);
 		return 1;
 	}
 
-	if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc,
-					      part_info->start + sector,
-					      block_len >> log2blksz,
-					      (void *)buf) !=
-					      block_len >> log2blksz) {
+	if (blk_dread(ext4fs_blk_desc, part_info->start + sector,
+		      block_len >> log2blksz, (void *)buf) !=
+			block_len >> log2blksz) {
 		printf(" ** %s read error - block\n", __func__);
 		return 0;
 	}
-	block_len = byte_len & ~(ext4fs_block_dev_desc->blksz - 1);
+	block_len = byte_len & ~(ext4fs_blk_desc->blksz - 1);
 	buf += block_len;
 	byte_len -= block_len;
-	sector += block_len / ext4fs_block_dev_desc->blksz;
+	sector += block_len / ext4fs_blk_desc->blksz;
 
 	if (byte_len != 0) {
 		/* read rest of data which are not in whole sector */
-		if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc,
-						      part_info->start + sector,
-						      1, (void *)sec_buf)
-		    != 1) {
+		if (blk_dread(ext4fs_blk_desc, part_info->start + sector, 1,
+			      (void *)sec_buf) != 1) {
 			printf("* %s read error - last part\n", __func__);
 			return 0;
 		}
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 294a46e..84fba76 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -81,29 +81,20 @@
 	}
 
 	if (remainder) {
-		if (fs->dev_desc->block_read) {
-			fs->dev_desc->block_read(fs->dev_desc,
-						 startblock, 1, sec_buf);
-			temp_ptr = sec_buf;
-			memcpy((temp_ptr + remainder),
-			       (unsigned char *)buf, size);
-			fs->dev_desc->block_write(fs->dev_desc,
-						  startblock, 1, sec_buf);
-		}
+		blk_dread(fs->dev_desc, startblock, 1, sec_buf);
+		temp_ptr = sec_buf;
+		memcpy((temp_ptr + remainder), (unsigned char *)buf, size);
+		blk_dwrite(fs->dev_desc, startblock, 1, sec_buf);
 	} else {
 		if (size >> log2blksz != 0) {
-			fs->dev_desc->block_write(fs->dev_desc,
-						  startblock,
-						  size >> log2blksz,
-						  (unsigned long *)buf);
+			blk_dwrite(fs->dev_desc, startblock, size >> log2blksz,
+				   (unsigned long *)buf);
 		} else {
-			fs->dev_desc->block_read(fs->dev_desc,
-						 startblock, 1, sec_buf);
+			blk_dread(fs->dev_desc, startblock, 1, sec_buf);
 			temp_ptr = sec_buf;
 			memcpy(temp_ptr, buf, size);
-			fs->dev_desc->block_write(fs->dev_desc,
-						  startblock, 1,
-						  (unsigned long *)sec_buf);
+			blk_dwrite(fs->dev_desc, startblock, 1,
+				   (unsigned long *)sec_buf);
 		}
 	}
 }
diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
index 258b937..43c8897 100644
--- a/fs/ext4/ext4fs.c
+++ b/fs/ext4/ext4fs.c
@@ -198,7 +198,7 @@
 	return ext4fs_read_file(ext4fs_file, 0, len, buf, actread);
 }
 
-int ext4fs_probe(block_dev_desc_t *fs_dev_desc,
+int ext4fs_probe(struct blk_desc *fs_dev_desc,
 		 disk_partition_t *fs_partition)
 {
 	ext4fs_set_blk_dev(fs_dev_desc, fs_partition);
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 472a63e..600a90e 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -10,6 +10,7 @@
  */
 
 #include <common.h>
+#include <blk.h>
 #include <config.h>
 #include <exports.h>
 #include <fat.h>
@@ -37,7 +38,7 @@
 	}
 }
 
-static block_dev_desc_t *cur_dev;
+static struct blk_desc *cur_dev;
 static disk_partition_t cur_part_info;
 
 #define DOS_BOOT_MAGIC_OFFSET	0x1fe
@@ -48,11 +49,10 @@
 {
 	ulong ret;
 
-	if (!cur_dev || !cur_dev->block_read)
+	if (!cur_dev)
 		return -1;
 
-	ret = cur_dev->block_read(cur_dev, cur_part_info.start + block,
-				  nr_blocks, buf);
+	ret = blk_dread(cur_dev, cur_part_info.start + block, nr_blocks, buf);
 
 	if (nr_blocks && ret == 0)
 		return -1;
@@ -60,7 +60,7 @@
 	return ret;
 }
 
-int fat_set_blk_dev(block_dev_desc_t *dev_desc, disk_partition_t *info)
+int fat_set_blk_dev(struct blk_desc *dev_desc, disk_partition_t *info)
 {
 	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
 
@@ -89,7 +89,7 @@
 	return -1;
 }
 
-int fat_register_device(block_dev_desc_t *dev_desc, int part_no)
+int fat_register_device(struct blk_desc *dev_desc, int part_no)
 {
 	disk_partition_t info;
 
@@ -97,10 +97,10 @@
 	cur_dev = NULL;
 
 	/* Read the partition table, if present */
-	if (get_partition_info(dev_desc, part_no, &info)) {
+	if (part_get_info(dev_desc, part_no, &info)) {
 		if (part_no != 0) {
 			printf("** Partition %d not valid on device %d **\n",
-					part_no, dev_desc->dev);
+					part_no, dev_desc->devnum);
 			return -1;
 		}
 
@@ -1284,7 +1284,7 @@
 		printf("Unknown");
 	}
 
-	printf("\n  Device %d: ", cur_dev->dev);
+	printf("\n  Device %d: ", cur_dev->devnum);
 	dev_print(cur_dev);
 #endif
 
diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
index 5ed324c..baa85ec 100644
--- a/fs/fat/fat_write.c
+++ b/fs/fat/fat_write.c
@@ -32,7 +32,7 @@
 {
 	ulong ret;
 
-	if (!cur_dev || !cur_dev->block_write)
+	if (!cur_dev)
 		return -1;
 
 	if (cur_part_info.start + block + nr_blocks >
@@ -41,8 +41,7 @@
 		return -1;
 	}
 
-	ret = cur_dev->block_write(cur_dev, cur_part_info.start + block,
-				   nr_blocks, buf);
+	ret = blk_dwrite(cur_dev, cur_part_info.start + block, nr_blocks, buf);
 	if (nr_blocks && ret == 0)
 		return -1;
 
diff --git a/fs/fs.c b/fs/fs.c
index d123d29..595ff1f 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -20,11 +20,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static block_dev_desc_t *fs_dev_desc;
+static struct blk_desc *fs_dev_desc;
 static disk_partition_t fs_partition;
 static int fs_type = FS_TYPE_ANY;
 
-static inline int fs_probe_unsupported(block_dev_desc_t *fs_dev_desc,
+static inline int fs_probe_unsupported(struct blk_desc *fs_dev_desc,
 				      disk_partition_t *fs_partition)
 {
 	printf("** Unrecognized filesystem type **\n");
@@ -81,7 +81,7 @@
 	 * filesystem.
 	 */
 	bool null_dev_desc_ok;
-	int (*probe)(block_dev_desc_t *fs_dev_desc,
+	int (*probe)(struct blk_desc *fs_dev_desc,
 		     disk_partition_t *fs_partition);
 	int (*ls)(const char *dirname);
 	int (*exists)(const char *filename);
@@ -213,7 +213,7 @@
 	}
 #endif
 
-	part = get_device_and_partition(ifname, dev_part_str, &fs_dev_desc,
+	part = blk_get_device_part_str(ifname, dev_part_str, &fs_dev_desc,
 					&fs_partition, 1);
 	if (part < 0)
 		return -1;
diff --git a/fs/reiserfs/dev.c b/fs/reiserfs/dev.c
index 7b24d6a..5a1ab0a 100644
--- a/fs/reiserfs/dev.c
+++ b/fs/reiserfs/dev.c
@@ -12,13 +12,13 @@
 
 #include "reiserfs_private.h"
 
-static block_dev_desc_t *reiserfs_block_dev_desc;
+static struct blk_desc *reiserfs_blk_desc;
 static disk_partition_t *part_info;
 
 
-void reiserfs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info)
+void reiserfs_set_blk_dev(struct blk_desc *rbdd, disk_partition_t *info)
 {
-	reiserfs_block_dev_desc = rbdd;
+	reiserfs_blk_desc = rbdd;
 	part_info = info;
 }
 
@@ -53,17 +53,15 @@
 #endif
 
 
-	if (reiserfs_block_dev_desc == NULL)
+	if (reiserfs_blk_desc == NULL)
 		return 0;
 
 
 	if (byte_offset != 0) {
 		/* read first part which isn't aligned with start of sector */
-		if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc,
-							part_info->start +
-								sector,
-							1, (void *)sec_buf)
-		    != 1) {
+		if (reiserfs_blk_desc->block_read(reiserfs_blk_desc,
+						  part_info->start + sector,
+						  1, (void *)sec_buf) != 1) {
 			printf (" ** reiserfs_devread() read error\n");
 			return 0;
 		}
@@ -75,11 +73,10 @@
 
 	/* read sector aligned part */
 	block_len = byte_len & ~(SECTOR_SIZE-1);
-	if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc,
-						part_info->start + sector,
-						block_len / SECTOR_SIZE,
-						(void *)buf)
-	    != block_len/SECTOR_SIZE) {
+	if (reiserfs_blk_desc->block_read(reiserfs_blk_desc,
+					  part_info->start + sector,
+					  block_len / SECTOR_SIZE, (void *)buf)
+			!= block_len/SECTOR_SIZE) {
 		printf (" ** reiserfs_devread() read error - block\n");
 		return 0;
 	}
@@ -89,11 +86,9 @@
 
 	if ( byte_len != 0 ) {
 		/* read rest of data which are not in whole sector */
-		if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc,
-							part_info->start +
-							    sector,
-							1, (void *)sec_buf)
-		    != 1) {
+		if (reiserfs_blk_desc->block_read(reiserfs_blk_desc,
+						  part_info->start + sector,
+						  1, (void *)sec_buf) != 1) {
 			printf (" ** reiserfs_devread() read error - last part\n");
 			return 0;
 		}
diff --git a/fs/sandbox/sandboxfs.c b/fs/sandbox/sandboxfs.c
index 5acfc03..2703eed 100644
--- a/fs/sandbox/sandboxfs.c
+++ b/fs/sandbox/sandboxfs.c
@@ -8,10 +8,10 @@
 #include <fs.h>
 #include <os.h>
 
-int sandbox_fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info)
+int sandbox_fs_set_blk_dev(struct blk_desc *rbdd, disk_partition_t *info)
 {
 	/*
-	 * Only accept a NULL block_dev_desc_t for the sandbox, which is when
+	 * Only accept a NULL struct blk_desc for the sandbox, which is when
 	 * hostfs interface is used
 	 */
 	return rbdd != NULL;
diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c
index a992a00..cdc04c6 100644
--- a/fs/ubifs/ubifs.c
+++ b/fs/ubifs/ubifs.c
@@ -561,7 +561,7 @@
 	return 0;
 }
 
-int ubifs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info)
+int ubifs_set_blk_dev(struct blk_desc *rbdd, disk_partition_t *info)
 {
 	if (rbdd) {
 		debug("UBIFS cannot be used with normal block devices\n");
@@ -569,7 +569,7 @@
 	}
 
 	/*
-	 * Should never happen since get_device_and_partition() already checks
+	 * Should never happen since blk_get_device_part_str() already checks
 	 * this, but better safe then sorry.
 	 */
 	if (!ubifs_is_mounted()) {
diff --git a/fs/zfs/dev.c b/fs/zfs/dev.c
index 67d1265..2f409e6 100644
--- a/fs/zfs/dev.c
+++ b/fs/zfs/dev.c
@@ -13,12 +13,12 @@
 #include <config.h>
 #include <zfs_common.h>
 
-static block_dev_desc_t *zfs_block_dev_desc;
+static struct blk_desc *zfs_blk_desc;
 static disk_partition_t *part_info;
 
-void zfs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info)
+void zfs_set_blk_dev(struct blk_desc *rbdd, disk_partition_t *info)
 {
-	zfs_block_dev_desc = rbdd;
+	zfs_blk_desc = rbdd;
 	part_info = info;
 }
 
@@ -48,17 +48,16 @@
 
 	debug(" <%d, %d, %d>\n", sector, byte_offset, byte_len);
 
-	if (zfs_block_dev_desc == NULL) {
+	if (zfs_blk_desc == NULL) {
 		printf("** Invalid Block Device Descriptor (NULL)\n");
 		return 1;
 	}
 
 	if (byte_offset != 0) {
 		/* read first part which isn't aligned with start of sector */
-		if (zfs_block_dev_desc->block_read(zfs_block_dev_desc,
-						   part_info->start + sector, 1,
-						   (void *)sec_buf)
-		    != 1) {
+		if (zfs_blk_desc->block_read(zfs_blk_desc,
+					     part_info->start + sector, 1,
+					     (void *)sec_buf) != 1) {
 			printf(" ** zfs_devread() read error **\n");
 			return 1;
 		}
@@ -79,18 +78,16 @@
 		u8 p[SECTOR_SIZE];
 
 		block_len = SECTOR_SIZE;
-		zfs_block_dev_desc->block_read(zfs_block_dev_desc,
-					       part_info->start + sector,
-					       1, (void *)p);
+		zfs_blk_desc->block_read(zfs_blk_desc,
+					 part_info->start + sector,
+					 1, (void *)p);
 		memcpy(buf, p, byte_len);
 		return 0;
 	}
 
-	if (zfs_block_dev_desc->block_read(zfs_block_dev_desc,
-					   part_info->start + sector,
-					   block_len / SECTOR_SIZE,
-					   (void *)buf)
-	    != block_len / SECTOR_SIZE) {
+	if (zfs_blk_desc->block_read(zfs_blk_desc, part_info->start + sector,
+				     block_len / SECTOR_SIZE,
+				     (void *)buf) != block_len / SECTOR_SIZE) {
 		printf(" ** zfs_devread() read error - block\n");
 		return 1;
 	}
@@ -102,9 +99,9 @@
 
 	if (byte_len != 0) {
 		/* read rest of data which are not in whole sector */
-		if (zfs_block_dev_desc->block_read(zfs_block_dev_desc,
-						   part_info->start + sector,
-						   1, (void *)sec_buf) != 1) {
+		if (zfs_blk_desc->block_read(zfs_blk_desc,
+					     part_info->start + sector,
+					     1, (void *)sec_buf) != 1) {
 			printf(" ** zfs_devread() read error - last part\n");
 			return 1;
 		}
diff --git a/fs/zfs/zfs.c b/fs/zfs/zfs.c
index fb2b3ee..ca67afb 100644
--- a/fs/zfs/zfs.c
+++ b/fs/zfs/zfs.c
@@ -20,7 +20,7 @@
 #include "zfs_common.h"
 #include "div64.h"
 
-block_dev_desc_t *zfs_dev_desc;
+struct blk_desc *zfs_dev_desc;
 
 /*
  * The zfs plug-in routines for GRUB are:
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 0af599f..68b5f0b 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -133,7 +133,7 @@
  *		previously returned by gpio_request_by_name()
  * @return true if valid, false if not
  */
-static inline bool dm_gpio_is_valid(struct gpio_desc *desc)
+static inline bool dm_gpio_is_valid(const struct gpio_desc *desc)
 {
 	return desc->dev != NULL;
 }
@@ -360,6 +360,18 @@
 int gpio_get_values_as_int(const int *gpio_list);
 
 /**
+ * dm_gpio_get_values_as_int() - Turn the values of a list of GPIOs into an int
+ *
+ * This puts the value of the first GPIO into bit 0, the second into bit 1,
+ * etc. then returns the resulting integer.
+ *
+ * @desc_list: List of GPIOs to collect
+ * @count: Number of GPIOs
+ * @return resulting integer value, or -ve on error
+ */
+int dm_gpio_get_values_as_int(const struct gpio_desc *desc_list, int count);
+
+/**
  * gpio_claim_vector() - claim a number of GPIOs for input
  *
  * @gpio_num_array:	array of gpios to claim, terminated by -1
@@ -524,9 +536,9 @@
  *		previously returned by gpio_request_by_name()
  * @return GPIO value (0 for inactive, 1 for active) or -ve on error
  */
-int dm_gpio_get_value(struct gpio_desc *desc);
+int dm_gpio_get_value(const struct gpio_desc *desc);
 
-int dm_gpio_set_value(struct gpio_desc *desc, int value);
+int dm_gpio_set_value(const struct gpio_desc *desc, int value);
 
 /**
  * dm_gpio_set_dir() - Set the direction for a GPIO
@@ -565,6 +577,6 @@
  *		previously returned by gpio_request_by_name()
  * @return GPIO number, or -ve if not found
  */
-int gpio_get_number(struct gpio_desc *desc);
+int gpio_get_number(const struct gpio_desc *desc);
 
 #endif	/* _ASM_GENERIC_GPIO_H_ */
diff --git a/include/blk.h b/include/blk.h
new file mode 100644
index 0000000..e83c144
--- /dev/null
+++ b/include/blk.h
@@ -0,0 +1,248 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef BLK_H
+#define BLK_H
+
+#ifdef CONFIG_SYS_64BIT_LBA
+typedef uint64_t lbaint_t;
+#define LBAFlength "ll"
+#else
+typedef ulong lbaint_t;
+#define LBAFlength "l"
+#endif
+#define LBAF "%" LBAFlength "x"
+#define LBAFU "%" LBAFlength "u"
+
+/* Interface types: */
+enum if_type {
+	IF_TYPE_UNKNOWN = 0,
+	IF_TYPE_IDE,
+	IF_TYPE_SCSI,
+	IF_TYPE_ATAPI,
+	IF_TYPE_USB,
+	IF_TYPE_DOC,
+	IF_TYPE_MMC,
+	IF_TYPE_SD,
+	IF_TYPE_SATA,
+	IF_TYPE_HOST,
+
+	IF_TYPE_COUNT,			/* Number of interface types */
+};
+
+/*
+ * With driver model (CONFIG_BLK) this is uclass platform data, accessible
+ * with dev_get_uclass_platdata(dev)
+ */
+struct blk_desc {
+	/*
+	 * TODO: With driver model we should be able to use the parent
+	 * device's uclass instead.
+	 */
+	enum if_type	if_type;	/* type of the interface */
+	int		devnum;		/* device number */
+	unsigned char	part_type;	/* partition type */
+	unsigned char	target;		/* target SCSI ID */
+	unsigned char	lun;		/* target LUN */
+	unsigned char	hwpart;		/* HW partition, e.g. for eMMC */
+	unsigned char	type;		/* device type */
+	unsigned char	removable;	/* removable device */
+#ifdef CONFIG_LBA48
+	/* device can use 48bit addr (ATA/ATAPI v7) */
+	unsigned char	lba48;
+#endif
+	lbaint_t	lba;		/* number of blocks */
+	unsigned long	blksz;		/* block size */
+	int		log2blksz;	/* for convenience: log2(blksz) */
+	char		vendor[40+1];	/* IDE model, SCSI Vendor */
+	char		product[20+1];	/* IDE Serial no, SCSI product */
+	char		revision[8+1];	/* firmware revision */
+#ifdef CONFIG_BLK
+	struct udevice *bdev;
+#else
+	unsigned long	(*block_read)(struct blk_desc *block_dev,
+				      lbaint_t start,
+				      lbaint_t blkcnt,
+				      void *buffer);
+	unsigned long	(*block_write)(struct blk_desc *block_dev,
+				       lbaint_t start,
+				       lbaint_t blkcnt,
+				       const void *buffer);
+	unsigned long	(*block_erase)(struct blk_desc *block_dev,
+				       lbaint_t start,
+				       lbaint_t blkcnt);
+	void		*priv;		/* driver private struct pointer */
+#endif
+};
+
+#define BLOCK_CNT(size, blk_desc) (PAD_COUNT(size, blk_desc->blksz))
+#define PAD_TO_BLOCKSIZE(size, blk_desc) \
+	(PAD_SIZE(size, blk_desc->blksz))
+
+#ifdef CONFIG_BLK
+struct udevice;
+
+/* Operations on block devices */
+struct blk_ops {
+	/**
+	 * read() - read from a block device
+	 *
+	 * @dev:	Device to read from
+	 * @start:	Start block number to read (0=first)
+	 * @blkcnt:	Number of blocks to read
+	 * @buffer:	Destination buffer for data read
+	 * @return number of blocks read, or -ve error number (see the
+	 * IS_ERR_VALUE() macro
+	 */
+	unsigned long (*read)(struct udevice *dev, lbaint_t start,
+			      lbaint_t blkcnt, void *buffer);
+
+	/**
+	 * write() - write to a block device
+	 *
+	 * @dev:	Device to write to
+	 * @start:	Start block number to write (0=first)
+	 * @blkcnt:	Number of blocks to write
+	 * @buffer:	Source buffer for data to write
+	 * @return number of blocks written, or -ve error number (see the
+	 * IS_ERR_VALUE() macro
+	 */
+	unsigned long (*write)(struct udevice *dev, lbaint_t start,
+			       lbaint_t blkcnt, const void *buffer);
+
+	/**
+	 * erase() - erase a section of a block device
+	 *
+	 * @dev:	Device to (partially) erase
+	 * @start:	Start block number to erase (0=first)
+	 * @blkcnt:	Number of blocks to erase
+	 * @return number of blocks erased, or -ve error number (see the
+	 * IS_ERR_VALUE() macro
+	 */
+	unsigned long (*erase)(struct udevice *dev, lbaint_t start,
+			       lbaint_t blkcnt);
+};
+
+#define blk_get_ops(dev)	((struct blk_ops *)(dev)->driver->ops)
+
+/*
+ * These functions should take struct udevice instead of struct blk_desc,
+ * but this is convenient for migration to driver model. Add a 'd' prefix
+ * to the function operations, so that blk_read(), etc. can be reserved for
+ * functions with the correct arguments.
+ */
+unsigned long blk_dread(struct blk_desc *block_dev, lbaint_t start,
+			lbaint_t blkcnt, void *buffer);
+unsigned long blk_dwrite(struct blk_desc *block_dev, lbaint_t start,
+			 lbaint_t blkcnt, const void *buffer);
+unsigned long blk_derase(struct blk_desc *block_dev, lbaint_t start,
+			 lbaint_t blkcnt);
+
+/**
+ * blk_get_device() - Find and probe a block device ready for use
+ *
+ * @if_type:	Interface type (enum if_type_t)
+ * @devnum:	Device number (specific to each interface type)
+ * @devp:	the device, if found
+ * @return - if found, -ENODEV if no device found, or other -ve error value
+ */
+int blk_get_device(int if_type, int devnum, struct udevice **devp);
+
+/**
+ * blk_first_device() - Find the first device for a given interface
+ *
+ * The device is probed ready for use
+ *
+ * @devnum:	Device number (specific to each interface type)
+ * @devp:	the device, if found
+ * @return 0 if found, -ENODEV if no device, or other -ve error value
+ */
+int blk_first_device(int if_type, struct udevice **devp);
+
+/**
+ * blk_next_device() - Find the next device for a given interface
+ *
+ * This can be called repeatedly after blk_first_device() to iterate through
+ * all devices of the given interface type.
+ *
+ * The device is probed ready for use
+ *
+ * @devp:	On entry, the previous device returned. On exit, the next
+ *		device, if found
+ * @return 0 if found, -ENODEV if no device, or other -ve error value
+ */
+int blk_next_device(struct udevice **devp);
+
+/**
+ * blk_create_device() - Create a new block device
+ *
+ * @parent:	Parent of the new device
+ * @drv_name:	Driver name to use for the block device
+ * @name:	Name for the device
+ * @if_type:	Interface type (enum if_type_t)
+ * @devnum:	Device number, specific to the interface type
+ * @blksz:	Block size of the device in bytes (typically 512)
+ * @size:	Total size of the device in bytes
+ * @devp:	the new device (which has not been probed)
+ */
+int blk_create_device(struct udevice *parent, const char *drv_name,
+		      const char *name, int if_type, int devnum, int blksz,
+		      lbaint_t size, struct udevice **devp);
+
+/**
+ * blk_prepare_device() - Prepare a block device for use
+ *
+ * This reads partition information from the device if supported.
+ *
+ * @dev:	Device to prepare
+ * @return 0 if ok, -ve on error
+ */
+int blk_prepare_device(struct udevice *dev);
+
+/**
+ * blk_unbind_all() - Unbind all device of the given interface type
+ *
+ * The devices are removed and then unbound.
+ *
+ * @if_type:	Interface type to unbind
+ * @return 0 if OK, -ve on error
+ */
+int blk_unbind_all(int if_type);
+
+#else
+#include <errno.h>
+/*
+ * These functions should take struct udevice instead of struct blk_desc,
+ * but this is convenient for migration to driver model. Add a 'd' prefix
+ * to the function operations, so that blk_read(), etc. can be reserved for
+ * functions with the correct arguments.
+ */
+static inline ulong blk_dread(struct blk_desc *block_dev, lbaint_t start,
+			      lbaint_t blkcnt, void *buffer)
+{
+	/*
+	 * We could check if block_read is NULL and return -ENOSYS. But this
+	 * bloats the code slightly (cause some board to fail to build), and
+	 * it would be an error to try an operation that does not exist.
+	 */
+	return block_dev->block_read(block_dev, start, blkcnt, buffer);
+}
+
+static inline ulong blk_dwrite(struct blk_desc *block_dev, lbaint_t start,
+			       lbaint_t blkcnt, const void *buffer)
+{
+	return block_dev->block_write(block_dev, start, blkcnt, buffer);
+}
+
+static inline ulong blk_derase(struct blk_desc *block_dev, lbaint_t start,
+			       lbaint_t blkcnt)
+{
+	return block_dev->block_erase(block_dev, start, blkcnt);
+}
+#endif /* !CONFIG_BLK */
+
+#endif
diff --git a/include/common.h b/include/common.h
index 1563d64..f9f4605 100644
--- a/include/common.h
+++ b/include/common.h
@@ -596,12 +596,8 @@
 ulong	get_tbclk     (void);
 void	reset_misc    (void);
 void	reset_cpu     (ulong addr);
-#if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
 void ft_cpu_setup(void *blob, bd_t *bd);
-#ifdef CONFIG_PCI
 void ft_pci_setup(void *blob, bd_t *bd);
-#endif
-#endif
 
 void smp_set_core_boot_addr(unsigned long addr, int corenr);
 void smp_kick_all_cpus(void);
@@ -660,10 +656,8 @@
 #if defined(CONFIG_MPC85xx)
 typedef MPC85xx_SYS_INFO sys_info_t;
 void	get_sys_info  ( sys_info_t * );
-#  if defined(CONFIG_OF_LIBFDT)
-	void ft_fixup_cpu(void *, u64);
-	void ft_fixup_num_cores(void *);
-#  endif
+void ft_fixup_cpu(void *, u64);
+void ft_fixup_num_cores(void *);
 #endif
 #if defined(CONFIG_MPC86xx)
 typedef MPC86xx_SYS_INFO sys_info_t;
@@ -813,7 +807,7 @@
  *				for files under 4GiB
  */
 int gzwrite(unsigned char *src, int len,
-	    struct block_dev_desc *dev,
+	    struct blk_desc *dev,
 	    unsigned long szwritebuf,
 	    u64 startoffs,
 	    u64 szexpected);
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 37c6b43..ad9045e 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -90,6 +90,48 @@
 	BOOT_TARGET_DEVICES_references_UBIFS_without_CONFIG_CMD_UBIFS
 #endif
 
+#ifdef CONFIG_EFI_LOADER
+#if defined(CONFIG_ARM64)
+#define BOOTEFI_NAME "bootaa64.efi"
+#elif defined(CONFIG_ARM)
+#define BOOTEFI_NAME "bootarm.efi"
+#endif
+#endif
+
+#ifdef BOOTEFI_NAME
+#define BOOTENV_SHARED_EFI                                                \
+	"boot_efi_binary="                                                \
+		"load ${devtype} ${devnum}:${distro_bootpart} "           \
+			"${kernel_addr_r} efi/boot/"BOOTEFI_NAME"; "      \
+		"bootefi ${kernel_addr_r}\0"                              \
+	\
+	"load_efi_dtb="                                                   \
+		"load ${devtype} ${devnum}:${distro_bootpart} "           \
+			"${fdt_addr_r} ${prefix}${fdtfile}; "             \
+		"fdt addr ${fdt_addr_r}\0"                                \
+	\
+	"efi_dtb_prefixes=/ /dtb/ /dtb/current/\0"                        \
+	"scan_dev_for_efi="                                               \
+		"for prefix in ${efi_dtb_prefixes}; do "                  \
+			"if test -e ${devtype} "                          \
+					"${devnum}:${distro_bootpart} "   \
+					"${prefix}${fdtfile}; then "      \
+				"run load_efi_dtb; "                      \
+			"fi;"                                             \
+		"done;"                                                   \
+		"if test -e ${devtype} ${devnum}:${distro_bootpart} "     \
+					"efi/boot/"BOOTEFI_NAME"; then "  \
+				"echo Found EFI removable media binary "  \
+					"efi/boot/"BOOTEFI_NAME"; "       \
+				"run boot_efi_binary; "                   \
+				"echo EFI LOAD FAILED: continuing...; "   \
+		"fi; \0"
+#define SCAN_DEV_FOR_EFI "run scan_dev_for_efi;"
+#else
+#define BOOTENV_SHARED_EFI
+#define SCAN_DEV_FOR_EFI
+#endif
+
 #ifdef CONFIG_CMD_SATA
 #define BOOTENV_SHARED_SATA	BOOTENV_SHARED_BLKDEV(sata)
 #define BOOTENV_DEV_SATA	BOOTENV_DEV_BLKDEV
@@ -217,6 +259,7 @@
 	BOOTENV_SHARED_SCSI \
 	BOOTENV_SHARED_IDE \
 	BOOTENV_SHARED_UBIFS \
+	BOOTENV_SHARED_EFI \
 	"boot_prefixes=/ /boot/\0" \
 	"boot_scripts=boot.scr.uimg boot.scr\0" \
 	"boot_script_dhcp=boot.scr.uimg\0" \
@@ -258,7 +301,9 @@
 		"for prefix in ${boot_prefixes}; do "                     \
 			"run scan_dev_for_extlinux; "                     \
 			"run scan_dev_for_scripts; "                      \
-		"done\0"                                                  \
+		"done;"                                                   \
+		SCAN_DEV_FOR_EFI                                          \
+		"\0"                                                      \
 	\
 	"scan_dev_for_boot_part="                                         \
 		"part list ${devtype} ${devnum} -bootable devplist; "     \
diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h
index 0f85cd0..2ba7cf4 100644
--- a/include/config_distro_defaults.h
+++ b/include/config_distro_defaults.h
@@ -41,8 +41,6 @@
 #define CONFIG_BOOTP_PXE_CLIENTARCH     0x9
 #endif
 
-#define CONFIG_OF_LIBFDT
-
 #ifdef CONFIG_ARM64
 #define CONFIG_CMD_BOOTI
 #else
diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h
index 8dfe2a8..2076ef0 100644
--- a/include/configs/10m50_devboard.h
+++ b/include/configs/10m50_devboard.h
@@ -49,8 +49,6 @@
 /*
  * FDT options
  */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
 #define CONFIG_LMB
 
 /*
diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h
index 2e94b69..802ac752 100644
--- a/include/configs/3c120_devboard.h
+++ b/include/configs/3c120_devboard.h
@@ -52,8 +52,6 @@
 /*
  * FDT options
  */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
 #define CONFIG_LMB
 
 /*
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index bcbae50..2d9be20 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -503,15 +503,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index 4b5ad0e..9c32a01 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -247,17 +247,6 @@
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 89907dc..9f7ceb8 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -431,17 +431,6 @@
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400800 /* I2C speed and slave address*/
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 16920c6..4cbc9ad 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -396,17 +396,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index 1e5285c..1b5b907 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -209,9 +209,6 @@
  */
 #define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 955ce62..9e9765c 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -23,10 +23,6 @@
 
 #define CONFIG_MISC_INIT_R
 
-/* new uImage format support */
-#define CONFIG_FIT			1
-#define CONFIG_FIT_VERBOSE		1
-
 #define CONFIG_MMC     1
 
 #ifdef CONFIG_MMC
@@ -329,9 +325,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 
 /* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
 /* I2C */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index fa6dd6f..d440d88 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -359,11 +359,6 @@
 
 #endif
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
 #define CONFIG_MPC83XX_GPIO 1
 
 /*
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index ba952e3..3b49f1c 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -305,11 +305,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index a1d45d8..97f48e2 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -227,11 +227,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index b3322ae..d218f59 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -307,11 +307,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 71dcc6c..5b0900a 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -333,11 +333,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index ded73b4..4346eda 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -366,11 +366,6 @@
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
 /*
  * PCI
  */
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index df47888..2475ae4 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -321,11 +321,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index e77848e..aa66927 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -347,11 +347,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 294be3b..9298c30 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -385,13 +385,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 
 /*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-/*
  * I2C
  */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 921180f..0a6d5bc 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -236,11 +236,6 @@
 #ifdef  CONFIG_SYS_HUSH_PARSER
 #endif
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
 /*
  * I2C
  */
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index d5805c1..79f81ec 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -259,11 +259,6 @@
 #ifdef  CONFIG_SYS_HUSH_PARSER
 #endif
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
 /*
  * I2C
  */
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 0fa5fd3..494c46f 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -209,11 +209,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index a84ebfd..8d29762 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -334,11 +334,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
 /*
  * I2C
  */
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 84b8174..b64bbe5 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -257,11 +257,6 @@
 #ifdef  CONFIG_SYS_HUSH_PARSER
 #endif
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
 /*
  * I2C
  */
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 69ce13c..2284646 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -231,11 +231,6 @@
 #ifdef  CONFIG_SYS_HUSH_PARSER
 #endif
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
 /*
  * I2C
  */
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 03ba806..a130001 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -242,11 +242,6 @@
 #ifdef  CONFIG_SYS_HUSH_PARSER
 #endif
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
 /*
  * I2C
  */
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index f86d10f..0e003e5 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -253,11 +253,6 @@
 #ifdef  CONFIG_SYS_HUSH_PARSER
 #endif
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
 /*
  * I2C
  */
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index b34a033..cfcd5b9 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -380,17 +380,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-/* new uImage format support */
-#define CONFIG_FIT		1
-#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index f8aef2e..ac219d1 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -236,14 +236,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/*
- * Pass open firmware flat tree to kernel
- */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-
 /* maximum size of the flat tree (8K) */
 #define OF_FLAT_TREE_MAX_SIZE	8192
 
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index a84db51..bd0a3f5 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -273,13 +273,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 
 /*
- * Pass open firmware flat tree to kernel
- */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-/*
  * I2C
  */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 3c0faca..81af871 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -622,17 +622,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 6235bbb..bc4c733 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -443,17 +443,6 @@
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #endif
 
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index bc479f6..a53b1ac 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -175,17 +175,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index f250e7f..2d27fcf 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -339,15 +339,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 4eb5fe1..345affa 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -73,9 +73,6 @@
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_USB
 
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h
index ce0c49f..bb0c8bb 100644
--- a/include/configs/PMC405DE.h
+++ b/include/configs/PMC405DE.h
@@ -64,9 +64,6 @@
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
 
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-
 #undef  CONFIG_WATCHDOG			/* watchdog disabled */
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
 #define CONFIG_PRAM		0
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index 05ad315..dab4fa7 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -407,10 +407,6 @@
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #endif
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #define CONFIG_API		1
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index e5df784..f07b2d1 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -536,15 +536,6 @@
 #endif
 #endif
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 3cda3b1..1a22bee 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -534,15 +534,6 @@
 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 #endif
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 2e7892f..aa0f802 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -435,15 +435,6 @@
 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 #endif
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 5fc3497..84e195d 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -487,15 +487,6 @@
 #endif
 #endif
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 3caf40b..5957fa8 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -459,15 +459,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 /*
  * I2C
  */
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index b5290a1..e0769d0 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -419,15 +419,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 /*
  * I2C
  */
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index c1a0a6c..faf06a0 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -213,15 +213,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 535dc6e..e646c00 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -730,9 +730,6 @@
  * Open firmware flat tree support
  *-----------------------------------------------------------------------
  */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #define OF_CPU			"PowerPC,5200@0"
 #define OF_SOC			"soc5200@f0000000"
 #define OF_TBCLK		(bd->bi_busfreq / 4)
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index 013e40e..d03f2e6 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -457,9 +457,6 @@
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_HWCONFIG		1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
index fbb2f84..7d39766 100644
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -453,9 +453,6 @@
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_HWCONFIG		1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 58a17f5..9ed469a 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -327,11 +327,6 @@
 
 #undef CONFIG_WATCHDOG		/* watchdog disabled */
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 256 MB of memory, since this is
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index 0077105..c70c4d7 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -441,9 +441,6 @@
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_HWCONFIG		1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
index 4a443ed..52cba86 100644
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -443,9 +443,6 @@
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_HWCONFIG		1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index 3fbc1ad..fb2652b 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -449,9 +449,6 @@
 #define CONFIG_FEC_ENET
 #define CONFIG_ETHPRIME		"SCC"
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_HWCONFIG		1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index d2729d6..301a0a8 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -480,9 +480,6 @@
 #define CONFIG_FEC_ENET
 #define CONFIG_ETHPRIME		"SCC"
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_HWCONFIG		1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index 764568d..a390e3f 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -448,9 +448,6 @@
 #define CONFIG_FEC_ENET
 #define CONFIG_ETHPRIME		"SCC"
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT       1
-#define CONFIG_OF_BOARD_SETUP  1
 #define CONFIG_HWCONFIG		1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index 0894f59..0d2e119 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -453,9 +453,6 @@
 #define CONFIG_FEC_ENET
 #define CONFIG_ETHPRIME		"SCC"
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_HWCONFIG		1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index 9650b8d..6fd08c7 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -453,9 +453,6 @@
 #define CONFIG_FEC_ENET
 #define CONFIG_ETHPRIME		"SCC"
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_HWCONFIG		1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
index 8b8db89..fcdc3e5 100644
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -454,9 +454,6 @@
 #define CONFIG_FEC_ENET
 #define CONFIG_ETHPRIME		"SCC"
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_HWCONFIG		1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index a011d2e..2a0fdf5 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -472,9 +472,6 @@
 #define CONFIG_FEC_ENET
 #define CONFIG_ETHPRIME		"SCC"
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_HWCONFIG		1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
index 023736e..c9925ab 100644
--- a/include/configs/TQM885D.h
+++ b/include/configs/TQM885D.h
@@ -472,9 +472,6 @@
 
 #define CONFIG_ETHPRIME		"SCC"
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_HWCONFIG		1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index 2354009..139e629 100644
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -345,17 +345,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
@@ -495,7 +484,6 @@
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_CRAMFS
-#define CONFIG_CRAMFS_CMDLINE
 
 /*
  * USB
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
index 6cbf1b7..a734c28 100644
--- a/include/configs/VOM405.h
+++ b/include/configs/VOM405.h
@@ -66,9 +66,6 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_EEPROM
 
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
index 4839ede..cf931a6 100644
--- a/include/configs/a3m071.h
+++ b/include/configs/a3m071.h
@@ -82,7 +82,6 @@
 #define CONFIG_CMD_MTDPARTS
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
-#define CONFIG_FIT
 
 /*
  * IPB Bus clocking configuration.
@@ -95,10 +94,6 @@
 #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
 #endif
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-
 /* maximum size of the flat tree (8K) */
 #define OF_FLAT_TREE_MAX_SIZE	8192
 
diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h
index 0ff5164..a883afb 100644
--- a/include/configs/a4m072.h
+++ b/include/configs/a4m072.h
@@ -354,9 +354,6 @@
  * Open firmware flat tree support
  *-----------------------------------------------------------------------
  */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #define OF_CPU			"PowerPC,5200@0"
 #define OF_SOC			"soc5200@f0000000"
 #define OF_TBCLK		(bd->bi_busfreq / 4)
diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h
index 320be8f..750d8ff 100644
--- a/include/configs/ac14xx.h
+++ b/include/configs/ac14xx.h
@@ -557,9 +557,6 @@
 
 #define CONFIG_ARP_TIMEOUT	200UL
 
-#define CONFIG_FIT		1
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
 
 #define OF_CPU			"PowerPC,5121@0"
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 6ebe0b3..150c523 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -19,9 +19,6 @@
 #include <configs/ti_am335x_common.h>
 
 #ifndef CONFIG_SPL_BUILD
-#ifndef CONFIG_FIT
-# define CONFIG_FIT
-#endif
 # define CONFIG_TIMESTAMP
 # define CONFIG_LZO
 #endif
@@ -94,6 +91,7 @@
 
 #define CONFIG_BOOTCOMMAND \
 	"run findfdt; " \
+	"run envboot; " \
 	"run distro_bootcmd"
 
 #include <config_distro_bootcmd.h>
@@ -123,13 +121,6 @@
 		"${optargs} " \
 		"root=${spiroot} " \
 		"rootfstype=${spirootfstype}\0" \
-	"bootenv=uEnv.txt\0" \
-	"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
-	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
-		"source ${loadaddr}\0" \
-	"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
-	"importbootenv=echo Importing environment from mmc ...; " \
-		"env import -t -r $loadaddr $filesize\0" \
 	"ramargs=setenv bootargs console=${console} " \
 		"${optargs} " \
 		"root=${ramroot} " \
@@ -154,21 +145,10 @@
 	"mmcboot=mmc dev ${mmcdev}; " \
 		"if mmc rescan; then " \
 			"echo SD/MMC found on device ${mmcdev};" \
-			"if run loadbootscript; then " \
-				"run bootscript;" \
-			"else " \
-				"if run loadbootenv; then " \
-					"echo Loaded environment from ${bootenv};" \
-					"run importbootenv;" \
-				"fi;" \
-				"if test -n $uenvcmd; then " \
-					"echo Running uenvcmd ...;" \
-					"run uenvcmd;" \
-				"fi;" \
-				"if run loadimage; then " \
-					"run mmcloados;" \
-				"fi;" \
-			"fi ;" \
+			"run envboot; " \
+			"if run loadimage; then " \
+				"run mmcloados;" \
+			"fi;" \
 		"fi;\0" \
 	"spiboot=echo Booting from spi ...; " \
 		"run spiargs; " \
@@ -200,7 +180,6 @@
 	BOOTENV
 #endif
 
-
 /* NS16550 Configuration */
 #define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
 #define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h
index 1bdb96e..e9e971e 100644
--- a/include/configs/am335x_sl50.h
+++ b/include/configs/am335x_sl50.h
@@ -13,9 +13,6 @@
 #undef CONFIG_BOOTDELAY
 
 #ifndef CONFIG_SPL_BUILD
-#ifndef CONFIG_FIT
-# define CONFIG_FIT
-#endif
 # define CONFIG_TIMESTAMP
 # define CONFIG_LZO
 #endif
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 5b689a8..fae8138 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -47,7 +47,6 @@
 /* Display CPU and Board information */
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_OF_LIBFDT
 #define CONFIG_MISC_INIT_R
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 1428aa9..b982ed6 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -105,8 +105,10 @@
 /* SPL USB Support */
 #ifdef CONFIG_SPL_USB_HOST_SUPPORT
 #define CONFIG_SPL_USB_SUPPORT
-#define CONFIG_SYS_USB_FAT_BOOT_PARTITION		1
+#endif
 
+#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_USB_FAT_BOOT_PARTITION		1
 #define CONFIG_CMD_USB
 #define CONFIG_USB_HOST
 #define CONFIG_USB_XHCI
@@ -257,10 +259,6 @@
 		"${optargs} " \
 		"root=${usbroot} " \
 		"rootfstype=${usbrootfstype}\0" \
-	"bootenv=uEnv.txt\0" \
-	"loadbootenv=load ${devtype} ${devnum} ${loadaddr} ${bootenv}\0" \
-	"importbootenv=echo Importing environment from mmc ...; " \
-		"env import -t $loadaddr $filesize\0" \
 	"ramargs=setenv bootargs console=${console} " \
 		"${optargs} " \
 		"root=${ramroot} " \
@@ -273,14 +271,6 @@
 		"setenv devtype mmc; " \
 		"if mmc rescan; then " \
 			"echo SD/MMC found on device ${devnum};" \
-			"if run loadbootenv; then " \
-				"echo Loaded environment from ${bootenv};" \
-				"run importbootenv;" \
-			"fi;" \
-			"if test -n $uenvcmd; then " \
-				"echo Running uenvcmd ...;" \
-				"run uenvcmd;" \
-			"fi;" \
 			"if run loadimage; then " \
 				"run loadfdt; " \
 				"echo Booting from mmc${mmcdev} ...; " \
@@ -327,6 +317,7 @@
 
 #define CONFIG_BOOTCOMMAND \
 	"run findfdt; " \
+	"run envboot;" \
 	"run mmcboot;" \
 	"run usbboot;" \
 	NANDBOOT \
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index 6308cab..1fffdb1 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -88,4 +88,8 @@
 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 						CONFIG_SYS_SCSI_MAX_LUN)
 
+/* EEPROM */
+#define CONFIG_EEPROM_CHIP_ADDRESS 0x50
+#define CONFIG_EEPROM_BUS_ADDRESS 0
+
 #endif /* __CONFIG_AM57XX_EVM_H */
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index 60d6be7..0388ffc 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -121,11 +121,6 @@
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port*/
 #endif
 
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
 /* Update size in "reg" property of NOR FLASH device tree nodes */
 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
 
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
index 5b286d2..018d586 100644
--- a/include/configs/apf27.h
+++ b/include/configs/apf27.h
@@ -161,8 +161,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS	/* send memory definition to kernel */
 #define CONFIG_INITRD_TAG		/* send initrd params	*/
 
-#define CONFIG_OF_LIBFDT
-
 #define CONFIG_BOOTDELAY	5
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 #define	CONFIG_BOOTFILE		__stringify(CONFIG_BOARD_NAME) "-linux.bin"
diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h
index 63f61ae..8a860ee 100644
--- a/include/configs/arcangel4.h
+++ b/include/configs/arcangel4.h
@@ -41,9 +41,6 @@
 /*
  * Command line configuration
  */
-
-#define CONFIG_OF_LIBFDT
-
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_MAXARGS		16
 
diff --git a/include/configs/aria.h b/include/configs/aria.h
index c38bf3c..c56a2e3 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -572,8 +572,6 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
 
 #define OF_CPU			"PowerPC,5121@0"
diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h
index 0b97ccc..efbf816 100644
--- a/include/configs/aristainetos-common.h
+++ b/include/configs/aristainetos-common.h
@@ -240,8 +240,6 @@
 #define CONFIG_HW_WATCHDOG
 #define CONFIG_IMX_WATCHDOG
 
-#define CONFIG_FIT
-
 /* Framebuffer */
 #define CONFIG_VIDEO
 #define CONFIG_VIDEO_IPUV3
diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h
index dfbd60d..1ce9b9a 100644
--- a/include/configs/armadillo-800eva.h
+++ b/include/configs/armadillo-800eva.h
@@ -23,7 +23,6 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_BOOTZ
 
-#define CONFIG_OF_LIBFDT
 #define BOARD_LATE_INIT
 
 #define CONFIG_BAUDRATE		115200
diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h
index d692106..6525b5c 100644
--- a/include/configs/at91-sama5_common.h
+++ b/include/configs/at91-sama5_common.h
@@ -31,8 +31,6 @@
 
 #define CONFIG_ENV_VARS_UBOOT_CONFIG
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_OF_LIBFDT		/* Device Tree support */
-
 
 /* general purpose I/O */
 #define CONFIG_AT91_GPIO
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index 9274024..5903f7c 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -59,7 +59,6 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_OF_LIBFDT
 
 
 /*
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index cc3e69c..7820295 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -46,8 +46,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_OF_LIBFDT
-
 
 /* general purpose I/O */
 #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index 64fb38b..c7ba9eb 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -31,9 +31,6 @@
 
 #define CONFIG_DISPLAY_CPUINFO
 
-#define CONFIG_OF_LIBFDT
-
-
 #define CONFIG_ATMEL_LEGACY
 #define CONFIG_SYS_TEXT_BASE		0x21f00000
 
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index 89ee9fe..c826427 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -46,8 +46,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_OF_LIBFDT
-
 
 /*
  * Hardware drivers
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index cc42c90..d4baf48 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -31,8 +31,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_OF_LIBFDT
-
 
 /* general purpose I/O */
 #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index ba91d1f..14a8436 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -30,8 +30,6 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DISPLAY_CPUINFO
 
-#define CONFIG_OF_LIBFDT
-
 /* general purpose I/O */
 #define CONFIG_AT91_GPIO
 
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index a7a0502..0d45354 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -32,8 +32,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_OF_LIBFDT
-
 
 #define CONFIG_ATMEL_LEGACY
 #define CONFIG_AT91_GPIO		1
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index 45bb861..cd91a7b 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -27,8 +27,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_OF_LIBFDT
-
 
 /* general purpose I/O */
 #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
diff --git a/include/configs/axs101.h b/include/configs/axs101.h
index 98fff63..006ddb3 100644
--- a/include/configs/axs101.h
+++ b/include/configs/axs101.h
@@ -39,8 +39,6 @@
 #define CONFIG_BOARD_TYPES
 #define CONFIG_BOARD_EARLY_INIT_F
 
-#define CONFIG_OF_LIBFDT
-
 /*
  * NAND Flash configuration
  */
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index e9b4fe1..b8c915c 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -41,7 +41,6 @@
 
 /* FIT support */
 #define CONFIG_SYS_BOOTM_LEN         SZ_64M
-#define CONFIG_OF_BOARD_SETUP
 
 /* UBI Support */
 #define CONFIG_CMD_MTDPARTS
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
index e61a098..a9df0b3 100644
--- a/include/configs/bav335x.h
+++ b/include/configs/bav335x.h
@@ -21,12 +21,9 @@
 #define CONFIG_ENV_IS_NOWHERE
 
 #ifndef CONFIG_SPL_BUILD
-# define CONFIG_FIT
 # define CONFIG_TIMESTAMP
 # define CONFIG_LZO
 # ifdef CONFIG_ENABLE_VBOOT
-#  define CONFIG_FIT_SIGNATURE
-#  define CONFIG_RSA
 # endif
 #endif
 
diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h
index 1d4869b..344f89d 100644
--- a/include/configs/bcm_ep_board.h
+++ b/include/configs/bcm_ep_board.h
@@ -86,9 +86,6 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_FAT_WRITE
 
-/* Enable devicetree support */
-#define CONFIG_OF_LIBFDT
-
 /* SHA hashing */
 #define CONFIG_CMD_HASH
 #define CONFIG_HASH_VERIFY
diff --git a/include/configs/chromebook_samus.h b/include/configs/chromebook_samus.h
new file mode 100644
index 0000000..b89ba41
--- /dev/null
+++ b/include/configs/chromebook_samus.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+#include <configs/x86-chromebook.h>
+
+#undef CONFIG_CFB_CONSOLE
+
+#undef CONFIG_STD_DEVICES_SETTINGS
+#define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,i8042-kbd,serial\0" \
+					"stdout=vidconsole,serial\0" \
+					"stderr=vidconsole,serial\0"
+
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0x003f8000
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h
index 69b2674..3744af2 100644
--- a/include/configs/cm5200.h
+++ b/include/configs/cm5200.h
@@ -315,8 +315,6 @@
 /*
  * Flat Device Tree support
  */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
 #define OF_CPU			"PowerPC,5200@0"
 #define OF_SOC			"soc5200@f0000000"
 #define OF_TBCLK		(bd->bi_busfreq / 4)
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 180ea28..b36ba14 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -225,7 +225,6 @@
 #define CONFIG_STACKSIZE			(128 * 1024)
 #define CONFIG_SYS_MALLOC_LEN			(10 * 1024 * 1024)
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	800 /* 400 KB */
-#define CONFIG_OF_BOARD_SETUP
 #define CONFIG_MISC_INIT_R
 
 /* SPL */
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 24ae14d..3910b46 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -48,8 +48,6 @@
 
 #define CONFIG_MISC_INIT_R
 
-#define CONFIG_OF_LIBFDT		1
-
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h
index 7a07de4..d8a29f0 100644
--- a/include/configs/cm_t3517.h
+++ b/include/configs/cm_t3517.h
@@ -51,7 +51,6 @@
 
 #define CONFIG_MISC_INIT_R
 
-#define CONFIG_OF_LIBFDT
 /*
  * The early kernel mapping on ARM currently only maps from the base of DRAM
  * to the end of the kernel image.  The kernel is loaded at DRAM base + 0x8000.
diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h
index 6d57cd6..c8c67c4 100644
--- a/include/configs/cm_t54.h
+++ b/include/configs/cm_t54.h
@@ -18,10 +18,6 @@
 
 #undef CONFIG_SPL_OS_BOOT
 
-/* Device Tree defines */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-
 /* EEPROM related defines */
 #define CONFIG_SYS_I2C_OMAP34XX
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
index 0fc24a0..e8851e7 100644
--- a/include/configs/colibri_pxa270.h
+++ b/include/configs/colibri_pxa270.h
@@ -41,7 +41,6 @@
 #define	CONFIG_CMDLINE_TAG
 #define	CONFIG_SETUP_MEMORY_TAGS
 #define	CONFIG_LZMA			/* LZMA compression support */
-#define	CONFIG_OF_LIBFDT
 
 /*
  * Serial Console Configuration
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 60aee8f..9c73cff 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -219,7 +219,6 @@
 #define CONFIG_ENV_OFFSET		(12 * 64 * 2048)
 #endif
 
-#define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
 
 #define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h
new file mode 100644
index 0000000..556d44e
--- /dev/null
+++ b/include/configs/conga-qeval20-qa3-e3845.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(1 << 20)
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_ARCH_MISC_INIT
+
+#define CONFIG_PCI_PNP
+
+#define CONFIG_STD_DEVICES_SETTINGS     "stdin=serial\0" \
+					"stdout=serial\0" \
+					"stderr=serial\0"
+
+#define CONFIG_SCSI_DEV_LIST		\
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
+
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_SDMA
+#define CONFIG_CMD_MMC
+
+#undef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT		1
+
+#define VIDEO_IO_OFFSET				0
+#define CONFIG_X86EMU_RAW_IO
+#define CONFIG_CMD_BMP
+
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0x007fe000
+
+#undef CONFIG_BOOTARGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_BOOTARGS		\
+	"root=/dev/sda1 ro quiet"
+#define CONFIG_BOOTCOMMAND	\
+	"load scsi 0:1 03000000 /boot/vmlinuz-4.2.0-26-generic;" \
+	"load scsi 0:1 04000000 /boot/initrd.img-4.2.0-26-generic;" \
+	"run boot"
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"boot=zboot 03000000 0 04000000 ${filesize}\0"		\
+	"upd_uboot=tftp 100000 conga/u-boot.rom;"		\
+		"sf probe;sf update 100000 0 7fe000\0"
+
+#define CONFIG_PREBOOT
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 641aa7c..fa64a1e 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -400,17 +400,6 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_LAST_STAGE_INIT
 
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE
-
 #else /* CONFIG_TRAILBLAZER */
 
 #define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index a099eee..d30d7ff 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -344,15 +344,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 97797e2..a1fd93f 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -40,7 +40,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_OF_LIBFDT
 
 /* general purpose I/O */
 #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index 99b3aef..b4bf350e 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -231,14 +231,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 63abb80..24e55e8 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -270,7 +270,6 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CRC32_VERIFY
 #define CONFIG_MX_CYCLIC
-#define CONFIG_OF_LIBFDT
 
 /*
  * Linux Information
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index 99d9148..a8ce7e1 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -152,7 +152,6 @@
 /*
  * Pass open firmware flat tree
  */
-#define CONFIG_OF_LIBFDT
 
 /*
  * Environment
diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h
index f802c8d..0041ab9 100644
--- a/include/configs/digsy_mtc.h
+++ b/include/configs/digsy_mtc.h
@@ -296,9 +296,6 @@
 #define CONFIG_SYS_FLASH_ERASE_TOUT	240000
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500
 
-#define CONFIG_OF_LIBFDT  1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #define OF_CPU			"PowerPC,5200@0"
 #define OF_SOC			"soc5200@f0000000"
 #define OF_TBCLK		(bd->bi_busfreq / 4)
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index b614f19..9f9bcb8 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -36,8 +36,6 @@
 #define PLLMR1_DEFAULT PLLMR1_266_133_66
 
 /* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
 #define CONFIG_FIT_DISABLE_SHA256
 
 #define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h
index 90e839a..1e461f5 100644
--- a/include/configs/dlvision.h
+++ b/include/configs/dlvision.h
@@ -32,8 +32,6 @@
 #define PLLMR1_DEFAULT PLLMR1_266_133_66_33
 
 /* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
 #define CONFIG_FIT_DISABLE_SHA256
 
 #define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
diff --git a/include/configs/dns325.h b/include/configs/dns325.h
index c59a324..80f7a1e 100644
--- a/include/configs/dns325.h
+++ b/include/configs/dns325.h
@@ -91,11 +91,6 @@
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
 /*
- * Enable device tree support
- */
-#define CONFIG_OF_LIBFDT
-
-/*
  * Display cpu info at boot
  */
 #define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 0196280..45bda4f 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -19,6 +19,11 @@
 #define CONFIG_IODELAY_RECALIBRATION
 #endif
 
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_PHYS_64BIT
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_MAX_MEM_MAPPED		0x80000000
+
 #ifndef CONFIG_QSPI_BOOT
 /* MMC ENV related defines */
 #define CONFIG_ENV_IS_IN_MMC
@@ -341,4 +346,8 @@
 #endif
 #endif  /* NOR support */
 
+/* EEPROM */
+#define CONFIG_EEPROM_CHIP_ADDRESS 0x50
+#define CONFIG_EEPROM_BUS_ADDRESS 0
+
 #endif /* __CONFIG_DRA7XX_EVM_H */
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index 834a22f..7d600bf 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -170,6 +170,7 @@
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 #define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_RTL8152
 
 /* USB boot mode */
 #define CONFIG_USB_BOOTING
@@ -177,10 +178,6 @@
 #define EXYNOS_USB_SECONDARY_BOOT	0xfeed0002
 #define EXYNOS_IRAM_SECONDARY_BASE	0x02020018
 
-/* Enable FIT support and comparison */
-#define CONFIG_FIT
-#define CONFIG_FIT_BEST_MATCH
-
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 1) \
 	func(MMC, mmc, 0) \
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index 99bf7d6..3e4aaf6 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -252,6 +252,5 @@
 
 /* Enable FIT images support */
 #define CONFIG_CMD_FDT
-#define CONFIG_FIT
 
 #endif				/* __CONFIG_H */
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index b7b9c78..38c921a 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -97,10 +97,6 @@
 
 #endif /* CONFIG_SPI_FLASH */
 
-/* Flattened Image Tree Suport */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE
-
 /* I2C Configs */
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
@@ -442,7 +438,6 @@
 	"done"
 
 /* Device Tree Support */
-#define CONFIG_OF_BOARD_SETUP
 #define CONFIG_FDT_FIXUP_PARTITIONS
 
 #endif			       /* __CONFIG_H */
diff --git a/include/configs/h2200.h b/include/configs/h2200.h
index 6fbbe6e..fe0211a 100644
--- a/include/configs/h2200.h
+++ b/include/configs/h2200.h
@@ -115,7 +115,6 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 38400, 115200 }
 
-#define CONFIG_FIT
 #define CONFIG_FIT_DISABLE_SHA256
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG
diff --git a/include/configs/highbank.h b/include/configs/highbank.h
index f02575a..510741b 100644
--- a/include/configs/highbank.h
+++ b/include/configs/highbank.h
@@ -14,8 +14,6 @@
 
 #define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_FIT
 #define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
 
 #define CONFIG_SYS_TIMER_RATE		(150000000/256)
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
index 796861e..0851626 100644
--- a/include/configs/hikey.h
+++ b/include/configs/hikey.h
@@ -21,14 +21,11 @@
 
 #define CONFIG_SUPPORT_RAW_INITRD
 
-/* Cache Definitions */
-#define CONFIG_SYS_DCACHE_OFF
+/* MMU Definitions */
+#define CONFIG_SYS_CACHELINE_SIZE	64
 
 #define CONFIG_IDENT_STRING		"hikey"
 
-/* Flat Device Tree Definitions */
-#define CONFIG_OF_LIBFDT
-
 #define CONFIG_BOARD_EARLY_INIT_F
 
 /* Physical Memory Map */
@@ -121,7 +118,7 @@
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 				"kernel_name=Image\0"	\
 				"kernel_addr_r=0x00080000\0" \
-				"fdt_name=hi6220-hikey.dtb\0" \
+				"fdtfile=hi6220-hikey.dtb\0" \
 				"fdt_addr_r=0x02000000\0" \
 				"fdt_high=0xffffffffffffffff\0" \
 				"initrd_high=0xffffffffffffffff\0" \
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index 801be68..c984613 100644
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -31,10 +31,6 @@
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_LAST_STAGE_INIT
 
-/* new uImage format support */
-#define CONFIG_FIT			1
-#define CONFIG_FIT_VERBOSE		1
-
 #define CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
@@ -318,9 +314,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 
 /* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
 /* I2C */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index 0a5a9f1..5855d81 100644
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -429,10 +429,6 @@
 #define CONFIG_BOOTP_HOSTNAME
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_BOOTFILESIZE
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
 
 /*
  * The reserved memory
diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h
index 639a30a..43d2c3d 100644
--- a/include/configs/integrator-common.h
+++ b/include/configs/integrator-common.h
@@ -27,7 +27,6 @@
 
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
 #define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_OF_LIBFDT		/* enable passing a Device Tree */
 #define CONFIG_MISC_INIT_R		/* call misc_init_r during start up */
 
 /*
diff --git a/include/configs/intip.h b/include/configs/intip.h
index 60c9e2c..913fdab 100644
--- a/include/configs/intip.h
+++ b/include/configs/intip.h
@@ -46,7 +46,6 @@
 #define CONFIG_BOARD_EARLY_INIT_R	1	/* Call board_early_init_r */
 #define CONFIG_MISC_INIT_R		1	/* Call misc_init_r */
 #define CONFIG_BOARD_TYPES		1	/* support board types */
-#define CONFIG_FIT
 #define CFG_ALT_MEMTEST
 
 #undef CONFIG_ZERO_BOOTDELAY_CHECK     /* ignore keypress on bootdelay==0 */
diff --git a/include/configs/io.h b/include/configs/io.h
index 2c457d4..1213fe2 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -36,8 +36,6 @@
 #undef CONFIG_ZERO_BOOTDELAY_CHECK	/* ignore keypress on bootdelay==0 */
 
 /* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
 #define CONFIG_FIT_DISABLE_SHA256
 
 #define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
diff --git a/include/configs/io64.h b/include/configs/io64.h
index 25bd014..1a6275e 100644
--- a/include/configs/io64.h
+++ b/include/configs/io64.h
@@ -46,10 +46,6 @@
 
 #undef CONFIG_ZERO_BOOTDELAY_CHECK	/* ignore keypress on bootdelay==0 */
 
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE
-
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h
index 637bbb3..ea9d8b0 100644
--- a/include/configs/ipek01.h
+++ b/include/configs/ipek01.h
@@ -170,9 +170,6 @@
 /*
  * Open firmware flat tree support
  */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #define OF_CPU			"PowerPC,5200@0"
 #define OF_SOC			"soc5200@f0000000"
 #define OF_TBCLK		(bd->bi_busfreq / 4)
diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h
index ba96d97..b494683 100644
--- a/include/configs/jupiter.h
+++ b/include/configs/jupiter.h
@@ -134,9 +134,6 @@
 
 #if 0
 /* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #define OF_CPU			"PowerPC,5200@0"
 #define OF_SOC			"soc5200@f0000000"
 #define OF_TBCLK		(bd->bi_busfreq / 8)
diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
index 4f4ebf5..07f975b 100644
--- a/include/configs/k2e_evm.h
+++ b/include/configs/k2e_evm.h
@@ -16,6 +16,8 @@
 
 /* U-Boot general configuration */
 #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS				\
+	DEFAULT_FW_INITRAMFS_BOOT_ENV					\
+	"boot=ubi\0"							\
 	"addr_mon=0x0c140000\0"						\
 	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
 	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"	\
@@ -38,4 +40,6 @@
 #define CONFIG_KSNET_CPSW_NUM_PORTS	9
 #define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
 
+#define CONFIG_DDR_SPD
+
 #endif /* __CONFIG_K2E_EVM_H */
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index d9ad8cf..7bc506f 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -17,9 +17,12 @@
 /* U-Boot general configuration */
 #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS				\
 	DEFAULT_MMC_TI_ARGS						\
+	DEFAULT_PMMC_BOOT_ENV						\
+	"boot=mmc\0"							\
 	"console=ttyS0,115200n8\0"					\
 	"bootpart=0:2\0"						\
 	"bootdir=/boot\0"						\
+	"rd_spec=-\0"							\
 	"addr_mon=0x0c040000\0"						\
 	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
 	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"	\
@@ -28,10 +31,18 @@
 	"name_ubi=k2g-evm-ubifs.ubi\0"					\
 	"name_uboot=u-boot-spi-k2g-evm.gph\0"				\
 	"init_mmc=run args_all args_mmc\0"				\
+	"soc_variant=k2g\0"						\
 	"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0"\
 	"get_kern_mmc=load mmc ${bootpart} ${loadaddr} "		\
 		"${bootdir}/${name_kern}\0"				\
 	"get_mon_mmc=load mmc ${bootpart} ${addr_mon} ${bootdir}/${name_mon}\0"\
+	"name_fs=arago-base-tisdk-image-k2g-evm.cpio\0"
+
+#define CONFIG_BOOTCOMMAND						\
+	"run envboot; "							\
+	"run set_name_pmmc init_${boot} get_pmmc_${boot} run_pmmc "	\
+	"get_fdt_${boot} get_mon_${boot} get_kern_${boot} "		\
+	"run_mon run_kern"
 
 #include <configs/ti_armv7_keystone2.h>
 
@@ -53,6 +64,12 @@
 #define CONFIG_OMAP_HSMMC
 #define CONFIG_CMD_MMC
 
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE		"mmc"
+#define FAT_ENV_DEVICE_AND_PART		"0:1"
+#define FAT_ENV_FILE			"uboot.env"
+
 #define CONFIG_SF_DEFAULT_BUS		1
 #define CONFIG_SF_DEFAULT_CS		0
 
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index 6c6dcb1..a268a86 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -16,6 +16,8 @@
 
 /* U-Boot general configuration */
 #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS				\
+	DEFAULT_FW_INITRAMFS_BOOT_ENV					\
+	"boot=ubi\0"							\
 	"addr_mon=0x0c5f0000\0"						\
 	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
 	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"	\
@@ -37,4 +39,6 @@
 #define CONFIG_KSNET_NETCP_V1_0
 #define CONFIG_KSNET_CPSW_NUM_PORTS	5
 
+#define CONFIG_DDR_SPD
+
 #endif /* __CONFIG_K2HK_EVM_H */
diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h
index 9bacfa4..f366e67 100644
--- a/include/configs/k2l_evm.h
+++ b/include/configs/k2l_evm.h
@@ -16,6 +16,8 @@
 
 /* U-Boot general configuration */
 #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS				\
+	DEFAULT_FW_INITRAMFS_BOOT_ENV					\
+	"boot=ubi\0"							\
 	"addr_mon=0x0c140000\0"						\
 	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
 	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,4096\0"	\
diff --git a/include/configs/kc1.h b/include/configs/kc1.h
new file mode 100644
index 0000000..c2ac148
--- /dev/null
+++ b/include/configs/kc1.h
@@ -0,0 +1,275 @@
+/*
+ * Amazon Kindle Fire (first generation) codename kc1 config
+ *
+ * Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap.h>
+
+/*
+ * Build
+ */
+
+#define CONFIG_SYS_THUMB_BUILD
+
+/*
+ * CPU
+ */
+
+#define CONFIG_SYS_L2_PL310		1
+#define CONFIG_SYS_PL310_BASE		0x48242000
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+/*
+ * Platform
+ */
+
+#define CONFIG_OMAP
+#define CONFIG_OMAP4430
+#define CONFIG_OMAP_COMMON
+
+/*
+ * Board
+ */
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * Clocks
+ */
+
+#define CONFIG_SYS_TIMERBASE	GPT2_BASE
+#define CONFIG_SYS_PTV		2
+
+/*
+ * DRAM
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+
+/*
+ * Memory
+ */
+
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR		(NON_SECURE_SRAM_END - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024 + CONFIG_ENV_SIZE)
+
+/*
+ * GPIO
+ */
+
+#define CONFIG_OMAP_GPIO
+
+/*
+ * I2C
+ */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	400000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP24XX
+#define CONFIG_I2C_MULTI_BUS
+
+#define CONFIG_CMD_I2C
+
+/*
+ * Flash
+ */
+
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * MMC
+ */
+
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+
+#define CONFIG_CMD_MMC
+
+/*
+ * Power
+ */
+
+#define CONFIG_TWL6030_POWER
+
+/*
+ * Input
+ */
+
+#define CONFIG_TWL6030_INPUT
+
+/*
+ * Partitions
+ */
+
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
+/*
+ * SPL
+ */
+
+#define CONFIG_SPL_FRAMEWORK
+
+#define CONFIG_SPL_TEXT_BASE		0x40300000
+#define CONFIG_SPL_MAX_SIZE		(48 * 1024)
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		(512 * 1024)
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	(1024 * 1024)
+
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_BOARD_INIT
+
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION	2
+
+/*
+ * Console
+ */
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_AUTO_COMPLETE
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_CBSIZE	512
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) \
+				 + 16)
+
+/*
+ * Serial
+ */
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		48000000
+#define CONFIG_SYS_NS16550_COM3		UART3_BASE
+#define CONFIG_CONS_INDEX		3
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 4800, 9600, 19200, 38400, 57600, \
+					  115200 }
+
+/*
+ * USB gadget
+ */
+
+#define CONFIG_USB_MUSB_PIO_ONLY
+#define CONFIG_USB_MUSB_OMAP2PLUS
+
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW	0
+
+/*
+ * Download
+ */
+
+#define CONFIG_USB_GADGET_DOWNLOAD
+
+#define CONFIG_G_DNL_VENDOR_NUM		0x0451
+#define CONFIG_G_DNL_PRODUCT_NUM	0xd022
+#define CONFIG_G_DNL_MANUFACTURER	"Texas Instruments"
+
+/*
+ * Fastboot
+ */
+
+#define CONFIG_USB_FUNCTION_FASTBOOT
+
+#define CONFIG_FASTBOOT_BUF_ADDR	CONFIG_SYS_LOAD_ADDR
+#define CONFIG_FASTBOOT_BUF_SIZE	0x2000000
+
+#define CONFIG_FASTBOOT_FLASH
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV	0
+
+#define CONFIG_CMD_FASTBOOT
+
+/*
+ * Environment
+ */
+
+#define CONFIG_ENV_SIZE		(128 * 1024)
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel_addr_r=0x82000000\0" \
+	"loadaddr=0x82000000\0" \
+	"fdt_addr_r=0x88000000\0" \
+	"fdtaddr=0x88000000\0" \
+	"ramdisk_addr_r=0x88080000\0" \
+	"pxefile_addr_r=0x80100000\0" \
+	"scriptaddr=0x80000000\0" \
+	"bootm_size=0x10000000\0" \
+	"boot_mmc_dev=0\0" \
+	"kernel_mmc_part=7\0" \
+	"recovery_mmc_part=5\0" \
+	"bootargs=mem=512M console=ttyO2\0"
+
+/*
+ * ATAGs
+ */
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+
+/*
+ * Boot
+ */
+
+#define CONFIG_SYS_LOAD_ADDR	0x82000000
+
+#define CONFIG_ANDROID_BOOT_IMAGE
+
+#define CONFIG_BOOTCOMMAND \
+	"setenv boot_mmc_part ${kernel_mmc_part}; " \
+	"if test reboot-${reboot-mode} = reboot-r; then " \
+	"echo recovery; setenv boot_mmc_part ${recovery_mmc_part}; fi; " \
+	"if test reboot-${reboot-mode} = reboot-b; then " \
+	"echo fastboot; fastboot 0; fi; " \
+	"part start mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_start; " \
+	"part size mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_size; " \
+	"mmc dev ${boot_mmc_dev}; " \
+	"mmc read ${kernel_addr_r} ${boot_mmc_start} ${boot_mmc_size} && " \
+	"bootm ${kernel_addr_r};"
+
+/*
+ * Defaults
+ */
+
+#include <config_defaults.h>
+#include <config_distro_defaults.h>
+
+#endif
diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index 91b29b3..5edc8f6 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h
@@ -83,7 +83,6 @@
 #define CONFIG_MTD_CONCAT
 
 #define CONFIG_CMD_CRAMFS
-#define CONFIG_CRAMFS_CMDLINE
 
 #ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS
 #define CONFIG_KM_DEF_ENV_BOOTPARAMS \
diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h
index eba7479..8293607 100644
--- a/include/configs/km/km-powerpc.h
+++ b/include/configs/km/km-powerpc.h
@@ -17,10 +17,6 @@
 #define CONFIG_CMD_DTT
 #define CONFIG_JFFS2_CMDLINE
 
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-
 /* standard km ethernet_present for piggy */
 #define CONFIG_KM_COMMON_ETH_INIT
 
diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h
index d86b7fc..6a9d739 100644
--- a/include/configs/km/km83xx-common.h
+++ b/include/configs/km/km83xx-common.h
@@ -151,8 +151,6 @@
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
 /*
  * QE UEC ethernet configuration
  */
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index d1f0b12..dfc1c7e 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -93,9 +93,6 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
 #define CONFIG_MISC_INIT_R
 
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-
 /*
  * NS16550 Configuration
  */
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index 6860ad2..d981951 100644
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -258,15 +258,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 /* I2C */
 
 #define CONFIG_SYS_I2C
diff --git a/include/configs/km82xx.h b/include/configs/km82xx.h
index 4cfc1dc..1f9c720 100644
--- a/include/configs/km82xx.h
+++ b/include/configs/km82xx.h
@@ -430,8 +430,6 @@
 
 #define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address */
 
-#define CONFIG_FIT		1
-
 #define OF_TBCLK		(bd->bi_busfreq / 4)
 #define OF_STDOUT_PATH		"/soc/cpm/serial@11a90"
 
diff --git a/include/configs/kwb.h b/include/configs/kwb.h
index 60e6496..1f2d2a4 100644
--- a/include/configs/kwb.h
+++ b/include/configs/kwb.h
@@ -112,7 +112,6 @@
 #undef CONFIG_BOOTM_RTEMS
 
 /* Support both device trees and ATAGs. */
-#define CONFIG_OF_LIBFDT
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
index d5cbb33..6c9eed4 100644
--- a/include/configs/kzm9g.h
+++ b/include/configs/kzm9g.h
@@ -23,7 +23,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_OF_LIBFDT
 
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
index f8cae40..842169d 100644
--- a/include/configs/lacie_kw.h
+++ b/include/configs/lacie_kw.h
@@ -176,11 +176,6 @@
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
 /*
- * Enable device tree support
- */
-#define CONFIG_OF_LIBFDT
-
-/*
  * Environment variables configurations
  */
 #define CONFIG_ENV_IS_IN_SPI_FLASH
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
new file mode 100644
index 0000000..79fa3c4
--- /dev/null
+++ b/include/configs/legoev3.h
@@ -0,0 +1,255 @@
+/*
+ * Copyright (C) 2016 David Lechner <david@lechnology.com>
+ *
+ * Based on da850evm.h
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_DAVINCI_DA850_EVM
+#define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
+#define CONFIG_SOC_DA850		/* TI DA850 SoC */
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ		24000000
+#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_DA850_PLL_INIT
+#define CONFIG_SYS_DA850_DDR_INIT
+
+#define CONFIG_SYS_TEXT_BASE		0xc1080000
+
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE	(64 << 20) /* SDRAM size 64MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END 	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
+
+#define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
+
+#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
+	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
+	DAVINCI_SYSCFG_SUSPSRC_SPI0 |		\
+	DAVINCI_SYSCFG_SUSPSRC_UART1 |		\
+	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
+	DAVINCI_SYSCFG_SUSPSRC_I2C)
+
+/*
+ * PLL configuration
+ */
+#define CONFIG_SYS_DV_CLKMODE          0
+#define CONFIG_SYS_DA850_PLL0_POSTDIV  1
+#define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
+#define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
+#define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
+#define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
+#define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
+#define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
+#define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005
+
+#define CONFIG_SYS_DA850_PLL1_POSTDIV  1
+#define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
+#define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
+#define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8002
+
+#define CONFIG_SYS_DA850_PLL0_PLLM     24
+#define CONFIG_SYS_DA850_PLL1_PLLM     21
+
+/*
+ * DDR2 memory configuration
+ */
+#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+					DV_DDR_PHY_EXT_STRBEN | \
+					(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDBCR (		\
+	(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |	\
+	(1 << DV_DDR_SDCR_DDREN_SHIFT) |	\
+	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |	\
+	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |	\
+	(0x3 << DV_DDR_SDCR_CL_SHIFT) |		\
+	(0x2 << DV_DDR_SDCR_IBANK_SHIFT) |	\
+	(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
+
+/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
+#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR (		\
+	(14 << DV_DDR_SDTMR1_RFC_SHIFT) |	\
+	(2 << DV_DDR_SDTMR1_RP_SHIFT) |		\
+	(2 << DV_DDR_SDTMR1_RCD_SHIFT) |	\
+	(1 << DV_DDR_SDTMR1_WR_SHIFT) |		\
+	(5 << DV_DDR_SDTMR1_RAS_SHIFT) |	\
+	(8 << DV_DDR_SDTMR1_RC_SHIFT) |		\
+	(1 << DV_DDR_SDTMR1_RRD_SHIFT) |	\
+	(0 << DV_DDR_SDTMR1_WTR_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		\
+	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |	\
+	(0 << DV_DDR_SDTMR2_XP_SHIFT) |		\
+	(0 << DV_DDR_SDTMR2_ODT_SHIFT) |	\
+	(17 << DV_DDR_SDTMR2_XSNR_SHIFT) |	\
+	(199 << DV_DDR_SDTMR2_XSRD_SHIFT) |	\
+	(0 << DV_DDR_SDTMR2_RTP_SHIFT) |	\
+	(0 << DV_DDR_SDTMR2_CKE_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
+#define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1	DAVINCI_UART1_BASE /* Base address of UART1 */
+#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+
+#define CONFIG_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI0_BASE
+#define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI0_CLKID)
+#define CONFIG_SF_DEFAULT_SPEED		50000000
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+
+/*
+ * I2C Configuration
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED		400000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE   10 /* Bogus, master-only in U-Boot */
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOOTFILE		"uImage" /* Boot file name */
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
+#define CONFIG_HWCONFIG		/* enable hwconfig */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SETUP_INITRD_TAG
+#define CONFIG_BOOTDELAY	0
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_BOOTCOMMAND \
+	"if mmc rescan; then " \
+		"if run loadbootscr; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loadimage; then " \
+				"run mmcargs; " \
+				"run mmcboot; " \
+			"else " \
+				"run flashargs; " \
+				"run flashboot; " \
+			"fi; " \
+		"fi; " \
+	"else " \
+		"run flashargs; " \
+		"run flashboot; " \
+	"fi"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"hostname=EV3\0" \
+	"memsize=64M\0" \
+	"filesyssize=10M\0" \
+	"verify=n\0" \
+	"console=ttyS1,115200n8\0" \
+	"bootscraddr=0xC0600000\0" \
+	"loadaddr=0xC0007FC0\0" \
+	"filesysaddr=0xC1180000\0" \
+	"fwupdateboot=mw 0xFFFF1FFC 0x5555AAAA; reset\0" \
+	"mmcargs=setenv bootargs mem=${memsize} console=${console} root=/dev/mmcblk0p2 rw rootwait lpj=747520\0" \
+	"mmcboot=bootm ${loadaddr}\0" \
+	"flashargs=setenv bootargs mem=${memsize} initrd=${filesysaddr},${filesyssize} root=/dev/ram0 rw rootfstype=squashfs console=${console} lpj=747520\0" \
+	"flashboot=sf probe 0; sf read ${loadaddr} 0x50000 0x300000; sf read ${filesysaddr} 0x350000 0x960000; bootm ${loadaddr}\0" \
+	"loadimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"loadbootscr=fatload mmc 0 ${bootscraddr} boot.scr\0" \
+	"bootscript=source ${bootscraddr}\0" \
+
+/*
+ * U-Boot commands
+ */
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+#define CONFIG_CMD_SPI
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE		(16 << 10)
+
+/* SD/MMC configuration */
+#define CONFIG_MMC
+#define CONFIG_DAVINCI_MMC_SD1
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DAVINCI_MMC
+
+/*
+ * Enable MMC commands only when
+ * MMC support is present
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT3
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+#endif
+
+/* additions for new relocation code, must added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		0xc0000000
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x80010000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 39d747f..d7025f6 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -666,9 +666,6 @@
 #define CONFIG_ENV_SECT_SIZE		0x20000 /* 128K (one sector) */
 #endif
 
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
 #define CONFIG_CMD_BOOTZ
 
 #define CONFIG_MISC_INIT_R
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index ae58646..cee6281 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -509,9 +509,6 @@
 #define CONFIG_ENV_SECT_SIZE		0x20000 /* 128K (one sector) */
 #endif
 
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
 #define CONFIG_CMD_BOOTZ
 
 #define CONFIG_MISC_INIT_R
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 6150bc1..ea25aad 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -28,14 +28,6 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BOARD_EARLY_INIT_F	1
 
-/* Flat Device Tree Definitions */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 #ifndef CONFIG_SYS_FSL_DDR4
 #define CONFIG_SYS_FSL_DDR3		/* Use DDR3 memory */
 #endif
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 158cf02..68e00c8 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -454,8 +454,6 @@
 #define CONFIG_ENV_SIZE			0x20000
 #endif
 
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_MII
 #define CONFIG_CMDLINE_TAG
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 64b82e8..c9b0a2f 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -44,15 +44,6 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BOARD_EARLY_INIT_F	1
 
-/* Flat Device Tree Definitions */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 #ifndef CONFIG_SPL
 #define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
 #endif
diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h
index 19ee5bc..8fb0135 100644
--- a/include/configs/lsxl.h
+++ b/include/configs/lsxl.h
@@ -37,7 +37,6 @@
 #define CONFIG_SHOW_BOOT_PROGRESS
 
 #define CONFIG_KIRKWOOD_GPIO
-#define CONFIG_OF_LIBFDT
 
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_SYS_HUSH_PARSER
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 69172bb..648e189 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -300,16 +300,9 @@
 					 CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
 					 CONFIG_SYS_I2C_DSPIC_IO_ADDR }
 
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
 /* Update size in "reg" property of NOR FLASH device tree nodes */
 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
 
-#define CONFIG_FIT			/* enable FIT image support	*/
-
 #define	CONFIG_POST_KEY_MAGIC	"3C+3E"	/* press F3 + F5 keys to force POST */
 
 #define	CONFIG_PREBOOT		"setenv bootdelay 15"
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index 8063a1e..57599f9 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -12,8 +12,6 @@
 #define MACH_TYPE_M28EVK	3613
 #define CONFIG_MACH_TYPE	MACH_TYPE_M28EVK
 
-#define CONFIG_FIT
-
 #define CONFIG_TIMESTAMP		/* Print image info with timestamp */
 
 /* U-Boot Commands */
diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index fbaa600..1efe48c 100644
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -19,8 +19,6 @@
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_SYS_FSL_CLK
 
-#define CONFIG_FIT
-
 #define CONFIG_TIMESTAMP		/* Print image info with timestamp */
 
 /*
@@ -247,7 +245,6 @@
 #define CONFIG_LOADADDR		0x70800000
 #define CONFIG_BOOTCOMMAND	"run mmc_mmc"
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
-#define CONFIG_OF_LIBFDT
 
 /*
  * NAND SPL
diff --git a/include/configs/ma5d4evk.h b/include/configs/ma5d4evk.h
index f0d5e9d..7f8a59f 100644
--- a/include/configs/ma5d4evk.h
+++ b/include/configs/ma5d4evk.h
@@ -10,8 +10,6 @@
 
 #define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_FIT
-
 #define CONFIG_TIMESTAMP		/* Print image info with timestamp */
 
 #include "at91-sama5_common.h"
diff --git a/include/configs/manroland/common.h b/include/configs/manroland/common.h
index 941290c..3c081a2 100644
--- a/include/configs/manroland/common.h
+++ b/include/configs/manroland/common.h
@@ -115,8 +115,4 @@
  */
 #define CONFIG_LOOPW
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #endif /* __MANROLAND_COMMON_H */
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 4eea06d..174cb5c 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -33,9 +33,6 @@
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap.h>
 
-#define CONFIG_OF_LIBFDT
-#define CONFIG_FIT
-
 /*
  * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
  * and older u-boot.bin with the new U-Boot SPL.
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
index 0f39964..e561026 100644
--- a/include/configs/mecp5123.h
+++ b/include/configs/mecp5123.h
@@ -427,9 +427,6 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-
 #define OF_CPU			"PowerPC,5121@0"
 #define OF_SOC_COMPAT		"fsl,mpc5121-immr"
 #define OF_TBCLK		(bd->bi_busfreq / 4)
diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h
index cd89fa5..4c05fc8 100644
--- a/include/configs/medcom-wide.h
+++ b/include/configs/medcom-wide.h
@@ -50,9 +50,6 @@
 /* LCD support */
 #define CONFIG_SYS_WHITE_ON_BLACK
 
-/* support the new (FDT-based) image format */
-#define CONFIG_FIT
-
 #include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index 10a6ce9..88fb3e8 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -57,7 +57,6 @@
 #define CONFIG_PREBOOT				/* enable preboot variable */
 
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_OF_LIBFDT
 
 /*
  * Hardware drivers
@@ -153,7 +152,6 @@
 /* Ethernet */
 #define CONFIG_MACB
 #define CONFIG_RMII
-#define CONFIG_FIT
 #define CONFIG_NET_RETRY_COUNT			20
 #undef CONFIG_RESET_PHY_R
 
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 97a0d86..27668f2 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -284,7 +284,6 @@
 
 /* Enable flat device tree support */
 #define CONFIG_LMB		1
-#define CONFIG_OF_LIBFDT	1
 
 #if defined(CONFIG_XILINX_AXIEMAC)
 # define CONFIG_MII		1
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 1cb135b..10ca05f 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -42,9 +42,6 @@
 #define VIDEO_IO_OFFSET				0
 #define CONFIG_X86EMU_RAW_IO
 
-#define CONFIG_FIT_SIGNATURE
-#define CONFIG_RSA
-
 #define CONFIG_ENV_SECT_SIZE		0x1000
 #define CONFIG_ENV_OFFSET		0x007fe000
 
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index a8cf201..f4d5dbc 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -377,10 +377,6 @@
 /* Not needed for MPC 5xxx U-Boot, but used by tools/updater */
 #define CONFIG_SYS_RESET_ADDRESS	0xfff00100
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #define OF_CPU			"PowerPC,5200@0"
 #define OF_SOC			"soc5200@f0000000"
 #define OF_TBCLK		(bd->bi_busfreq / 4)
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index 5f4e157..4ac291c 100644
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -586,8 +586,6 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
 
 #define OF_CPU			"PowerPC,5121@0"
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index a90083f..1bab9ab 100644
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -305,11 +305,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/munices.h b/include/configs/munices.h
index c34cba3..0601256 100644
--- a/include/configs/munices.h
+++ b/include/configs/munices.h
@@ -184,10 +184,6 @@
 #define CONFIG_SYS_CS_DEADCYCLE	0x33333333
 #define CONFIG_SYS_RESET_ADDRESS	0xff000000
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #define OF_CPU			"PowerPC,5200@0"
 #define OF_TBCLK		(bd->bi_busfreq / 4)
 #define OF_SOC                  "soc5200@f0000000"
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index d12d725..674aa0a 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -60,8 +60,6 @@
 #define CONFIG_BOOTDELAY	3	/* default enable autoboot */
 #define CONFIG_PREBOOT
 
-#define CONFIG_OF_LIBFDT		/* Device tree support */
-
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
diff --git a/include/configs/mv-plug-common.h b/include/configs/mv-plug-common.h
index d7d8d81..496bc1f 100644
--- a/include/configs/mv-plug-common.h
+++ b/include/configs/mv-plug-common.h
@@ -28,11 +28,6 @@
 #endif /* CONFIG_SYS_MVFS */
 
 /*
- * Enable device tree support
- */
-#define CONFIG_OF_LIBFDT
-
-/*
  * Commands configuration
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
index f113302..6dbeeca 100644
--- a/include/configs/mx25pdk.h
+++ b/include/configs/mx25pdk.h
@@ -82,7 +82,6 @@
 #define CONFIG_SYS_LONGHELP
 
 /* U-Boot commands */
-#define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_MMC
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index ae9f091..5f94e19 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -22,16 +22,6 @@
 
 #define CONFIG_MACH_TYPE	MACH_TYPE_MX31ADS
 
-/*
- * Disabled for now due to build problems under Debian and a significant increase
- * in the final file size: 144260 vs. 109536 Bytes.
- */
-#if 0
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_FIT			1
-#define CONFIG_FIT_VERBOSE		1
-#endif
-
 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS	1
 #define CONFIG_INITRD_TAG		1
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index 1b2f952..1177b0a 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -79,7 +79,6 @@
 /*
  * Command definition
  */
-#define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 32cd58e..31cd5bb 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -28,8 +28,6 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
 
-#define CONFIG_OF_LIBFDT
-
 #define CONFIG_MACH_TYPE	MACH_TYPE_MX51_BABBAGE
 /*
  * Size of malloc() pool
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index 25a4630..22e1b68 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -225,7 +225,6 @@
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV	0
 
-#define CONFIG_OF_LIBFDT
 
 #define MX53ARD_CS1GCR1		(CSEN | DSZ(2))
 #define MX53ARD_CS1RCR1		(RCSN(2) | OEN (1) | RWSC(22))
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index 37430f0..fca567d 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -25,8 +25,6 @@
 
 #define CONFIG_SYS_FSL_CLK
 
-#define CONFIG_OF_LIBFDT
-
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
 
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 54d3e3e..cfb3ae3 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -217,8 +217,6 @@
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV 0
 
-#define CONFIG_OF_LIBFDT
-
 #define CONFIG_CMD_SATA
 #ifdef CONFIG_CMD_SATA
 	#define CONFIG_DWC_AHSATA
diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
index d915b88..33d2163 100644
--- a/include/configs/mx53smd.h
+++ b/include/configs/mx53smd.h
@@ -159,6 +159,4 @@
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV 0
 
-#define CONFIG_OF_LIBFDT
-
 #endif				/* __CONFIG_H */
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 179b4f9..3abc773 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -69,7 +69,6 @@
 #define CONFIG_BAUDRATE         115200
 
 /* Filesystems and image support */
-#define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_SUPPORT_RAW_INITRD
 #define CONFIG_CMD_FS_GENERIC
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index 29d1f91..a6d821b 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -225,7 +225,11 @@
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK 260000000
+#ifdef CONFIG_MX6DL
+#define CONFIG_IPUV3_CLK 198000000
+#else
+#define CONFIG_IPUV3_CLK 264000000
+#endif
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index c7e10f9..2fff34a 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -187,7 +187,6 @@
 #define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
 #define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
 
-#define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_BMODE
 
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index bfad696..dcc53f0 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -50,7 +50,6 @@
 #define CONFIG_BAUDRATE                 115200
 
 /* Filesystems and image support */
-#define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_DOS_PARTITION
 #define CONFIG_CMD_EXT2
diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index 4c490ae..a4ffe75 100644
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
@@ -41,9 +41,6 @@
  * CPU specifics
  */
 
-/* MXS uses FDT */
-#define CONFIG_OF_LIBFDT
-
 /* Startup hooks */
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_ARCH_MISC_INIT
diff --git a/include/configs/nas220.h b/include/configs/nas220.h
index e5ff7e1..36a00d3 100644
--- a/include/configs/nas220.h
+++ b/include/configs/nas220.h
@@ -137,12 +137,6 @@
 #define CONFIG_SYS_ATA_IDE1_OFFSET      MV_SATA_PORT1_OFFSET
 #endif
 
-
-/*
- * Device Tree
- */
-#define CONFIG_OF_LIBFDT
-
 /*
  * EFI partition
  */
diff --git a/include/configs/neo.h b/include/configs/neo.h
index bc01416..bd2b190 100644
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -35,8 +35,6 @@
 #define PLLMR1_DEFAULT PLLMR1_266_133_66_33
 
 /* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
 #define CONFIG_FIT_DISABLE_SHA256
 
 #define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
diff --git a/include/configs/novena.h b/include/configs/novena.h
index a541613..d11cdc3 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -13,7 +13,6 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_LATE_INIT
 #define CONFIG_MISC_INIT_R
-#define CONFIG_FIT
 #define CONFIG_KEYBOARD
 
 #include <config_distro_defaults.h>
diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h
index d528fac..0b6173b 100644
--- a/include/configs/nyan-big.h
+++ b/include/configs/nyan-big.h
@@ -65,10 +65,6 @@
 /* General networking support */
 #define CONFIG_CMD_DHCP
 
-#define CONFIG_FIT
-#define CONFIG_FIT_BEST_MATCH
-#define CONFIG_OF_LIBFDT
-
 #define CONFIG_KEYBOARD
 
 #undef CONFIG_LOADADDR
diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h
index 8b0dbdc..73a44a7 100644
--- a/include/configs/o2dnt-common.h
+++ b/include/configs/o2dnt-common.h
@@ -332,9 +332,6 @@
 /*
  * DT support
  */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #define OF_CPU			"PowerPC,5200@0"
 #define OF_SOC			"soc5200@f0000000"
 #define OF_TBCLK		(bd->bi_busfreq / 4)
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index 8e67159..9d764d5 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -47,8 +47,6 @@
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE
 #define CONFIG_BOOTARGS			"Please use defined boot"
 #define CONFIG_BOOTCOMMAND		"run autoboot"
 #define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index bce4fad..fc7bfce 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -196,7 +196,6 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CRC32_VERIFY
 #define CONFIG_MX_CYCLIC
-#define CONFIG_OF_LIBFDT
 
 /*
  * Linux Information
diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h
index c854189..28e4275 100644
--- a/include/configs/openrisc-generic.h
+++ b/include/configs/openrisc-generic.h
@@ -120,7 +120,6 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PING
 
-#define CONFIG_OF_LIBFDT
 #define CONFIG_LMB
 
 /*
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 60bedaa..799521e 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -665,17 +665,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index 77ba2d8..1e49ee6 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -231,17 +231,6 @@
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL			/* Use FSL common I2C driver */
diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h
index 29feb7b..b4a7225 100644
--- a/include/configs/pcm030.h
+++ b/include/configs/pcm030.h
@@ -418,9 +418,6 @@
 #define CONFIG_USB_STORAGE
 
 /* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-
 #define OF_CPU				"PowerPC,5200@0"
 #define OF_TBCLK			CONFIG_SYS_MPC5XXX_CLKIN
 #define OF_SOC				"soc5200@f0000000"
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index 9d80306..4e29cf3 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -267,7 +267,6 @@
 #define CONFIG_ENV_OFFSET_REDUND	0xC0000
 #endif
 
-#define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
 
 #endif
diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h
index a6e7e9c..f2c05f8 100644
--- a/include/configs/pdm360ng.h
+++ b/include/configs/pdm360ng.h
@@ -461,11 +461,7 @@
 
 #define CONFIG_BOOTCOMMAND	"run env_cont"
 
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE
 
 #define OF_CPU			"PowerPC,5121@0"
 #define OF_SOC_COMPAT		"fsl,mpc5121-immr"
diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h
index 47613de..b2ba6fc 100644
--- a/include/configs/picosam9g45.h
+++ b/include/configs/picosam9g45.h
@@ -34,8 +34,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_OF_LIBFDT
-
 
 /* general purpose I/O */
 #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
diff --git a/include/configs/plutux.h b/include/configs/plutux.h
index 1d6df32..4590063 100644
--- a/include/configs/plutux.h
+++ b/include/configs/plutux.h
@@ -47,9 +47,6 @@
 /* General networking support */
 #define CONFIG_CMD_DHCP
 
-/* support the new (FDT-based) image format */
-#define CONFIG_FIT
-
 #include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h
index d896bca..145a933 100644
--- a/include/configs/pxm2.h
+++ b/include/configs/pxm2.h
@@ -149,8 +149,4 @@
 #define CONFIG_SYS_CONSOLE_FG_COL	0x00
 #endif
 
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_FIT
-#endif
-
 #endif	/* ! __CONFIG_PXM2_H */
diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
index 2dfea33..293684e 100644
--- a/include/configs/qemu-ppce500.h
+++ b/include/configs/qemu-ppce500.h
@@ -117,15 +117,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h
index f750b53..6bc33e0 100644
--- a/include/configs/rcar-gen2-common.h
+++ b/include/configs/rcar-gen2-common.h
@@ -40,7 +40,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 #define CONFIG_CMDLINE_EDITING
-#define CONFIG_OF_LIBFDT
 
 #define CONFIG_BAUDRATE		38400
 #define CONFIG_BOOTDELAY	3
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 427ac4b..5322685 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -19,7 +19,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SYS_THUMB_BUILD
-#define CONFIG_OF_LIBFDT
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_SYS_TIMER_RATE		(24 * 1000 * 1000)
diff --git a/include/configs/rpi-common.h b/include/configs/rpi-common.h
index 2c3b026..7250e37 100644
--- a/include/configs/rpi-common.h
+++ b/include/configs/rpi-common.h
@@ -126,8 +126,6 @@
 #define CONFIG_PARTITION_UUIDS
 #define CONFIG_CMD_PART
 
-/* Device tree support */
-#define CONFIG_OF_BOARD_SETUP
 /* ATAGs support for bootm/bootz */
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG
diff --git a/include/configs/rut.h b/include/configs/rut.h
index 78264ba..cf018e0 100644
--- a/include/configs/rut.h
+++ b/include/configs/rut.h
@@ -148,8 +148,4 @@
 #define CONFIG_SYS_CONSOLE_FG_COL	0x00
 #endif
 
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_FIT
-#endif
-
 #endif	/* ! __CONFIG_RUT_H */
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index f92c23d..40fb5ed 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -278,7 +278,4 @@
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
-#define CONFIG_OF_LIBFDT
-
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 4bffd8d..cc22467 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -28,7 +28,6 @@
 /* Number of bits in a C 'long' on this architecture */
 #define CONFIG_SANDBOX_BITS_PER_LONG	64
 
-#define CONFIG_OF_LIBFDT
 #define CONFIG_LMB
 #define CONFIG_CMD_FDT
 #define CONFIG_ANDROID_BOOT_IMAGE
@@ -44,6 +43,8 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_CBFS
+#define CONFIG_CMD_CRAMFS
 #define CONFIG_CMD_PART
 #define CONFIG_DOS_PARTITION
 #define CONFIG_HOST_MAX_DEVICES 4
@@ -53,8 +54,11 @@
 
 #define CONFIG_CMD_GPT
 #define CONFIG_PARTITION_UUIDS
-#define CONFIG_EFI_PARTITION
+#define CONFIG_AMIGA_PARTITION
 #define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_MAC_PARTITION
 
 /*
  * Size of malloc() pool, before and after relocation
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 25ec7bc..b74a268 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -282,11 +282,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 9783804..56c197c 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -419,11 +419,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
 /*
  * I2C
  */
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index f88d685..b7238fb 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -263,13 +263,6 @@
 #endif
 
 /*
- * Pass open firmware flat tree to kernel
- */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-/*
  * I2C
  */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index ebc3d64..c529636 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -60,12 +60,12 @@
  */
 #define CONFIG_BOOTCOMMAND		"${x_bootcmd_kernel}; "	\
 	"setenv bootargs ${x_bootargs} ${x_bootargs_root}; "	\
-	"${x_bootcmd_usb}; bootm 0x6400000;"
+	"bootm 0x6400000;"
 
 #define CONFIG_MTDPARTS		\
-	"mtdparts=orion_nand:512K(uboot),"				\
+	"orion_nand:512K(uboot),"				\
 	"512K(env),1M(script),6M(kernel),"				\
-	"12M(ramdisk),4M(spare),-(rootfs)"
+	"12M(ramdisk),4M(spare),-(rootfs)\0"
 
 #define CONFIG_EXTRA_ENV_SETTINGS	"x_bootargs=console"	\
 	"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS	\
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index eac7270..3a8b90e 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -625,7 +625,6 @@
 #define CONFIG_BOOTCOUNT_ENV
 
 /* Enable Device-Tree (FDT) support */
-#define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_FDT
 
 #endif	/* ! __CONFIG_SIEMENS_AM33X_COMMON_H */
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index de7b6bc..d06e648 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -241,12 +241,7 @@
 # undef CONFIG_CMD_NFS
 #endif /* CONFIG_MACB */
 
-#if !defined(CONFIG_SPL_BUILD)
-/* Enable Device-Tree (FDT) support */
-#define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_FDT
-#define CONFIG_FIT
-#endif
 
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_INIT_SP_ADDR		0x301000
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index db79e54..d52f500 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -214,7 +214,4 @@
 #define CONFIG_ENV_SROM_BANK   3       /* Select SROM Bank-3 for Ethernet*/
 #endif /* CONFIG_CMD_NET */
 
-#define CONFIG_OF_LIBFDT
-
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
index e5cf7d2..a708c68 100644
--- a/include/configs/snapper9260.h
+++ b/include/configs/snapper9260.h
@@ -29,7 +29,6 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_FIT
 
 /* SDRAM */
 #define CONFIG_NR_DRAM_BANKS		1
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 0501bd1..cd48c9e 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -24,8 +24,6 @@
 
 #define CONFIG_CRC32_VERIFY
 
-#define CONFIG_FIT
-#define CONFIG_OF_LIBFDT
 #define CONFIG_SYS_BOOTMAPSZ		(64 * 1024 * 1024)
 
 #define CONFIG_TIMESTAMP		/* Print image info with timestamp */
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index f8bddca..62be008 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -17,11 +17,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/* new uImage format support */
-#define CONFIG_FIT		1
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
-
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE			*/
 #define CONFIG_E500		1	/* BOOKE e500 family		*/
@@ -429,8 +424,6 @@
 #define CONFIG_BOOTCOMMAND	"run boot_nor"
 
 /* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
 
 /* USB support */
 #define CONFIG_USB_OHCI_NEW		1
diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h
index 85d492d..41f1b69 100644
--- a/include/configs/stm32f429-discovery.h
+++ b/include/configs/stm32f429-discovery.h
@@ -11,8 +11,6 @@
 #define CONFIG_SYS_THUMB_BUILD
 #define CONFIG_STM32F4DISCOVERY
 
-#define CONFIG_OF_LIBFDT
-
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_MISC_INIT_R
 
diff --git a/include/configs/strider.h b/include/configs/strider.h
index 8771cdc..0342400 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -30,10 +30,6 @@
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_LAST_STAGE_INIT
 
-/* new uImage format support */
-#define CONFIG_FIT			1
-#define CONFIG_FIT_VERBOSE		1
-
 #define CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
@@ -322,9 +318,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 
 /* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
 /* I2C */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index 6db628a..375159e 100644
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h
@@ -71,8 +71,6 @@
 #define CONFIG_BOOTDELAY                       3
 #define CONFIG_BOOTCOMMAND                     "go 0x40040000"
 
-#define CONFIG_OF_LIBFDT
-
 /*
 + * QSPI support
 + */
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 40850e5..b26363d 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -174,6 +174,7 @@
 
 #define CONFIG_SYS_MONITOR_LEN		(768 << 10)	/* 768 KiB */
 #define CONFIG_IDENT_STRING		" Allwinner Technology"
+#define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_ENV_OFFSET		(544 << 10) /* (8 + 24 + 512) KiB */
 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
@@ -296,11 +297,6 @@
 /* stop x86 thinking in cfbconsole from trying to init a pc keyboard */
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 
-/* To be able to hook simplefb into dt */
-#ifdef CONFIG_VIDEO_DT_SIMPLEFB
-#define CONFIG_OF_BOARD_SETUP
-#endif
-
 #endif /* CONFIG_VIDEO */
 
 /* Ethernet support */
diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h
index 7942865..1ac54e2 100644
--- a/include/configs/t3corp.h
+++ b/include/configs/t3corp.h
@@ -34,7 +34,6 @@
 #define CONFIG_BOARD_EARLY_INIT_R	1	/* Call board_early_init_r */
 #define CONFIG_MISC_INIT_R		1	/* Call misc_init_r */
 #define CONFIG_BOARD_TYPES		1	/* support board types */
-#define CONFIG_FIT
 #define CFG_ALT_MEMTEST
 
 /*
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 5788a70..ca6d285 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -157,15 +157,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index 2d941ca..a532417 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -258,8 +258,6 @@
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
 
-#define CONFIG_OF_LIBFDT
-#define CONFIG_FIT
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
 #define CONFIG_RBTREE
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index d5aba70..73cd0a0 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -46,8 +46,6 @@
 
 #define CONFIG_MISC_INIT_R
 
-#define CONFIG_OF_LIBFDT
-
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 1d6f9c3..c1581d8 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -52,7 +52,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_OF_LIBFDT
 
 /* general purpose I/O */
 #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
diff --git a/include/configs/tb100.h b/include/configs/tb100.h
index e06484f..62b9de3 100644
--- a/include/configs/tb100.h
+++ b/include/configs/tb100.h
@@ -68,8 +68,6 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PING
 
-#define CONFIG_OF_LIBFDT
-
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_MAXARGS		16
 
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index 0f23034..33ac955 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -61,7 +61,6 @@
 
 /* Filesystems / image support */
 #define CONFIG_EFI_PARTITION
-#define CONFIG_FIT
 
 /* MMC */
 #define CONFIG_SYS_FSL_USDHC_NUM	3
diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h
index a9e3e66..019e32c 100644
--- a/include/configs/tec-ng.h
+++ b/include/configs/tec-ng.h
@@ -58,8 +58,6 @@
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
-/* support the new (FDT-based) image format */
-#define CONFIG_FIT
 
 #include "tegra-common-post.h"
 
diff --git a/include/configs/tec.h b/include/configs/tec.h
index 50b9e97..a947214 100644
--- a/include/configs/tec.h
+++ b/include/configs/tec.h
@@ -50,9 +50,6 @@
 /* LCD support */
 #define CONFIG_SYS_WHITE_ON_BLACK
 
-/* support the new (FDT-based) image format */
-#define CONFIG_FIT
-
 #include "tegra-common-post.h"
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index ba819c4..b07ee56 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -141,6 +141,4 @@
 #define CONFIG_FAT_WRITE
 #endif
 
-#define CONFIG_OF_SYSTEM_SETUP
-
 #endif /* _TEGRA_COMMON_H_ */
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
index cd9d6b6..9f186ad 100644
--- a/include/configs/theadorable.h
+++ b/include/configs/theadorable.h
@@ -77,7 +77,6 @@
 #define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_PREBOOT
-#define CONFIG_FIT
 
 #define CONFIG_SYS_HUSH_PARSER			/* Use the HUSH parser	*/
 #define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h
index cece4dd..46d91e2 100644
--- a/include/configs/thunderx_88xx.h
+++ b/include/configs/thunderx_88xx.h
@@ -22,45 +22,12 @@
 
 #define MEM_BASE			0x00500000
 
-#define CONFIG_COREID_MASK             0xffffff
-
-#define CONFIG_SYS_FULL_VA
-
 #define CONFIG_SYS_LOWMEM_BASE		MEM_BASE
 
-#define CONFIG_SYS_MEM_MAP		{{0x000000000000UL, 0x40000000000UL, \
-					  PTL2_MEMTYPE(MT_NORMAL) |	     \
-					  PTL2_BLOCK_NON_SHARE},	     \
-					 {0x800000000000UL, 0x40000000000UL, \
-					  PTL2_MEMTYPE(MT_DEVICE_NGNRNE) |   \
-					  PTL2_BLOCK_NON_SHARE},	     \
-					 {0x840000000000UL, 0x40000000000UL, \
-					  PTL2_MEMTYPE(MT_DEVICE_NGNRNE) |   \
-					  PTL2_BLOCK_NON_SHARE},	     \
-					}
-
-#define CONFIG_SYS_MEM_MAP_SIZE		3
-
-#define CONFIG_SYS_VA_BITS		48
-#define CONFIG_SYS_PTL2_BITS		42
-#define CONFIG_SYS_BLOCK_SHIFT		29
-#define CONFIG_SYS_PTL1_ENTRIES		64
-#define CONFIG_SYS_PTL2_ENTRIES		8192
-
-#define CONFIG_SYS_PGTABLE_SIZE		\
-	((CONFIG_SYS_PTL1_ENTRIES + \
-	  CONFIG_SYS_MEM_MAP_SIZE * CONFIG_SYS_PTL2_ENTRIES) * 8)
-#define CONFIG_SYS_TCR_EL1_IPS_BITS	(5UL << 32)
-#define CONFIG_SYS_TCR_EL2_IPS_BITS	(5 << 16)
-#define CONFIG_SYS_TCR_EL3_IPS_BITS	(5 << 16)
-
 /* Link Definitions */
 #define CONFIG_SYS_TEXT_BASE		0x00500000
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fff0)
 
-/* Flat Device Tree Definitions */
-#define CONFIG_OF_LIBFDT
-
 /* SMP Spin Table Definitions */
 #define CPU_RELEASE_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fff0)
 
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index 3d0498d..f00072e 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -33,7 +33,6 @@
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_MACH_TYPE		MACH_TYPE_TI8148EVM
 
-#define CONFIG_OF_LIBFDT
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG		/* for ramdisk support */
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index 533fae7..e09efc7 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -28,7 +28,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_MACH_TYPE		MACH_TYPE_TI8168EVM
 
-#define CONFIG_OF_LIBFDT
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG		/* required for ramdisk support */
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
index edbd820..4535b8c 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -28,6 +28,7 @@
 #endif
 #define CONFIG_SYS_NS16550_CLK		48000000
 
+#ifndef CONFIG_SPL_BUILD
 /* Network defines. */
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
@@ -38,9 +39,10 @@
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_NET_RETRY_COUNT         10
 #define CONFIG_CMD_PING
-#define CONFIG_DRIVER_TI_CPSW		/* Driver for IP block */
 #define CONFIG_MII			/* Required in net/eth.c */
+#endif
 
+#define CONFIG_DRIVER_TI_CPSW		/* Driver for IP block */
 /*
  * RTC related defines. To use bootcount you must set bootlimit in the
  * environment to a non-zero value and enable CONFIG_BOOTCOUNT_LIMIT
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 199612b..787d04a 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -24,7 +24,6 @@
 #define CONFIG_SYS_NO_FLASH
 
 /* Support both device trees and ATAGs. */
-#define CONFIG_OF_LIBFDT
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
@@ -64,7 +63,30 @@
 	"args_mmc=run finduuid;setenv bootargs console=${console} " \
 		"${optargs} " \
 		"root=PARTUUID=${uuid} rw " \
-		"rootfstype=${mmcrootfstype}\0"
+		"rootfstype=${mmcrootfstype}\0" \
+	"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+		"source ${loadaddr}\0" \
+	"bootenvfile=uEnv.txt\0" \
+	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}\0" \
+	"envboot=mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${mmcdev};" \
+			"if run loadbootscript; then " \
+				"run bootscript;" \
+			"else " \
+				"if run loadbootenv; then " \
+					"echo Loaded env from ${bootenvfile};" \
+					"run importbootenv;" \
+				"fi;" \
+				"if test -n $uenvcmd; then " \
+					"echo Running uenvcmd ...;" \
+					"run uenvcmd;" \
+				"fi;" \
+			"fi;" \
+		"fi;\0" \
 
 /*
  * DDR information.  If the CONFIG_NR_DRAM_BANKS is not defined,
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index a7206f4..6a3beac 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -195,6 +195,7 @@
 #define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_XHCI_KEYSTONE
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
 #define CONFIG_EFI_PARTITION
 #define CONFIG_FS_FAT
 #define CONFIG_SYS_CACHELINE_SIZE		64
@@ -223,10 +224,31 @@
 /* EDMA3 */
 #define CONFIG_TI_EDMA3
 
+#define DEFAULT_FW_INITRAMFS_BOOT_ENV					\
+	"name_fw_rd=k2-fw-initrd.cpio.gz\0"				\
+	"set_rd_spec=setenv rd_spec ${rdaddr}:${filesize}\0"		\
+	"init_fw_rd_net=dhcp ${rdaddr} ${tftp_root}/${name_fw_rd}; "	\
+		"run set_rd_spec\0"					\
+	"init_fw_rd_ramfs=setenv rd_spec -\0"				\
+	"init_fw_rd_ubi=ubifsload ${rdaddr} ${bootdir}/${name_fw_rd}; "	\
+		"run set_rd_spec\0"					\
+
+#define DEFAULT_PMMC_BOOT_ENV						\
+	"set_name_pmmc=setenv name_pmmc ti-sci-firmware-${soc_variant}.bin\0" \
+	"dev_pmmc=0\0"							\
+	"get_pmmc_net=dhcp ${loadaddr} ${tftp_root}/${name_pmmc}\0"	\
+	"get_pmmc_ramfs=run get_pmmc_net\0"				\
+	"get_pmmc_mmc=load mmc ${bootpart} ${loadaddr} "		\
+			"${bootdir}/${name_pmmc}\0"			\
+	"get_pmmc_ubi=ubifsload ${loadaddr} ${bootdir}/${name_pmmc}\0"	\
+	"run_pmmc=rproc init; rproc list; "				\
+		"rproc load ${dev_pmmc} ${loadaddr} 0x${filesize}; "	\
+		"rproc start ${dev_pmmc}\0"				\
+
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	DEFAULT_LINUX_BOOT_ENV						\
 	CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS				\
-	"boot=ubi\0"							\
+	"bootdir=/boot\0" \
 	"tftp_root=/\0"							\
 	"nfs_root=/export\0"						\
 	"mem_lpae=1\0"							\
@@ -235,18 +257,22 @@
 	"addr_secdb_key=0xc000000\0"					\
 	"name_kern=zImage\0"						\
 	"run_mon=mon_install ${addr_mon}\0"				\
-	"run_kern=bootz ${loadaddr} - ${fdtaddr}\0"			\
+	"run_kern=bootz ${loadaddr} ${rd_spec} ${fdtaddr}\0"		\
 	"init_net=run args_all args_net\0"				\
+	"init_nfs=setenv autoload no; dhcp; run args_all args_net\0"	\
 	"init_ubi=run args_all args_ubi; "				\
-		"ubi part ubifs; ubifsmount ubi:boot;"			\
-		"ubifsload ${addr_secdb_key} securedb.key.bin;\0"       \
+		"ubi part ubifs; ubifsmount ubi:rootfs;\0"			\
 	"get_fdt_net=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0"	\
-	"get_fdt_ubi=ubifsload ${fdtaddr} ${name_fdt}\0"		\
+	"get_fdt_nfs=nfs ${fdtaddr} ${nfs_root}/boot/${name_fdt}\0"	\
+	"get_fdt_ubi=ubifsload ${fdtaddr} ${bootdir}/${name_fdt}\0"		\
 	"get_kern_net=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0"	\
-	"get_kern_ubi=ubifsload ${loadaddr} ${name_kern}\0"		\
+	"get_kern_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_kern}\0"	\
+	"get_kern_ubi=ubifsload ${loadaddr} ${bootdir}/${name_kern}\0"		\
 	"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"	\
-	"get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0"		\
+	"get_mon_nfs=nfs ${addr_mon} ${nfs_root}/boot/${name_mon}\0"	\
+	"get_mon_ubi=ubifsload ${addr_mon} ${bootdir}/${name_mon}\0"		\
 	"get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0"	\
+	"get_uboot_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_uboot}\0" \
 	"burn_uboot_spi=sf probe; sf erase 0 0x80000; "		\
 		"sf write ${loadaddr} 0 ${filesize}\0"		\
 	"burn_uboot_nand=nand erase 0 0x100000; "			\
@@ -261,6 +287,7 @@
 	"get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"	\
 	"get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs}\0"	\
 	"get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0"	\
+	"get_ubi_nfs=nfs ${addr_ubi} ${nfs_root}/boot/${name_ubi}\0"	\
 	"burn_ubi=nand erase.part ubifs; "				\
 		"nand write ${addr_ubi} ubifs ${filesize}\0"		\
 	"init_ramfs=run args_all args_ramfs get_fs_ramfs\0"		\
@@ -271,15 +298,14 @@
 	"mtdparts=mtdparts=davinci_nand.0:"				\
 		"1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"
 
+#ifndef CONFIG_BOOTCOMMAND
 #define CONFIG_BOOTCOMMAND						\
-	"run init_${boot} get_fdt_${boot} get_mon_${boot} "		\
-		"get_kern_${boot} run_mon run_kern"
+	"run init_${boot} init_fw_rd_${boot} get_fdt_${boot} "		\
+		"get_mon_${boot} get_kern_${boot} run_mon run_kern"
+#endif
 
 #define CONFIG_BOOTARGS							\
 
-/* Linux interfacing */
-#define CONFIG_OF_BOARD_SETUP
-
 /* Now for the remaining common defines */
 #include <configs/ti_armv7_common.h>
 
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
index 8b6c065..586d848 100644
--- a/include/configs/ti_omap4_common.h
+++ b/include/configs/ti_omap4_common.h
@@ -17,7 +17,6 @@
  */
 #define CONFIG_OMAP4430		1	/* which is in a 4430 */
 #define CONFIG_MISC_INIT_R
-#define CONFIG_ARCH_CPU_INIT
 #define CONFIG_DISPLAY_CPUINFO		1
 #define CONFIG_DISPLAY_BOARDINFO	1
 
@@ -104,6 +103,7 @@
 
 #define CONFIG_BOOTCOMMAND \
 	"run findfdt; " \
+	"run envboot; " \
 	"run distro_bootcmd"
 
 #include <config_distro_bootcmd.h>
@@ -118,12 +118,6 @@
 	"bootfile=zImage\0" \
 	"usbtty=cdc_acm\0" \
 	"vram=16M\0" \
-	"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
-	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
-		"source ${loadaddr}\0" \
-	"loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
-	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
-		"env import -t ${loadaddr} ${filesize}\0" \
 	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
 	"loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \
 	"mmcboot=echo Booting from mmc${mmcdev} ...; " \
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index d164e6a..202b18c 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -19,7 +19,6 @@
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_ARCH_CPU_INIT
 
 /* Common ARM Erratas */
 #define CONFIG_ARM_ERRATA_798870
@@ -85,22 +84,10 @@
 	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
 		"source ${loadaddr}\0" \
-	"bootenv=uEnv.txt\0" \
-	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
-	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
-		"env import -t ${loadaddr} ${filesize}\0" \
 	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
 	"mmcboot=mmc dev ${mmcdev}; " \
 		"if mmc rescan; then " \
 			"echo SD/MMC found on device ${mmcdev};" \
-			"if run loadbootenv; then " \
-				"echo Loaded environment from ${bootenv};" \
-				"run importbootenv;" \
-			"fi;" \
-			"if test -n $uenvcmd; then " \
-				"echo Running uenvcmd ...;" \
-				"run uenvcmd;" \
-			"fi;" \
 			"if run loadimage; then " \
 				"run loadfdt; " \
 				"echo Booting from mmc${mmcdev} ...; " \
@@ -117,6 +104,8 @@
 			"setenv fdtfile dra72-evm.dtb; fi;" \
 		"if test $board_name = beagle_x15; then " \
 			"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
+		"if test $board_name = am57xx_evm; then " \
+			"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
 		"if test $fdtfile = undefined; then " \
 			"echo WARNING: Could not determine device tree to use; fi; \0" \
 	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
@@ -131,6 +120,7 @@
 		"echo Booting into fastboot ...; fastboot 0;" \
 	"fi;" \
 	"run findfdt; " \
+	"run envboot; " \
 	"run mmcboot;" \
 	"setenv mmcdev 1; " \
 	"setenv bootpart 1:2; " \
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
index 31d7757..1fd3f2a 100644
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h
@@ -378,11 +378,6 @@
 #define CONFIG_SYS_INIT_SP_ADDR \
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE
-
 /*
  * All the defines above are for the TQMa6 SoM
  *
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 5fb991b..7caf0ac 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -49,8 +49,6 @@
 #define MACH_TYPE_TRATS			3928
 #define CONFIG_MACH_TYPE		MACH_TYPE_TRATS
 
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE
 #define CONFIG_BOOTARGS			"Please use defined boot"
 #define CONFIG_BOOTCOMMAND		"run autoboot"
 #define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index f12a952..a5f6c11 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -41,8 +41,6 @@
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE
 #define CONFIG_BOOTARGS			"Please use defined boot"
 #define CONFIG_BOOTCOMMAND		"run autoboot"
 #define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 2ec2f01..915cbd8 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -60,8 +60,6 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
 
-#define CONFIG_OF_LIBFDT
-
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(1024*1024)
 
diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h
index 50e1abb..fcc9d80 100644
--- a/include/configs/ts4800.h
+++ b/include/configs/ts4800.h
@@ -24,8 +24,6 @@
 
 #define CONFIG_HW_WATCHDOG
 
-#define CONFIG_OF_LIBFDT
-
 #define CONFIG_MACH_TYPE	MACH_TYPE_TS48XX
 
 /* text base address used when linking */
diff --git a/include/configs/tseries.h b/include/configs/tseries.h
index 43cf965..901dfd7 100644
--- a/include/configs/tseries.h
+++ b/include/configs/tseries.h
@@ -42,9 +42,7 @@
 #define CONFIG_POWER_TPS65217
 
 /* Support both device trees and ATAGs. */
-#define CONFIG_OF_LIBFDT
 #define CONFIG_USE_FDT			/* use fdt within board code */
-#define CONFIG_OF_BOARD_SETUP
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index b1c8ccb..1a74489 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -249,9 +249,6 @@
 
 #define CONFIG_SYS_BOOTMAPSZ			0x20000000
 
-/* Open Firmware flat tree */
-#define CONFIG_OF_LIBFDT
-
 #define CONFIG_SYS_SDRAM_BASE		0x80000000
 #define CONFIG_NR_DRAM_BANKS		2
 
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h
index 54daede..7b2f1ca 100644
--- a/include/configs/usb_a9263.h
+++ b/include/configs/usb_a9263.h
@@ -33,7 +33,6 @@
 
 #define CONFIG_DISPLAY_CPUINFO
 
-#define CONFIG_OF_LIBFDT
 #define CONFIG_SYS_TEXT_BASE		0x23f00000
 
 /*
diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h
index 6f66662..7e24fc6 100644
--- a/include/configs/usbarmory.h
+++ b/include/configs/usbarmory.h
@@ -16,7 +16,6 @@
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_SYS_FSL_CLK
 #define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_OF_LIBFDT
 #define CONFIG_MXC_GPIO
 
 #include <asm/arch/imx-regs.h>
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index bc2d441..de5c3ce 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -242,11 +242,6 @@
 				| OR_GPCM_EAD)
 				/* 0xfe0009f7 */
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
 /*
  * Serial Port
  */
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index 133041b..31b1a24 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -19,9 +19,8 @@
 
 #define CONFIG_SUPPORT_RAW_INITRD
 
-/* Cache Definitions */
-#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_ICACHE_OFF
+/* MMU Definitions */
+#define CONFIG_SYS_CACHELINE_SIZE	64
 
 #define CONFIG_IDENT_STRING		" vexpress_aemv8a"
 #define CONFIG_BOOTP_VCI_STRING		"U-Boot.armv8.vexpress_aemv8a"
@@ -39,9 +38,6 @@
 
 #define CONFIG_SYS_BOOTM_LEN (64 << 20)      /* Increase max gunzip size */
 
-/* Flat Device Tree Definitions */
-#define CONFIG_OF_LIBFDT
-
 /* CS register bases for the original memory map. */
 #define V2M_PA_CS0			0x00000000
 #define V2M_PA_CS1			0x14000000
@@ -192,7 +188,7 @@
 				"kernel_addr=0x80080000\0" \
 				"initrd_name=ramdisk.img\0"	\
 				"initrd_addr=0x84000000\0"	\
-				"fdt_name=board.dtb\0" \
+				"fdtfile=board.dtb\0" \
 				"fdt_alt_name=juno\0" \
 				"fdt_addr=0x83000000\0" \
 				"fdt_high=0xffffffffffffffff\0" \
@@ -214,10 +210,10 @@
 				"${kernel_name}; "\
 				"  afs load ${kernel_alt_name} ${kernel_addr};"\
 				"fi ; "\
-				"afs load  ${fdt_name} ${fdt_addr} ; " \
+				"afs load  ${fdtfile} ${fdt_addr} ; " \
 				"if test $? -eq 1; then "\
 				"  echo Loading ${fdt_alt_name} instead of "\
-				"${fdt_name}; "\
+				"${fdtfile}; "\
 				"  afs load ${fdt_alt_name} ${fdt_addr}; "\
 				"fi ; "\
 				"fdt addr ${fdt_addr}; fdt resize; " \
@@ -236,7 +232,7 @@
 				"kernel_addr=0x80080000\0"	\
 				"initrd_name=ramdisk.img\0"	\
 				"initrd_addr=0x88000000\0"	\
-				"fdt_name=devtree.dtb\0"	\
+				"fdtfile=devtree.dtb\0"		\
 				"fdt_addr=0x83000000\0"		\
 				"fdt_high=0xffffffffffffffff\0"	\
 				"initrd_high=0xffffffffffffffff\0"
@@ -246,7 +242,7 @@
 				"loglevel=9"
 
 #define CONFIG_BOOTCOMMAND	"smhload ${kernel_name} ${kernel_addr}; " \
-				"smhload ${fdt_name} ${fdt_addr}; " \
+				"smhload ${fdtfile} ${fdt_addr}; " \
 				"smhload ${initrd_name} ${initrd_addr} "\
 				"initrd_end; " \
 				"fdt addr ${fdt_addr}; fdt resize; " \
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 955aef4..0809fbb 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -274,7 +274,6 @@
 #define CONFIG_ENV_OFFSET		0x180000
 #endif
 
-#define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
 
 #endif
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 714ebee..7433d7e 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -215,11 +215,6 @@
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 0263c50..ac477eb 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -152,7 +152,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_BOOT_PARAMS_ADDR			0x00000100
 #define CONFIG_CMDLINE_TAG
-#define CONFIG_OF_LIBFDT		/* enable passing of devicetree */
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_MISC_INIT_R
 #define CONFIG_BOARD_LATE_INIT
diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index c575dab..312987e 100644
--- a/include/configs/x86-chromebook.h
+++ b/include/configs/x86-chromebook.h
@@ -1,5 +1,4 @@
 /*
- *
  * Copyright (c) 2015 Google, Inc
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -14,13 +13,16 @@
 #define CONFIG_MISC_INIT_R
 
 #define CONFIG_X86_MRC_ADDR			0xfffa0000
+#define CONFIG_X86_REFCODE_ADDR			0xffea0000
+#define CONFIG_X86_REFCODE_RUN_ADDR		0
 
 #define CONFIG_SCSI_DEV_LIST	\
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}, \
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI}
 
 #define CONFIG_PCI_MEM_BUS	0xe0000000
 #define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
@@ -49,6 +51,8 @@
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_OFFSET		0x003f8000
 
+#define CONFIG_SYS_WHITE_ON_BLACK
+
 #define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,i8042-kbd,serial\0" \
 					"stdout=vga,serial\0" \
 					"stderr=vga,serial\0"
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index 3ae4366..ea815c2 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -24,10 +24,8 @@
 #define CONFIG_NR_DRAM_BANKS		8
 
 #define CONFIG_LMB
-#define CONFIG_OF_LIBFDT
 
 #define CONFIG_LZO
-#define CONFIG_FIT
 #undef CONFIG_ZLIB
 #undef CONFIG_GZIP
 #define CONFIG_SYS_BOOTM_LEN		(16 << 20)
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 1121ea4..9d9ffd0 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -42,7 +42,6 @@
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fff0)
 
 /* Flat Device Tree Definitions */
-#define CONFIG_OF_LIBFDT
 
 /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */
 #if !defined(COUNTER_FREQUENCY)
diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h
index 5bc926f..6f162dc 100644
--- a/include/configs/xpedite1000.h
+++ b/include/configs/xpedite1000.h
@@ -210,8 +210,6 @@
 #define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
 #define CONFIG_PREBOOT				/* enable preboot variable */
-#define CONFIG_FIT		1
-#define CONFIG_FIT_VERBOSE	1
 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h
index 96b357b..70af1e1 100644
--- a/include/configs/xpedite517x.h
+++ b/include/configs/xpedite517x.h
@@ -231,13 +231,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 
 /*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-/*
  * I2C
  */
 #define CONFIG_SYS_I2C
@@ -557,8 +550,6 @@
 #define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
 #define CONFIG_PREBOOT				/* enable preboot variable */
-#define CONFIG_FIT		1
-#define CONFIG_FIT_VERBOSE	1
 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
 
 /*
diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h
index b2d6a1e..1972373 100644
--- a/include/configs/xpedite520x.h
+++ b/include/configs/xpedite520x.h
@@ -194,13 +194,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 
 /*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-/*
  * I2C
  */
 #define CONFIG_SYS_I2C
@@ -340,8 +333,6 @@
 #define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
 #define CONFIG_PREBOOT				/* enable preboot variable */
-#define CONFIG_FIT		1
-#define CONFIG_FIT_VERBOSE	1
 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
 
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index 8b4d4d9..1be043f 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -230,13 +230,6 @@
 #define CONFIG_SYS_HUSH_PARSER
 
 /*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-/*
  * I2C
  */
 #define CONFIG_SYS_I2C
@@ -412,8 +405,6 @@
 #define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
 #define CONFIG_PREBOOT				/* enable preboot variable */
-#define CONFIG_FIT		1
-#define CONFIG_FIT_VERBOSE	1
 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
 
 /*
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index c7e25d9..0697714 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -220,12 +220,6 @@
  */
 #define CONFIG_SYS_HUSH_PARSER
 
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
 #define CONFIG_FDT_FIXUP_PCI_IRQ	1
 
 /*
@@ -397,8 +391,6 @@
 #define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
 #define CONFIG_PREBOOT				/* enable preboot variable */
-#define CONFIG_FIT		1
-#define CONFIG_FIT_VERBOSE	1
 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
 
 /*
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 982905d..77edbb8 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -274,9 +274,6 @@
 #define CONFIG_CMD_FPGA_LOADBP
 #define CONFIG_CMD_FPGA_LOADFS
 
-/* Open Firmware flat tree */
-#define CONFIG_OF_LIBFDT
-
 /* FIT support */
 #define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */
 
diff --git a/include/cpu.h b/include/cpu.h
index bfb0db2..bda5315 100644
--- a/include/cpu.h
+++ b/include/cpu.h
@@ -15,15 +15,20 @@
  * device.
  *
  * @cpu_id:	Platform-specific way of identifying the CPU.
+ * @ucode_version: Microcode version, if CPU_FEAT_UCODE is set
  */
 struct cpu_platdata {
 	int cpu_id;
+	int ucode_version;
+	ulong device_id;
 };
 
 /* CPU features - mostly just a placeholder for now */
 enum {
 	CPU_FEAT_L1_CACHE	= 0,	/* Supports level 1 cache */
 	CPU_FEAT_MMU		= 1,	/* Supports virtual memory */
+	CPU_FEAT_UCODE		= 2,	/* Requires/uses microcode */
+	CPU_FEAT_DEVICE_ID	= 3,	/* Provides a device ID */
 
 	CPU_FEAT_COUNT,
 };
diff --git a/include/crc.h b/include/crc.h
index 5085d4e..111cb4a 100644
--- a/include/crc.h
+++ b/include/crc.h
@@ -36,34 +36,8 @@
 # endif
 #endif
 
-/* Compute a CRC, using the POSIX 1003 definition */
-extern uint32_t
-cyg_posix_crc32(unsigned char *s, int len);
-
-/* Gary S. Brown's 32 bit CRC */
-
-extern uint32_t
-cyg_crc32(unsigned char *s, int len);
-
-/* Gary S. Brown's 32 bit CRC, but accumulate the result from a */
-/* previous CRC calculation */
-
-extern uint32_t
-cyg_crc32_accumulate(uint32_t crc, unsigned char *s, int len);
-
-/* Ethernet FCS Algorithm */
-
-extern uint32_t
-cyg_ether_crc32(unsigned char *s, int len);
-
-/* Ethernet FCS algorithm, but accumulate the result from a previous */
-/* CRC calculation. */
-
-extern uint32_t
-cyg_ether_crc32_accumulate(uint32_t crc, unsigned char *s, int len);
-
-/* 16 bit CRC with polynomial x^16+x^12+x^5+1 */
+/* 16 bit CRC with polynomial x^16+x^12+x^5+1 (CRC-CCITT) */
 
-extern uint16_t cyg_crc16(unsigned char *s, int len);
+uint16_t crc16_ccitt(uint16_t crc_start, unsigned char *s, int len);
 
 #endif /* _SERVICES_CRC_CRC_H_ */
diff --git a/include/debug_uart.h b/include/debug_uart.h
index 5d5349b..0d640b9 100644
--- a/include/debug_uart.h
+++ b/include/debug_uart.h
@@ -117,13 +117,15 @@
 #define DEBUG_UART_FUNCS \
 	void printch(int ch) \
 	{ \
+		if (ch == '\n') \
+			_debug_uart_putc('\r'); \
 		_debug_uart_putc(ch); \
 	} \
 \
 	void printascii(const char *str) \
 	{ \
 		while (*str) \
-			_debug_uart_putc(*str++); \
+			printch(*str++); \
 	} \
 \
 	static inline void printhex1(uint digit) \
diff --git a/include/display.h b/include/display.h
index c180e76..b1c4766 100644
--- a/include/display.h
+++ b/include/display.h
@@ -23,7 +23,7 @@
 };
 
 /**
- * display_read_timing() - Read timing information from EDID
+ * display_read_timing() - Read timing information
  *
  * @dev:	Device to read from
  * @return 0 if OK, -ve on error
@@ -43,6 +43,15 @@
 
 struct dm_display_ops {
 	/**
+	 * read_timing() - Read information directly
+	 *
+	 * @dev:	Device to read from
+	 * @timing:	Display timings
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*read_timing)(struct udevice *dev, struct display_timing *timing);
+
+	/**
 	 * read_edid() - Read information from EDID
 	 *
 	 * @dev:	Device to read from
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 3bea308..37c4176 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -26,6 +26,7 @@
 
 	/* U-Boot uclasses start here - in alphabetical order */
 	UCLASS_ADC,		/* Analog-to-digital converter */
+	UCLASS_BLK,		/* Block device */
 	UCLASS_CLK,		/* Clock source, e.g. used by peripherals */
 	UCLASS_CPU,		/* CPU, typically part of an SoC */
 	UCLASS_CROS_EC,		/* Chrome OS EC */
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index bfbd27a..fd368b6 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -200,18 +200,29 @@
  *
  * @id: Uclass ID to look up
  * @devp: Returns pointer to the first device in that uclass, or NULL if none
- * @return 0 if OK (found or not found), -1 on error
+ * @return 0 if OK (found or not found), other -ve on error
  */
 int uclass_first_device(enum uclass_id id, struct udevice **devp);
 
 /**
+ * uclass_first_device_err() - Get the first device in a uclass
+ *
+ * The device returned is probed if necessary, and ready for use
+ *
+ * @id: Uclass ID to look up
+ * @devp: Returns pointer to the first device in that uclass, or NULL if none
+ * @return 0 if found, -ENODEV if not found, other -ve on error
+ */
+int uclass_first_device_err(enum uclass_id id, struct udevice **devp);
+
+/**
  * uclass_next_device() - Get the next device in a uclass
  *
  * The device returned is probed if necessary, and ready for use
  *
  * @devp: On entry, pointer to device to lookup. On exit, returns pointer
  * to the next device in the same uclass, or NULL if none
- * @return 0 if OK (found or not found), -1 on error
+ * @return 0 if OK (found or not found), other -ve on error
  */
 int uclass_next_device(struct udevice **devp);
 
diff --git a/include/dt-bindings/gpio/x86-gpio.h b/include/dt-bindings/gpio/x86-gpio.h
index 7f1de30..3998a8e 100644
--- a/include/dt-bindings/gpio/x86-gpio.h
+++ b/include/dt-bindings/gpio/x86-gpio.h
@@ -28,4 +28,16 @@
 #define PULL_STR_2K		0
 #define PULL_STR_20K	2
 
+#define ROUTE_SCI	0
+#define ROUTE_SMI	1
+
+#define OWNER_ACPI	0
+#define OWNER_GPIO	1
+
+#define PIRQ_APIC_MASK	0
+#define PIRQ_APIC_ROUTE	1
+
+#define TRIGGER_EDGE	0
+#define TRIGGER_LEVEL	1
+
 #endif
diff --git a/include/dt-bindings/video/rk3288.h b/include/dt-bindings/video/rk3288.h
new file mode 100644
index 0000000..7bfd247
--- /dev/null
+++ b/include/dt-bindings/video/rk3288.h
@@ -0,0 +1,11 @@
+#ifndef __DT_BINDINGS_VIDEO_RK3288_H__
+#define __DT_BINDINGS_VIDEO_RK3288_H__
+
+#define LVDS_OUTPUT_RGB     0
+#define LVDS_OUTPUT_SINGLE  1
+#define LVDS_OUTPUT_DUAL    2
+
+#define LVDS_FORMAT_VESA    0
+#define LVDS_FORMAT_JEIDA   1
+
+#endif
diff --git a/include/efi.h b/include/efi.h
index fcafda0..1dbc3b7 100644
--- a/include/efi.h
+++ b/include/efi.h
@@ -38,6 +38,7 @@
 #define EFI_WRITE_PROTECTED	(8 | (1UL << (BITS_PER_LONG - 1)))
 #define EFI_OUT_OF_RESOURCES	(9 | (1UL << (BITS_PER_LONG - 1)))
 #define EFI_NOT_FOUND		(14 | (1UL << (BITS_PER_LONG - 1)))
+#define EFI_ACCESS_DENIED	(15 | (1UL << (BITS_PER_LONG - 1)))
 #define EFI_SECURITY_VIOLATION	(26 | (1UL << (BITS_PER_LONG - 1)))
 
 typedef unsigned long efi_status_t;
@@ -139,6 +140,7 @@
 
 #define EFI_PAGE_SHIFT		12
 #define EFI_PAGE_SIZE		(1UL << EFI_PAGE_SHIFT)
+#define EFI_PAGE_MASK		(EFI_PAGE_SIZE - 1)
 
 struct efi_mem_desc {
 	u32 type;
diff --git a/include/efi_api.h b/include/efi_api.h
index 4fd17d6..03f6687 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -17,11 +17,18 @@
 
 #include <efi.h>
 
+/* Types and defines for EFI CreateEvent */
+enum efi_event_type {
+	EFI_TIMER_STOP = 0,
+	EFI_TIMER_PERIODIC = 1,
+	EFI_TIMER_RELATIVE = 2
+};
+
 /* EFI Boot Services table */
 struct efi_boot_services {
 	struct efi_table_hdr hdr;
-	void *raise_tpl;
-	void *restore_tpl;
+	efi_status_t (EFIAPI *raise_tpl)(unsigned long new_tpl);
+	void (EFIAPI *restore_tpl)(unsigned long old_tpl);
 
 	efi_status_t (EFIAPI *allocate_pages)(int, int, unsigned long,
 					      efi_physical_addr_t *);
@@ -32,21 +39,33 @@
 	efi_status_t (EFIAPI *allocate_pool)(int, unsigned long, void **);
 	efi_status_t (EFIAPI *free_pool)(void *);
 
-	void *create_event;
-	void *set_timer;
-	efi_status_t(EFIAPI *wait_for_event)(unsigned long number_of_events,
-					     void *event, unsigned long *index);
-	void *signal_event;
-	void *close_event;
-	void *check_event;
+	efi_status_t (EFIAPI *create_event)(enum efi_event_type type,
+			unsigned long notify_tpl,
+			void (EFIAPI *notify_function) (void *event,
+							void *context),
+			void *notify_context, void **event);
+	efi_status_t (EFIAPI *set_timer)(void *event, int type,
+			uint64_t trigger_time);
+	efi_status_t (EFIAPI *wait_for_event)(unsigned long number_of_events,
+			void *event, unsigned long *index);
+	efi_status_t (EFIAPI *signal_event)(void *event);
+	efi_status_t (EFIAPI *close_event)(void *event);
+	efi_status_t (EFIAPI *check_event)(void *event);
 
-	void *install_protocol_interface;
-	void *reinstall_protocol_interface;
-	void *uninstall_protocol_interface;
+	efi_status_t (EFIAPI *install_protocol_interface)(
+			void **handle, efi_guid_t *protocol,
+			int protocol_interface_type, void *protocol_interface);
+	efi_status_t (EFIAPI *reinstall_protocol_interface)(
+			void *handle, efi_guid_t *protocol,
+			void *old_interface, void *new_interface);
+	efi_status_t (EFIAPI *uninstall_protocol_interface)(void *handle,
+			efi_guid_t *protocol, void *protocol_interface);
 	efi_status_t (EFIAPI *handle_protocol)(efi_handle_t, efi_guid_t *,
 					       void **);
 	void *reserved;
-	void *register_protocol_notify;
+	efi_status_t (EFIAPI *register_protocol_notify)(
+			efi_guid_t *protocol, void *event,
+			void **registration);
 	efi_status_t (EFIAPI *locate_handle)(
 			enum efi_locate_search_type search_type,
 			efi_guid_t *protocol, void *search_key,
@@ -54,7 +73,8 @@
 	efi_status_t (EFIAPI *locate_device_path)(efi_guid_t *protocol,
 			struct efi_device_path **device_path,
 			efi_handle_t *device);
-	void *install_configuration_table;
+	efi_status_t (EFIAPI *install_configuration_table)(
+			efi_guid_t *guid, void *table);
 
 	efi_status_t (EFIAPI *load_image)(bool boot_policiy,
 			efi_handle_t parent_image,
@@ -66,17 +86,20 @@
 	efi_status_t (EFIAPI *exit)(efi_handle_t handle,
 				    efi_status_t exit_status,
 				    unsigned long exitdata_size, s16 *exitdata);
-	void *unload_image;
+	efi_status_t (EFIAPI *unload_image)(void *image_handle);
 	efi_status_t (EFIAPI *exit_boot_services)(efi_handle_t, unsigned long);
 
 	efi_status_t (EFIAPI *get_next_monotonic_count)(u64 *count);
 	efi_status_t (EFIAPI *stall)(unsigned long usecs);
-	void *set_watchdog_timer;
+	efi_status_t (EFIAPI *set_watchdog_timer)(unsigned long timeout,
+			uint64_t watchdog_code, unsigned long data_size,
+			uint16_t *watchdog_data);
 	efi_status_t(EFIAPI *connect_controller)(efi_handle_t controller_handle,
 			efi_handle_t *driver_image_handle,
 			struct efi_device_path *remaining_device_path,
 			bool recursive);
-	void *disconnect_controller;
+	efi_status_t (EFIAPI *disconnect_controller)(void *controller_handle,
+			void *driver_image_handle, void *child_handle);
 #define EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL  0x00000001
 #define EFI_OPEN_PROTOCOL_GET_PROTOCOL        0x00000002
 #define EFI_OPEN_PROTOCOL_TEST_PROTOCOL       0x00000004
@@ -87,7 +110,9 @@
 			efi_guid_t *protocol, void **interface,
 			efi_handle_t agent_handle,
 			efi_handle_t controller_handle, u32 attributes);
-	void *close_protocol;
+	efi_status_t (EFIAPI *close_protocol)(void *handle,
+			efi_guid_t *protocol, void *agent_handle,
+			void *controller_handle);
 	efi_status_t(EFIAPI *open_protocol_information)(efi_handle_t handle,
 			efi_guid_t *protocol,
 			struct efi_open_protocol_info_entry **entry_buffer,
@@ -99,12 +124,18 @@
 			enum efi_locate_search_type search_type,
 			efi_guid_t *protocol, void *search_key,
 			unsigned long *no_handles, efi_handle_t **buffer);
-	void *locate_protocol;
-	void *install_multiple_protocol_interfaces;
-	void *uninstall_multiple_protocol_interfaces;
-	void *calculate_crc32;
-	void *copy_mem;
-	void *set_mem;
+	efi_status_t (EFIAPI *locate_protocol)(efi_guid_t *protocol,
+			void *registration, void **protocol_interface);
+	efi_status_t (EFIAPI *install_multiple_protocol_interfaces)(
+			void **handle, ...);
+	efi_status_t (EFIAPI *uninstall_multiple_protocol_interfaces)(
+			void *handle, ...);
+	efi_status_t (EFIAPI *calculate_crc32)(void *data,
+			unsigned long data_size, uint32_t *crc32);
+	void (EFIAPI *copy_mem)(void *destination, void *source,
+			unsigned long length);
+	void (EFIAPI *set_mem)(void *buffer, unsigned long size,
+			uint8_t value);
 	void *create_event_ex;
 };
 
@@ -121,12 +152,19 @@
 
 struct efi_runtime_services {
 	struct efi_table_hdr hdr;
-	void *get_time;
-	void *set_time;
-	void *get_wakeup_time;
-	void *set_wakeup_time;
-	void *set_virtual_address_map;
-	void *convert_pointer;
+	efi_status_t (EFIAPI *get_time)(struct efi_time *time,
+			struct efi_time_cap *capabilities);
+	efi_status_t (EFIAPI *set_time)(struct efi_time *time);
+	efi_status_t (EFIAPI *get_wakeup_time)(char *enabled, char *pending,
+			struct efi_time *time);
+	efi_status_t (EFIAPI *set_wakeup_time)(char enabled,
+			struct efi_time *time);
+	efi_status_t (EFIAPI *set_virtual_address_map)(
+			unsigned long memory_map_size,
+			unsigned long descriptor_size,
+			uint32_t descriptor_version,
+			struct efi_mem_desc *virtmap);
+	efi_status_t (*convert_pointer)(unsigned long dbg, void **address);
 	efi_status_t (EFIAPI *get_variable)(s16 *variable_name,
 			efi_guid_t *vendor, u32 *attributes,
 			unsigned long *data_size, void *data);
@@ -136,7 +174,8 @@
 	efi_status_t (EFIAPI *set_variable)(s16 *variable_name,
 			efi_guid_t *vendor, u32 attributes,
 			unsigned long data_size, void *data);
-	void *get_next_high_mono_count;
+	efi_status_t (EFIAPI *get_next_high_mono_count)(
+			uint32_t *high_count);
 	void (EFIAPI *reset_system)(enum efi_reset_type reset_type,
 				    efi_status_t reset_status,
 				    unsigned long data_size, void *reset_data);
@@ -154,6 +193,18 @@
 	EFI_GUID(0x5b1b31a1, 0x9562, 0x11d2, 0x8e, 0x3f, \
 		 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
 
+#define EFI_FDT_GUID \
+	EFI_GUID(0xb1b621d5, 0xf19c, 0x41a5, \
+		 0x83, 0x0b, 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0)
+
+struct efi_configuration_table
+{
+	efi_guid_t guid;
+	void *table;
+};
+
+#define EFI_SYSTEM_TABLE_SIGNATURE ((u64)0x5453595320494249ULL)
+
 struct efi_system_table {
 	struct efi_table_hdr hdr;
 	unsigned long fw_vendor;   /* physical addr of wchar_t vendor string */
@@ -163,13 +214,17 @@
 	unsigned long con_out_handle;
 	struct efi_simple_text_output_protocol *con_out;
 	unsigned long stderr_handle;
-	unsigned long std_err;
+	struct efi_simple_text_output_protocol *std_err;
 	struct efi_runtime_services *runtime;
 	struct efi_boot_services *boottime;
 	unsigned long nr_tables;
-	unsigned long tables;
+	struct efi_configuration_table *tables;
 };
 
+#define LOADED_IMAGE_GUID \
+	EFI_GUID(0x5b1b31a1, 0x9562, 0x11d2, \
+		 0x8e, 0x3f, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
+
 struct efi_loaded_image {
 	u32 revision;
 	void *parent_handle;
@@ -186,12 +241,60 @@
 	unsigned long unload;
 };
 
+#define DEVICE_PATH_GUID \
+	EFI_GUID(0x09576e91, 0x6d3f, 0x11d2, \
+		 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b )
+
+#define DEVICE_PATH_TYPE_END			0x7f
+#  define DEVICE_PATH_SUB_TYPE_END		0xff
+
 struct efi_device_path {
 	u8 type;
 	u8 sub_type;
 	u16 length;
 };
 
+#define DEVICE_PATH_TYPE_MEDIA_DEVICE		0x04
+#  define DEVICE_PATH_SUB_TYPE_FILE_PATH	0x04
+
+struct efi_device_path_file_path {
+	struct efi_device_path dp;
+	u16 str[16];
+};
+
+#define BLOCK_IO_GUID \
+	EFI_GUID(0x964e5b21, 0x6459, 0x11d2, \
+		 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
+
+struct efi_block_io_media
+{
+	u32 media_id;
+	char removable_media;
+	char media_present;
+	char logical_partition;
+	char read_only;
+	char write_caching;
+	u8 pad[3];
+	u32 block_size;
+	u32 io_align;
+	u8 pad2[4];
+	u64 last_block;
+};
+
+struct efi_block_io {
+	u64 revision;
+	struct efi_block_io_media *media;
+	efi_status_t (EFIAPI *reset)(struct efi_block_io *this,
+			char extended_verification);
+	efi_status_t (EFIAPI *read_blocks)(struct efi_block_io *this,
+			u32 media_id, u64 lba, unsigned long buffer_size,
+			void *buffer);
+	efi_status_t (EFIAPI *write_blocks)(struct efi_block_io *this,
+			u32 media_id, u64 lba, unsigned long buffer_size,
+			void *buffer);
+	efi_status_t (EFIAPI *flush_blocks)(struct efi_block_io *this);
+};
+
 struct simple_text_output_mode {
 	s32 max_mode;
 	s32 mode;
@@ -206,8 +309,9 @@
 	efi_status_t (EFIAPI *output_string)(
 			struct efi_simple_text_output_protocol *this,
 			const unsigned short *str);
-	void *test_string;
-
+	efi_status_t (EFIAPI *test_string)(
+			struct efi_simple_text_output_protocol *this,
+			const unsigned short *str);
 	efi_status_t(EFIAPI *query_mode)(
 			struct efi_simple_text_output_protocol *this,
 			unsigned long mode_number, unsigned long *columns,
@@ -223,7 +327,9 @@
 	efi_status_t(EFIAPI *set_cursor_position) (
 			struct efi_simple_text_output_protocol *this,
 			unsigned long column, unsigned long row);
-	efi_status_t(EFIAPI *enable_cursor)(void *, bool enable);
+	efi_status_t(EFIAPI *enable_cursor)(
+			struct efi_simple_text_output_protocol *this,
+			bool enable);
 	struct simple_text_output_mode *mode;
 };
 
@@ -241,4 +347,22 @@
 	void *wait_for_key;
 };
 
+#define CONSOLE_CONTROL_GUID \
+	EFI_GUID(0xf42f7782, 0x12e, 0x4c12, \
+		 0x99, 0x56, 0x49, 0xf9, 0x43, 0x4, 0xf7, 0x21)
+#define EFI_CONSOLE_MODE_TEXT	0
+#define EFI_CONSOLE_MODE_GFX	1
+
+struct efi_console_control_protocol
+{
+	efi_status_t (EFIAPI *get_mode)(
+			struct efi_console_control_protocol *this, int *mode,
+			char *uga_exists, char *std_in_locked);
+	efi_status_t (EFIAPI *set_mode)(
+			struct efi_console_control_protocol *this, int mode);
+	efi_status_t (EFIAPI *lock_std_in)(
+			struct efi_console_control_protocol *this,
+			uint16_t *password);
+};
+
 #endif
diff --git a/include/efi_loader.h b/include/efi_loader.h
new file mode 100644
index 0000000..74bed26
--- /dev/null
+++ b/include/efi_loader.h
@@ -0,0 +1,158 @@
+/*
+ *  EFI application loader
+ *
+ *  Copyright (c) 2016 Alexander Graf
+ *
+ *  SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <part_efi.h>
+#include <efi_api.h>
+
+/* No need for efi loader support in SPL */
+#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
+
+#include <linux/list.h>
+
+/* #define DEBUG_EFI */
+
+#ifdef DEBUG_EFI
+#define EFI_ENTRY(format, ...) do { \
+	efi_restore_gd(); \
+	printf("EFI: Entry %s(" format ")\n", __func__, ##__VA_ARGS__); \
+	} while(0)
+#else
+#define EFI_ENTRY(format, ...) do { \
+	efi_restore_gd(); \
+	} while(0)
+#endif
+
+#define EFI_EXIT(ret) efi_exit_func(ret);
+
+extern struct efi_runtime_services efi_runtime_services;
+extern struct efi_system_table systab;
+
+extern const struct efi_simple_text_output_protocol efi_con_out;
+extern const struct efi_simple_input_interface efi_con_in;
+extern const struct efi_console_control_protocol efi_console_control;
+
+extern const efi_guid_t efi_guid_console_control;
+extern const efi_guid_t efi_guid_device_path;
+extern const efi_guid_t efi_guid_loaded_image;
+
+extern unsigned int __efi_runtime_start, __efi_runtime_stop;
+extern unsigned int __efi_runtime_rel_start, __efi_runtime_rel_stop;
+
+/*
+ * While UEFI objects can have callbacks, you can also call functions on
+ * protocols (classes) themselves. This struct maps a protocol GUID to its
+ * interface (usually a struct with callback functions).
+ */
+struct efi_class_map {
+	const efi_guid_t *guid;
+	const void *interface;
+};
+
+/*
+ * When the UEFI payload wants to open a protocol on an object to get its
+ * interface (usually a struct with callback functions), this struct maps the
+ * protocol GUID to the respective protocol handler open function for that
+ * object protocol combination.
+ */
+struct efi_handler {
+	const efi_guid_t *guid;
+	efi_status_t (EFIAPI *open)(void *handle,
+			efi_guid_t *protocol, void **protocol_interface,
+			void *agent_handle, void *controller_handle,
+			uint32_t attributes);
+};
+
+/*
+ * UEFI has a poor man's OO model where one "object" can be polymorphic and have
+ * multiple different protocols (classes) attached to it.
+ *
+ * This struct is the parent struct for all of our actual implementation objects
+ * that can include it to make themselves an EFI object
+ */
+struct efi_object {
+	/* Every UEFI object is part of a global object list */
+	struct list_head link;
+	/* We support up to 4 "protocols" an object can be accessed through */
+	struct efi_handler protocols[4];
+	/* The object spawner can either use this for data or as identifier */
+	void *handle;
+};
+
+/* This list contains all UEFI objects we know of */
+extern struct list_head efi_obj_list;
+
+/* Called by bootefi to make all disk storage accessible as EFI objects */
+int efi_disk_register(void);
+/*
+ * Stub implementation for a protocol opener that just returns the handle as
+ * interface
+ */
+efi_status_t efi_return_handle(void *handle,
+		efi_guid_t *protocol, void **protocol_interface,
+		void *agent_handle, void *controller_handle,
+		uint32_t attributes);
+/* Called from places to check whether a timer expired */
+void efi_timer_check(void);
+/* PE loader implementation */
+void *efi_load_pe(void *efi, struct efi_loaded_image *loaded_image_info);
+/* Called once to store the pristine gd pointer */
+void efi_save_gd(void);
+/* Called from EFI_ENTRY on callback entry to put gd into the gd register */
+void efi_restore_gd(void);
+/* Called from EFI_EXIT on callback exit to restore the gd register */
+efi_status_t efi_exit_func(efi_status_t ret);
+/* Call this to relocate the runtime section to an address space */
+void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map);
+/* Call this to set the current device name */
+void efi_set_bootdev(const char *dev, const char *devnr);
+
+/* Generic EFI memory allocator, call this to get memory */
+void *efi_alloc(uint64_t len, int memory_type);
+/* More specific EFI memory allocator, called by EFI payloads */
+efi_status_t efi_allocate_pages(int type, int memory_type, unsigned long pages,
+				uint64_t *memory);
+/* EFI memory free function. Not implemented today */
+efi_status_t efi_free_pages(uint64_t memory, unsigned long pages);
+/* Returns the EFI memory map */
+efi_status_t efi_get_memory_map(unsigned long *memory_map_size,
+				struct efi_mem_desc *memory_map,
+				unsigned long *map_key,
+				unsigned long *descriptor_size,
+				uint32_t *descriptor_version);
+/* Adds a range into the EFI memory map */
+uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
+			    bool overlap_only_ram);
+/* Called by board init to initialize the EFI memory map */
+int efi_memory_init(void);
+
+/* Convert strings from normal C strings to uEFI strings */
+static inline void ascii2unicode(u16 *unicode, char *ascii)
+{
+	while (*ascii)
+		*(unicode++) = *(ascii++);
+}
+
+/*
+ * Use these to indicate that your code / data should go into the EFI runtime
+ * section and thus still be available when the OS is running
+ */
+#define EFI_RUNTIME_DATA __attribute__ ((section ("efi_runtime_data")))
+#define EFI_RUNTIME_TEXT __attribute__ ((section ("efi_runtime_text")))
+
+#else /* defined(EFI_LOADER) && !defined(CONFIG_SPL_BUILD) */
+
+/* Without CONFIG_EFI_LOADER we don't have a runtime section, stub it out */
+#define EFI_RUNTIME_DATA
+#define EFI_RUNTIME_TEXT
+
+/* No loader configured, stub out EFI_ENTRY */
+static inline void efi_restore_gd(void) { }
+static inline void efi_set_bootdev(const char *dev, const char *devnr) { }
+
+#endif
diff --git a/include/ext4fs.h b/include/ext4fs.h
index 6888adc..cc765ae 100644
--- a/include/ext4fs.h
+++ b/include/ext4fs.h
@@ -110,7 +110,7 @@
 	/* Journal Related */
 
 	/* Block Device Descriptor */
-	block_dev_desc_t *dev_desc;
+	struct blk_desc *dev_desc;
 };
 
 extern struct ext2_data *ext4fs_root;
@@ -141,9 +141,9 @@
 int ext4fs_size(const char *filename, loff_t *size);
 void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot);
 int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf);
-void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
+void ext4fs_set_blk_dev(struct blk_desc *rbdd, disk_partition_t *info);
 long int read_allocated_block(struct ext2_inode *inode, int fileblock);
-int ext4fs_probe(block_dev_desc_t *fs_dev_desc,
+int ext4fs_probe(struct blk_desc *fs_dev_desc,
 		 disk_partition_t *fs_partition);
 int ext4_read_file(const char *filename, void *buf, loff_t offset, loff_t len,
 		   loff_t *actread);
diff --git a/include/fat.h b/include/fat.h
index 3038bd7..9d053e6 100644
--- a/include/fat.h
+++ b/include/fat.h
@@ -203,8 +203,8 @@
 		     loff_t maxsize, loff_t *actread);
 int file_fat_read(const char *filename, void *buffer, int maxsize);
 const char *file_getfsname(int idx);
-int fat_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
-int fat_register_device(block_dev_desc_t *dev_desc, int part_no);
+int fat_set_blk_dev(struct blk_desc *rbdd, disk_partition_t *info);
+int fat_register_device(struct blk_desc *dev_desc, int part_no);
 
 int file_fat_write(const char *filename, void *buf, loff_t offset, loff_t len,
 		   loff_t *actwrite);
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 4caf3b6..fb88273 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -152,14 +152,12 @@
 	COMPAT_SAMSUNG_EXYNOS5_I2C,	/* Exynos5 High Speed I2C Controller */
 	COMPAT_SAMSUNG_EXYNOS_SYSMMU,	/* Exynos sysmmu */
 	COMPAT_INTEL_MICROCODE,		/* Intel microcode update */
-	COMPAT_MEMORY_SPD,		/* Memory SPD information */
 	COMPAT_INTEL_PANTHERPOINT_AHCI,	/* Intel Pantherpoint AHCI */
 	COMPAT_INTEL_MODEL_206AX,	/* Intel Model 206AX CPU */
 	COMPAT_INTEL_GMA,		/* Intel Graphics Media Accelerator */
 	COMPAT_AMS_AS3722,		/* AMS AS3722 PMIC */
 	COMPAT_INTEL_ICH_SPI,		/* Intel ICH7/9 SPI controller */
 	COMPAT_INTEL_QRK_MRC,		/* Intel Quark MRC */
-	COMPAT_INTEL_X86_PINCTRL,	/* Intel ICH7/9 pin control */
 	COMPAT_SOCIONEXT_XHCI,		/* Socionext UniPhier xHCI */
 	COMPAT_INTEL_PCH,		/* Intel PCH */
 	COMPAT_ALTERA_SOCFPGA_DWMAC,	/* SoCFPGA Ethernet controller */
diff --git a/include/i8042.h b/include/i8042.h
index 9723b6a..0766488 100644
--- a/include/i8042.h
+++ b/include/i8042.h
@@ -35,6 +35,7 @@
 #define CMD_KBD_DIS	0xad	/* keyboard disable */
 #define CMD_KBD_EN	0xae	/* keyboard enable */
 #define CMD_SET_KBD_LED	0xed	/* set keyboard led */
+#define CMD_DRAIN_OUTPUT 0xf4   /* drain output buffer */
 #define CMD_RESET_KBD	0xff	/* reset keyboard */
 
 /* i8042 command result */
diff --git a/include/ide.h b/include/ide.h
index f9357be..a4e65cf 100644
--- a/include/ide.h
+++ b/include/ide.h
@@ -8,6 +8,8 @@
 #ifndef	_IDE_H
 #define _IDE_H
 
+#include <blk.h>
+
 #define IDE_BUS(dev)	(dev / (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS))
 
 #define	ATA_CURR_BASE(dev)	(CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])
@@ -26,25 +28,15 @@
 void ide_led(uchar led, uchar status);
 #endif /* CONFIG_IDE_LED */
 
-#ifdef CONFIG_SYS_64BIT_LBA
-typedef uint64_t lbaint_t;
-#define LBAFlength "ll"
-#else
-typedef ulong lbaint_t;
-#define LBAFlength "l"
-#endif
-#define LBAF "%" LBAFlength "x"
-#define LBAFU "%" LBAFlength "u"
-
 /*
  * Function Prototypes
  */
 
 void ide_init(void);
-typedef struct block_dev_desc block_dev_desc_t;
-ulong ide_read(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+struct blk_desc;
+ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
 	       void *buffer);
-ulong ide_write(block_dev_desc_t *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
 		const void *buffer);
 
 #ifdef CONFIG_IDE_PREINIT
diff --git a/include/image.h b/include/image.h
index 518a4f5..f9ee564 100644
--- a/include/image.h
+++ b/include/image.h
@@ -26,8 +26,8 @@
 #include <sys/types.h>
 
 /* new uImage format support enabled on host */
-#define CONFIG_FIT		1
-#define CONFIG_OF_LIBFDT	1
+#define IMAGE_ENABLE_FIT	1
+#define IMAGE_ENABLE_OF_LIBFDT	1
 #define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
 
 #define IMAGE_ENABLE_IGNORE	0
@@ -43,9 +43,12 @@
 #define IMAGE_ENABLE_IGNORE	1
 #define IMAGE_INDENT_STRING	"   "
 
+#define IMAGE_ENABLE_FIT	CONFIG_IS_ENABLED(FIT)
+#define IMAGE_ENABLE_OF_LIBFDT	CONFIG_IS_ENABLED(OF_LIBFDT)
+
 #endif /* USE_HOSTCC */
 
-#if defined(CONFIG_FIT)
+#if IMAGE_ENABLE_FIT
 #include <hash.h>
 #include <libfdt.h>
 #include <fdt_support.h>
@@ -94,7 +97,7 @@
 #define IMAGE_ENABLE_SHA256	0
 #endif
 
-#endif /* CONFIG_FIT */
+#endif /* IMAGE_ENABLE_FIT */
 
 #ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
 # define IMAGE_ENABLE_RAMDISK_HIGH	1
@@ -102,12 +105,6 @@
 # define IMAGE_ENABLE_RAMDISK_HIGH	0
 #endif
 
-#ifdef CONFIG_OF_LIBFDT
-# define IMAGE_ENABLE_OF_LIBFDT	1
-#else
-# define IMAGE_ENABLE_OF_LIBFDT	0
-#endif
-
 #ifdef CONFIG_SYS_BOOT_GET_CMDLINE
 # define IMAGE_BOOT_GET_CMDLINE		1
 #else
@@ -309,7 +306,7 @@
 	image_header_t	legacy_hdr_os_copy;	/* header copy */
 	ulong		legacy_hdr_valid;
 
-#if defined(CONFIG_FIT)
+#if IMAGE_ENABLE_FIT
 	const char	*fit_uname_cfg;	/* configuration node unit name */
 
 	void		*fit_hdr_os;	/* os FIT image header */
@@ -416,7 +413,25 @@
 char *get_table_entry_name(const table_entry_t *table, char *msg, int id);
 
 const char *genimg_get_os_name(uint8_t os);
+
+/**
+ * genimg_get_os_short_name() - get the short name for an OS
+ *
+ * @param os	OS (IH_OS_...)
+ * @return OS short name, or "unknown" if unknown
+ */
+const char *genimg_get_os_short_name(uint8_t comp);
+
 const char *genimg_get_arch_name(uint8_t arch);
+
+/**
+ * genimg_get_arch_short_name() - get the short name for an architecture
+ *
+ * @param arch	Architecture type (IH_ARCH_...)
+ * @return architecture short name, or "unknown" if unknown
+ */
+const char *genimg_get_arch_short_name(uint8_t arch);
+
 const char *genimg_get_type_name(uint8_t type);
 
 /**
@@ -428,6 +443,15 @@
 const char *genimg_get_type_short_name(uint8_t type);
 
 const char *genimg_get_comp_name(uint8_t comp);
+
+/**
+ * genimg_get_comp_short_name() - get the short name for a compression method
+ *
+ * @param comp	compression method (IH_COMP_...)
+ * @return compression method short name, or "unknown" if unknown
+ */
+const char *genimg_get_comp_short_name(uint8_t comp);
+
 int genimg_get_os_id(const char *name);
 int genimg_get_arch_id(const char *name);
 int genimg_get_type_id(const char *name);
@@ -756,7 +780,6 @@
 /*******************************************************************/
 /* New uImage format specific code (prefixed with fit_) */
 /*******************************************************************/
-#if defined(CONFIG_FIT)
 
 #define FIT_IMAGES_PATH		"/images"
 #define FIT_CONFS_PATH		"/configurations"
@@ -789,6 +812,7 @@
 
 #define FIT_MAX_HASH_LEN	HASH_MAX_DIGEST_SIZE
 
+#if IMAGE_ENABLE_FIT
 /* cmdline argument format parsing */
 int fit_parse_conf(const char *spec, ulong addr_curr,
 		ulong *addr, const char **conf_name);
@@ -952,6 +976,7 @@
 	int required_keynode;		/* Node offset of key to use: -1=any */
 	const char *require_keys;	/* Value for 'required' property */
 };
+#endif /* Allow struct image_region to always be defined for rsa.h */
 
 /* A part of an image, used for hashing */
 struct image_region {
@@ -959,6 +984,8 @@
 	int size;
 };
 
+#if IMAGE_ENABLE_FIT
+
 #if IMAGE_ENABLE_VERIFY
 # include <u-boot/rsa-checksum.h>
 #endif
@@ -1127,4 +1154,17 @@
 
 #endif /* CONFIG_ANDROID_BOOT_IMAGE */
 
+/**
+ * board_fit_config_name_match() - Check for a matching board name
+ *
+ * This is used when SPL loads a FIT containing multiple device tree files
+ * and wants to work out which one to use. The description of each one is
+ * passed to this function. The description comes from the 'description' field
+ * in each (FDT) image node.
+ *
+ * @name: Device tree description
+ * @return 0 if this device tree should be used, non-zero to try the next
+ */
+int board_fit_config_name_match(const char *name);
+
 #endif	/* __IMAGE_H__ */
diff --git a/include/libfdt.h b/include/libfdt.h
index e48c21a..74b1d14 100644
--- a/include/libfdt.h
+++ b/include/libfdt.h
@@ -1181,6 +1181,22 @@
 {
 	return fdt_property_u32(fdt, name, val);
 }
+
+/**
+ * fdt_property_placeholder - add a new property and return a ptr to its value
+ *
+ * @fdt: pointer to the device tree blob
+ * @name: name of property to add
+ * @len: length of property value in bytes
+ * @valp: returns a pointer to where where the value should be placed
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_NOSPACE, standard meanings
+ */
+int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp);
+
 #define fdt_property_string(fdt, name, str) \
 	fdt_property(fdt, name, str, strlen(str)+1)
 int fdt_end_node(void *fdt);
diff --git a/include/mmc.h b/include/mmc.h
index d652c14..cdb56e7 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -376,7 +376,7 @@
 	u64 capacity_gp[4];
 	u64 enh_user_start;
 	u64 enh_user_size;
-	block_dev_desc_t block_dev;
+	struct blk_desc block_dev;
 	char op_cond_pending;	/* 1 if we are waiting on an op_cond command */
 	char init_in_progress;	/* 1 if we have done mmc_start_init() */
 	char preinit;		/* start init as early as possible */
diff --git a/include/ns16550.h b/include/ns16550.h
index 4e62067..1311f4c 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -56,6 +56,7 @@
 	unsigned long base;
 	int reg_shift;
 	int clock;
+	int reg_offset;
 };
 
 struct udevice;
diff --git a/include/part.h b/include/part.h
index dc23949..dc8e72e 100644
--- a/include/part.h
+++ b/include/part.h
@@ -7,62 +7,20 @@
 #ifndef _PART_H
 #define _PART_H
 
+#include <blk.h>
 #include <ide.h>
-#include <common.h>
 
-struct block_dev_desc {
-	int		if_type;	/* type of the interface */
-	int		dev;		/* device number */
-	unsigned char	part_type;	/* partition type */
-	unsigned char	target;		/* target SCSI ID */
-	unsigned char	lun;		/* target LUN */
-	unsigned char	hwpart;		/* HW partition, e.g. for eMMC */
-	unsigned char	type;		/* device type */
-	unsigned char	removable;	/* removable device */
-#ifdef CONFIG_LBA48
-	unsigned char	lba48;		/* device can use 48bit addr (ATA/ATAPI v7) */
-#endif
-	lbaint_t	lba;		/* number of blocks */
-	unsigned long	blksz;		/* block size */
-	int		log2blksz;	/* for convenience: log2(blksz) */
-	char		vendor [40+1];	/* IDE model, SCSI Vendor */
-	char		product[20+1];	/* IDE Serial no, SCSI product */
-	char		revision[8+1];	/* firmware revision */
-	unsigned long	(*block_read)(block_dev_desc_t *block_dev,
-				      lbaint_t start,
-				      lbaint_t blkcnt,
-				      void *buffer);
-	unsigned long	(*block_write)(block_dev_desc_t *block_dev,
-				       lbaint_t start,
-				       lbaint_t blkcnt,
-				       const void *buffer);
-	unsigned long	(*block_erase)(block_dev_desc_t *block_dev,
-				       lbaint_t start,
-				       lbaint_t blkcnt);
-	void		*priv;		/* driver private struct pointer */
+struct block_drvr {
+	char *name;
+	struct blk_desc* (*get_dev)(int dev);
+	int (*select_hwpart)(int dev_num, int hwpart);
 };
 
-#define BLOCK_CNT(size, block_dev_desc) (PAD_COUNT(size, block_dev_desc->blksz))
-#define PAD_TO_BLOCKSIZE(size, block_dev_desc) \
-	(PAD_SIZE(size, block_dev_desc->blksz))
 #define LOG2(x) (((x & 0xaaaaaaaa) ? 1 : 0) + ((x & 0xcccccccc) ? 2 : 0) + \
 		 ((x & 0xf0f0f0f0) ? 4 : 0) + ((x & 0xff00ff00) ? 8 : 0) + \
 		 ((x & 0xffff0000) ? 16 : 0))
 #define LOG2_INVALID(type) ((type)((sizeof(type)<<3)-1))
 
-/* Interface types: */
-#define IF_TYPE_UNKNOWN		0
-#define IF_TYPE_IDE		1
-#define IF_TYPE_SCSI		2
-#define IF_TYPE_ATAPI		3
-#define IF_TYPE_USB		4
-#define IF_TYPE_DOC		5
-#define IF_TYPE_MMC		6
-#define IF_TYPE_SD		7
-#define IF_TYPE_SATA		8
-#define IF_TYPE_HOST		9
-#define IF_TYPE_MAX		10	/* Max number of IF_TYPE_* supported */
-
 /* Part types */
 #define PART_TYPE_UNKNOWN	0x00
 #define PART_TYPE_MAC		0x01
@@ -101,91 +59,206 @@
 
 /* Misc _get_dev functions */
 #ifdef CONFIG_PARTITIONS
-block_dev_desc_t *get_dev(const char *ifname, int dev);
-block_dev_desc_t* ide_get_dev(int dev);
-block_dev_desc_t* sata_get_dev(int dev);
-block_dev_desc_t* scsi_get_dev(int dev);
-block_dev_desc_t* usb_stor_get_dev(int dev);
-block_dev_desc_t* mmc_get_dev(int dev);
+/**
+ * blk_get_dev() - get a pointer to a block device given its type and number
+ *
+ * Each interface allocates its own devices and typically struct blk_desc is
+ * contained with the interface's data structure. There is no global
+ * numbering for block devices, so the interface name must be provided.
+ *
+ * @ifname:	Interface name (e.g. "ide", "scsi")
+ * @dev:	Device number (0 for first device on that interface, 1 for
+ *		second, etc.
+ * @return pointer to the block device, or NULL if not available, or an
+ *	   error occurred.
+ */
+struct blk_desc *blk_get_dev(const char *ifname, int dev);
+struct blk_desc *ide_get_dev(int dev);
+struct blk_desc *sata_get_dev(int dev);
+struct blk_desc *scsi_get_dev(int dev);
+struct blk_desc *usb_stor_get_dev(int dev);
+struct blk_desc *mmc_get_dev(int dev);
+
+/**
+ * mmc_select_hwpart() - Select the MMC hardware partiion on an MMC device
+ *
+ * MMC devices can support partitioning at the hardware level. This is quite
+ * separate from the normal idea of software-based partitions. MMC hardware
+ * partitions must be explicitly selected. Once selected only the region of
+ * the device covered by that partition is accessible.
+ *
+ * The MMC standard provides for two boot partitions (numbered 1 and 2),
+ * rpmb (3), and up to 4 addition general-purpose partitions (4-7).
+ *
+ * @dev_num:	Block device number (struct blk_desc->dev value)
+ * @hwpart:	Hardware partition number to select. 0 means the raw device,
+ *		1 is the first partition, 2 is the second, etc.
+ * @return 0 if OK, other value for an error
+ */
 int mmc_select_hwpart(int dev_num, int hwpart);
-block_dev_desc_t* systemace_get_dev(int dev);
-block_dev_desc_t* mg_disk_get_dev(int dev);
-block_dev_desc_t *host_get_dev(int dev);
-int host_get_dev_err(int dev, block_dev_desc_t **blk_devp);
+struct blk_desc *systemace_get_dev(int dev);
+struct blk_desc *mg_disk_get_dev(int dev);
+struct blk_desc *host_get_dev(int dev);
+int host_get_dev_err(int dev, struct blk_desc **blk_devp);
 
 /* disk/part.c */
-int get_partition_info (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
-void print_part (block_dev_desc_t *dev_desc);
-void  init_part (block_dev_desc_t *dev_desc);
-void dev_print(block_dev_desc_t *dev_desc);
-int get_device(const char *ifname, const char *dev_str,
-	       block_dev_desc_t **dev_desc);
-int get_device_and_partition(const char *ifname, const char *dev_part_str,
-			     block_dev_desc_t **dev_desc,
-			     disk_partition_t *info, int allow_whole_dev);
+int part_get_info(struct blk_desc *dev_desc, int part, disk_partition_t *info);
+void part_print(struct blk_desc *dev_desc);
+void part_init(struct blk_desc *dev_desc);
+void dev_print(struct blk_desc *dev_desc);
+
+/**
+ * blk_get_device_by_str() - Get a block device given its interface/hw partition
+ *
+ * Each interface allocates its own devices and typically struct blk_desc is
+ * contained with the interface's data structure. There is no global
+ * numbering for block devices, so the interface name must be provided.
+ *
+ * The hardware parition is not related to the normal software partitioning
+ * of a device - each hardware partition is effectively a separately
+ * accessible block device. When a hardware parition is selected on MMC the
+ * other hardware partitions become inaccessible. The same block device is
+ * used to access all hardware partitions, but its capacity may change when a
+ * different hardware partition is selected.
+ *
+ * When a hardware partition number is given, the block device switches to
+ * that hardware partition.
+ *
+ * @ifname:	Interface name (e.g. "ide", "scsi")
+ * @dev_str:	Device and optional hw partition. This can either be a string
+ *		containing the device number (e.g. "2") or the device number
+ *		and hardware partition number (e.g. "2.4") for devices that
+ *		support it (currently only MMC).
+ * @dev_desc:	Returns a pointer to the block device on success
+ * @return block device number (local to the interface), or -1 on error
+ */
+int blk_get_device_by_str(const char *ifname, const char *dev_str,
+			  struct blk_desc **dev_desc);
+
+/**
+ * blk_get_device_part_str() - Get a block device and partition
+ *
+ * This calls blk_get_device_by_str() to look up a device. It also looks up
+ * a partition and returns information about it.
+ *
+ * @dev_part_str is in the format:
+ *	<dev>.<hw_part>:<part> where <dev> is the device number,
+ *	<hw_part> is the optional hardware partition number and
+ *	<part> is the partition number
+ *
+ * If ifname is "hostfs" then this function returns the sandbox host block
+ * device.
+ *
+ * If ifname is ubi, then this function returns 0, with @info set to a
+ * special UBI device.
+ *
+ * If @dev_part_str is NULL or empty or "-", then this function looks up
+ * the "bootdevice" environment variable and uses that string instead.
+ *
+ * If the partition string is empty then the first partition is used. If the
+ * partition string is "auto" then the first bootable partition is used.
+ *
+ * @ifname:	Interface name (e.g. "ide", "scsi")
+ * @dev_part_str:	Device and partition string
+ * @dev_desc:	Returns a pointer to the block device on success
+ * @info:	Returns partition information
+ * @allow_whole_dev:	true to allow the user to select partition 0
+ *		(which means the whole device), false to require a valid
+ *		partition number >= 1
+ * @return partition number, or -1 on error
+ *
+ */
+int blk_get_device_part_str(const char *ifname, const char *dev_part_str,
+			    struct blk_desc **dev_desc,
+			    disk_partition_t *info, int allow_whole_dev);
+extern const struct block_drvr block_drvr[];
 #else
-static inline block_dev_desc_t *get_dev(const char *ifname, int dev)
+static inline struct blk_desc *blk_get_dev(const char *ifname, int dev)
 { return NULL; }
-static inline block_dev_desc_t* ide_get_dev(int dev) { return NULL; }
-static inline block_dev_desc_t* sata_get_dev(int dev) { return NULL; }
-static inline block_dev_desc_t* scsi_get_dev(int dev) { return NULL; }
-static inline block_dev_desc_t* usb_stor_get_dev(int dev) { return NULL; }
-static inline block_dev_desc_t* mmc_get_dev(int dev) { return NULL; }
+static inline struct blk_desc *ide_get_dev(int dev) { return NULL; }
+static inline struct blk_desc *sata_get_dev(int dev) { return NULL; }
+static inline struct blk_desc *scsi_get_dev(int dev) { return NULL; }
+static inline struct blk_desc *usb_stor_get_dev(int dev) { return NULL; }
+static inline struct blk_desc *mmc_get_dev(int dev) { return NULL; }
 static inline int mmc_select_hwpart(int dev_num, int hwpart) { return -1; }
-static inline block_dev_desc_t* systemace_get_dev(int dev) { return NULL; }
-static inline block_dev_desc_t* mg_disk_get_dev(int dev) { return NULL; }
-static inline block_dev_desc_t *host_get_dev(int dev) { return NULL; }
+static inline struct blk_desc *systemace_get_dev(int dev) { return NULL; }
+static inline struct blk_desc *mg_disk_get_dev(int dev) { return NULL; }
+static inline struct blk_desc *host_get_dev(int dev) { return NULL; }
 
-static inline int get_partition_info (block_dev_desc_t * dev_desc, int part,
-	disk_partition_t *info) { return -1; }
-static inline void print_part (block_dev_desc_t *dev_desc) {}
-static inline void  init_part (block_dev_desc_t *dev_desc) {}
-static inline void dev_print(block_dev_desc_t *dev_desc) {}
-static inline int get_device(const char *ifname, const char *dev_str,
-	       block_dev_desc_t **dev_desc)
+static inline int part_get_info(struct blk_desc *dev_desc, int part,
+				disk_partition_t *info) { return -1; }
+static inline void part_print(struct blk_desc *dev_desc) {}
+static inline void part_init(struct blk_desc *dev_desc) {}
+static inline void dev_print(struct blk_desc *dev_desc) {}
+static inline int blk_get_device_by_str(const char *ifname, const char *dev_str,
+					struct blk_desc **dev_desc)
 { return -1; }
-static inline int get_device_and_partition(const char *ifname,
+static inline int blk_get_device_part_str(const char *ifname,
 					   const char *dev_part_str,
-					   block_dev_desc_t **dev_desc,
+					   struct blk_desc **dev_desc,
 					   disk_partition_t *info,
 					   int allow_whole_dev)
 { *dev_desc = NULL; return -1; }
 #endif
 
-#ifdef CONFIG_MAC_PARTITION
-/* disk/part_mac.c */
-int get_partition_info_mac (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
-void print_part_mac (block_dev_desc_t *dev_desc);
-int   test_part_mac (block_dev_desc_t *dev_desc);
+/*
+ * We don't support printing partition information in SPL and only support
+ * getting partition information in a few cases.
+ */
+#ifdef CONFIG_SPL_BUILD
+# define part_print_ptr(x)	NULL
+# if defined(CONFIG_SPL_EXT_SUPPORT) || \
+	defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION)
+#  define part_get_info_ptr(x)	x
+# else
+#  define part_get_info_ptr(x)	NULL
+# endif
+#else
+#define part_print_ptr(x)	x
+#define part_get_info_ptr(x)	x
 #endif
 
-#ifdef CONFIG_DOS_PARTITION
-/* disk/part_dos.c */
-int get_partition_info_dos (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
-void print_part_dos (block_dev_desc_t *dev_desc);
-int   test_part_dos (block_dev_desc_t *dev_desc);
-#endif
 
-#ifdef CONFIG_ISO_PARTITION
-/* disk/part_iso.c */
-int get_partition_info_iso (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
-void print_part_iso (block_dev_desc_t *dev_desc);
-int   test_part_iso (block_dev_desc_t *dev_desc);
-#endif
+struct part_driver {
+	const char *name;
+	int part_type;
 
-#ifdef CONFIG_AMIGA_PARTITION
-/* disk/part_amiga.c */
-int get_partition_info_amiga (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
-void print_part_amiga (block_dev_desc_t *dev_desc);
-int   test_part_amiga (block_dev_desc_t *dev_desc);
-#endif
+	/**
+	 * get_info() - Get information about a partition
+	 *
+	 * @dev_desc:	Block device descriptor
+	 * @part:	Partition number (1 = first)
+	 * @info:	Returns partition information
+	 */
+	int (*get_info)(struct blk_desc *dev_desc, int part,
+			disk_partition_t *info);
+
+	/**
+	 * print() - Print partition information
+	 *
+	 * @dev_desc:	Block device descriptor
+	 */
+	void (*print)(struct blk_desc *dev_desc);
+
+	/**
+	 * test() - Test if a device contains this partition type
+	 *
+	 * @dev_desc:	Block device descriptor
+	 * @return 0 if the block device appears to contain this partition
+	 *	   type, -ve if not
+	 */
+	int (*test)(struct blk_desc *dev_desc);
+};
+
+/* Declare a new U-Boot partition 'driver' */
+#define U_BOOT_PART_TYPE(__name)					\
+	ll_entry_declare(struct part_driver, __name, part_driver)
 
 #ifdef CONFIG_EFI_PARTITION
 #include <part_efi.h>
 /* disk/part_efi.c */
-int get_partition_info_efi (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
 /**
- * get_partition_info_efi_by_name() - Find the specified GPT partition table entry
+ * part_get_info_efi_by_name() - Find the specified GPT partition table entry
  *
  * @param dev_desc - block device descriptor
  * @param gpt_name - the specified table entry name
@@ -193,10 +266,8 @@
  *
  * @return - '0' on match, '-1' on no match, otherwise error
  */
-int get_partition_info_efi_by_name(block_dev_desc_t *dev_desc,
-	const char *name, disk_partition_t *info);
-void print_part_efi (block_dev_desc_t *dev_desc);
-int   test_part_efi (block_dev_desc_t *dev_desc);
+int part_get_info_efi_by_name(struct blk_desc *dev_desc,
+			      const char *name, disk_partition_t *info);
 
 /**
  * write_gpt_table() - Write the GUID Partition Table to disk
@@ -207,7 +278,7 @@
  *
  * @return - zero on success, otherwise error
  */
-int write_gpt_table(block_dev_desc_t *dev_desc,
+int write_gpt_table(struct blk_desc *dev_desc,
 		  gpt_header *gpt_h, gpt_entry *gpt_e);
 
 /**
@@ -233,7 +304,7 @@
  *
  * @return - error on str_guid conversion error
  */
-int gpt_fill_header(block_dev_desc_t *dev_desc, gpt_header *gpt_h,
+int gpt_fill_header(struct blk_desc *dev_desc, gpt_header *gpt_h,
 		char *str_guid, int parts_count);
 
 /**
@@ -246,7 +317,7 @@
  *
  * @return zero on success
  */
-int gpt_restore(block_dev_desc_t *dev_desc, char *str_disk_guid,
+int gpt_restore(struct blk_desc *dev_desc, char *str_disk_guid,
 		disk_partition_t *partitions, const int parts_count);
 
 /**
@@ -257,7 +328,7 @@
  *
  * @return - '0' on success, otherwise error
  */
-int is_valid_gpt_buf(block_dev_desc_t *dev_desc, void *buf);
+int is_valid_gpt_buf(struct blk_desc *dev_desc, void *buf);
 
 /**
  * write_mbr_and_gpt_partitions() - write MBR, Primary GPT and Backup GPT
@@ -267,7 +338,7 @@
  *
  * @return - '0' on success, otherwise error
  */
-int write_mbr_and_gpt_partitions(block_dev_desc_t *dev_desc, void *buf);
+int write_mbr_and_gpt_partitions(struct blk_desc *dev_desc, void *buf);
 
 /**
  * gpt_verify_headers() - Function to read and CRC32 check of the GPT's header
@@ -281,7 +352,7 @@
  *
  * @return - '0' on success, otherwise error
  */
-int gpt_verify_headers(block_dev_desc_t *dev_desc, gpt_header *gpt_head,
+int gpt_verify_headers(struct blk_desc *dev_desc, gpt_header *gpt_head,
 		       gpt_entry **gpt_pte);
 
 /**
@@ -300,7 +371,7 @@
  *
  * @return - '0' on success, otherwise error
  */
-int gpt_verify_partitions(block_dev_desc_t *dev_desc,
+int gpt_verify_partitions(struct blk_desc *dev_desc,
 			  disk_partition_t *partitions, int parts,
 			  gpt_header *gpt_head, gpt_entry **gpt_pte);
 #endif
diff --git a/include/pci.h b/include/pci.h
index 68548b0..87de7ab 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -1007,6 +1007,7 @@
  *
  * @bus:	Bus to read from
  * @bdf:	PCI device address: bus, device and function -see PCI_BDF()
+ * @offset:	Register offset to read
  * @valuep:	Place to put the returned value
  * @size:	Access size
  * @return 0 if OK, -ve on error
@@ -1019,6 +1020,7 @@
  *
  * @bus:	Bus to write from
  * @bdf:	PCI device address: bus, device and function -see PCI_BDF()
+ * @offset:	Register offset to write
  * @value:	Value to write
  * @size:	Access size
  * @return 0 if OK, -ve on error
@@ -1027,6 +1029,21 @@
 			 unsigned long value, enum pci_size_t size);
 
 /**
+ * pci_bus_clrset_config32() - Update a configuration value for a device
+ *
+ * The register at @offset is updated to (oldvalue & ~clr) | set.
+ *
+ * @bus:	Bus to access
+ * @bdf:	PCI device address: bus, device and function -see PCI_BDF()
+ * @offset:	Register offset to update
+ * @clr:	Bits to clear
+ * @set:	Bits to set
+ * @return 0 if OK, -ve on error
+ */
+int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
+			    u32 clr, u32 set);
+
+/**
  * Driver model PCI config access functions. Use these in preference to others
  * when you have a valid device
  */
@@ -1044,6 +1061,14 @@
 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
 
+/**
+ * These permit convenient read/modify/write on PCI configuration. The
+ * register is updated to (oldvalue & ~clr) | set.
+ */
+int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
+int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);
+int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);
+
 /*
  * The following functions provide access to the above without needing the
  * size parameter. We are trying to encourage the use of the 8/16/32-style
@@ -1237,9 +1262,9 @@
 #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
 	dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
 #define dm_pci_virt_to_io(dev, addr) \
-	dm_dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
+	dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
 #define dm_pci_io_to_virt(dev, addr, len, map_flags) \
-	dm_dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
+	dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
 
 /**
  * dm_pci_find_device() - find a device by vendor/device ID
diff --git a/include/pe.h b/include/pe.h
new file mode 100644
index 0000000..deb35a0
--- /dev/null
+++ b/include/pe.h
@@ -0,0 +1,263 @@
+/*
+ *  Portable Executable binary format structures
+ *
+ *  Copyright (c) 2016 Alexander Graf
+ *
+ *  Based on wine code
+ *
+ *  SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _PE_H
+#define _PE_H
+
+typedef struct _IMAGE_DOS_HEADER {
+	uint16_t e_magic;	/* 00: MZ Header signature */
+	uint16_t e_cblp;	/* 02: Bytes on last page of file */
+	uint16_t e_cp;		/* 04: Pages in file */
+	uint16_t e_crlc;	/* 06: Relocations */
+	uint16_t e_cparhdr;	/* 08: Size of header in paragraphs */
+	uint16_t e_minalloc;	/* 0a: Minimum extra paragraphs needed */
+	uint16_t e_maxalloc;	/* 0c: Maximum extra paragraphs needed */
+	uint16_t e_ss;		/* 0e: Initial (relative) SS value */
+	uint16_t e_sp;		/* 10: Initial SP value */
+	uint16_t e_csum;	/* 12: Checksum */
+	uint16_t e_ip;		/* 14: Initial IP value */
+	uint16_t e_cs;		/* 16: Initial (relative) CS value */
+	uint16_t e_lfarlc;	/* 18: File address of relocation table */
+	uint16_t e_ovno;	/* 1a: Overlay number */
+	uint16_t e_res[4];	/* 1c: Reserved words */
+	uint16_t e_oemid;	/* 24: OEM identifier (for e_oeminfo) */
+	uint16_t e_oeminfo;	/* 26: OEM information; e_oemid specific */
+	uint16_t e_res2[10];	/* 28: Reserved words */
+	uint32_t e_lfanew;	/* 3c: Offset to extended header */
+} IMAGE_DOS_HEADER, *PIMAGE_DOS_HEADER;
+
+#define IMAGE_DOS_SIGNATURE		0x5A4D     /* MZ   */
+#define IMAGE_NT_SIGNATURE		0x00004550 /* PE00 */
+
+#define IMAGE_FILE_MACHINE_ARM		0x01c0
+#define IMAGE_FILE_MACHINE_THUMB	0x01c2
+#define IMAGE_FILE_MACHINE_ARMNT	0x01c4
+#define IMAGE_FILE_MACHINE_AMD64	0x8664
+#define IMAGE_FILE_MACHINE_ARM64	0xaa64
+#define IMAGE_NT_OPTIONAL_HDR32_MAGIC	0x10b
+#define IMAGE_NT_OPTIONAL_HDR64_MAGIC	0x20b
+#define IMAGE_SUBSYSTEM_EFI_APPLICATION	10
+
+typedef struct _IMAGE_FILE_HEADER {
+	uint16_t Machine;
+	uint16_t NumberOfSections;
+	uint32_t TimeDateStamp;
+	uint32_t PointerToSymbolTable;
+	uint32_t NumberOfSymbols;
+	uint16_t SizeOfOptionalHeader;
+	uint16_t Characteristics;
+} IMAGE_FILE_HEADER, *PIMAGE_FILE_HEADER;
+
+typedef struct _IMAGE_DATA_DIRECTORY {
+	uint32_t VirtualAddress;
+	uint32_t Size;
+} IMAGE_DATA_DIRECTORY, *PIMAGE_DATA_DIRECTORY;
+
+#define IMAGE_NUMBEROF_DIRECTORY_ENTRIES 16
+
+typedef struct _IMAGE_OPTIONAL_HEADER64 {
+	uint16_t Magic; /* 0x20b */
+	uint8_t  MajorLinkerVersion;
+	uint8_t  MinorLinkerVersion;
+	uint32_t SizeOfCode;
+	uint32_t SizeOfInitializedData;
+	uint32_t SizeOfUninitializedData;
+	uint32_t AddressOfEntryPoint;
+	uint32_t BaseOfCode;
+	uint64_t ImageBase;
+	uint32_t SectionAlignment;
+	uint32_t FileAlignment;
+	uint16_t MajorOperatingSystemVersion;
+	uint16_t MinorOperatingSystemVersion;
+	uint16_t MajorImageVersion;
+	uint16_t MinorImageVersion;
+	uint16_t MajorSubsystemVersion;
+	uint16_t MinorSubsystemVersion;
+	uint32_t Win32VersionValue;
+	uint32_t SizeOfImage;
+	uint32_t SizeOfHeaders;
+	uint32_t CheckSum;
+	uint16_t Subsystem;
+	uint16_t DllCharacteristics;
+	uint64_t SizeOfStackReserve;
+	uint64_t SizeOfStackCommit;
+	uint64_t SizeOfHeapReserve;
+	uint64_t SizeOfHeapCommit;
+	uint32_t LoaderFlags;
+	uint32_t NumberOfRvaAndSizes;
+	IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES];
+} IMAGE_OPTIONAL_HEADER64, *PIMAGE_OPTIONAL_HEADER64;
+
+typedef struct _IMAGE_NT_HEADERS64 {
+	uint32_t Signature;
+	IMAGE_FILE_HEADER FileHeader;
+	IMAGE_OPTIONAL_HEADER64 OptionalHeader;
+} IMAGE_NT_HEADERS64, *PIMAGE_NT_HEADERS64;
+
+typedef struct _IMAGE_OPTIONAL_HEADER {
+
+	/* Standard fields */
+
+	uint16_t Magic; /* 0x10b or 0x107 */     /* 0x00 */
+	uint8_t  MajorLinkerVersion;
+	uint8_t  MinorLinkerVersion;
+	uint32_t SizeOfCode;
+	uint32_t SizeOfInitializedData;
+	uint32_t SizeOfUninitializedData;
+	uint32_t AddressOfEntryPoint;            /* 0x10 */
+	uint32_t BaseOfCode;
+	uint32_t BaseOfData;
+
+	/* NT additional fields */
+
+	uint32_t ImageBase;
+	uint32_t SectionAlignment;               /* 0x20 */
+	uint32_t FileAlignment;
+	uint16_t MajorOperatingSystemVersion;
+	uint16_t MinorOperatingSystemVersion;
+	uint16_t MajorImageVersion;
+	uint16_t MinorImageVersion;
+	uint16_t MajorSubsystemVersion;          /* 0x30 */
+	uint16_t MinorSubsystemVersion;
+	uint32_t Win32VersionValue;
+	uint32_t SizeOfImage;
+	uint32_t SizeOfHeaders;
+	uint32_t CheckSum;                       /* 0x40 */
+	uint16_t Subsystem;
+	uint16_t DllCharacteristics;
+	uint32_t SizeOfStackReserve;
+	uint32_t SizeOfStackCommit;
+	uint32_t SizeOfHeapReserve;              /* 0x50 */
+	uint32_t SizeOfHeapCommit;
+	uint32_t LoaderFlags;
+	uint32_t NumberOfRvaAndSizes;
+	IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES]; /* 0x60 */
+	/* 0xE0 */
+} IMAGE_OPTIONAL_HEADER32, *PIMAGE_OPTIONAL_HEADER32;
+
+typedef struct _IMAGE_NT_HEADERS {
+	uint32_t Signature; /* "PE"\0\0 */       /* 0x00 */
+	IMAGE_FILE_HEADER FileHeader;         /* 0x04 */
+	IMAGE_OPTIONAL_HEADER32 OptionalHeader;       /* 0x18 */
+} IMAGE_NT_HEADERS32, *PIMAGE_NT_HEADERS32;
+
+#define IMAGE_SIZEOF_SHORT_NAME 8
+
+typedef struct _IMAGE_SECTION_HEADER {
+	uint8_t	Name[IMAGE_SIZEOF_SHORT_NAME];
+	union {
+		uint32_t PhysicalAddress;
+		uint32_t VirtualSize;
+	} Misc;
+	uint32_t VirtualAddress;
+	uint32_t SizeOfRawData;
+	uint32_t PointerToRawData;
+	uint32_t PointerToRelocations;
+	uint32_t PointerToLinenumbers;
+	uint16_t NumberOfRelocations;
+	uint16_t NumberOfLinenumbers;
+	uint32_t Characteristics;
+} IMAGE_SECTION_HEADER, *PIMAGE_SECTION_HEADER;
+
+#define IMAGE_DIRECTORY_ENTRY_BASERELOC         5
+
+typedef struct _IMAGE_BASE_RELOCATION
+{
+        uint32_t VirtualAddress;
+        uint32_t SizeOfBlock;
+        /* WORD TypeOffset[1]; */
+} IMAGE_BASE_RELOCATION,*PIMAGE_BASE_RELOCATION;
+
+typedef struct _IMAGE_RELOCATION
+{
+	union {
+		uint32_t VirtualAddress;
+		uint32_t RelocCount;
+	} DUMMYUNIONNAME;
+	uint32_t SymbolTableIndex;
+	uint16_t Type;
+} IMAGE_RELOCATION, *PIMAGE_RELOCATION;
+
+#define IMAGE_SIZEOF_RELOCATION 10
+
+/* generic relocation types */
+#define IMAGE_REL_BASED_ABSOLUTE                0
+#define IMAGE_REL_BASED_HIGH                    1
+#define IMAGE_REL_BASED_LOW                     2
+#define IMAGE_REL_BASED_HIGHLOW                 3
+#define IMAGE_REL_BASED_HIGHADJ                 4
+#define IMAGE_REL_BASED_MIPS_JMPADDR            5
+#define IMAGE_REL_BASED_ARM_MOV32A              5 /* yes, 5 too */
+#define IMAGE_REL_BASED_ARM_MOV32               5 /* yes, 5 too */
+#define IMAGE_REL_BASED_SECTION                 6
+#define IMAGE_REL_BASED_REL                     7
+#define IMAGE_REL_BASED_ARM_MOV32T              7 /* yes, 7 too */
+#define IMAGE_REL_BASED_THUMB_MOV32             7 /* yes, 7 too */
+#define IMAGE_REL_BASED_MIPS_JMPADDR16          9
+#define IMAGE_REL_BASED_IA64_IMM64              9 /* yes, 9 too */
+#define IMAGE_REL_BASED_DIR64                   10
+#define IMAGE_REL_BASED_HIGH3ADJ                11
+
+/* ARM relocation types */
+#define IMAGE_REL_ARM_ABSOLUTE          0x0000
+#define IMAGE_REL_ARM_ADDR              0x0001
+#define IMAGE_REL_ARM_ADDR32NB          0x0002
+#define IMAGE_REL_ARM_BRANCH24          0x0003
+#define IMAGE_REL_ARM_BRANCH11          0x0004
+#define IMAGE_REL_ARM_TOKEN             0x0005
+#define IMAGE_REL_ARM_GPREL12           0x0006
+#define IMAGE_REL_ARM_GPREL7            0x0007
+#define IMAGE_REL_ARM_BLX24             0x0008
+#define IMAGE_REL_ARM_BLX11             0x0009
+#define IMAGE_REL_ARM_SECTION           0x000E
+#define IMAGE_REL_ARM_SECREL            0x000F
+#define IMAGE_REL_ARM_MOV32A            0x0010
+#define IMAGE_REL_ARM_MOV32T            0x0011
+#define IMAGE_REL_ARM_BRANCH20T         0x0012
+#define IMAGE_REL_ARM_BRANCH24T         0x0014
+#define IMAGE_REL_ARM_BLX23T            0x0015
+
+/* ARM64 relocation types */
+#define IMAGE_REL_ARM64_ABSOLUTE        0x0000
+#define IMAGE_REL_ARM64_ADDR32          0x0001
+#define IMAGE_REL_ARM64_ADDR32NB        0x0002
+#define IMAGE_REL_ARM64_BRANCH26        0x0003
+#define IMAGE_REL_ARM64_PAGEBASE_REL21  0x0004
+#define IMAGE_REL_ARM64_REL21           0x0005
+#define IMAGE_REL_ARM64_PAGEOFFSET_12A  0x0006
+#define IMAGE_REL_ARM64_PAGEOFFSET_12L  0x0007
+#define IMAGE_REL_ARM64_SECREL          0x0008
+#define IMAGE_REL_ARM64_SECREL_LOW12A   0x0009
+#define IMAGE_REL_ARM64_SECREL_HIGH12A  0x000A
+#define IMAGE_REL_ARM64_SECREL_LOW12L   0x000B
+#define IMAGE_REL_ARM64_TOKEN           0x000C
+#define IMAGE_REL_ARM64_SECTION         0x000D
+#define IMAGE_REL_ARM64_ADDR64          0x000E
+
+/* AMD64 relocation types */
+#define IMAGE_REL_AMD64_ABSOLUTE        0x0000
+#define IMAGE_REL_AMD64_ADDR64          0x0001
+#define IMAGE_REL_AMD64_ADDR32          0x0002
+#define IMAGE_REL_AMD64_ADDR32NB        0x0003
+#define IMAGE_REL_AMD64_REL32           0x0004
+#define IMAGE_REL_AMD64_REL32_1         0x0005
+#define IMAGE_REL_AMD64_REL32_2         0x0006
+#define IMAGE_REL_AMD64_REL32_3         0x0007
+#define IMAGE_REL_AMD64_REL32_4         0x0008
+#define IMAGE_REL_AMD64_REL32_5         0x0009
+#define IMAGE_REL_AMD64_SECTION         0x000A
+#define IMAGE_REL_AMD64_SECREL          0x000B
+#define IMAGE_REL_AMD64_SECREL7         0x000C
+#define IMAGE_REL_AMD64_TOKEN           0x000D
+#define IMAGE_REL_AMD64_SREL32          0x000E
+#define IMAGE_REL_AMD64_PAIR            0x000F
+#define IMAGE_REL_AMD64_SSPAN32         0x0010
+
+#endif /* _PE_H */
diff --git a/include/reiserfs.h b/include/reiserfs.h
index 2d14d48..ffe4e46 100644
--- a/include/reiserfs.h
+++ b/include/reiserfs.h
@@ -63,7 +63,7 @@
 } reiserfs_error_t;
 
 
-extern void reiserfs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
+void reiserfs_set_blk_dev(struct blk_desc *rbdd, disk_partition_t *info);
 extern int reiserfs_ls (char *dirname);
 extern int reiserfs_open (char *filename);
 extern int reiserfs_read (char *buf, unsigned len);
diff --git a/include/sandboxblockdev.h b/include/sandboxblockdev.h
index 627787a..5174f45 100644
--- a/include/sandboxblockdev.h
+++ b/include/sandboxblockdev.h
@@ -8,7 +8,9 @@
 #define __SANDBOX_BLOCK_DEV__
 
 struct host_block_dev {
-	block_dev_desc_t blk_dev;
+#ifndef CONFIG_BLK
+	struct blk_desc blk_dev;
+#endif
 	char *filename;
 	int fd;
 };
diff --git a/include/sandboxfs.h b/include/sandboxfs.h
index 4c7745d..6e6e3c6 100644
--- a/include/sandboxfs.h
+++ b/include/sandboxfs.h
@@ -18,7 +18,7 @@
 #ifndef __SANDBOX_FS__
 #define __SANDBOX_FS__
 
-int sandbox_fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
+int sandbox_fs_set_blk_dev(struct blk_desc *rbdd, disk_partition_t *info);
 
 int sandbox_fs_read_at(const char *filename, loff_t pos, void *buffer,
 		       loff_t maxsize, loff_t *actread);
diff --git a/include/sata.h b/include/sata.h
index fa61da8..b35359a 100644
--- a/include/sata.h
+++ b/include/sata.h
@@ -14,6 +14,6 @@
 int __sata_stop(void);
 int sata_port_status(int dev, int port);
 
-extern block_dev_desc_t sata_dev_desc[];
+extern struct blk_desc sata_dev_desc[];
 
 #endif
diff --git a/include/spl.h b/include/spl.h
index 92cdc04..de4f70a 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -29,6 +29,24 @@
 	u32 flags;
 };
 
+/*
+ * Information required to load data from a device
+ *
+ * @dev: Pointer to the device, e.g. struct mmc *
+ * @priv: Private data for the device
+ * @bl_len: Block length for reading in bytes
+ * @read: Function to call to read from the device
+ */
+struct spl_load_info {
+	void *dev;
+	void *priv;
+	int bl_len;
+	ulong (*read)(struct spl_load_info *load, ulong sector, ulong count,
+		      void *buf);
+};
+
+int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fdt);
+
 #define SPL_COPY_PAYLOAD_ONLY	1
 
 extern struct spl_image_info spl_image;
@@ -72,14 +90,16 @@
 int spl_sata_load_image(void);
 
 /* SPL FAT image functions */
-int spl_load_image_fat(block_dev_desc_t *block_dev, int partition, const char *filename);
-int spl_load_image_fat_os(block_dev_desc_t *block_dev, int partition);
+int spl_load_image_fat(struct blk_desc *block_dev, int partition,
+		       const char *filename);
+int spl_load_image_fat_os(struct blk_desc *block_dev, int partition);
 
 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image);
 
 /* SPL EXT image functions */
-int spl_load_image_ext(block_dev_desc_t *block_dev, int partition, const char *filename);
-int spl_load_image_ext_os(block_dev_desc_t *block_dev, int partition);
+int spl_load_image_ext(struct blk_desc *block_dev, int partition,
+		       const char *filename);
+int spl_load_image_ext_os(struct blk_desc *block_dev, int partition);
 
 /**
  * spl_init() - Set up device tree and driver model in SPL if enabled
diff --git a/include/systemace.h b/include/systemace.h
index 3f342d5..3b6ec7d 100644
--- a/include/systemace.h
+++ b/include/systemace.h
@@ -11,7 +11,7 @@
 
 # include  <part.h>
 
-block_dev_desc_t *  systemace_get_dev(int dev);
+struct blk_desc *systemace_get_dev(int dev);
 
 #endif	/* CONFIG_SYSTEMACE */
 #endif	/* __SYSTEMACE_H */
diff --git a/include/twl6030.h b/include/twl6030.h
index 7898699..40e2c11 100644
--- a/include/twl6030.h
+++ b/include/twl6030.h
@@ -20,19 +20,54 @@
 #define TWL6030_CHIP_PWM	0x49
 
 /* Slave Address 0x48 */
-#define VMMC_CFG_STATE		0x9A
-#define VMMC_CFG_VOLTATE	0x9B
-#define VUSB_CFG_STATE		0xA2
+#define TWL6030_STS_HW_CONDITIONS	0x21
+
+#define TWL6030_STS_HW_CONDITIONS_PWRON	(1 << 0)
+
+#define TWL6030_PHOENIX_DEV_ON		0x25
+
+#define TWL6030_PHOENIX_APP_DEVOFF	(1 << 0)
+#define TWL6030_PHOENIX_CON_DEVOFF	(1 << 1)
+#define TWL6030_PHOENIX_MOD_DEVOFF	(1 << 2)
+
+#define TWL6030_PH_STS_BOOT		0x29
+
+#define TWL6030_PH_STS_BOOT0		(1 << 0)
+#define TWL6030_PH_STS_BOOT1		(1 << 1)
+#define TWL6030_PH_STS_BOOT2		(1 << 2)
+#define TWL6030_PH_STS_BOOT3		(1 << 3)
+
+#define TWL6030_VAUX1_CFG_STATE		0x86
+#define TWL6030_VAUX1_CFG_VOLTAGE	0x87
+#define TWL6030_VMMC_CFG_STATE		0x9A
+#define TWL6030_VMMC_CFG_VOLTAGE	0x9B
+#define TWL6030_VUSB_CFG_STATE		0xA2
+#define TWL6030_VUSB_CFG_VOLTAGE	0xA3
+
+#define TWL6030_CFG_GRP_P1		(1 << 0)
+#define TWL6030_CFG_STATE_ON		(1 << 0)
+#define TWL6030_CFG_STATE_P1		(TWL6030_CFG_GRP_P1 << 5)
+#define TWL6030_CFG_VOLTAGE_18		0x09
+#define TWL6030_CFG_VOLTAGE_28		0x13
+#define TWL6030_CFG_VOLTAGE_30		0x15
+#define TWL6030_CFG_VOLTAGE_33		0x18
 
 #define MISC1			0xE4
 #define VAC_MEAS		(1 << 2)
 #define VBAT_MEAS		(1 << 1)
 #define BB_MEAS			(1 << 0)
 
-#define MISC2			0xE5
+#define TWL6030_MISC2			0xE5
+#define TWL6030_MISC2_VUSB_IN_PMID	(1 << 3)
+#define TWL6030_MISC2_VUSB_IN_VSYS	(1 << 4)
 
 /* Slave Address 0x49 */
 
+#define TWL6030_CONTROLLER_STAT1		0xE3
+
+#define TWL6030_CONTROLLER_STAT1_VAC_DET	(1 << 3)
+#define TWL6030_CONTROLLER_STAT1_VBUS_DET	(1 << 2)
+
 /* Battery CHARGER REGISTERS */
 #define CONTROLLER_INT_MASK	0xE0
 #define CONTROLLER_CTRL1	0xE1
@@ -162,12 +197,25 @@
 	return i2c_read(chip_no, reg, 1, val, 1);
 }
 
+/*
+ * Power
+ */
+
+void twl6030_power_off(void);
 void twl6030_init_battery_charging(void);
 void twl6030_usb_device_settings(void);
 void twl6030_start_usb_charging(void);
 void twl6030_stop_usb_charging(void);
 int twl6030_get_battery_voltage(void);
 int twl6030_get_battery_current(void);
-void twl6030_power_mmc_init(void);
+void twl6030_power_mmc_init(int dev_index);
+
+/*
+ * Input
+ */
+
+int twl6030_input_power_button(void);
+int twl6030_input_charger(void);
+int twl6030_input_usb(void);
 
 #endif /* TWL6030_H */
diff --git a/include/u-boot/rsa.h b/include/u-boot/rsa.h
index fd08a61..0e96c38 100644
--- a/include/u-boot/rsa.h
+++ b/include/u-boot/rsa.h
@@ -30,6 +30,8 @@
 	uint64_t exponent;	/* public exponent */
 };
 
+struct image_sign_info;
+
 #if IMAGE_ENABLE_SIGN
 /**
  * sign() - calculate and return signature for given input data
diff --git a/include/ubifs_uboot.h b/include/ubifs_uboot.h
index dab433a..d86da27 100644
--- a/include/ubifs_uboot.h
+++ b/include/ubifs_uboot.h
@@ -21,7 +21,7 @@
 int ubifs_is_mounted(void);
 int ubifs_load(char *filename, u32 addr, u32 size);
 
-int ubifs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
+int ubifs_set_blk_dev(struct blk_desc *rbdd, disk_partition_t *info);
 int ubifs_ls(const char *dir_name);
 int ubifs_exists(const char *filename);
 int ubifs_size(const char *filename, loff_t *size);
diff --git a/include/usb.h b/include/usb.h
index 0b410b6..c2fa684 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -228,7 +228,7 @@
 #ifdef CONFIG_USB_STORAGE
 
 #define USB_MAX_STOR_DEV 7
-block_dev_desc_t *usb_stor_get_dev(int index);
+struct blk_desc *usb_stor_get_dev(int index);
 int usb_stor_scan(int mode);
 int usb_stor_info(void);
 
diff --git a/include/usb_mass_storage.h b/include/usb_mass_storage.h
index 5804b70..8229f62 100644
--- a/include/usb_mass_storage.h
+++ b/include/usb_mass_storage.h
@@ -23,7 +23,7 @@
 	unsigned int start_sector;
 	unsigned int num_sectors;
 	const char *name;
-	block_dev_desc_t block_dev;
+	struct blk_desc block_dev;
 };
 
 int fsg_init(struct ums *ums_devs, int count);
diff --git a/include/zfs_common.h b/include/zfs_common.h
index 3bd575e..bca3dff 100644
--- a/include/zfs_common.h
+++ b/include/zfs_common.h
@@ -63,7 +63,7 @@
 struct zfs_filesystem {
 
 	/* Block Device Descriptor */
-	block_dev_desc_t *dev_desc;
+	struct blk_desc *dev_desc;
 };
 
 struct device_s {
@@ -98,7 +98,7 @@
 int zfs_ls(device_t dev, const char *path,
 		   int (*hook) (const char *, const struct zfs_dirhook_info *));
 int zfs_devread(int sector, int byte_offset, int byte_len, char *buf);
-void zfs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
+void zfs_set_blk_dev(struct blk_desc *rbdd, disk_partition_t *info);
 void zfs_unmount(struct zfs_data *data);
 int lzjb_decompress(void *, void *, uint32_t, uint32_t);
 #endif
diff --git a/lib/Kconfig b/lib/Kconfig
index c7eab46..7a45336 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -128,6 +128,27 @@
 	  - if errno is null or positive number - a pointer to "Success" message
 	  - if errno is negative - a pointer to errno related message
 
+config OF_LIBFDT
+	bool "Enable the FDT library"
+	default y if OF_CONTROL
+	help
+	  This enables the FDT library (libfdt). It provides functions for
+	  accessing binary device tree images in memory, such as adding and
+	  removing notes and properties, scanning through the tree and finding
+	  particular compatible nodes. The library operates on a flattened
+	  version of the device tree.
+
+config SPL_OF_LIBFDT
+	bool "Enable the FDT library for SPL"
+	default y if SPL_OF_CONTROL
+	help
+	  This enables the FDT library (libfdt). It provides functions for
+	  accessing binary device tree images in memory, such as adding and
+	  removing notes and properties, scanning through the tree and finding
+	  particular compatible nodes. The library operates on a flattened
+	  version of the device tree.
+
 source lib/efi/Kconfig
+source lib/efi_loader/Kconfig
 
 endmenu
diff --git a/lib/Makefile b/lib/Makefile
index 1e21bcc..02dfa29 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -8,14 +8,13 @@
 ifndef CONFIG_SPL_BUILD
 
 obj-$(CONFIG_EFI) += efi/
+obj-$(CONFIG_EFI_LOADER) += efi_loader/
 obj-$(CONFIG_RSA) += rsa/
 obj-$(CONFIG_LZMA) += lzma/
 obj-$(CONFIG_LZO) += lzo/
 obj-$(CONFIG_ZLIB) += zlib/
 obj-$(CONFIG_BZIP2) += bzip2/
 obj-$(CONFIG_TIZEN) += tizen/
-obj-$(CONFIG_OF_LIBFDT) += libfdt/
-obj-$(CONFIG_FIT) += libfdt/
 obj-$(CONFIG_FIT) += libfdt/
 obj-$(CONFIG_CMD_DHRYSTONE) += dhry/
 
@@ -50,9 +49,7 @@
 obj-y += list_sort.o
 endif
 
-ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_OF_LIBFDT) += libfdt/
-endif
+obj-$(CONFIG_$(SPL_)OF_LIBFDT) += libfdt/
 ifdef CONFIG_SPL_OF_CONTROL
 obj-$(CONFIG_OF_LIBFDT) += libfdt/
 endif
diff --git a/lib/crc16.c b/lib/crc16.c
index c63fde9..753b987 100644
--- a/lib/crc16.c
+++ b/lib/crc16.c
@@ -27,49 +27,48 @@
 
 /* Table of CRC constants - implements x^16+x^12+x^5+1 */
 static const uint16_t crc16_tab[] = {
-    0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7,
-    0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef,
-    0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
-    0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de,
-    0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485,
-    0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d,
-    0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4,
-    0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc,
-    0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823,
-    0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b,
-    0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12,
-    0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a,
-    0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41,
-    0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49,
-    0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70,
-    0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78,
-    0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f,
-    0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067,
-    0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e,
-    0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256,
-    0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d,
-    0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
-    0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c,
-    0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634,
-    0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab,
-    0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3,
-    0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a,
-    0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92,
-    0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9,
-    0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1,
-    0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8,
-    0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0,
+	0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7,
+	0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef,
+	0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
+	0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de,
+	0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485,
+	0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d,
+	0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4,
+	0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc,
+	0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823,
+	0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b,
+	0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12,
+	0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a,
+	0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41,
+	0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49,
+	0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70,
+	0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78,
+	0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f,
+	0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067,
+	0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e,
+	0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256,
+	0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d,
+	0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
+	0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c,
+	0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634,
+	0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab,
+	0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3,
+	0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a,
+	0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92,
+	0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9,
+	0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1,
+	0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8,
+	0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0,
 };
 
-uint16_t
-cyg_crc16(unsigned char *buf, int len)
+uint16_t crc16_ccitt(uint16_t crc_start, unsigned char *buf, int len)
 {
-    int i;
-    uint16_t cksum;
+	int i;
+	uint16_t cksum;
+
+	cksum = crc_start;
+	for (i = 0;  i < len;  i++)
+		cksum = crc16_tab[((cksum>>8) ^ *buf++) & 0xff] ^ (cksum << 8);
 
-    cksum = 0;
-    for (i = 0;  i < len;  i++) {
-	cksum = crc16_tab[((cksum>>8) ^ *buf++) & 0xFF] ^ (cksum << 8);
-    }
-    return cksum;
+	return cksum;
 }
diff --git a/lib/dhry/cmd_dhry.c b/lib/dhry/cmd_dhry.c
index 5dc191e..f44305b 100644
--- a/lib/dhry/cmd_dhry.c
+++ b/lib/dhry/cmd_dhry.c
@@ -6,11 +6,13 @@
 
 #include <common.h>
 #include <command.h>
+#include <div64.h>
 #include "dhry.h"
 
 static int do_dhry(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	ulong start, duration, dhry_per_sec, vax_mips;
+	ulong start, duration, vax_mips;
+	u64 dhry_per_sec;
 	int iterations = 1000000;
 
 	if (argc > 1)
@@ -19,10 +21,10 @@
 	start = get_timer(0);
 	dhry(iterations);
 	duration = get_timer(start);
-	dhry_per_sec = iterations * 1000 / duration;
-	vax_mips = dhry_per_sec / 1757;
+	dhry_per_sec = lldiv(iterations * 1000ULL, duration);
+	vax_mips = lldiv(dhry_per_sec, 1757);
 	printf("%d iterations in %lu ms: %lu/s, %lu DMIPS\n", iterations,
-	       duration, dhry_per_sec, vax_mips);
+	       duration, (ulong)dhry_per_sec, vax_mips);
 
 	return 0;
 }
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
new file mode 100644
index 0000000..14c99ec
--- /dev/null
+++ b/lib/efi_loader/Kconfig
@@ -0,0 +1,9 @@
+config EFI_LOADER
+	bool "Support running EFI Applications in U-Boot"
+	depends on (ARM64 || ARM) && OF_LIBFDT
+	default y
+	help
+	  Select this option if you want to run EFI applications (like grub2)
+	  on top of U-Boot. If this option is enabled, U-Boot will expose EFI
+	  interfaces to a loaded EFI application, enabling it to reuse U-Boot's
+	  device drivers.
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
new file mode 100644
index 0000000..28725a2
--- /dev/null
+++ b/lib/efi_loader/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2016 Alexander Graf
+#
+#  SPDX-License-Identifier:     GPL-2.0+
+#
+
+# This file only gets included with CONFIG_EFI_LOADER set, so all
+# object inclusion implicitly depends on it
+
+obj-y += efi_image_loader.o efi_boottime.o efi_runtime.o efi_console.o
+obj-y += efi_memory.o
+obj-$(CONFIG_PARTITIONS) += efi_disk.o
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
new file mode 100644
index 0000000..87400de
--- /dev/null
+++ b/lib/efi_loader/efi_boottime.c
@@ -0,0 +1,781 @@
+/*
+ *  EFI application boot time services
+ *
+ *  Copyright (c) 2016 Alexander Graf
+ *
+ *  SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* #define DEBUG_EFI */
+
+#include <common.h>
+#include <efi_loader.h>
+#include <malloc.h>
+#include <asm/global_data.h>
+#include <libfdt_env.h>
+#include <u-boot/crc.h>
+#include <bootm.h>
+#include <inttypes.h>
+#include <watchdog.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* This list contains all the EFI objects our payload has access to */
+LIST_HEAD(efi_obj_list);
+
+/*
+ * If we're running on nasty systems (32bit ARM booting into non-EFI Linux)
+ * we need to do trickery with caches. Since we don't want to break the EFI
+ * aware boot path, only apply hacks when loading exiting directly (breaking
+ * direct Linux EFI booting along the way - oh well).
+ */
+static bool efi_is_direct_boot = true;
+
+/*
+ * EFI can pass arbitrary additional "tables" containing vendor specific
+ * information to the payload. One such table is the FDT table which contains
+ * a pointer to a flattened device tree blob.
+ *
+ * In most cases we want to pass an FDT to the payload, so reserve one slot of
+ * config table space for it. The pointer gets populated by do_bootefi_exec().
+ */
+static struct efi_configuration_table EFI_RUNTIME_DATA efi_conf_table[1];
+
+/*
+ * The "gd" pointer lives in a register on ARM and AArch64 that we declare
+ * fixed when compiling U-Boot. However, the payload does not know about that
+ * restriction so we need to manually swap its and our view of that register on
+ * EFI callback entry/exit.
+ */
+static volatile void *efi_gd, *app_gd;
+
+/* Called from do_bootefi_exec() */
+void efi_save_gd(void)
+{
+	efi_gd = gd;
+}
+
+/* Called on every callback entry */
+void efi_restore_gd(void)
+{
+	/* Only restore if we're already in EFI context */
+	if (!efi_gd)
+		return;
+
+	if (gd != efi_gd)
+		app_gd = gd;
+	gd = efi_gd;
+}
+
+/* Called on every callback exit */
+efi_status_t efi_exit_func(efi_status_t ret)
+{
+	gd = app_gd;
+	return ret;
+}
+
+static efi_status_t efi_unsupported(const char *funcname)
+{
+#ifdef DEBUG_EFI
+	printf("EFI: App called into unimplemented function %s\n", funcname);
+#endif
+	return EFI_EXIT(EFI_UNSUPPORTED);
+}
+
+static int guidcmp(const efi_guid_t *g1, const efi_guid_t *g2)
+{
+	return memcmp(g1, g2, sizeof(efi_guid_t));
+}
+
+static unsigned long EFIAPI efi_raise_tpl(unsigned long new_tpl)
+{
+	EFI_ENTRY("0x%lx", new_tpl);
+	return EFI_EXIT(0);
+}
+
+static void EFIAPI efi_restore_tpl(unsigned long old_tpl)
+{
+	EFI_ENTRY("0x%lx", old_tpl);
+	EFI_EXIT(efi_unsupported(__func__));
+}
+
+efi_status_t EFIAPI efi_allocate_pages_ext(int type, int memory_type,
+					   unsigned long pages,
+					   uint64_t *memory)
+{
+	efi_status_t r;
+
+	EFI_ENTRY("%d, %d, 0x%lx, %p", type, memory_type, pages, memory);
+	r = efi_allocate_pages(type, memory_type, pages, memory);
+	return EFI_EXIT(r);
+}
+
+efi_status_t EFIAPI efi_free_pages_ext(uint64_t memory, unsigned long pages)
+{
+	efi_status_t r;
+
+	EFI_ENTRY("%"PRIx64", 0x%lx", memory, pages);
+	r = efi_free_pages(memory, pages);
+	return EFI_EXIT(r);
+}
+
+efi_status_t EFIAPI efi_get_memory_map_ext(unsigned long *memory_map_size,
+					   struct efi_mem_desc *memory_map,
+					   unsigned long *map_key,
+					   unsigned long *descriptor_size,
+					   uint32_t *descriptor_version)
+{
+	efi_status_t r;
+
+	EFI_ENTRY("%p, %p, %p, %p, %p", memory_map_size, memory_map,
+		  map_key, descriptor_size, descriptor_version);
+	r = efi_get_memory_map(memory_map_size, memory_map, map_key,
+			       descriptor_size, descriptor_version);
+	return EFI_EXIT(r);
+}
+
+static efi_status_t EFIAPI efi_allocate_pool(int pool_type, unsigned long size,
+					     void **buffer)
+{
+	return efi_allocate_pages(0, pool_type, (size + 0xfff) >> 12, (void*)buffer);
+}
+
+static efi_status_t EFIAPI efi_free_pool(void *buffer)
+{
+	return efi_free_pages((ulong)buffer, 0);
+}
+
+/*
+ * Our event capabilities are very limited. Only support a single
+ * event to exist, so we don't need to maintain lists.
+ */
+static struct {
+	enum efi_event_type type;
+	u32 trigger_type;
+	u32 trigger_time;
+	u64 trigger_next;
+	unsigned long notify_tpl;
+	void (*notify_function) (void *event, void *context);
+	void *notify_context;
+} efi_event = {
+	/* Disable timers on bootup */
+	.trigger_next = -1ULL,
+};
+
+static efi_status_t EFIAPI efi_create_event(
+			enum efi_event_type type, ulong notify_tpl,
+			void (*notify_function) (void *event, void *context),
+			void *notify_context, void **event)
+{
+	EFI_ENTRY("%d, 0x%lx, %p, %p", type, notify_tpl, notify_function,
+		  notify_context);
+	if (efi_event.notify_function) {
+		/* We only support one event at a time */
+		return EFI_EXIT(EFI_OUT_OF_RESOURCES);
+	}
+
+	efi_event.type = type;
+	efi_event.notify_tpl = notify_tpl;
+	efi_event.notify_function = notify_function;
+	efi_event.notify_context = notify_context;
+	*event = &efi_event;
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+/*
+ * Our timers have to work without interrupts, so we check whenever keyboard
+ * input or disk accesses happen if enough time elapsed for it to fire.
+ */
+void efi_timer_check(void)
+{
+	u64 now = timer_get_us();
+
+	if (now >= efi_event.trigger_next) {
+		/* Triggering! */
+		if (efi_event.trigger_type == EFI_TIMER_PERIODIC)
+			efi_event.trigger_next += efi_event.trigger_time / 10;
+		efi_event.notify_function(&efi_event, efi_event.notify_context);
+	}
+
+	WATCHDOG_RESET();
+}
+
+static efi_status_t EFIAPI efi_set_timer(void *event, int type,
+					 uint64_t trigger_time)
+{
+	/* We don't have 64bit division available everywhere, so limit timer
+	 * distances to 32bit bits. */
+	u32 trigger32 = trigger_time;
+
+	EFI_ENTRY("%p, %d, %"PRIx64, event, type, trigger_time);
+
+	if (trigger32 < trigger_time) {
+		printf("WARNING: Truncating timer from %"PRIx64" to %x\n",
+		       trigger_time, trigger32);
+	}
+
+	if (event != &efi_event) {
+		/* We only support one event at a time */
+		return EFI_EXIT(EFI_INVALID_PARAMETER);
+	}
+
+	switch (type) {
+	case EFI_TIMER_STOP:
+		efi_event.trigger_next = -1ULL;
+		break;
+	case EFI_TIMER_PERIODIC:
+	case EFI_TIMER_RELATIVE:
+		efi_event.trigger_next = timer_get_us() + (trigger32 / 10);
+		break;
+	default:
+		return EFI_EXIT(EFI_INVALID_PARAMETER);
+	}
+	efi_event.trigger_type = type;
+	efi_event.trigger_time = trigger_time;
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_wait_for_event(unsigned long num_events,
+					      void *event, unsigned long *index)
+{
+	u64 now;
+
+	EFI_ENTRY("%ld, %p, %p", num_events, event, index);
+
+	now = timer_get_us();
+	while (now < efi_event.trigger_next) { }
+	efi_timer_check();
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_signal_event(void *event)
+{
+	EFI_ENTRY("%p", event);
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_close_event(void *event)
+{
+	EFI_ENTRY("%p", event);
+	efi_event.trigger_next = -1ULL;
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_check_event(void *event)
+{
+	EFI_ENTRY("%p", event);
+	return EFI_EXIT(EFI_NOT_READY);
+}
+
+static efi_status_t EFIAPI efi_install_protocol_interface(void **handle,
+			efi_guid_t *protocol, int protocol_interface_type,
+			void *protocol_interface)
+{
+	EFI_ENTRY("%p, %p, %d, %p", handle, protocol, protocol_interface_type,
+		  protocol_interface);
+	return EFI_EXIT(EFI_OUT_OF_RESOURCES);
+}
+static efi_status_t EFIAPI efi_reinstall_protocol_interface(void *handle,
+			efi_guid_t *protocol, void *old_interface,
+			void *new_interface)
+{
+	EFI_ENTRY("%p, %p, %p, %p", handle, protocol, old_interface,
+		  new_interface);
+	return EFI_EXIT(EFI_ACCESS_DENIED);
+}
+
+static efi_status_t EFIAPI efi_uninstall_protocol_interface(void *handle,
+			efi_guid_t *protocol, void *protocol_interface)
+{
+	EFI_ENTRY("%p, %p, %p", handle, protocol, protocol_interface);
+	return EFI_EXIT(EFI_NOT_FOUND);
+}
+
+static efi_status_t EFIAPI efi_register_protocol_notify(efi_guid_t *protocol,
+							void *event,
+							void **registration)
+{
+	EFI_ENTRY("%p, %p, %p", protocol, event, registration);
+	return EFI_EXIT(EFI_OUT_OF_RESOURCES);
+}
+
+static int efi_search(enum efi_locate_search_type search_type,
+		      efi_guid_t *protocol, void *search_key,
+		      struct efi_object *efiobj)
+{
+	int i;
+
+	switch (search_type) {
+	case all_handles:
+		return 0;
+	case by_register_notify:
+		return -1;
+	case by_protocol:
+		for (i = 0; i < ARRAY_SIZE(efiobj->protocols); i++) {
+			const efi_guid_t *guid = efiobj->protocols[i].guid;
+			if (guid && !guidcmp(guid, protocol))
+				return 0;
+		}
+		return -1;
+	}
+
+	return -1;
+}
+
+static efi_status_t EFIAPI efi_locate_handle(
+			enum efi_locate_search_type search_type,
+			efi_guid_t *protocol, void *search_key,
+			unsigned long *buffer_size, efi_handle_t *buffer)
+{
+	struct list_head *lhandle;
+	unsigned long size = 0;
+
+	EFI_ENTRY("%d, %p, %p, %p, %p", search_type, protocol, search_key,
+		  buffer_size, buffer);
+
+	/* Count how much space we need */
+	list_for_each(lhandle, &efi_obj_list) {
+		struct efi_object *efiobj;
+		efiobj = list_entry(lhandle, struct efi_object, link);
+		if (!efi_search(search_type, protocol, search_key, efiobj)) {
+			size += sizeof(void*);
+		}
+	}
+
+	if (*buffer_size < size) {
+		*buffer_size = size;
+		return EFI_EXIT(EFI_BUFFER_TOO_SMALL);
+	}
+
+	/* Then fill the array */
+	list_for_each(lhandle, &efi_obj_list) {
+		struct efi_object *efiobj;
+		efiobj = list_entry(lhandle, struct efi_object, link);
+		if (!efi_search(search_type, protocol, search_key, efiobj)) {
+			*(buffer++) = efiobj->handle;
+		}
+	}
+
+	*buffer_size = size;
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_locate_device_path(efi_guid_t *protocol,
+			struct efi_device_path **device_path,
+			efi_handle_t *device)
+{
+	EFI_ENTRY("%p, %p, %p", protocol, device_path, device);
+	return EFI_EXIT(EFI_NOT_FOUND);
+}
+
+static efi_status_t EFIAPI efi_install_configuration_table(efi_guid_t *guid,
+							   void *table)
+{
+	int i;
+
+	EFI_ENTRY("%p, %p", guid, table);
+
+	/* Check for guid override */
+	for (i = 0; i < systab.nr_tables; i++) {
+		if (!guidcmp(guid, &efi_conf_table[i].guid)) {
+			efi_conf_table[i].table = table;
+			return EFI_EXIT(EFI_SUCCESS);
+		}
+	}
+
+	/* No override, check for overflow */
+	if (i >= ARRAY_SIZE(efi_conf_table))
+		return EFI_EXIT(EFI_OUT_OF_RESOURCES);
+
+	/* Add a new entry */
+	memcpy(&efi_conf_table[i].guid, guid, sizeof(*guid));
+	efi_conf_table[i].table = table;
+	systab.nr_tables = i;
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_load_image(bool boot_policy,
+					  efi_handle_t parent_image,
+					  struct efi_device_path *file_path,
+					  void *source_buffer,
+					  unsigned long source_size,
+					  efi_handle_t *image_handle)
+{
+	static struct efi_object loaded_image_info_obj = {
+		.protocols = {
+			{
+				.guid = &efi_guid_loaded_image,
+				.open = &efi_return_handle,
+			},
+		},
+	};
+	struct efi_loaded_image *info;
+	struct efi_object *obj;
+
+	EFI_ENTRY("%d, %p, %p, %p, %ld, %p", boot_policy, parent_image,
+		  file_path, source_buffer, source_size, image_handle);
+	info = malloc(sizeof(*info));
+	obj = malloc(sizeof(loaded_image_info_obj));
+	memset(info, 0, sizeof(*info));
+	memcpy(obj, &loaded_image_info_obj, sizeof(loaded_image_info_obj));
+	obj->handle = info;
+	info->file_path = file_path;
+	info->reserved = efi_load_pe(source_buffer, info);
+	if (!info->reserved) {
+		free(info);
+		free(obj);
+		return EFI_EXIT(EFI_UNSUPPORTED);
+	}
+
+	*image_handle = info;
+	list_add_tail(&obj->link, &efi_obj_list);
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle,
+					   unsigned long *exit_data_size,
+					   s16 **exit_data)
+{
+	ulong (*entry)(void *image_handle, struct efi_system_table *st);
+	struct efi_loaded_image *info = image_handle;
+
+	EFI_ENTRY("%p, %p, %p", image_handle, exit_data_size, exit_data);
+	entry = info->reserved;
+
+	efi_is_direct_boot = false;
+
+	/* call the image! */
+	entry(image_handle, &systab);
+
+	/* Should usually never get here */
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_exit(void *image_handle, long exit_status,
+				    unsigned long exit_data_size,
+				    uint16_t *exit_data)
+{
+	EFI_ENTRY("%p, %ld, %ld, %p", image_handle, exit_status,
+		  exit_data_size, exit_data);
+	return EFI_EXIT(efi_unsupported(__func__));
+}
+
+static struct efi_object *efi_search_obj(void *handle)
+{
+	struct list_head *lhandle;
+
+	list_for_each(lhandle, &efi_obj_list) {
+		struct efi_object *efiobj;
+		efiobj = list_entry(lhandle, struct efi_object, link);
+		if (efiobj->handle == handle)
+			return efiobj;
+	}
+
+	return NULL;
+}
+
+static efi_status_t EFIAPI efi_unload_image(void *image_handle)
+{
+	struct efi_object *efiobj;
+
+	EFI_ENTRY("%p", image_handle);
+	efiobj = efi_search_obj(image_handle);
+	if (efiobj)
+		list_del(&efiobj->link);
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static void efi_exit_caches(void)
+{
+#if defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
+	/*
+	 * Grub on 32bit ARM needs to have caches disabled before jumping into
+	 * a zImage, but does not know of all cache layers. Give it a hand.
+	 */
+	if (efi_is_direct_boot)
+		cleanup_before_linux();
+#endif
+}
+
+static efi_status_t EFIAPI efi_exit_boot_services(void *image_handle,
+						  unsigned long map_key)
+{
+	EFI_ENTRY("%p, %ld", image_handle, map_key);
+
+	/* Fix up caches for EFI payloads if necessary */
+	efi_exit_caches();
+
+	/* This stops all lingering devices */
+	bootm_disable_interrupts();
+
+	/* Give the payload some time to boot */
+	WATCHDOG_RESET();
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_get_next_monotonic_count(uint64_t *count)
+{
+	static uint64_t mono = 0;
+	EFI_ENTRY("%p", count);
+	*count = mono++;
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_stall(unsigned long microseconds)
+{
+	EFI_ENTRY("%ld", microseconds);
+	udelay(microseconds);
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_set_watchdog_timer(unsigned long timeout,
+						  uint64_t watchdog_code,
+						  unsigned long data_size,
+						  uint16_t *watchdog_data)
+{
+	EFI_ENTRY("%ld, 0x%"PRIx64", %ld, %p", timeout, watchdog_code,
+		  data_size, watchdog_data);
+	return EFI_EXIT(efi_unsupported(__func__));
+}
+
+static efi_status_t EFIAPI efi_connect_controller(
+			efi_handle_t controller_handle,
+			efi_handle_t *driver_image_handle,
+			struct efi_device_path *remain_device_path,
+			bool recursive)
+{
+	EFI_ENTRY("%p, %p, %p, %d", controller_handle, driver_image_handle,
+		  remain_device_path, recursive);
+	return EFI_EXIT(EFI_NOT_FOUND);
+}
+
+static efi_status_t EFIAPI efi_disconnect_controller(void *controller_handle,
+						     void *driver_image_handle,
+						     void *child_handle)
+{
+	EFI_ENTRY("%p, %p, %p", controller_handle, driver_image_handle,
+		  child_handle);
+	return EFI_EXIT(EFI_INVALID_PARAMETER);
+}
+
+static efi_status_t EFIAPI efi_close_protocol(void *handle,
+					      efi_guid_t *protocol,
+					      void *agent_handle,
+					      void *controller_handle)
+{
+	EFI_ENTRY("%p, %p, %p, %p", handle, protocol, agent_handle,
+		  controller_handle);
+	return EFI_EXIT(EFI_NOT_FOUND);
+}
+
+static efi_status_t EFIAPI efi_open_protocol_information(efi_handle_t handle,
+			efi_guid_t *protocol,
+			struct efi_open_protocol_info_entry **entry_buffer,
+			unsigned long *entry_count)
+{
+	EFI_ENTRY("%p, %p, %p, %p", handle, protocol, entry_buffer,
+		  entry_count);
+	return EFI_EXIT(EFI_NOT_FOUND);
+}
+
+static efi_status_t EFIAPI efi_protocols_per_handle(void *handle,
+			efi_guid_t ***protocol_buffer,
+			unsigned long *protocol_buffer_count)
+{
+	EFI_ENTRY("%p, %p, %p", handle, protocol_buffer,
+		  protocol_buffer_count);
+	return EFI_EXIT(EFI_OUT_OF_RESOURCES);
+}
+
+static efi_status_t EFIAPI efi_locate_handle_buffer(
+			enum efi_locate_search_type search_type,
+			efi_guid_t *protocol, void *search_key,
+			unsigned long *no_handles, efi_handle_t **buffer)
+{
+	EFI_ENTRY("%d, %p, %p, %p, %p", search_type, protocol, search_key,
+		  no_handles, buffer);
+	return EFI_EXIT(EFI_NOT_FOUND);
+}
+
+static struct efi_class_map efi_class_maps[] = {
+	{
+		.guid = &efi_guid_console_control,
+		.interface = &efi_console_control
+	},
+};
+
+static efi_status_t EFIAPI efi_locate_protocol(efi_guid_t *protocol,
+					       void *registration,
+					       void **protocol_interface)
+{
+	int i;
+
+	EFI_ENTRY("%p, %p, %p", protocol, registration, protocol_interface);
+	for (i = 0; i < ARRAY_SIZE(efi_class_maps); i++) {
+		struct efi_class_map *curmap = &efi_class_maps[i];
+		if (!guidcmp(protocol, curmap->guid)) {
+			*protocol_interface = (void*)curmap->interface;
+			return EFI_EXIT(EFI_SUCCESS);
+		}
+	}
+
+	return EFI_EXIT(EFI_NOT_FOUND);
+}
+
+static efi_status_t EFIAPI efi_install_multiple_protocol_interfaces(
+			void **handle, ...)
+{
+	EFI_ENTRY("%p", handle);
+	return EFI_EXIT(EFI_OUT_OF_RESOURCES);
+}
+
+static efi_status_t EFIAPI efi_uninstall_multiple_protocol_interfaces(
+			void *handle, ...)
+{
+	EFI_ENTRY("%p", handle);
+	return EFI_EXIT(EFI_INVALID_PARAMETER);
+}
+
+static efi_status_t EFIAPI efi_calculate_crc32(void *data,
+					       unsigned long data_size,
+					       uint32_t *crc32_p)
+{
+	EFI_ENTRY("%p, %ld", data, data_size);
+	*crc32_p = crc32(0, data, data_size);
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static void EFIAPI efi_copy_mem(void *destination, void *source,
+				unsigned long length)
+{
+	EFI_ENTRY("%p, %p, %ld", destination, source, length);
+	memcpy(destination, source, length);
+}
+
+static void EFIAPI efi_set_mem(void *buffer, unsigned long size, uint8_t value)
+{
+	EFI_ENTRY("%p, %ld, 0x%x", buffer, size, value);
+	memset(buffer, value, size);
+}
+
+static efi_status_t EFIAPI efi_open_protocol(
+			void *handle, efi_guid_t *protocol,
+			void **protocol_interface, void *agent_handle,
+			void *controller_handle, uint32_t attributes)
+{
+	struct list_head *lhandle;
+	int i;
+	efi_status_t r = EFI_UNSUPPORTED;
+
+	EFI_ENTRY("%p, %p, %p, %p, %p, 0x%x", handle, protocol,
+		  protocol_interface, agent_handle, controller_handle,
+		  attributes);
+	list_for_each(lhandle, &efi_obj_list) {
+		struct efi_object *efiobj;
+		efiobj = list_entry(lhandle, struct efi_object, link);
+
+		if (efiobj->handle != handle)
+			continue;
+
+		for (i = 0; i < ARRAY_SIZE(efiobj->protocols); i++) {
+			struct efi_handler *handler = &efiobj->protocols[i];
+			const efi_guid_t *hprotocol = handler->guid;
+			if (!hprotocol)
+				break;
+			if (!guidcmp(hprotocol, protocol)) {
+				r = handler->open(handle, protocol,
+				    protocol_interface, agent_handle,
+				    controller_handle, attributes);
+				goto out;
+			}
+		}
+	}
+
+out:
+	return EFI_EXIT(r);
+}
+
+static efi_status_t EFIAPI efi_handle_protocol(void *handle,
+					       efi_guid_t *protocol,
+					       void **protocol_interface)
+{
+	EFI_ENTRY("%p, %p, %p", handle, protocol, protocol_interface);
+	return efi_open_protocol(handle, protocol, protocol_interface,
+				 NULL, NULL, 0);
+}
+
+static const struct efi_boot_services efi_boot_services = {
+	.hdr = {
+		.headersize = sizeof(struct efi_table_hdr),
+	},
+	.raise_tpl = efi_raise_tpl,
+	.restore_tpl = efi_restore_tpl,
+	.allocate_pages = efi_allocate_pages_ext,
+	.free_pages = efi_free_pages_ext,
+	.get_memory_map = efi_get_memory_map_ext,
+	.allocate_pool = efi_allocate_pool,
+	.free_pool = efi_free_pool,
+	.create_event = efi_create_event,
+	.set_timer = efi_set_timer,
+	.wait_for_event = efi_wait_for_event,
+	.signal_event = efi_signal_event,
+	.close_event = efi_close_event,
+	.check_event = efi_check_event,
+	.install_protocol_interface = efi_install_protocol_interface,
+	.reinstall_protocol_interface = efi_reinstall_protocol_interface,
+	.uninstall_protocol_interface = efi_uninstall_protocol_interface,
+	.handle_protocol = efi_handle_protocol,
+	.reserved = NULL,
+	.register_protocol_notify = efi_register_protocol_notify,
+	.locate_handle = efi_locate_handle,
+	.locate_device_path = efi_locate_device_path,
+	.install_configuration_table = efi_install_configuration_table,
+	.load_image = efi_load_image,
+	.start_image = efi_start_image,
+	.exit = (void*)efi_exit,
+	.unload_image = efi_unload_image,
+	.exit_boot_services = efi_exit_boot_services,
+	.get_next_monotonic_count = efi_get_next_monotonic_count,
+	.stall = efi_stall,
+	.set_watchdog_timer = efi_set_watchdog_timer,
+	.connect_controller = efi_connect_controller,
+	.disconnect_controller = efi_disconnect_controller,
+	.open_protocol = efi_open_protocol,
+	.close_protocol = efi_close_protocol,
+	.open_protocol_information = efi_open_protocol_information,
+	.protocols_per_handle = efi_protocols_per_handle,
+	.locate_handle_buffer = efi_locate_handle_buffer,
+	.locate_protocol = efi_locate_protocol,
+	.install_multiple_protocol_interfaces = efi_install_multiple_protocol_interfaces,
+	.uninstall_multiple_protocol_interfaces = efi_uninstall_multiple_protocol_interfaces,
+	.calculate_crc32 = efi_calculate_crc32,
+	.copy_mem = efi_copy_mem,
+	.set_mem = efi_set_mem,
+};
+
+
+static uint16_t EFI_RUNTIME_DATA firmware_vendor[] =
+	{ 'D','a','s',' ','U','-','b','o','o','t',0 };
+
+struct efi_system_table EFI_RUNTIME_DATA systab = {
+	.hdr = {
+		.signature = EFI_SYSTEM_TABLE_SIGNATURE,
+		.revision = 0x20005, /* 2.5 */
+		.headersize = sizeof(struct efi_table_hdr),
+	},
+	.fw_vendor = (long)firmware_vendor,
+	.con_in = (void*)&efi_con_in,
+	.con_out = (void*)&efi_con_out,
+	.std_err = (void*)&efi_con_out,
+	.runtime = (void*)&efi_runtime_services,
+	.boottime = (void*)&efi_boot_services,
+	.nr_tables = 0,
+	.tables = (void*)efi_conf_table,
+};
diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c
new file mode 100644
index 0000000..2e0228c
--- /dev/null
+++ b/lib/efi_loader/efi_console.c
@@ -0,0 +1,360 @@
+/*
+ *  EFI application console interface
+ *
+ *  Copyright (c) 2016 Alexander Graf
+ *
+ *  SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <efi_loader.h>
+
+/* If we can't determine the console size, default to 80x24 */
+static int console_columns = 80;
+static int console_rows = 24;
+static bool console_size_queried;
+
+const efi_guid_t efi_guid_console_control = CONSOLE_CONTROL_GUID;
+
+#define cESC '\x1b'
+#define ESC "\x1b"
+
+static efi_status_t EFIAPI efi_cin_get_mode(
+			struct efi_console_control_protocol *this,
+			int *mode, char *uga_exists, char *std_in_locked)
+{
+	EFI_ENTRY("%p, %p, %p, %p", this, mode, uga_exists, std_in_locked);
+
+	if (mode)
+		*mode = EFI_CONSOLE_MODE_TEXT;
+	if (uga_exists)
+		*uga_exists = 0;
+	if (std_in_locked)
+		*std_in_locked = 0;
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_cin_set_mode(
+			struct efi_console_control_protocol *this, int mode)
+{
+	EFI_ENTRY("%p, %d", this, mode);
+	return EFI_EXIT(EFI_UNSUPPORTED);
+}
+
+static efi_status_t EFIAPI efi_cin_lock_std_in(
+			struct efi_console_control_protocol *this,
+			uint16_t *password)
+{
+	EFI_ENTRY("%p, %p", this, password);
+	return EFI_EXIT(EFI_UNSUPPORTED);
+}
+
+const struct efi_console_control_protocol efi_console_control = {
+	.get_mode = efi_cin_get_mode,
+	.set_mode = efi_cin_set_mode,
+	.lock_std_in = efi_cin_lock_std_in,
+};
+
+static struct simple_text_output_mode efi_con_mode = {
+	.max_mode = 0,
+	.mode = 0,
+	.attribute = 0,
+	.cursor_column = 0,
+	.cursor_row = 0,
+	.cursor_visible = 1,
+};
+
+static int term_read_reply(int *n, int maxnum, char end_char)
+{
+	char c;
+	int i = 0;
+
+	c = getc();
+	if (c != cESC)
+		return -1;
+	c = getc();
+	if (c != '[')
+		return -1;
+
+	n[0] = 0;
+	while (1) {
+		c = getc();
+		if (c == ';') {
+			i++;
+			if (i >= maxnum)
+				return -1;
+			n[i] = 0;
+			continue;
+		} else if (c == end_char) {
+			break;
+		} else if (c > '9' || c < '0') {
+			return -1;
+		}
+
+		/* Read one more decimal position */
+		n[i] *= 10;
+		n[i] += c - '0';
+	}
+
+	return 0;
+}
+
+static efi_status_t EFIAPI efi_cout_reset(
+			struct efi_simple_text_output_protocol *this,
+			char extended_verification)
+{
+	EFI_ENTRY("%p, %d", this, extended_verification);
+	return EFI_EXIT(EFI_UNSUPPORTED);
+}
+
+static void print_unicode_in_utf8(u16 c)
+{
+	char utf8[4] = { 0 };
+	char *b = utf8;
+
+	if (c < 0x80) {
+		*(b++) = c;
+	} else if (c < 0x800) {
+		*(b++) = 192 + c / 64;
+		*(b++) = 128 + c % 64;
+	} else {
+		*(b++) = 224 + c / 4096;
+		*(b++) = 128 + c / 64 % 64;
+		*(b++) = 128 + c % 64;
+	}
+
+	puts(utf8);
+}
+
+static efi_status_t EFIAPI efi_cout_output_string(
+			struct efi_simple_text_output_protocol *this,
+			const unsigned short *string)
+{
+	u16 ch;
+
+	EFI_ENTRY("%p, %p", this, string);
+	for (;(ch = *string); string++) {
+		print_unicode_in_utf8(ch);
+		efi_con_mode.cursor_column++;
+		if (ch == '\n') {
+			efi_con_mode.cursor_column = 1;
+			efi_con_mode.cursor_row++;
+		} else if (efi_con_mode.cursor_column > console_columns) {
+			efi_con_mode.cursor_column = 1;
+			efi_con_mode.cursor_row++;
+		}
+		if (efi_con_mode.cursor_row > console_rows) {
+			efi_con_mode.cursor_row = console_rows;
+		}
+	}
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_cout_test_string(
+			struct efi_simple_text_output_protocol *this,
+			const unsigned short *string)
+{
+	EFI_ENTRY("%p, %p", this, string);
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_cout_query_mode(
+			struct efi_simple_text_output_protocol *this,
+			unsigned long mode_number, unsigned long *columns,
+			unsigned long *rows)
+{
+	EFI_ENTRY("%p, %ld, %p, %p", this, mode_number, columns, rows);
+
+	if (!console_size_queried) {
+		/* Ask the terminal about its size */
+		int n[3];
+		u64 timeout;
+
+		console_size_queried = true;
+
+		/* Empty input buffer */
+		while (tstc())
+			getc();
+
+		printf(ESC"[18t");
+
+		/* Check if we have a terminal that understands */
+		timeout = timer_get_us() + 1000000;
+		while (!tstc())
+			if (timer_get_us() > timeout)
+				goto out;
+
+		/* Read {depth,rows,cols} */
+		if (term_read_reply(n, 3, 't')) {
+			goto out;
+		}
+
+		console_columns = n[2];
+		console_rows = n[1];
+	}
+
+out:
+	if (columns)
+		*columns = console_columns;
+	if (rows)
+		*rows = console_rows;
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_cout_set_mode(
+			struct efi_simple_text_output_protocol *this,
+			unsigned long mode_number)
+{
+	EFI_ENTRY("%p, %ld", this, mode_number);
+
+	/* We only support text output for now */
+	if (mode_number == EFI_CONSOLE_MODE_TEXT)
+		return EFI_EXIT(EFI_SUCCESS);
+
+	return EFI_EXIT(EFI_UNSUPPORTED);
+}
+
+static efi_status_t EFIAPI efi_cout_set_attribute(
+			struct efi_simple_text_output_protocol *this,
+			unsigned long attribute)
+{
+	EFI_ENTRY("%p, %lx", this, attribute);
+
+	/* Just ignore attributes (colors) for now */
+	return EFI_EXIT(EFI_UNSUPPORTED);
+}
+
+static efi_status_t EFIAPI efi_cout_clear_screen(
+			struct efi_simple_text_output_protocol *this)
+{
+	EFI_ENTRY("%p", this);
+
+	printf(ESC"[2J");
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_cout_set_cursor_position(
+			struct efi_simple_text_output_protocol *this,
+			unsigned long column, unsigned long row)
+{
+	EFI_ENTRY("%p, %ld, %ld", this, column, row);
+
+	printf(ESC"[%d;%df", (int)row, (int)column);
+	efi_con_mode.cursor_column = column;
+	efi_con_mode.cursor_row = row;
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_cout_enable_cursor(
+			struct efi_simple_text_output_protocol *this,
+			bool enable)
+{
+	EFI_ENTRY("%p, %d", this, enable);
+
+	printf(ESC"[?25%c", enable ? 'h' : 'l');
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+const struct efi_simple_text_output_protocol efi_con_out = {
+	.reset = efi_cout_reset,
+	.output_string = efi_cout_output_string,
+	.test_string = efi_cout_test_string,
+	.query_mode = efi_cout_query_mode,
+	.set_mode = efi_cout_set_mode,
+	.set_attribute = efi_cout_set_attribute,
+	.clear_screen = efi_cout_clear_screen,
+	.set_cursor_position = efi_cout_set_cursor_position,
+	.enable_cursor = efi_cout_enable_cursor,
+	.mode = (void*)&efi_con_mode,
+};
+
+static efi_status_t EFIAPI efi_cin_reset(
+			struct efi_simple_input_interface *this,
+			bool extended_verification)
+{
+	EFI_ENTRY("%p, %d", this, extended_verification);
+	return EFI_EXIT(EFI_UNSUPPORTED);
+}
+
+static efi_status_t EFIAPI efi_cin_read_key_stroke(
+			struct efi_simple_input_interface *this,
+			struct efi_input_key *key)
+{
+	struct efi_input_key pressed_key = {
+		.scan_code = 0,
+		.unicode_char = 0,
+	};
+	char ch;
+
+	EFI_ENTRY("%p, %p", this, key);
+
+	/* We don't do interrupts, so check for timers cooperatively */
+	efi_timer_check();
+
+	if (!tstc()) {
+		/* No key pressed */
+		return EFI_EXIT(EFI_NOT_READY);
+	}
+
+	ch = getc();
+	if (ch == cESC) {
+		/* Escape Sequence */
+		ch = getc();
+		switch (ch) {
+		case cESC: /* ESC */
+			pressed_key.scan_code = 23;
+			break;
+		case 'O': /* F1 - F4 */
+			pressed_key.scan_code = getc() - 'P' + 11;
+			break;
+		case 'a'...'z':
+			ch = ch - 'a';
+			break;
+		case '[':
+			ch = getc();
+			switch (ch) {
+			case 'A'...'D': /* up, down right, left */
+				pressed_key.scan_code = ch - 'A' + 1;
+				break;
+			case 'F': /* End */
+				pressed_key.scan_code = 6;
+				break;
+			case 'H': /* Home */
+				pressed_key.scan_code = 5;
+				break;
+			case '1': /* F5 - F8 */
+				pressed_key.scan_code = getc() - '0' + 11;
+				getc();
+				break;
+			case '2': /* F9 - F12 */
+				pressed_key.scan_code = getc() - '0' + 19;
+				getc();
+				break;
+			case '3': /* DEL */
+				pressed_key.scan_code = 8;
+				getc();
+				break;
+			}
+			break;
+		}
+	} else if (ch == 0x7f) {
+		/* Backspace */
+		ch = 0x08;
+	}
+	pressed_key.unicode_char = ch;
+	*key = pressed_key;
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+const struct efi_simple_input_interface efi_con_in = {
+	.reset = efi_cin_reset,
+	.read_key_stroke = efi_cin_read_key_stroke,
+	.wait_for_key = NULL,
+};
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
new file mode 100644
index 0000000..aaff947
--- /dev/null
+++ b/lib/efi_loader/efi_disk.c
@@ -0,0 +1,212 @@
+/*
+ *  EFI application disk support
+ *
+ *  Copyright (c) 2016 Alexander Graf
+ *
+ *  SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <efi_loader.h>
+#include <inttypes.h>
+#include <part.h>
+#include <malloc.h>
+
+static const efi_guid_t efi_block_io_guid = BLOCK_IO_GUID;
+
+struct efi_disk_obj {
+	/* Generic EFI object parent class data */
+	struct efi_object parent;
+	/* EFI Interface callback struct for block I/O */
+	struct efi_block_io ops;
+	/* U-Boot ifname for block device */
+	const char *ifname;
+	/* U-Boot dev_index for block device */
+	int dev_index;
+	/* EFI Interface Media descriptor struct, referenced by ops */
+	struct efi_block_io_media media;
+	/* EFI device path to this block device */
+	struct efi_device_path_file_path *dp;
+};
+
+static efi_status_t efi_disk_open_block(void *handle, efi_guid_t *protocol,
+			void **protocol_interface, void *agent_handle,
+			void *controller_handle, uint32_t attributes)
+{
+	struct efi_disk_obj *diskobj = handle;
+
+	*protocol_interface = &diskobj->ops;
+
+	return EFI_SUCCESS;
+}
+
+static efi_status_t efi_disk_open_dp(void *handle, efi_guid_t *protocol,
+			void **protocol_interface, void *agent_handle,
+			void *controller_handle, uint32_t attributes)
+{
+	struct efi_disk_obj *diskobj = handle;
+
+	*protocol_interface = diskobj->dp;
+
+	return EFI_SUCCESS;
+}
+
+static efi_status_t EFIAPI efi_disk_reset(struct efi_block_io *this,
+			char extended_verification)
+{
+	EFI_ENTRY("%p, %x", this, extended_verification);
+	return EFI_EXIT(EFI_DEVICE_ERROR);
+}
+
+enum efi_disk_direction {
+	EFI_DISK_READ,
+	EFI_DISK_WRITE,
+};
+
+static efi_status_t EFIAPI efi_disk_rw_blocks(struct efi_block_io *this,
+			u32 media_id, u64 lba, unsigned long buffer_size,
+			void *buffer, enum efi_disk_direction direction)
+{
+	struct efi_disk_obj *diskobj;
+	struct blk_desc *desc;
+	int blksz;
+	int blocks;
+	unsigned long n;
+
+	EFI_ENTRY("%p, %x, %"PRIx64", %lx, %p", this, media_id, lba,
+		  buffer_size, buffer);
+
+	diskobj = container_of(this, struct efi_disk_obj, ops);
+	if (!(desc = blk_get_dev(diskobj->ifname, diskobj->dev_index)))
+		return EFI_EXIT(EFI_DEVICE_ERROR);
+	blksz = desc->blksz;
+	blocks = buffer_size / blksz;
+
+#ifdef DEBUG_EFI
+	printf("EFI: %s:%d blocks=%x lba=%"PRIx64" blksz=%x dir=%d\n", __func__,
+	       __LINE__, blocks, lba, blksz, direction);
+#endif
+
+	/* We only support full block access */
+	if (buffer_size & (blksz - 1))
+		return EFI_EXIT(EFI_DEVICE_ERROR);
+
+	if (direction == EFI_DISK_READ)
+		n = desc->block_read(desc, lba, blocks, buffer);
+	else
+		n = desc->block_write(desc, lba, blocks, buffer);
+
+	/* We don't do interrupts, so check for timers cooperatively */
+	efi_timer_check();
+
+#ifdef DEBUG_EFI
+	printf("EFI: %s:%d n=%lx blocks=%x\n", __func__, __LINE__, n, blocks);
+#endif
+	if (n != blocks)
+		return EFI_EXIT(EFI_DEVICE_ERROR);
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t efi_disk_read_blocks(struct efi_block_io *this,
+			u32 media_id, u64 lba, unsigned long buffer_size,
+			void *buffer)
+{
+	return efi_disk_rw_blocks(this, media_id, lba, buffer_size, buffer,
+				  EFI_DISK_READ);
+}
+
+static efi_status_t efi_disk_write_blocks(struct efi_block_io *this,
+			u32 media_id, u64 lba, unsigned long buffer_size,
+			void *buffer)
+{
+	return efi_disk_rw_blocks(this, media_id, lba, buffer_size, buffer,
+				  EFI_DISK_WRITE);
+}
+
+static efi_status_t EFIAPI efi_disk_flush_blocks(struct efi_block_io *this)
+{
+	/* We always write synchronously */
+	EFI_ENTRY("%p", this);
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static const struct efi_block_io block_io_disk_template = {
+	.reset = &efi_disk_reset,
+	.read_blocks = &efi_disk_read_blocks,
+	.write_blocks = &efi_disk_write_blocks,
+	.flush_blocks = &efi_disk_flush_blocks,
+};
+
+/*
+ * U-Boot doesn't have a list of all online disk devices. So when running our
+ * EFI payload, we scan through all of the potentially available ones and
+ * store them in our object pool.
+ *
+ * This gets called from do_bootefi_exec().
+ */
+int efi_disk_register(void)
+{
+	const struct block_drvr *cur_drvr;
+	int i;
+	int disks = 0;
+
+	/* Search for all available disk devices */
+	for (cur_drvr = block_drvr; cur_drvr->name; cur_drvr++) {
+		printf("Scanning disks on %s...\n", cur_drvr->name);
+		for (i = 0; i < 4; i++) {
+			struct blk_desc *desc;
+			struct efi_disk_obj *diskobj;
+			struct efi_device_path_file_path *dp;
+			int objlen = sizeof(*diskobj) + (sizeof(*dp) * 2);
+			char devname[16] = { 0 }; /* dp->str is u16[16] long */
+
+			desc = blk_get_dev(cur_drvr->name, i);
+			if (!desc)
+				continue;
+			if (desc->type == DEV_TYPE_UNKNOWN)
+				continue;
+
+			diskobj = calloc(1, objlen);
+
+			/* Fill in object data */
+			diskobj->parent.protocols[0].guid = &efi_block_io_guid;
+			diskobj->parent.protocols[0].open = efi_disk_open_block;
+			diskobj->parent.protocols[1].guid = &efi_guid_device_path;
+			diskobj->parent.protocols[1].open = efi_disk_open_dp;
+			diskobj->parent.handle = diskobj;
+			diskobj->ops = block_io_disk_template;
+			diskobj->ifname = cur_drvr->name;
+			diskobj->dev_index = i;
+
+			/* Fill in EFI IO Media info (for read/write callbacks) */
+			diskobj->media.removable_media = desc->removable;
+			diskobj->media.media_present = 1;
+			diskobj->media.block_size = desc->blksz;
+			diskobj->media.io_align = desc->blksz;
+			diskobj->media.last_block = desc->lba;
+			diskobj->ops.media = &diskobj->media;
+
+			/* Fill in device path */
+			dp = (void*)&diskobj[1];
+			diskobj->dp = dp;
+			dp[0].dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE;
+			dp[0].dp.sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH;
+			dp[0].dp.length = sizeof(*dp);
+			snprintf(devname, sizeof(devname), "%s%d",
+				 cur_drvr->name, i);
+			ascii2unicode(dp[0].str, devname);
+
+			dp[1].dp.type = DEVICE_PATH_TYPE_END;
+			dp[1].dp.sub_type = DEVICE_PATH_SUB_TYPE_END;
+			dp[1].dp.length = sizeof(*dp);
+
+			/* Hook up to the device list */
+			list_add_tail(&diskobj->parent.link, &efi_obj_list);
+			disks++;
+		}
+	}
+	printf("Found %d disks\n", disks);
+
+	return 0;
+}
diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c
new file mode 100644
index 0000000..d558f5a
--- /dev/null
+++ b/lib/efi_loader/efi_image_loader.c
@@ -0,0 +1,188 @@
+/*
+ *  EFI image loader
+ *
+ *  based partly on wine code
+ *
+ *  Copyright (c) 2016 Alexander Graf
+ *
+ *  SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <efi_loader.h>
+#include <pe.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const efi_guid_t efi_guid_device_path = DEVICE_PATH_GUID;
+const efi_guid_t efi_guid_loaded_image = LOADED_IMAGE_GUID;
+
+efi_status_t EFIAPI efi_return_handle(void *handle, efi_guid_t *protocol,
+			void **protocol_interface, void *agent_handle,
+			void *controller_handle, uint32_t attributes)
+{
+	EFI_ENTRY("%p, %p, %p, %p, %p, 0x%x", handle, protocol,
+		  protocol_interface, agent_handle, controller_handle,
+		  attributes);
+	*protocol_interface = handle;
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static void efi_loader_relocate(const IMAGE_BASE_RELOCATION *rel,
+			unsigned long rel_size, void *efi_reloc)
+{
+	const IMAGE_BASE_RELOCATION *end;
+	int i;
+
+	end = (const IMAGE_BASE_RELOCATION *)((const char *)rel + rel_size);
+	while (rel < end - 1 && rel->SizeOfBlock) {
+		const uint16_t *relocs = (const uint16_t *)(rel + 1);
+		i = (rel->SizeOfBlock - sizeof(*rel)) / sizeof(uint16_t);
+		while (i--) {
+			uint16_t offset = (*relocs & 0xfff) +
+					  rel->VirtualAddress;
+			int type = *relocs >> EFI_PAGE_SHIFT;
+			unsigned long delta = (unsigned long)efi_reloc;
+			uint64_t *x64 = efi_reloc + offset;
+			uint32_t *x32 = efi_reloc + offset;
+			uint16_t *x16 = efi_reloc + offset;
+
+			switch (type) {
+			case IMAGE_REL_BASED_ABSOLUTE:
+				break;
+			case IMAGE_REL_BASED_HIGH:
+				*x16 += ((uint32_t)delta) >> 16;
+				break;
+			case IMAGE_REL_BASED_LOW:
+				*x16 += (uint16_t)delta;
+				break;
+			case IMAGE_REL_BASED_HIGHLOW:
+				*x32 += (uint32_t)delta;
+				break;
+			case IMAGE_REL_BASED_DIR64:
+				*x64 += (uint64_t)delta;
+				break;
+			default:
+				printf("Unknown Relocation off %x type %x\n",
+				       offset, type);
+			}
+			relocs++;
+		}
+		rel = (const IMAGE_BASE_RELOCATION *)relocs;
+	}
+}
+
+void __weak invalidate_icache_all(void)
+{
+	/* If the system doesn't support icache_all flush, cross our fingers */
+}
+
+/*
+ * This function loads all sections from a PE binary into a newly reserved
+ * piece of memory. On successful load it then returns the entry point for
+ * the binary. Otherwise NULL.
+ */
+void *efi_load_pe(void *efi, struct efi_loaded_image *loaded_image_info)
+{
+	IMAGE_NT_HEADERS32 *nt;
+	IMAGE_DOS_HEADER *dos;
+	IMAGE_SECTION_HEADER *sections;
+	int num_sections;
+	void *efi_reloc;
+	int i;
+	const IMAGE_BASE_RELOCATION *rel;
+	unsigned long rel_size;
+	int rel_idx = IMAGE_DIRECTORY_ENTRY_BASERELOC;
+	void *entry;
+	uint64_t image_size;
+	unsigned long virt_size = 0;
+	bool can_run_nt64 = true;
+	bool can_run_nt32 = true;
+
+#if defined(CONFIG_ARM64)
+	can_run_nt32 = false;
+#elif defined(CONFIG_ARM)
+	can_run_nt64 = false;
+#endif
+
+	dos = efi;
+	if (dos->e_magic != IMAGE_DOS_SIGNATURE) {
+		printf("%s: Invalid DOS Signature\n", __func__);
+		return NULL;
+	}
+
+	nt = (void *) ((char *)efi + dos->e_lfanew);
+	if (nt->Signature != IMAGE_NT_SIGNATURE) {
+		printf("%s: Invalid NT Signature\n", __func__);
+		return NULL;
+	}
+
+	/* Calculate upper virtual address boundary */
+	num_sections = nt->FileHeader.NumberOfSections;
+	sections = (void *)&nt->OptionalHeader +
+			    nt->FileHeader.SizeOfOptionalHeader;
+
+	for (i = num_sections - 1; i >= 0; i--) {
+		IMAGE_SECTION_HEADER *sec = &sections[i];
+		virt_size = max_t(unsigned long, virt_size,
+				  sec->VirtualAddress + sec->Misc.VirtualSize);
+	}
+
+	/* Read 32/64bit specific header bits */
+	if (can_run_nt64 &&
+	    (nt->OptionalHeader.Magic == IMAGE_NT_OPTIONAL_HDR64_MAGIC)) {
+		IMAGE_NT_HEADERS64 *nt64 = (void *)nt;
+		IMAGE_OPTIONAL_HEADER64 *opt = &nt64->OptionalHeader;
+		image_size = opt->SizeOfImage;
+		efi_reloc = efi_alloc(virt_size, EFI_LOADER_DATA);
+		if (!efi_reloc) {
+			printf("%s: Could not allocate %ld bytes\n",
+				__func__, virt_size);
+			return NULL;
+		}
+		entry = efi_reloc + opt->AddressOfEntryPoint;
+		rel_size = opt->DataDirectory[rel_idx].Size;
+		rel = efi_reloc + opt->DataDirectory[rel_idx].VirtualAddress;
+	} else if (can_run_nt32 &&
+		   (nt->OptionalHeader.Magic == IMAGE_NT_OPTIONAL_HDR32_MAGIC)) {
+		IMAGE_OPTIONAL_HEADER32 *opt = &nt->OptionalHeader;
+		image_size = opt->SizeOfImage;
+		efi_reloc = efi_alloc(virt_size, EFI_LOADER_DATA);
+		if (!efi_reloc) {
+			printf("%s: Could not allocate %ld bytes\n",
+				__func__, virt_size);
+			return NULL;
+		}
+		entry = efi_reloc + opt->AddressOfEntryPoint;
+		rel_size = opt->DataDirectory[rel_idx].Size;
+		rel = efi_reloc + opt->DataDirectory[rel_idx].VirtualAddress;
+	} else {
+		printf("%s: Invalid optional header magic %x\n", __func__,
+		       nt->OptionalHeader.Magic);
+		return NULL;
+	}
+
+	/* Load sections into RAM */
+	for (i = num_sections - 1; i >= 0; i--) {
+		IMAGE_SECTION_HEADER *sec = &sections[i];
+		memset(efi_reloc + sec->VirtualAddress, 0,
+		       sec->Misc.VirtualSize);
+		memcpy(efi_reloc + sec->VirtualAddress,
+		       efi + sec->PointerToRawData,
+		       sec->SizeOfRawData);
+	}
+
+	/* Run through relocations */
+	efi_loader_relocate(rel, rel_size, efi_reloc);
+
+	/* Flush cache */
+	flush_cache((ulong)efi_reloc, virt_size);
+	invalidate_icache_all();
+
+	/* Populate the loaded image interface bits */
+	loaded_image_info->image_base = efi;
+	loaded_image_info->image_size = image_size;
+
+	return entry;
+}
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
new file mode 100644
index 0000000..c82b53f
--- /dev/null
+++ b/lib/efi_loader/efi_memory.c
@@ -0,0 +1,319 @@
+/*
+ *  EFI application memory management
+ *
+ *  Copyright (c) 2016 Alexander Graf
+ *
+ *  SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* #define DEBUG_EFI */
+
+#include <common.h>
+#include <efi_loader.h>
+#include <malloc.h>
+#include <asm/global_data.h>
+#include <libfdt_env.h>
+#include <inttypes.h>
+#include <watchdog.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct efi_mem_list {
+	struct list_head link;
+	struct efi_mem_desc desc;
+};
+
+/* This list contains all memory map items */
+LIST_HEAD(efi_mem);
+
+/*
+ * Unmaps all memory occupied by the carve_desc region from the
+ * list entry pointed to by map.
+ *
+ * Returns 1 if carving was performed or 0 if the regions don't overlap.
+ * Returns -1 if it would affect non-RAM regions but overlap_only_ram is set.
+ * Carving is only guaranteed to complete when all regions return 0.
+ */
+static int efi_mem_carve_out(struct efi_mem_list *map,
+			     struct efi_mem_desc *carve_desc,
+			     bool overlap_only_ram)
+{
+	struct efi_mem_list *newmap;
+	struct efi_mem_desc *map_desc = &map->desc;
+	uint64_t map_start = map_desc->physical_start;
+	uint64_t map_end = map_start + (map_desc->num_pages << EFI_PAGE_SHIFT);
+	uint64_t carve_start = carve_desc->physical_start;
+	uint64_t carve_end = carve_start +
+			     (carve_desc->num_pages << EFI_PAGE_SHIFT);
+
+	/* check whether we're overlapping */
+	if ((carve_end <= map_start) || (carve_start >= map_end))
+		return 0;
+
+	/* We're overlapping with non-RAM, warn the caller if desired */
+	if (overlap_only_ram && (map_desc->type != EFI_CONVENTIONAL_MEMORY))
+		return -1;
+
+	/* Sanitize carve_start and carve_end to lie within our bounds */
+	carve_start = max(carve_start, map_start);
+	carve_end = min(carve_end, map_end);
+
+	/* Carving at the beginning of our map? Just move it! */
+	if (carve_start == map_start) {
+		if (map_end == carve_end) {
+			/* Full overlap, just remove map */
+			list_del(&map->link);
+		}
+
+		map_desc->physical_start = carve_end;
+		map_desc->num_pages = (map_end - carve_end) >> EFI_PAGE_SHIFT;
+		return 1;
+	}
+
+	/*
+	 * Overlapping maps, just split the list map at carve_start,
+	 * it will get moved or removed in the next iteration.
+	 *
+	 * [ map_desc |__carve_start__| newmap ]
+	 */
+
+	/* Create a new map from [ carve_start ... map_end ] */
+	newmap = calloc(1, sizeof(*newmap));
+	newmap->desc = map->desc;
+	newmap->desc.physical_start = carve_start;
+	newmap->desc.num_pages = (map_end - carve_start) >> EFI_PAGE_SHIFT;
+        list_add_tail(&newmap->link, &efi_mem);
+
+	/* Shrink the map to [ map_start ... carve_start ] */
+	map_desc->num_pages = (carve_start - map_start) >> EFI_PAGE_SHIFT;
+
+	return 1;
+}
+
+uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
+			    bool overlap_only_ram)
+{
+	struct list_head *lhandle;
+	struct efi_mem_list *newlist;
+	bool do_carving;
+
+	if (!pages)
+		return start;
+
+	newlist = calloc(1, sizeof(*newlist));
+	newlist->desc.type = memory_type;
+	newlist->desc.physical_start = start;
+	newlist->desc.virtual_start = start;
+	newlist->desc.num_pages = pages;
+
+	switch (memory_type) {
+	case EFI_RUNTIME_SERVICES_CODE:
+	case EFI_RUNTIME_SERVICES_DATA:
+		newlist->desc.attribute = (1 << EFI_MEMORY_WB_SHIFT) |
+					  (1ULL << EFI_MEMORY_RUNTIME_SHIFT);
+		break;
+	case EFI_MMAP_IO:
+		newlist->desc.attribute = 1ULL << EFI_MEMORY_RUNTIME_SHIFT;
+		break;
+	default:
+		newlist->desc.attribute = 1 << EFI_MEMORY_WB_SHIFT;
+		break;
+	}
+
+	/* Add our new map */
+	do {
+		do_carving = false;
+		list_for_each(lhandle, &efi_mem) {
+			struct efi_mem_list *lmem;
+			int r;
+
+			lmem = list_entry(lhandle, struct efi_mem_list, link);
+			r = efi_mem_carve_out(lmem, &newlist->desc,
+					      overlap_only_ram);
+			if (r < 0) {
+				return 0;
+			} else if (r) {
+				do_carving = true;
+				break;
+			}
+		}
+	} while (do_carving);
+
+	/* Add our new map */
+        list_add_tail(&newlist->link, &efi_mem);
+
+	return start;
+}
+
+static uint64_t efi_find_free_memory(uint64_t len, uint64_t max_addr)
+{
+	struct list_head *lhandle;
+
+	list_for_each(lhandle, &efi_mem) {
+		struct efi_mem_list *lmem = list_entry(lhandle,
+			struct efi_mem_list, link);
+		struct efi_mem_desc *desc = &lmem->desc;
+		uint64_t desc_len = desc->num_pages << EFI_PAGE_SHIFT;
+		uint64_t desc_end = desc->physical_start + desc_len;
+		uint64_t curmax = min(max_addr, desc_end);
+		uint64_t ret = curmax - len;
+
+		/* We only take memory from free RAM */
+		if (desc->type != EFI_CONVENTIONAL_MEMORY)
+			continue;
+
+		/* Out of bounds for max_addr */
+		if ((ret + len) > max_addr)
+			continue;
+
+		/* Out of bounds for upper map limit */
+		if ((ret + len) > desc_end)
+			continue;
+
+		/* Out of bounds for lower map limit */
+		if (ret < desc->physical_start)
+			continue;
+
+		/* Return the highest address in this map within bounds */
+		return ret;
+	}
+
+	return 0;
+}
+
+efi_status_t efi_allocate_pages(int type, int memory_type,
+				unsigned long pages, uint64_t *memory)
+{
+	u64 len = pages << EFI_PAGE_SHIFT;
+	efi_status_t r = EFI_SUCCESS;
+	uint64_t addr;
+
+	switch (type) {
+	case 0:
+		/* Any page */
+		addr = efi_find_free_memory(len, gd->ram_top);
+		if (!addr) {
+			r = EFI_NOT_FOUND;
+			break;
+		}
+		break;
+	case 1:
+		/* Max address */
+		addr = efi_find_free_memory(len, *memory);
+		if (!addr) {
+			r = EFI_NOT_FOUND;
+			break;
+		}
+		break;
+	case 2:
+		/* Exact address, reserve it. The addr is already in *memory. */
+		addr = *memory;
+		break;
+	default:
+		/* UEFI doesn't specify other allocation types */
+		r = EFI_INVALID_PARAMETER;
+		break;
+	}
+
+	if (r == EFI_SUCCESS) {
+		uint64_t ret;
+
+		/* Reserve that map in our memory maps */
+		ret = efi_add_memory_map(addr, pages, memory_type, true);
+		if (ret == addr) {
+			*memory = addr;
+		} else {
+			/* Map would overlap, bail out */
+			r = EFI_OUT_OF_RESOURCES;
+		}
+	}
+
+	return r;
+}
+
+void *efi_alloc(uint64_t len, int memory_type)
+{
+	uint64_t ret = 0;
+	uint64_t pages = (len + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
+	efi_status_t r;
+
+	r = efi_allocate_pages(0, memory_type, pages, &ret);
+	if (r == EFI_SUCCESS)
+		return (void*)(uintptr_t)ret;
+
+	return NULL;
+}
+
+efi_status_t efi_free_pages(uint64_t memory, unsigned long pages)
+{
+	/* We don't free, let's cross our fingers we have plenty RAM */
+	return EFI_SUCCESS;
+}
+
+efi_status_t efi_get_memory_map(unsigned long *memory_map_size,
+			       struct efi_mem_desc *memory_map,
+			       unsigned long *map_key,
+			       unsigned long *descriptor_size,
+			       uint32_t *descriptor_version)
+{
+	ulong map_size = 0;
+	struct list_head *lhandle;
+
+	list_for_each(lhandle, &efi_mem)
+		map_size += sizeof(struct efi_mem_desc);
+
+	*memory_map_size = map_size;
+
+	if (descriptor_size)
+		*descriptor_size = sizeof(struct efi_mem_desc);
+
+	if (*memory_map_size < map_size)
+		return EFI_BUFFER_TOO_SMALL;
+
+	/* Copy list into array */
+	if (memory_map) {
+		list_for_each(lhandle, &efi_mem) {
+			struct efi_mem_list *lmem;
+
+			lmem = list_entry(lhandle, struct efi_mem_list, link);
+			*memory_map = lmem->desc;
+			memory_map++;
+		}
+	}
+
+	return EFI_SUCCESS;
+}
+
+int efi_memory_init(void)
+{
+	uint64_t runtime_start, runtime_end, runtime_pages;
+	uint64_t uboot_start, uboot_pages;
+	uint64_t uboot_stack_size = 16 * 1024 * 1024;
+	int i;
+
+	/* Add RAM */
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		u64 ram_start = gd->bd->bi_dram[i].start;
+		u64 ram_size = gd->bd->bi_dram[i].size;
+		u64 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
+		u64 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
+
+		efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
+				   false);
+	}
+
+	/* Add U-Boot */
+	uboot_start = (gd->start_addr_sp - uboot_stack_size) & ~EFI_PAGE_MASK;
+	uboot_pages = (gd->ram_top - uboot_start) >> EFI_PAGE_SHIFT;
+	efi_add_memory_map(uboot_start, uboot_pages, EFI_LOADER_DATA, false);
+
+	/* Add Runtime Services */
+	runtime_start = (ulong)&__efi_runtime_start & ~EFI_PAGE_MASK;
+	runtime_end = (ulong)&__efi_runtime_stop;
+	runtime_end = (runtime_end + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
+	runtime_pages = (runtime_end - runtime_start) >> EFI_PAGE_SHIFT;
+	efi_add_memory_map(runtime_start, runtime_pages,
+			   EFI_RUNTIME_SERVICES_CODE, false);
+
+	return 0;
+}
diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
new file mode 100644
index 0000000..22bcd08
--- /dev/null
+++ b/lib/efi_loader/efi_runtime.c
@@ -0,0 +1,290 @@
+/*
+ *  EFI application runtime services
+ *
+ *  Copyright (c) 2016 Alexander Graf
+ *
+ *  SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <efi_loader.h>
+#include <rtc.h>
+#include <asm/global_data.h>
+
+/* For manual relocation support */
+DECLARE_GLOBAL_DATA_PTR;
+
+static efi_status_t EFI_RUNTIME_TEXT EFIAPI efi_unimplemented(void);
+static efi_status_t EFI_RUNTIME_TEXT EFIAPI efi_device_error(void);
+static efi_status_t EFI_RUNTIME_TEXT EFIAPI efi_invalid_parameter(void);
+
+#if defined(CONFIG_ARM64)
+#define R_RELATIVE	1027
+#define R_MASK		0xffffffffULL
+#define IS_RELA		1
+#elif defined(CONFIG_ARM)
+#define R_RELATIVE	23
+#define R_MASK		0xffULL
+#else
+#error Need to add relocation awareness
+#endif
+
+struct elf_rel {
+	ulong *offset;
+	ulong info;
+};
+
+struct elf_rela {
+	ulong *offset;
+	ulong info;
+	long addend;
+};
+
+/*
+ * EFI Runtime code lives in 2 stages. In the first stage, U-Boot and an EFI
+ * payload are running concurrently at the same time. In this mode, we can
+ * handle a good number of runtime callbacks
+ */
+
+static void EFIAPI efi_reset_system(enum efi_reset_type reset_type,
+				    efi_status_t reset_status,
+				    unsigned long data_size, void *reset_data)
+{
+	EFI_ENTRY("%d %lx %lx %p", reset_type, reset_status, data_size,
+		  reset_data);
+
+	switch (reset_type) {
+	case EFI_RESET_COLD:
+	case EFI_RESET_WARM:
+		do_reset(NULL, 0, 0, NULL);
+		break;
+	case EFI_RESET_SHUTDOWN:
+		/* We don't have anything to map this to */
+		break;
+	}
+
+	EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_get_time(struct efi_time *time,
+					struct efi_time_cap *capabilities)
+{
+#if defined(CONFIG_CMD_DATE) && defined(CONFIG_DM_RTC)
+	struct rtc_time tm;
+	int r;
+	struct udevice *dev;
+
+	EFI_ENTRY("%p %p", time, capabilities);
+
+	r = uclass_get_device(UCLASS_RTC, 0, &dev);
+	if (r)
+		return EFI_EXIT(EFI_DEVICE_ERROR);
+
+	r = dm_rtc_get(dev, &tm);
+	if (r)
+		return EFI_EXIT(EFI_DEVICE_ERROR);
+
+	memset(time, 0, sizeof(*time));
+	time->year = tm.tm_year;
+	time->month = tm.tm_mon;
+	time->day = tm.tm_mday;
+	time->hour = tm.tm_hour;
+	time->minute = tm.tm_min;
+	time->daylight = tm.tm_isdst;
+
+	return EFI_EXIT(EFI_SUCCESS);
+#else
+	return EFI_DEVICE_ERROR;
+#endif
+}
+
+struct efi_runtime_detach_list_struct {
+	void *ptr;
+	void *patchto;
+};
+
+static const struct efi_runtime_detach_list_struct efi_runtime_detach_list[] = {
+	{
+		/* do_reset is gone */
+		.ptr = &efi_runtime_services.reset_system,
+		.patchto = NULL,
+	}, {
+		/* invalidate_*cache_all are gone */
+		.ptr = &efi_runtime_services.set_virtual_address_map,
+		.patchto = &efi_invalid_parameter,
+	}, {
+		/* RTC accessors are gone */
+		.ptr = &efi_runtime_services.get_time,
+		.patchto = &efi_device_error,
+	},
+};
+
+static bool efi_runtime_tobedetached(void *p)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(efi_runtime_detach_list); i++)
+		if (efi_runtime_detach_list[i].ptr == p)
+			return true;
+
+	return false;
+}
+
+static void efi_runtime_detach(ulong offset)
+{
+	int i;
+	ulong patchoff = offset - (ulong)gd->relocaddr;
+
+	for (i = 0; i < ARRAY_SIZE(efi_runtime_detach_list); i++) {
+		ulong patchto = (ulong)efi_runtime_detach_list[i].patchto;
+		ulong *p = efi_runtime_detach_list[i].ptr;
+		ulong newaddr = patchto ? (patchto + patchoff) : 0;
+
+#ifdef DEBUG_EFI
+		printf("%s: Setting %p to %lx\n", __func__, p, newaddr);
+#endif
+		*p = newaddr;
+	}
+}
+
+/* Relocate EFI runtime to uboot_reloc_base = offset */
+void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map)
+{
+#ifdef IS_RELA
+	struct elf_rela *rel = (void*)&__efi_runtime_rel_start;
+#else
+	struct elf_rel *rel = (void*)&__efi_runtime_rel_start;
+	static ulong lastoff = CONFIG_SYS_TEXT_BASE;
+#endif
+
+#ifdef DEBUG_EFI
+	printf("%s: Relocating to offset=%lx\n", __func__, offset);
+#endif
+
+	for (; (ulong)rel < (ulong)&__efi_runtime_rel_stop; rel++) {
+		ulong base = CONFIG_SYS_TEXT_BASE;
+		ulong *p;
+		ulong newaddr;
+
+		p = (void*)((ulong)rel->offset - base) + gd->relocaddr;
+
+		if ((rel->info & R_MASK) != R_RELATIVE) {
+			continue;
+		}
+
+#ifdef IS_RELA
+		newaddr = rel->addend + offset - CONFIG_SYS_TEXT_BASE;
+#else
+		newaddr = *p - lastoff + offset;
+#endif
+
+		/* Check if the relocation is inside bounds */
+		if (map && ((newaddr < map->virtual_start) ||
+		    newaddr > (map->virtual_start + (map->num_pages << 12)))) {
+			if (!efi_runtime_tobedetached(p))
+				printf("U-Boot EFI: Relocation at %p is out of "
+				       "range (%lx)\n", p, newaddr);
+			continue;
+		}
+
+#ifdef DEBUG_EFI
+		printf("%s: Setting %p to %lx\n", __func__, p, newaddr);
+#endif
+
+		*p = newaddr;
+		flush_dcache_range((ulong)p, (ulong)&p[1]);
+	}
+
+#ifndef IS_RELA
+	lastoff = offset;
+#endif
+
+        invalidate_icache_all();
+}
+
+static efi_status_t EFIAPI efi_set_virtual_address_map(
+			unsigned long memory_map_size,
+			unsigned long descriptor_size,
+			uint32_t descriptor_version,
+			struct efi_mem_desc *virtmap)
+{
+	ulong runtime_start = (ulong)&__efi_runtime_start & ~0xfffULL;
+	int n = memory_map_size / descriptor_size;
+	int i;
+
+	EFI_ENTRY("%lx %lx %x %p", memory_map_size, descriptor_size,
+		  descriptor_version, virtmap);
+
+	for (i = 0; i < n; i++) {
+		struct efi_mem_desc *map;
+
+		map = (void*)virtmap + (descriptor_size * i);
+		if (map->type == EFI_RUNTIME_SERVICES_CODE) {
+			ulong new_offset = map->virtual_start - (runtime_start - gd->relocaddr);
+
+			efi_runtime_relocate(new_offset, map);
+			/* Once we're virtual, we can no longer handle
+			   complex callbacks */
+			efi_runtime_detach(new_offset);
+			return EFI_EXIT(EFI_SUCCESS);
+		}
+	}
+
+	return EFI_EXIT(EFI_INVALID_PARAMETER);
+}
+
+/*
+ * In the second stage, U-Boot has disappeared. To isolate our runtime code
+ * that at this point still exists from the rest, we put it into a special
+ * section.
+ *
+ *        !!WARNING!!
+ *
+ * This means that we can not rely on any code outside of this file in any
+ * function or variable below this line.
+ *
+ * Please keep everything fully self-contained and annotated with
+ * EFI_RUNTIME_TEXT and EFI_RUNTIME_DATA markers.
+ */
+
+/*
+ * Relocate the EFI runtime stub to a different place. We need to call this
+ * the first time we expose the runtime interface to a user and on set virtual
+ * address map calls.
+ */
+
+static efi_status_t EFI_RUNTIME_TEXT EFIAPI efi_unimplemented(void)
+{
+	return EFI_UNSUPPORTED;
+}
+
+static efi_status_t EFI_RUNTIME_TEXT EFIAPI efi_device_error(void)
+{
+	return EFI_DEVICE_ERROR;
+}
+
+static efi_status_t EFI_RUNTIME_TEXT EFIAPI efi_invalid_parameter(void)
+{
+	return EFI_INVALID_PARAMETER;
+}
+
+struct efi_runtime_services EFI_RUNTIME_DATA efi_runtime_services = {
+	.hdr = {
+		.signature = EFI_RUNTIME_SERVICES_SIGNATURE,
+		.revision = EFI_RUNTIME_SERVICES_REVISION,
+		.headersize = sizeof(struct efi_table_hdr),
+	},
+	.get_time = &efi_get_time,
+	.set_time = (void *)&efi_device_error,
+	.get_wakeup_time = (void *)&efi_unimplemented,
+	.set_wakeup_time = (void *)&efi_unimplemented,
+	.set_virtual_address_map = &efi_set_virtual_address_map,
+	.convert_pointer = (void *)&efi_invalid_parameter,
+	.get_variable = (void *)&efi_device_error,
+	.get_next_variable = (void *)&efi_device_error,
+	.set_variable = (void *)&efi_device_error,
+	.get_next_high_mono_count = (void *)&efi_device_error,
+	.reset_system = &efi_reset_system,
+};
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index b361a25..70acc29 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -57,14 +57,12 @@
 	COMPAT(SAMSUNG_EXYNOS5_I2C, "samsung,exynos5-hsi2c"),
 	COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
 	COMPAT(INTEL_MICROCODE, "intel,microcode"),
-	COMPAT(MEMORY_SPD, "memory-spd"),
 	COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"),
 	COMPAT(INTEL_MODEL_206AX, "intel,model-206ax"),
 	COMPAT(INTEL_GMA, "intel,gma"),
 	COMPAT(AMS_AS3722, "ams,as3722"),
 	COMPAT(INTEL_ICH_SPI, "intel,ich-spi"),
 	COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"),
-	COMPAT(INTEL_X86_PINCTRL, "intel,x86-pinctrl"),
 	COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"),
 	COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"),
 	COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
@@ -123,9 +121,10 @@
 
 	if (sizep) {
 		*sizep = fdtdec_get_number(prop_size, ns);
-		debug("addr=%08llx, size=%llx\n", (u64)addr, (u64)*sizep);
+		debug("addr=%08llx, size=%llx\n", (unsigned long long)addr,
+		      (unsigned long long)*sizep);
 	} else {
-		debug("addr=%08llx\n", (u64)addr);
+		debug("addr=%08llx\n", (unsigned long long)addr);
 	}
 
 	return addr;
diff --git a/lib/gunzip.c b/lib/gunzip.c
index da0c76c..6d65ccc 100644
--- a/lib/gunzip.c
+++ b/lib/gunzip.c
@@ -105,7 +105,7 @@
 }
 
 int gzwrite(unsigned char *src, int len,
-	    struct block_dev_desc *dev,
+	    struct blk_desc *dev,
 	    unsigned long szwritebuf,
 	    u64 startoffs,
 	    u64 szexpected)
diff --git a/lib/libfdt/fdt_sw.c b/lib/libfdt/fdt_sw.c
index 320a914..345a3ac 100644
--- a/lib/libfdt/fdt_sw.c
+++ b/lib/libfdt/fdt_sw.c
@@ -175,7 +175,7 @@
 	return offset;
 }
 
-int fdt_property(void *fdt, const char *name, const void *val, int len)
+int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp)
 {
 	struct fdt_property *prop;
 	int nameoff;
@@ -193,7 +193,19 @@
 	prop->tag = cpu_to_fdt32(FDT_PROP);
 	prop->nameoff = cpu_to_fdt32(nameoff);
 	prop->len = cpu_to_fdt32(len);
-	memcpy(prop->data, val, len);
+	*valp = prop->data;
+	return 0;
+}
+
+int fdt_property(void *fdt, const char *name, const void *val, int len)
+{
+	void *ptr;
+	int ret;
+
+	ret = fdt_property_placeholder(fdt, name, len, &ptr);
+	if (ret)
+		return ret;
+	memcpy(ptr, val, len);
 	return 0;
 }
 
diff --git a/lib/rsa/Kconfig b/lib/rsa/Kconfig
index 1268a1b..86df0a0 100644
--- a/lib/rsa/Kconfig
+++ b/lib/rsa/Kconfig
@@ -6,6 +6,12 @@
 	  RSA support. This enables the RSA algorithm used for FIT image
 	  verification in U-Boot.
 	  See doc/uImage.FIT/signature.txt for more details.
+	  The Modular Exponentiation algorithm in RSA is implemented using
+	  driver model. So CONFIG_DM needs to be enabled by default for this
+	  library to function.
+	  The signing part is build into mkimage regardless of this
+	  option. The software based modular exponentiation is built into
+	  mkimage irrespective of this option.
 
 if RSA
 config RSA_SOFTWARE_EXP
diff --git a/lib/tpm.c b/lib/tpm.c
index f428d45..88f2406 100644
--- a/lib/tpm.c
+++ b/lib/tpm.c
@@ -242,7 +242,7 @@
 		response_length = sizeof(response_buffer);
 	}
 
-	ret = uclass_first_device(UCLASS_TPM, &dev);
+	ret = uclass_first_device_err(UCLASS_TPM, &dev);
 	if (ret)
 		return ret;
 	err = tpm_xfer(dev, command, tpm_command_size(command),
@@ -261,8 +261,8 @@
 	int err;
 	struct udevice *dev;
 
-	err = uclass_first_device(UCLASS_TPM, &dev);
-	if (err || !dev)
+	err = uclass_first_device_err(UCLASS_TPM, &dev);
+	if (err)
 		return err;
 	return tpm_open(dev);
 }
diff --git a/scripts/coreboot.sed b/scripts/coreboot.sed
new file mode 100644
index 0000000..42e1f3a
--- /dev/null
+++ b/scripts/coreboot.sed
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Script to convert coreboot code to something similar to what U-Boot uses
+# sed -f coreboot.sed <coreboot_file.c>
+# Remember to add attribution to coreboot for new files added to U-Boot.
+s/REG_RES_WRITE32(\(.*\), \(.*\), \(.*\)),/writel(\3, base + \2);/
+s/REG_RES_POLL32(\(.*\), \(.*\), \(.*\), \(.*\), \(.*\)),/ret = poll32(base + \2, \3, \4, \5);/
+s/REG_RES_OR32(\(.*\), \(.*\), \(.*\)),/setbits_le32(base + \2, \3);/
+s/REG_RES_RMW32(\(.*\), \(.*\), \(.*\), \(.*\)),/clrsetbits_le32(base + \2, ~\3, \4);/
+/REG_SCRIPT_END/d
+s/read32/readl/
+s/write32(\(.*\), \(.*\))/writel(\2, \1)/
+s/conf->/plat->/
+s/static const struct reg_script \(.*\)_script\[\] = {/static int \1(struct udevice *dev)/
diff --git a/test/dm/Makefile b/test/dm/Makefile
index fd0198f..df2d71f 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -15,6 +15,7 @@
 # subsystem you must add sandbox tests here.
 obj-$(CONFIG_UT_DM) += core.o
 ifneq ($(CONFIG_SANDBOX),)
+obj-$(CONFIG_BLK) += blk.o
 obj-$(CONFIG_CLK) += clk.o
 obj-$(CONFIG_DM_ETH) += eth.o
 obj-$(CONFIG_DM_GPIO) += gpio.o
diff --git a/test/dm/blk.c b/test/dm/blk.c
new file mode 100644
index 0000000..f4ea32e
--- /dev/null
+++ b/test/dm/blk.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <usb.h>
+#include <asm/state.h>
+#include <dm/test.h>
+#include <test/ut.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Test that block devices can be created */
+static int dm_test_blk_base(struct unit_test_state *uts)
+{
+	struct udevice *blk, *usb_blk, *dev;
+
+	/* Make sure there are no block devices */
+	ut_asserteq(-ENODEV, uclass_get_device_by_seq(UCLASS_BLK, 0, &blk));
+
+	/* Create two, one the parent of the other */
+	ut_assertok(blk_create_device(gd->dm_root, "sandbox_host_blk", "test",
+				      IF_TYPE_HOST, 1, 512, 1024, &blk));
+	ut_assertok(blk_create_device(blk, "usb_storage_blk", "test",
+				      IF_TYPE_USB, 3, 512, 1024, &usb_blk));
+
+	/* Check we can find them */
+	ut_asserteq(-ENODEV, blk_get_device(IF_TYPE_HOST, 0, &dev));
+	ut_assertok(blk_get_device(IF_TYPE_HOST, 1, &dev));
+	ut_asserteq_ptr(blk, dev);
+
+	ut_asserteq(-ENODEV, blk_get_device(IF_TYPE_USB, 0, &dev));
+	ut_assertok(blk_get_device(IF_TYPE_USB, 3, &dev));
+	ut_asserteq_ptr(usb_blk, dev);
+
+	/* Check we can iterate */
+	ut_assertok(blk_first_device(IF_TYPE_HOST, &dev));
+	ut_asserteq_ptr(blk, dev);
+	ut_asserteq(-ENODEV, blk_next_device(&dev));
+
+	ut_assertok(blk_first_device(IF_TYPE_USB, &dev));
+	ut_asserteq_ptr(usb_blk, dev);
+	ut_asserteq(-ENODEV, blk_next_device(&dev));
+
+	return 0;
+}
+DM_TEST(dm_test_blk_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static int count_blk_devices(void)
+{
+	struct udevice *blk;
+	struct uclass *uc;
+	int count = 0;
+	int ret;
+
+	ret = uclass_get(UCLASS_BLK, &uc);
+	if (ret)
+		return ret;
+
+	uclass_foreach_dev(blk, uc)
+		count++;
+
+	return count;
+}
+
+/* Test that block devices work correctly with USB */
+static int dm_test_blk_usb(struct unit_test_state *uts)
+{
+	struct udevice *usb_dev, *dev;
+	struct blk_desc *dev_desc;
+
+	/* Get a flash device */
+	state_set_skip_delays(true);
+	ut_assertok(usb_init());
+	ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 0, &usb_dev));
+	ut_assertok(blk_get_device_by_str("usb", "0", &dev_desc));
+
+	/* The parent should be a block device */
+	ut_assertok(blk_get_device(IF_TYPE_USB, 0, &dev));
+	ut_asserteq_ptr(usb_dev, dev_get_parent(dev));
+
+	/* Check we have one block device for each mass storage device */
+	ut_asserteq(3, count_blk_devices());
+
+	/* Now go around again, making sure the old devices were unbound */
+	ut_assertok(usb_stop());
+	ut_assertok(usb_init());
+	ut_asserteq(3, count_blk_devices());
+	ut_assertok(usb_stop());
+
+	return 0;
+}
+DM_TEST(dm_test_blk_usb, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/usb.c b/test/dm/usb.c
index 3a2e52b..b46ae60 100644
--- a/test/dm/usb.c
+++ b/test/dm/usb.c
@@ -39,19 +39,20 @@
 static int dm_test_usb_flash(struct unit_test_state *uts)
 {
 	struct udevice *dev;
-	block_dev_desc_t *dev_desc;
+	struct blk_desc *dev_desc;
 	char cmp[1024];
 
 	state_set_skip_delays(true);
 	ut_assertok(usb_init());
 	ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 0, &dev));
-	ut_assertok(get_device("usb", "0", &dev_desc));
+	ut_assertok(blk_get_device_by_str("usb", "0", &dev_desc));
 
 	/* Read a few blocks and look for the string we expect */
 	ut_asserteq(512, dev_desc->blksz);
 	memset(cmp, '\0', sizeof(cmp));
-	ut_asserteq(2, dev_desc->block_read(dev_desc, 0, 2, cmp));
+	ut_asserteq(2, blk_dread(dev_desc, 0, 2, cmp));
 	ut_assertok(strcmp(cmp, "this is a test"));
+	ut_assertok(usb_stop());
 
 	return 0;
 }
@@ -67,6 +68,7 @@
 	ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 0, &dev));
 	ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 1, &dev));
 	ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 2, &dev));
+	ut_assertok(usb_stop());
 
 	return 0;
 }
diff --git a/tools/Makefile b/tools/Makefile
index 2881a7c..1e4b4aa 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -59,7 +59,7 @@
 # Flattened device tree objects
 LIBFDT_OBJS := $(addprefix lib/libfdt/, \
 			fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_wip.o \
-			fdt_region.o)
+			fdt_region.o fdt_sw.o)
 RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := $(addprefix lib/rsa/, \
 					rsa-sign.o rsa-verify.o rsa-checksum.o \
 					rsa-mod-exp.o)
diff --git a/tools/buildman/README b/tools/buildman/README
index 6f41008..4705d26 100644
--- a/tools/buildman/README
+++ b/tools/buildman/README
@@ -169,6 +169,28 @@
 The toolchain-alias section indicates that the i386 toolchain should be used
 to build x86 commits.
 
+Note that you can also specific exactly toolchain prefixes if you like:
+
+[toolchain-prefix]
+arm: /opt/arm-eabi-4.6/bin/arm-eabi-
+
+or even:
+
+[toolchain-prefix]
+arm: /opt/arm-eabi-4.6/bin/arm-eabi-gcc
+
+This tells buildman that you want to use this exact toolchain for the arm
+architecture. This will override any toolchains found by searching using the
+[toolchain] settings.
+
+Since the toolchain prefix is an explicit request, buildman will report an
+error if a toolchain is not found with that prefix. The current PATH will be
+searched, so it is possible to use:
+
+[toolchain-prefix]
+arm: arm-none-eabi-
+
+and buildman will find arm-none-eabi-gcc in /usr/bin if you have it installed.
 
 3. Make sure you have the require Python pre-requisites
 
@@ -185,124 +207,180 @@
 
 $ ./tools/buildman/buildman --list-tool-chains
 Scanning for tool chains
+   - scanning prefix '/opt/gcc-4.6.3-nolibc/x86_64-linux/bin/x86_64-linux-'
+Tool chain test:  OK, arch='x86', priority 1
+   - scanning prefix '/opt/arm-eabi-4.6/bin/arm-eabi-'
+Tool chain test:  OK, arch='arm', priority 1
+   - scanning path '/toolchains/gcc-4.9.0-nolibc/i386-linux'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/i386-linux/.'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/i386-linux/bin'
+         - found '/toolchains/gcc-4.9.0-nolibc/i386-linux/bin/i386-linux-gcc'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/i386-linux/usr/bin'
+Tool chain test:  OK, arch='i386', priority 4
+   - scanning path '/toolchains/gcc-4.9.0-nolibc/aarch64-linux'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/aarch64-linux/.'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/aarch64-linux/bin'
+         - found '/toolchains/gcc-4.9.0-nolibc/aarch64-linux/bin/aarch64-linux-gcc'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/aarch64-linux/usr/bin'
+Tool chain test:  OK, arch='aarch64', priority 4
+   - scanning path '/toolchains/gcc-4.9.0-nolibc/microblaze-linux'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/microblaze-linux/.'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/microblaze-linux/bin'
+         - found '/toolchains/gcc-4.9.0-nolibc/microblaze-linux/bin/microblaze-linux-gcc'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/microblaze-linux/usr/bin'
+Tool chain test:  OK, arch='microblaze', priority 4
+   - scanning path '/toolchains/gcc-4.9.0-nolibc/mips64-linux'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/mips64-linux/.'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/mips64-linux/bin'
+         - found '/toolchains/gcc-4.9.0-nolibc/mips64-linux/bin/mips64-linux-gcc'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/mips64-linux/usr/bin'
+Tool chain test:  OK, arch='mips64', priority 4
+   - scanning path '/toolchains/gcc-4.9.0-nolibc/sparc64-linux'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/sparc64-linux/.'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/sparc64-linux/bin'
+         - found '/toolchains/gcc-4.9.0-nolibc/sparc64-linux/bin/sparc64-linux-gcc'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/sparc64-linux/usr/bin'
+Tool chain test:  OK, arch='sparc64', priority 4
+   - scanning path '/toolchains/gcc-4.9.0-nolibc/arm-unknown-linux-gnueabi'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/arm-unknown-linux-gnueabi/.'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/arm-unknown-linux-gnueabi/bin'
+         - found '/toolchains/gcc-4.9.0-nolibc/arm-unknown-linux-gnueabi/bin/arm-unknown-linux-gnueabi-gcc'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/arm-unknown-linux-gnueabi/usr/bin'
+Tool chain test:  OK, arch='arm', priority 3
+Toolchain '/toolchains/gcc-4.9.0-nolibc/arm-unknown-linux-gnueabi/bin/arm-unknown-linux-gnueabi-gcc' at priority 3 will be ignored because another toolchain for arch 'arm' has priority 1
+   - scanning path '/toolchains/gcc-4.9.0-nolibc/sparc-linux'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/sparc-linux/.'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/sparc-linux/bin'
+         - found '/toolchains/gcc-4.9.0-nolibc/sparc-linux/bin/sparc-linux-gcc'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/sparc-linux/usr/bin'
+Tool chain test:  OK, arch='sparc', priority 4
+   - scanning path '/toolchains/gcc-4.9.0-nolibc/mips-linux'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/mips-linux/.'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/mips-linux/bin'
+         - found '/toolchains/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-gcc'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/mips-linux/usr/bin'
+Tool chain test:  OK, arch='mips', priority 4
+   - scanning path '/toolchains/gcc-4.9.0-nolibc/x86_64-linux'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/x86_64-linux/.'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/x86_64-linux/bin'
+         - found '/toolchains/gcc-4.9.0-nolibc/x86_64-linux/bin/x86_64-linux-gcc'
+         - found '/toolchains/gcc-4.9.0-nolibc/x86_64-linux/bin/x86_64-linux-x86_64-linux-gcc'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/x86_64-linux/usr/bin'
+Tool chain test:  OK, arch='x86_64', priority 4
+Tool chain test:  OK, arch='x86_64', priority 4
+Toolchain '/toolchains/gcc-4.9.0-nolibc/x86_64-linux/bin/x86_64-linux-x86_64-linux-gcc' at priority 4 will be ignored because another toolchain for arch 'x86_64' has priority 4
+   - scanning path '/toolchains/gcc-4.9.0-nolibc/m68k-linux'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/m68k-linux/.'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/m68k-linux/bin'
+         - found '/toolchains/gcc-4.9.0-nolibc/m68k-linux/bin/m68k-linux-gcc'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/m68k-linux/usr/bin'
+Tool chain test:  OK, arch='m68k', priority 4
+   - scanning path '/toolchains/gcc-4.9.0-nolibc/powerpc-linux'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/powerpc-linux/.'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/powerpc-linux/bin'
+         - found '/toolchains/gcc-4.9.0-nolibc/powerpc-linux/bin/powerpc-linux-gcc'
+      - looking in '/toolchains/gcc-4.9.0-nolibc/powerpc-linux/usr/bin'
+Tool chain test:  OK, arch='powerpc', priority 4
+   - scanning path '/toolchains/gcc-4.6.3-nolibc/bfin-uclinux'
+      - looking in '/toolchains/gcc-4.6.3-nolibc/bfin-uclinux/.'
+      - looking in '/toolchains/gcc-4.6.3-nolibc/bfin-uclinux/bin'
+         - found '/toolchains/gcc-4.6.3-nolibc/bfin-uclinux/bin/bfin-uclinux-gcc'
+      - looking in '/toolchains/gcc-4.6.3-nolibc/bfin-uclinux/usr/bin'
+Tool chain test:  OK, arch='bfin', priority 6
+   - scanning path '/toolchains/gcc-4.6.3-nolibc/sparc-linux'
+      - looking in '/toolchains/gcc-4.6.3-nolibc/sparc-linux/.'
+      - looking in '/toolchains/gcc-4.6.3-nolibc/sparc-linux/bin'
+         - found '/toolchains/gcc-4.6.3-nolibc/sparc-linux/bin/sparc-linux-gcc'
+      - looking in '/toolchains/gcc-4.6.3-nolibc/sparc-linux/usr/bin'
+Tool chain test:  OK, arch='sparc', priority 4
+Toolchain '/toolchains/gcc-4.6.3-nolibc/sparc-linux/bin/sparc-linux-gcc' at priority 4 will be ignored because another toolchain for arch 'sparc' has priority 4
+   - scanning path '/toolchains/gcc-4.6.3-nolibc/mips-linux'
+      - looking in '/toolchains/gcc-4.6.3-nolibc/mips-linux/.'
+      - looking in '/toolchains/gcc-4.6.3-nolibc/mips-linux/bin'
+         - found '/toolchains/gcc-4.6.3-nolibc/mips-linux/bin/mips-linux-gcc'
+      - looking in '/toolchains/gcc-4.6.3-nolibc/mips-linux/usr/bin'
+Tool chain test:  OK, arch='mips', priority 4
+Toolchain '/toolchains/gcc-4.6.3-nolibc/mips-linux/bin/mips-linux-gcc' at priority 4 will be ignored because another toolchain for arch 'mips' has priority 4
+   - scanning path '/toolchains/gcc-4.6.3-nolibc/m68k-linux'
+      - looking in '/toolchains/gcc-4.6.3-nolibc/m68k-linux/.'
+      - looking in '/toolchains/gcc-4.6.3-nolibc/m68k-linux/bin'
+         - found '/toolchains/gcc-4.6.3-nolibc/m68k-linux/bin/m68k-linux-gcc'
+      - looking in '/toolchains/gcc-4.6.3-nolibc/m68k-linux/usr/bin'
+Tool chain test:  OK, arch='m68k', priority 4
+Toolchain '/toolchains/gcc-4.6.3-nolibc/m68k-linux/bin/m68k-linux-gcc' at priority 4 will be ignored because another toolchain for arch 'm68k' has priority 4
+   - scanning path '/toolchains/gcc-4.6.3-nolibc/powerpc-linux'
+      - looking in '/toolchains/gcc-4.6.3-nolibc/powerpc-linux/.'
+      - looking in '/toolchains/gcc-4.6.3-nolibc/powerpc-linux/bin'
+         - found '/toolchains/gcc-4.6.3-nolibc/powerpc-linux/bin/powerpc-linux-gcc'
+      - looking in '/toolchains/gcc-4.6.3-nolibc/powerpc-linux/usr/bin'
+Tool chain test:  OK, arch='powerpc', priority 4
+Tool chain test:  OK, arch='or32', priority 4
+   - scanning path '/toolchains/gcc-4.2.4-nolibc/avr32-linux'
+      - looking in '/toolchains/gcc-4.2.4-nolibc/avr32-linux/.'
+      - looking in '/toolchains/gcc-4.2.4-nolibc/avr32-linux/bin'
+         - found '/toolchains/gcc-4.2.4-nolibc/avr32-linux/bin/avr32-linux-gcc'
+      - looking in '/toolchains/gcc-4.2.4-nolibc/avr32-linux/usr/bin'
+Tool chain test:  OK, arch='avr32', priority 4
    - scanning path '/'
       - looking in '/.'
       - looking in '/bin'
       - looking in '/usr/bin'
-         - found '/usr/bin/gcc'
-Tool chain test:  OK
+         - found '/usr/bin/i586-mingw32msvc-gcc'
          - found '/usr/bin/c89-gcc'
-Tool chain test:  OK
-         - found '/usr/bin/c99-gcc'
-Tool chain test:  OK
          - found '/usr/bin/x86_64-linux-gnu-gcc'
-Tool chain test:  OK
-   - scanning path '/toolchains/powerpc-linux'
-      - looking in '/toolchains/powerpc-linux/.'
-      - looking in '/toolchains/powerpc-linux/bin'
-         - found '/toolchains/powerpc-linux/bin/powerpc-linux-gcc'
-Tool chain test:  OK
-      - looking in '/toolchains/powerpc-linux/usr/bin'
-   - scanning path '/toolchains/nds32le-linux-glibc-v1f'
-      - looking in '/toolchains/nds32le-linux-glibc-v1f/.'
-      - looking in '/toolchains/nds32le-linux-glibc-v1f/bin'
-         - found '/toolchains/nds32le-linux-glibc-v1f/bin/nds32le-linux-gcc'
-Tool chain test:  OK
-      - looking in '/toolchains/nds32le-linux-glibc-v1f/usr/bin'
-   - scanning path '/toolchains/nios2'
-      - looking in '/toolchains/nios2/.'
-      - looking in '/toolchains/nios2/bin'
-         - found '/toolchains/nios2/bin/nios2-linux-gcc'
-Tool chain test:  OK
-         - found '/toolchains/nios2/bin/nios2-linux-uclibc-gcc'
-Tool chain test:  OK
-      - looking in '/toolchains/nios2/usr/bin'
-         - found '/toolchains/nios2/usr/bin/nios2-linux-gcc'
-Tool chain test:  OK
-         - found '/toolchains/nios2/usr/bin/nios2-linux-uclibc-gcc'
-Tool chain test:  OK
-   - scanning path '/toolchains/microblaze-unknown-linux-gnu'
-      - looking in '/toolchains/microblaze-unknown-linux-gnu/.'
-      - looking in '/toolchains/microblaze-unknown-linux-gnu/bin'
-         - found '/toolchains/microblaze-unknown-linux-gnu/bin/microblaze-unknown-linux-gnu-gcc'
-Tool chain test:  OK
-         - found '/toolchains/microblaze-unknown-linux-gnu/bin/mb-linux-gcc'
-Tool chain test:  OK
-      - looking in '/toolchains/microblaze-unknown-linux-gnu/usr/bin'
-   - scanning path '/toolchains/mips-linux'
-      - looking in '/toolchains/mips-linux/.'
-      - looking in '/toolchains/mips-linux/bin'
-         - found '/toolchains/mips-linux/bin/mips-linux-gcc'
-Tool chain test:  OK
-      - looking in '/toolchains/mips-linux/usr/bin'
-   - scanning path '/toolchains/old'
-      - looking in '/toolchains/old/.'
-      - looking in '/toolchains/old/bin'
-      - looking in '/toolchains/old/usr/bin'
-   - scanning path '/toolchains/i386-linux'
-      - looking in '/toolchains/i386-linux/.'
-      - looking in '/toolchains/i386-linux/bin'
-         - found '/toolchains/i386-linux/bin/i386-linux-gcc'
-Tool chain test:  OK
-      - looking in '/toolchains/i386-linux/usr/bin'
-   - scanning path '/toolchains/bfin-uclinux'
-      - looking in '/toolchains/bfin-uclinux/.'
-      - looking in '/toolchains/bfin-uclinux/bin'
-         - found '/toolchains/bfin-uclinux/bin/bfin-uclinux-gcc'
-Tool chain test:  OK
-      - looking in '/toolchains/bfin-uclinux/usr/bin'
-   - scanning path '/toolchains/sparc-elf'
-      - looking in '/toolchains/sparc-elf/.'
-      - looking in '/toolchains/sparc-elf/bin'
-         - found '/toolchains/sparc-elf/bin/sparc-elf-gcc'
-Tool chain test:  OK
-      - looking in '/toolchains/sparc-elf/usr/bin'
-   - scanning path '/toolchains/arm-2010q1'
-      - looking in '/toolchains/arm-2010q1/.'
-      - looking in '/toolchains/arm-2010q1/bin'
-         - found '/toolchains/arm-2010q1/bin/arm-none-linux-gnueabi-gcc'
-Tool chain test:  OK
-      - looking in '/toolchains/arm-2010q1/usr/bin'
-   - scanning path '/toolchains/from'
-      - looking in '/toolchains/from/.'
-      - looking in '/toolchains/from/bin'
-      - looking in '/toolchains/from/usr/bin'
-   - scanning path '/toolchains/sh4-gentoo-linux-gnu'
-      - looking in '/toolchains/sh4-gentoo-linux-gnu/.'
-      - looking in '/toolchains/sh4-gentoo-linux-gnu/bin'
-         - found '/toolchains/sh4-gentoo-linux-gnu/bin/sh4-gentoo-linux-gnu-gcc'
-Tool chain test:  OK
-      - looking in '/toolchains/sh4-gentoo-linux-gnu/usr/bin'
-   - scanning path '/toolchains/avr32-linux'
-      - looking in '/toolchains/avr32-linux/.'
-      - looking in '/toolchains/avr32-linux/bin'
-         - found '/toolchains/avr32-linux/bin/avr32-gcc'
-Tool chain test:  OK
-      - looking in '/toolchains/avr32-linux/usr/bin'
-   - scanning path '/toolchains/m68k-linux'
-      - looking in '/toolchains/m68k-linux/.'
-      - looking in '/toolchains/m68k-linux/bin'
-         - found '/toolchains/m68k-linux/bin/m68k-linux-gcc'
-Tool chain test:  OK
-      - looking in '/toolchains/m68k-linux/usr/bin'
-List of available toolchains (17):
-arm       : /toolchains/arm-2010q1/bin/arm-none-linux-gnueabi-gcc
-avr32     : /toolchains/avr32-linux/bin/avr32-gcc
-bfin      : /toolchains/bfin-uclinux/bin/bfin-uclinux-gcc
+         - found '/usr/bin/gcc'
+         - found '/usr/bin/c99-gcc'
+         - found '/usr/bin/arm-linux-gnueabi-gcc'
+         - found '/usr/bin/aarch64-linux-gnu-gcc'
+         - found '/usr/bin/winegcc'
+         - found '/usr/bin/arm-linux-gnueabihf-gcc'
+Tool chain test:  OK, arch='i586', priority 11
+Tool chain test:  OK, arch='c89', priority 11
+Tool chain test:  OK, arch='x86_64', priority 4
+Toolchain '/usr/bin/x86_64-linux-gnu-gcc' at priority 4 will be ignored because another toolchain for arch 'x86_64' has priority 4
+Tool chain test:  OK, arch='sandbox', priority 11
+Tool chain test:  OK, arch='c99', priority 11
+Tool chain test:  OK, arch='arm', priority 4
+Toolchain '/usr/bin/arm-linux-gnueabi-gcc' at priority 4 will be ignored because another toolchain for arch 'arm' has priority 1
+Tool chain test:  OK, arch='aarch64', priority 4
+Toolchain '/usr/bin/aarch64-linux-gnu-gcc' at priority 4 will be ignored because another toolchain for arch 'aarch64' has priority 4
+Tool chain test:  OK, arch='sandbox', priority 11
+Toolchain '/usr/bin/winegcc' at priority 11 will be ignored because another toolchain for arch 'sandbox' has priority 11
+Tool chain test:  OK, arch='arm', priority 4
+Toolchain '/usr/bin/arm-linux-gnueabihf-gcc' at priority 4 will be ignored because another toolchain for arch 'arm' has priority 1
+List of available toolchains (34):
+aarch64   : /toolchains/gcc-4.9.0-nolibc/aarch64-linux/bin/aarch64-linux-gcc
+alpha     : /toolchains/gcc-4.9.0-nolibc/alpha-linux/bin/alpha-linux-gcc
+am33_2.0  : /toolchains/gcc-4.9.0-nolibc/am33_2.0-linux/bin/am33_2.0-linux-gcc
+arm       : /opt/arm-eabi-4.6/bin/arm-eabi-gcc
+avr32     : /toolchains/gcc-4.2.4-nolibc/avr32-linux/bin/avr32-linux-gcc
+bfin      : /toolchains/gcc-4.6.3-nolibc/bfin-uclinux/bin/bfin-uclinux-gcc
 c89       : /usr/bin/c89-gcc
 c99       : /usr/bin/c99-gcc
-i386      : /toolchains/i386-linux/bin/i386-linux-gcc
-m68k      : /toolchains/m68k-linux/bin/m68k-linux-gcc
-mb        : /toolchains/microblaze-unknown-linux-gnu/bin/mb-linux-gcc
-microblaze: /toolchains/microblaze-unknown-linux-gnu/bin/microblaze-unknown-linux-gnu-gcc
-mips      : /toolchains/mips-linux/bin/mips-linux-gcc
-nds32le   : /toolchains/nds32le-linux-glibc-v1f/bin/nds32le-linux-gcc
-nios2     : /toolchains/nios2/bin/nios2-linux-gcc
-powerpc   : /toolchains/powerpc-linux/bin/powerpc-linux-gcc
+frv       : /toolchains/gcc-4.9.0-nolibc/frv-linux/bin/frv-linux-gcc
+h8300     : /toolchains/gcc-4.9.0-nolibc/h8300-elf/bin/h8300-elf-gcc
+hppa      : /toolchains/gcc-4.9.0-nolibc/hppa-linux/bin/hppa-linux-gcc
+hppa64    : /toolchains/gcc-4.9.0-nolibc/hppa64-linux/bin/hppa64-linux-gcc
+i386      : /toolchains/gcc-4.9.0-nolibc/i386-linux/bin/i386-linux-gcc
+i586      : /usr/bin/i586-mingw32msvc-gcc
+ia64      : /toolchains/gcc-4.9.0-nolibc/ia64-linux/bin/ia64-linux-gcc
+m32r      : /toolchains/gcc-4.9.0-nolibc/m32r-linux/bin/m32r-linux-gcc
+m68k      : /toolchains/gcc-4.9.0-nolibc/m68k-linux/bin/m68k-linux-gcc
+microblaze: /toolchains/gcc-4.9.0-nolibc/microblaze-linux/bin/microblaze-linux-gcc
+mips      : /toolchains/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-gcc
+mips64    : /toolchains/gcc-4.9.0-nolibc/mips64-linux/bin/mips64-linux-gcc
+or32      : /toolchains/gcc-4.5.1-nolibc/or32-linux/bin/or32-linux-gcc
+powerpc   : /toolchains/gcc-4.9.0-nolibc/powerpc-linux/bin/powerpc-linux-gcc
+powerpc64 : /toolchains/gcc-4.9.0-nolibc/powerpc64-linux/bin/powerpc64-linux-gcc
+ppc64le   : /toolchains/gcc-4.9.0-nolibc/ppc64le-linux/bin/ppc64le-linux-gcc
+s390x     : /toolchains/gcc-4.9.0-nolibc/s390x-linux/bin/s390x-linux-gcc
 sandbox   : /usr/bin/gcc
-sh4       : /toolchains/sh4-gentoo-linux-gnu/bin/sh4-gentoo-linux-gnu-gcc
-sparc     : /toolchains/sparc-elf/bin/sparc-elf-gcc
-x86_64    : /usr/bin/x86_64-linux-gnu-gcc
+sh4       : /toolchains/gcc-4.6.3-nolibc/sh4-linux/bin/sh4-linux-gcc
+sparc     : /toolchains/gcc-4.9.0-nolibc/sparc-linux/bin/sparc-linux-gcc
+sparc64   : /toolchains/gcc-4.9.0-nolibc/sparc64-linux/bin/sparc64-linux-gcc
+tilegx    : /toolchains/gcc-4.6.2-nolibc/tilegx-linux/bin/tilegx-linux-gcc
+x86       : /opt/gcc-4.6.3-nolibc/x86_64-linux/bin/x86_64-linux-gcc
+x86_64    : /toolchains/gcc-4.9.0-nolibc/x86_64-linux/bin/x86_64-linux-gcc
 
 
 You can see that everything is covered, even some strange ones that won't
@@ -534,7 +612,8 @@
    err:  Output from stderr, if any. Errors and warnings appear here.
 
    log:  Output from stdout. Normally there isn't any since buildman runs
-         in silent mode for now.
+         in silent mode. Use -V to force a verbose build (this passes V=1
+         to 'make')
 
    toolchain: Shows information about the toolchain used for the build.
 
diff --git a/tools/buildman/cmdline.py b/tools/buildman/cmdline.py
index 916ea57..8341ab1 100644
--- a/tools/buildman/cmdline.py
+++ b/tools/buildman/cmdline.py
@@ -85,7 +85,7 @@
     parser.add_option('-v', '--verbose', action='store_true',
           default=False, help='Show build results while the build progresses')
     parser.add_option('-V', '--verbose-build', action='store_true',
-          default=False, help='Run make with V=1, showing all output')
+          default=False, help='Run make with V=1, logging all output')
     parser.add_option('-x', '--exclude', dest='exclude',
           type='string', action='append',
           help='Specify a list of boards to exclude, separated by comma')
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index 8b3cd30..c2c54bf 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -101,7 +101,8 @@
         pager = os.getenv('PAGER')
         if not pager:
             pager = 'more'
-        fname = os.path.join(os.path.dirname(sys.argv[0]), 'README')
+        fname = os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])),
+                             'README')
         command.Run(pager, fname)
         return 0
 
diff --git a/tools/buildman/func_test.py b/tools/buildman/func_test.py
index 75eb3a9..a0bd46c 100644
--- a/tools/buildman/func_test.py
+++ b/tools/buildman/func_test.py
@@ -255,6 +255,8 @@
         self.assertEqual(gitutil.use_no_decorate, True)
 
     def _HandleCommandGitLog(self, args):
+        if args[-1] == '--':
+            args = args[:-1]
         if '-n0' in args:
             return command.CommandResult(return_code=0)
         elif args[-1] == 'upstream/master..%s' % self._test_branch:
diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index e33e105..3993db3 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -14,6 +14,9 @@
 import bsettings
 import command
 
+(PRIORITY_FULL_PREFIX, PRIORITY_PREFIX_GCC, PRIORITY_PREFIX_GCC_PATH,
+    PRIORITY_CALC) = range(4)
+
 # Simple class to collect links from a page
 class MyHTMLParser(HTMLParser):
     def __init__(self, arch):
@@ -50,13 +53,18 @@
         cross: Cross compile string, e.g. 'arm-linux-'
         arch: Architecture of toolchain as determined from the first
                 component of the filename. E.g. arm-linux-gcc becomes arm
+        priority: Toolchain priority (0=highest, 20=lowest)
     """
-    def __init__(self, fname, test, verbose=False):
+    def __init__(self, fname, test, verbose=False, priority=PRIORITY_CALC,
+                 arch=None):
         """Create a new toolchain object.
 
         Args:
             fname: Filename of the gcc component
             test: True to run the toolchain to test it
+            verbose: True to print out the information
+            priority: Priority to use for this toolchain, or PRIORITY_CALC to
+                calculate it
         """
         self.gcc = fname
         self.path = os.path.dirname(fname)
@@ -69,12 +77,19 @@
 
         # The architecture is the first part of the name
         pos = self.cross.find('-')
-        self.arch = self.cross[:pos] if pos != -1 else 'sandbox'
+        if arch:
+            self.arch = arch
+        else:
+            self.arch = self.cross[:pos] if pos != -1 else 'sandbox'
 
         env = self.MakeEnvironment(False)
 
         # As a basic sanity check, run the C compiler with --version
         cmd = [fname, '--version']
+        if priority == PRIORITY_CALC:
+            self.priority = self.GetPriority(fname)
+        else:
+            self.priority = priority
         if test:
             result = command.RunPipe([cmd], capture=True, env=env,
                                      raise_on_error=False)
@@ -82,7 +97,8 @@
             if verbose:
                 print 'Tool chain test: ',
                 if self.ok:
-                    print 'OK'
+                    print "OK, arch='%s', priority %d" % (self.arch,
+                                                          self.priority)
                 else:
                     print 'BAD'
                     print 'Command: ', cmd
@@ -90,7 +106,6 @@
                     print result.stderr
         else:
             self.ok = True
-        self.priority = self.GetPriority(fname)
 
     def GetPriority(self, fname):
         """Return the priority of the toolchain.
@@ -101,15 +116,15 @@
         Args:
             fname: Filename of toolchain
         Returns:
-            Priority of toolchain, 0=highest, 20=lowest.
+            Priority of toolchain, PRIORITY_CALC=highest, 20=lowest.
         """
         priority_list = ['-elf', '-unknown-linux-gnu', '-linux',
             '-none-linux-gnueabi', '-uclinux', '-none-eabi',
             '-gentoo-linux-gnu', '-linux-gnueabi', '-le-linux', '-uclinux']
         for prio in range(len(priority_list)):
             if priority_list[prio] in fname:
-                return prio
-        return prio
+                return PRIORITY_CALC + prio
+        return PRIORITY_CALC + prio
 
     def MakeEnvironment(self, full_path):
         """Returns an environment for using the toolchain.
@@ -138,11 +153,17 @@
 
     Public members:
         toolchains: Dict of Toolchain objects, keyed by architecture name
+        prefixes: Dict of prefixes to check, keyed by architecture. This can
+            be a full path and toolchain prefix, for example
+            {'x86', 'opt/i386-linux/bin/i386-linux-'}, or the name of
+            something on the search path, for example
+            {'arm', 'arm-linux-gnueabihf-'}. Wildcards are not supported.
         paths: List of paths to check for toolchains (may contain wildcards)
     """
 
     def __init__(self):
         self.toolchains = {}
+        self.prefixes = {}
         self.paths = []
         self._make_flags = dict(bsettings.GetItems('make-flags'))
 
@@ -155,8 +176,8 @@
         """
         toolchains = bsettings.GetItems('toolchain')
         if not toolchains:
-            print ("Warning: No tool chains - please add a [toolchain] section"
-                 " to your buildman config file %s. See README for details" %
+            print ('Warning: No tool chains - please add a [toolchain] section'
+                 ' to your buildman config file %s. See README for details' %
                  bsettings.config_fname)
 
         paths = []
@@ -168,9 +189,11 @@
         return paths
 
     def GetSettings(self):
+      self.prefixes = bsettings.GetItems('toolchain-prefix')
       self.paths += self.GetPathList()
 
-    def Add(self, fname, test=True, verbose=False):
+    def Add(self, fname, test=True, verbose=False, priority=PRIORITY_CALC,
+            arch=None):
         """Add a toolchain to our list
 
         We select the given toolchain as our preferred one for its
@@ -179,14 +202,21 @@
         Args:
             fname: Filename of toolchain's gcc driver
             test: True to run the toolchain to test it
+            priority: Priority to use for this toolchain
+            arch: Toolchain architecture, or None if not known
         """
-        toolchain = Toolchain(fname, test, verbose)
+        toolchain = Toolchain(fname, test, verbose, priority, arch)
         add_it = toolchain.ok
         if toolchain.arch in self.toolchains:
             add_it = (toolchain.priority <
                         self.toolchains[toolchain.arch].priority)
         if add_it:
             self.toolchains[toolchain.arch] = toolchain
+        elif verbose:
+            print ("Toolchain '%s' at priority %d will be ignored because "
+                   "another toolchain for arch '%s' has priority %d" %
+                   (toolchain.gcc, toolchain.priority, toolchain.arch,
+                    self.toolchains[toolchain.arch].priority))
 
     def ScanPath(self, path, verbose):
         """Scan a path for a valid toolchain
@@ -206,6 +236,21 @@
                 fnames.append(fname)
         return fnames
 
+    def ScanPathEnv(self, fname):
+        """Scan the PATH environment variable for a given filename.
+
+        Args:
+            fname: Filename to scan for
+        Returns:
+            List of matching pathanames, or [] if none
+        """
+        pathname_list = []
+        for path in os.environ["PATH"].split(os.pathsep):
+            path = path.strip('"')
+            pathname = os.path.join(path, fname)
+            if os.path.exists(pathname):
+                pathname_list.append(pathname)
+        return pathname_list
 
     def Scan(self, verbose):
         """Scan for available toolchains and select the best for each arch.
@@ -218,6 +263,21 @@
             verbose: True to print out progress information
         """
         if verbose: print 'Scanning for tool chains'
+        for name, value in self.prefixes:
+            if verbose: print "   - scanning prefix '%s'" % value
+            if os.path.exists(value):
+                self.Add(value, True, verbose, PRIORITY_FULL_PREFIX, name)
+                continue
+            fname = value + 'gcc'
+            if os.path.exists(fname):
+                self.Add(fname, True, verbose, PRIORITY_PREFIX_GCC, name)
+                continue
+            fname_list = self.ScanPathEnv(fname)
+            for f in fname_list:
+                self.Add(f, True, verbose, PRIORITY_PREFIX_GCC_PATH, name)
+            if not fname_list:
+                raise ValueError, ("No tool chain found for prefix '%s'" %
+                                   value)
         for path in self.paths:
             if verbose: print "   - scanning path '%s'" % path
             fnames = self.ScanPath(path, verbose)
@@ -367,14 +427,14 @@
                 Full path to the downloaded archive file in that directory,
                     or None if there was an error while downloading
         """
-        print "Downloading: %s" % url
+        print 'Downloading: %s' % url
         leaf = url.split('/')[-1]
         tmpdir = tempfile.mkdtemp('.buildman')
         response = urllib2.urlopen(url)
         fname = os.path.join(tmpdir, leaf)
         fd = open(fname, 'wb')
         meta = response.info()
-        size = int(meta.getheaders("Content-Length")[0])
+        size = int(meta.getheaders('Content-Length')[0])
         done = 0
         block_size = 1 << 16
         status = ''
@@ -388,7 +448,7 @@
 
             done += len(buffer)
             fd.write(buffer)
-            status = r"%10d MiB  [%3d%%]" % (done / 1024 / 1024,
+            status = r'%10d MiB  [%3d%%]' % (done / 1024 / 1024,
                                              done * 100 / size)
             status = status + chr(8) * (len(status) + 1)
             print status,
diff --git a/tools/fdtgrep.c b/tools/fdtgrep.c
index 67aa41a..8d3fef4 100644
--- a/tools/fdtgrep.c
+++ b/tools/fdtgrep.c
@@ -660,6 +660,8 @@
 		if (!ret)
 			count++;
 	}
+	if (ret && ret != -FDT_ERR_NOTFOUND)
+		return ret;
 
 	/* Find all the aliases and add those regions back in */
 	if (disp->add_aliases && count < max_regions) {
@@ -667,7 +669,11 @@
 
 		new_count = fdt_add_alias_regions(fdt, region, count,
 						  max_regions, &state);
-		if (new_count <= max_regions) {
+		if (new_count == -FDT_ERR_NOTFOUND) {
+			/* No alias node found */
+		} else if (new_count < 0) {
+			return new_count;
+		} else if (new_count <= max_regions) {
 			/*
 			* The alias regions will now be at the end of the list.
 			* Sort the regions by offset to get things into the
@@ -679,9 +685,6 @@
 		}
 	}
 
-	if (ret != -FDT_ERR_NOTFOUND)
-		return ret;
-
 	return count;
 }
 
@@ -807,6 +810,9 @@
 				disp->flags);
 		if (count < 0) {
 			report_error("fdt_find_regions", count);
+			if (count == -FDT_ERR_BADLAYOUT)
+				fprintf(stderr,
+					"/aliases node must come before all other nodes\n");
 			return -1;
 		}
 		if (count <= max_regions)
diff --git a/tools/fit_image.c b/tools/fit_image.c
index eb2a25e..3ecc88f 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -18,6 +18,8 @@
 #include "fit_common.h"
 #include "mkimage.h"
 #include <image.h>
+#include <stdarg.h>
+#include <version.h>
 #include <u-boot/crc.h>
 
 static image_header_t header;
@@ -71,6 +73,481 @@
 }
 
 /**
+ * fit_calc_size() - Calculate the approximate size of the FIT we will generate
+ */
+static int fit_calc_size(struct image_tool_params *params)
+{
+	struct content_info *cont;
+	int size, total_size;
+
+	size = imagetool_get_filesize(params, params->datafile);
+	if (size < 0)
+		return -1;
+
+	total_size = size;
+	for (cont = params->content_head; cont; cont = cont->next) {
+		size = imagetool_get_filesize(params, cont->fname);
+		if (size < 0)
+			return -1;
+
+		/* Add space for properties */
+		total_size += size + 300;
+	}
+
+	/* Add plenty of space for headers, properties, nodes, etc. */
+	total_size += 4096;
+
+	return total_size;
+}
+
+static int fdt_property_file(struct image_tool_params *params,
+			     void *fdt, const char *name, const char *fname)
+{
+	struct stat sbuf;
+	void *ptr;
+	int ret;
+	int fd;
+
+	fd = open(fname, O_RDWR | O_BINARY);
+	if (fd < 0) {
+		fprintf(stderr, "%s: Can't open %s: %s\n",
+			params->cmdname, fname, strerror(errno));
+		return -1;
+	}
+
+	if (fstat(fd, &sbuf) < 0) {
+		fprintf(stderr, "%s: Can't stat %s: %s\n",
+			params->cmdname, fname, strerror(errno));
+		goto err;
+	}
+
+	ret = fdt_property_placeholder(fdt, "data", sbuf.st_size, &ptr);
+	if (ret)
+		return ret;
+	ret = read(fd, ptr, sbuf.st_size);
+	if (ret != sbuf.st_size) {
+		fprintf(stderr, "%s: Can't read %s: %s\n",
+			params->cmdname, fname, strerror(errno));
+		goto err;
+	}
+
+	return 0;
+err:
+	close(fd);
+	return -1;
+}
+
+static int fdt_property_strf(void *fdt, const char *name, const char *fmt, ...)
+{
+	char str[100];
+	va_list ptr;
+
+	va_start(ptr, fmt);
+	vsnprintf(str, sizeof(str), fmt, ptr);
+	va_end(ptr);
+	return fdt_property_string(fdt, name, str);
+}
+
+static void get_basename(char *str, int size, const char *fname)
+{
+	const char *p, *start, *end;
+	int len;
+
+	/*
+	 * Use the base name as the 'name' field. So for example:
+	 *
+	 * "arch/arm/dts/sun7i-a20-bananapro.dtb"
+	 * becomes "sun7i-a20-bananapro"
+	 */
+	p = strrchr(fname, '/');
+	start = p ? p + 1 : fname;
+	p = strrchr(fname, '.');
+	end = p ? p : fname + strlen(fname);
+	len = end - start;
+	if (len >= size)
+		len = size - 1;
+	memcpy(str, start, len);
+	str[len] = '\0';
+}
+
+/**
+ * fit_write_images() - Write out a list of images to the FIT
+ *
+ * We always include the main image (params->datafile). If there are device
+ * tree files, we include an fdt@ node for each of those too.
+ */
+static int fit_write_images(struct image_tool_params *params, char *fdt)
+{
+	struct content_info *cont;
+	const char *typename;
+	char str[100];
+	int upto;
+	int ret;
+
+	fdt_begin_node(fdt, "images");
+
+	/* First the main image */
+	typename = genimg_get_type_short_name(params->fit_image_type);
+	snprintf(str, sizeof(str), "%s@1", typename);
+	fdt_begin_node(fdt, str);
+	fdt_property_string(fdt, "description", params->imagename);
+	fdt_property_string(fdt, "type", typename);
+	fdt_property_string(fdt, "arch", genimg_get_arch_name(params->arch));
+	fdt_property_string(fdt, "os", genimg_get_os_short_name(params->os));
+	fdt_property_string(fdt, "compression",
+			    genimg_get_comp_short_name(params->comp));
+	fdt_property_u32(fdt, "load", params->addr);
+	fdt_property_u32(fdt, "entry", params->ep);
+
+	/*
+	 * Put data last since it is large. SPL may only load the first part
+	 * of the DT, so this way it can access all the above fields.
+	 */
+	ret = fdt_property_file(params, fdt, "data", params->datafile);
+	if (ret)
+		return ret;
+	fdt_end_node(fdt);
+
+	/* Now the device tree files if available */
+	upto = 0;
+	for (cont = params->content_head; cont; cont = cont->next) {
+		if (cont->type != IH_TYPE_FLATDT)
+			continue;
+		snprintf(str, sizeof(str), "%s@%d", FIT_FDT_PROP, ++upto);
+		fdt_begin_node(fdt, str);
+
+		get_basename(str, sizeof(str), cont->fname);
+		fdt_property_string(fdt, "description", str);
+		ret = fdt_property_file(params, fdt, "data", cont->fname);
+		if (ret)
+			return ret;
+		fdt_property_string(fdt, "type", typename);
+		fdt_property_string(fdt, "arch",
+				    genimg_get_arch_short_name(params->arch));
+		fdt_property_string(fdt, "compression",
+				    genimg_get_comp_short_name(IH_COMP_NONE));
+		fdt_end_node(fdt);
+	}
+
+	fdt_end_node(fdt);
+
+	return 0;
+}
+
+/**
+ * fit_write_configs() - Write out a list of configurations to the FIT
+ *
+ * If there are device tree files, we include a configuration for each, which
+ * selects the main image (params->datafile) and its corresponding device
+ * tree file.
+ *
+ * Otherwise we just create a configuration with the main image in it.
+ */
+static void fit_write_configs(struct image_tool_params *params, char *fdt)
+{
+	struct content_info *cont;
+	const char *typename;
+	char str[100];
+	int upto;
+
+	fdt_begin_node(fdt, "configurations");
+	fdt_property_string(fdt, "default", "conf@1");
+
+	upto = 0;
+	for (cont = params->content_head; cont; cont = cont->next) {
+		if (cont->type != IH_TYPE_FLATDT)
+			continue;
+		typename = genimg_get_type_short_name(cont->type);
+		snprintf(str, sizeof(str), "conf@%d", ++upto);
+		fdt_begin_node(fdt, str);
+
+		get_basename(str, sizeof(str), cont->fname);
+		fdt_property_string(fdt, "description", str);
+
+		typename = genimg_get_type_short_name(params->fit_image_type);
+		snprintf(str, sizeof(str), "%s@1", typename);
+		fdt_property_string(fdt, typename, str);
+
+		snprintf(str, sizeof(str), FIT_FDT_PROP "@%d", upto);
+		fdt_property_string(fdt, FIT_FDT_PROP, str);
+		fdt_end_node(fdt);
+	}
+	if (!upto) {
+		fdt_begin_node(fdt, "conf@1");
+		typename = genimg_get_type_short_name(params->fit_image_type);
+		snprintf(str, sizeof(str), "%s@1", typename);
+		fdt_property_string(fdt, typename, str);
+		fdt_end_node(fdt);
+	}
+
+	fdt_end_node(fdt);
+}
+
+static int fit_build_fdt(struct image_tool_params *params, char *fdt, int size)
+{
+	int ret;
+
+	ret = fdt_create(fdt, size);
+	if (ret)
+		return ret;
+	fdt_finish_reservemap(fdt);
+	fdt_begin_node(fdt, "");
+	fdt_property_strf(fdt, "description",
+			  "%s image with one or more FDT blobs",
+			  genimg_get_type_name(params->fit_image_type));
+	fdt_property_strf(fdt, "creator", "U-Boot mkimage %s", PLAIN_VERSION);
+	fdt_property_u32(fdt, "#address-cells", 1);
+	ret = fit_write_images(params, fdt);
+	if (ret)
+		return ret;
+	fit_write_configs(params, fdt);
+	fdt_end_node(fdt);
+	ret = fdt_finish(fdt);
+	if (ret)
+		return ret;
+
+	return fdt_totalsize(fdt);
+}
+
+static int fit_build(struct image_tool_params *params, const char *fname)
+{
+	char *buf;
+	int size;
+	int ret;
+	int fd;
+
+	size = fit_calc_size(params);
+	if (size < 0)
+		return -1;
+	buf = malloc(size);
+	if (!buf) {
+		fprintf(stderr, "%s: Out of memory (%d bytes)\n",
+			params->cmdname, size);
+		return -1;
+	}
+	ret = fit_build_fdt(params, buf, size);
+	if (ret < 0) {
+		fprintf(stderr, "%s: Failed to build FIT image\n",
+			params->cmdname);
+		goto err;
+	}
+	size = ret;
+	fd = open(fname, O_RDWR | O_CREAT | O_TRUNC | O_BINARY, 0666);
+	if (fd < 0) {
+		fprintf(stderr, "%s: Can't open %s: %s\n",
+			params->cmdname, fname, strerror(errno));
+		goto err;
+	}
+	ret = write(fd, buf, size);
+	if (ret != size) {
+		fprintf(stderr, "%s: Can't write %s: %s\n",
+			params->cmdname, fname, strerror(errno));
+		close(fd);
+		goto err;
+	}
+	close(fd);
+
+	return 0;
+err:
+	free(buf);
+	return -1;
+}
+
+/**
+ * fit_extract_data() - Move all data outside the FIT
+ *
+ * This takes a normal FIT file and removes all the 'data' properties from it.
+ * The data is placed in an area after the FIT so that it can be accessed
+ * using an offset into that area. The 'data' properties turn into
+ * 'data-offset' properties.
+ *
+ * This function cannot cope with FITs with 'data-offset' properties. All
+ * data must be in 'data' properties on entry.
+ */
+static int fit_extract_data(struct image_tool_params *params, const char *fname)
+{
+	void *buf;
+	int buf_ptr;
+	int fit_size, new_size;
+	int fd;
+	struct stat sbuf;
+	void *fdt;
+	int ret;
+	int images;
+	int node;
+
+	fd = mmap_fdt(params->cmdname, fname, 0, &fdt, &sbuf, false);
+	if (fd < 0)
+		return -EIO;
+	fit_size = fdt_totalsize(fdt);
+
+	/* Allocate space to hold the image data we will extract */
+	buf = malloc(fit_size);
+	if (!buf) {
+		ret = -ENOMEM;
+		goto err;
+	}
+	buf_ptr = 0;
+
+	images = fdt_path_offset(fdt, FIT_IMAGES_PATH);
+	if (images < 0) {
+		debug("%s: Cannot find /images node: %d\n", __func__, images);
+		ret = -EINVAL;
+		goto err;
+	}
+
+	for (node = fdt_first_subnode(fdt, images);
+	     node >= 0;
+	     node = fdt_next_subnode(fdt, node)) {
+		const char *data;
+		int len;
+
+		data = fdt_getprop(fdt, node, "data", &len);
+		if (!data)
+			continue;
+		memcpy(buf + buf_ptr, data, len);
+		debug("Extracting data size %x\n", len);
+
+		ret = fdt_delprop(fdt, node, "data");
+		if (ret) {
+			ret = -EPERM;
+			goto err;
+		}
+		fdt_setprop_u32(fdt, node, "data-offset", buf_ptr);
+		fdt_setprop_u32(fdt, node, "data-size", len);
+
+		buf_ptr += (len + 3) & ~3;
+	}
+
+	/* Pack the FDT and place the data after it */
+	fdt_pack(fdt);
+
+	debug("Size reduced from %x to %x\n", fit_size, fdt_totalsize(fdt));
+	debug("External data size %x\n", buf_ptr);
+	new_size = fdt_totalsize(fdt);
+	new_size = (new_size + 3) & ~3;
+	munmap(fdt, sbuf.st_size);
+
+	if (ftruncate(fd, new_size)) {
+		debug("%s: Failed to truncate file: %s\n", __func__,
+		      strerror(errno));
+		ret = -EIO;
+		goto err;
+	}
+	if (lseek(fd, new_size, SEEK_SET) < 0) {
+		debug("%s: Failed to seek to end of file: %s\n", __func__,
+		      strerror(errno));
+		ret = -EIO;
+		goto err;
+	}
+	if (write(fd, buf, buf_ptr) != buf_ptr) {
+		debug("%s: Failed to write external data to file %s\n",
+		      __func__, strerror(errno));
+		ret = -EIO;
+		goto err;
+	}
+	close(fd);
+
+	ret = 0;
+
+err:
+	close(fd);
+	return ret;
+}
+
+static int fit_import_data(struct image_tool_params *params, const char *fname)
+{
+	void *fdt, *old_fdt;
+	int fit_size, new_size, size, data_base;
+	int fd;
+	struct stat sbuf;
+	int ret;
+	int images;
+	int node;
+
+	fd = mmap_fdt(params->cmdname, fname, 0, &old_fdt, &sbuf, false);
+	if (fd < 0)
+		return -EIO;
+	fit_size = fdt_totalsize(old_fdt);
+	data_base = (fit_size + 3) & ~3;
+
+	/* Allocate space to hold the new FIT */
+	size = sbuf.st_size + 16384;
+	fdt = malloc(size);
+	if (!fdt) {
+		fprintf(stderr, "%s: Failed to allocate memory (%d bytes)\n",
+			__func__, size);
+		ret = -ENOMEM;
+		goto err;
+	}
+	ret = fdt_open_into(old_fdt, fdt, size);
+	if (ret) {
+		debug("%s: Failed to expand FIT: %s\n", __func__,
+		      fdt_strerror(errno));
+		ret = -EINVAL;
+		goto err;
+	}
+
+	images = fdt_path_offset(fdt, FIT_IMAGES_PATH);
+	if (images < 0) {
+		debug("%s: Cannot find /images node: %d\n", __func__, images);
+		ret = -EINVAL;
+		goto err;
+	}
+
+	for (node = fdt_first_subnode(fdt, images);
+	     node >= 0;
+	     node = fdt_next_subnode(fdt, node)) {
+		int buf_ptr;
+		int len;
+
+		buf_ptr = fdtdec_get_int(fdt, node, "data-offset", -1);
+		len = fdtdec_get_int(fdt, node, "data-size", -1);
+		if (buf_ptr == -1 || len == -1)
+			continue;
+		debug("Importing data size %x\n", len);
+
+		ret = fdt_setprop(fdt, node, "data", fdt + data_base + buf_ptr,
+				  len);
+		if (ret) {
+			debug("%s: Failed to write property: %s\n", __func__,
+			      fdt_strerror(ret));
+			ret = -EINVAL;
+			goto err;
+		}
+	}
+
+	munmap(fdt, sbuf.st_size);
+	close(fd);
+
+	/* Pack the FDT and place the data after it */
+	fdt_pack(fdt);
+
+	new_size = fdt_totalsize(fdt);
+	debug("Size expanded from %x to %x\n", fit_size, new_size);
+
+	fd = open(fname, O_RDWR | O_CREAT | O_TRUNC | O_BINARY, 0666);
+	if (fd < 0) {
+		fprintf(stderr, "%s: Can't open %s: %s\n",
+			params->cmdname, fname, strerror(errno));
+		goto err;
+	}
+	if (write(fd, fdt, new_size) != new_size) {
+		debug("%s: Failed to write external data to file %s\n",
+		      __func__, strerror(errno));
+		ret = -EIO;
+		goto err;
+	}
+	close(fd);
+
+	ret = 0;
+
+err:
+	close(fd);
+	return ret;
+}
+
+/**
  * fit_handle_file - main FIT file processing function
  *
  * fit_handle_file() runs dtc to convert .its to .itb, includes
@@ -103,7 +580,14 @@
 	sprintf (tmpfile, "%s%s", params->imagefile, MKIMAGE_TMPFILE_SUFFIX);
 
 	/* We either compile the source file, or use the existing FIT image */
-	if (params->datafile) {
+	if (params->auto_its) {
+		if (fit_build(params, tmpfile)) {
+			fprintf(stderr, "%s: failed to build FIT\n",
+				params->cmdname);
+			return EXIT_FAILURE;
+		}
+		*cmd = '\0';
+	} else if (params->datafile) {
 		/* dtc -I dts -O dtb -p 500 datafile > tmpfile */
 		snprintf(cmd, sizeof(cmd), "%s %s %s > %s",
 			 MKIMAGE_DTC, params->dtc, params->datafile, tmpfile);
@@ -112,12 +596,17 @@
 		snprintf(cmd, sizeof(cmd), "cp %s %s",
 			 params->imagefile, tmpfile);
 	}
-	if (system (cmd) == -1) {
+	if (*cmd && system(cmd) == -1) {
 		fprintf (stderr, "%s: system(%s) failed: %s\n",
 				params->cmdname, cmd, strerror(errno));
 		goto err_system;
 	}
 
+	/* Move the data so it is internal to the FIT, if needed */
+	ret = fit_import_data(params, tmpfile);
+	if (ret)
+		goto err_system;
+
 	/*
 	 * Set hashes for images in the blob. Unfortunately we may need more
 	 * space in either FDT, so keep trying until we succeed.
@@ -140,6 +629,13 @@
 		goto err_system;
 	}
 
+	/* Move the data so it is external to the FIT, if requested */
+	if (params->external_data) {
+		ret = fit_extract_data(params, tmpfile);
+		if (ret)
+			goto err_system;
+	}
+
 	if (rename (tmpfile, params->imagefile) == -1) {
 		fprintf (stderr, "%s: Can't rename %s to %s: %s\n",
 				params->cmdname, tmpfile, params->imagefile,
@@ -248,6 +744,8 @@
 
 static int fit_check_params(struct image_tool_params *params)
 {
+	if (params->auto_its)
+		return 0;
 	return	((params->dflag && (params->fflag || params->lflag)) ||
 		(params->fflag && (params->dflag || params->lflag)) ||
 		(params->lflag && (params->dflag || params->fflag)));
diff --git a/tools/imagetool.c b/tools/imagetool.c
index 4b0b73d..351211c 100644
--- a/tools/imagetool.c
+++ b/tools/imagetool.c
@@ -91,3 +91,25 @@
 
 	return 0;
 }
+
+int imagetool_get_filesize(struct image_tool_params *params, const char *fname)
+{
+	struct stat sbuf;
+	int fd;
+
+	fd = open(fname, O_RDONLY | O_BINARY);
+	if (fd < 0) {
+		fprintf(stderr, "%s: Can't open %s: %s\n",
+			params->cmdname, fname, strerror(errno));
+		return -1;
+	}
+
+	if (fstat(fd, &sbuf) < 0) {
+		fprintf(stderr, "%s: Can't stat %s: %s\n",
+			params->cmdname, fname, strerror(errno));
+		return -1;
+	}
+	close(fd);
+
+	return sbuf.st_size;
+}
diff --git a/tools/imagetool.h b/tools/imagetool.h
index ad2deb5..24f8f4b 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -27,6 +27,13 @@
 
 #define IH_ARCH_DEFAULT		IH_ARCH_INVALID
 
+/* Information about a file that needs to be placed into the FIT */
+struct content_info {
+	struct content_info *next;
+	int type;		/* File type (IH_TYPE_...) */
+	const char *fname;
+};
+
 /*
  * This structure defines all such variables those are initialized by
  * mkimage and dumpimage main core and need to be referred by image
@@ -61,6 +68,11 @@
 	int require_keys;	/* 1 to mark signing keys as 'required' */
 	int file_size;		/* Total size of output file */
 	int orig_file_size;	/* Original size for file before padding */
+	bool auto_its;		/* Automatically create the .its file */
+	int fit_image_type;	/* Image type to put into the FIT */
+	struct content_info *content_head;	/* List of files to include */
+	struct content_info *content_tail;
+	bool external_data;	/* Store data outside the FIT */
 };
 
 /*
@@ -180,6 +192,18 @@
 	ulong file_data,
 	ulong file_len);
 
+/**
+ * imagetool_get_filesize() - Utility function to obtain the size of a file
+ *
+ * This function prints a message if an error occurs, showing the error that
+ * was obtained.
+ *
+ * @params:	mkimage parameters
+ * @fname:	filename to check
+ * @return size of file, or -ve value on error
+ */
+int imagetool_get_filesize(struct image_tool_params *params, const char *fname);
+
 /*
  * There is a c file associated with supported image type low level code
  * for ex. default_image.c, fit_image.c
diff --git a/tools/mkimage.c b/tools/mkimage.c
index facebcd..2931783 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -13,10 +13,9 @@
 #include <version.h>
 
 static void copy_file(int, const char *, int);
-static void usage(void);
 
 /* parameters initialized by core will be used by the image type code */
-struct image_tool_params params = {
+static struct image_tool_params params = {
 	.os = IH_OS_LINUX,
 	.arch = IH_ARCH_PPC,
 	.type = IH_TYPE_KERNEL,
@@ -67,6 +66,224 @@
 	fprintf(stderr, "\n");
 }
 
+static void usage(const char *msg)
+{
+	fprintf(stderr, "Error: %s\n", msg);
+	fprintf(stderr, "Usage: %s -l image\n"
+			 "          -l ==> list image header information\n",
+		params.cmdname);
+	fprintf(stderr,
+		"       %s [-x] -A arch -O os -T type -C comp -a addr -e ep -n name -d data_file[:data_file...] image\n"
+		"          -A ==> set architecture to 'arch'\n"
+		"          -O ==> set operating system to 'os'\n"
+		"          -T ==> set image type to 'type'\n"
+		"          -C ==> set compression type 'comp'\n"
+		"          -a ==> set load address to 'addr' (hex)\n"
+		"          -e ==> set entry point to 'ep' (hex)\n"
+		"          -n ==> set image name to 'name'\n"
+		"          -d ==> use image data from 'datafile'\n"
+		"          -x ==> set XIP (execute in place)\n",
+		params.cmdname);
+	fprintf(stderr,
+		"       %s [-D dtc_options] [-f fit-image.its|-f auto|-F] [-b <dtb_list>] fit-image\n"
+		"           <dtb_list> is used with -f auto, and is a space-separated list of .dtb files\n",
+		params.cmdname);
+	fprintf(stderr,
+		"          -D => set all options for device tree compiler\n"
+		"          -f => input filename for FIT source\n");
+#ifdef CONFIG_FIT_SIGNATURE
+	fprintf(stderr,
+		"Signing / verified boot options: [-k keydir] [-K dtb] [ -c <comment>] [-r]\n"
+		"          -k => set directory containing private keys\n"
+		"          -K => write public keys to this .dtb file\n"
+		"          -c => add comment in signature node\n"
+		"          -F => re-sign existing FIT image\n"
+		"          -r => mark keys used as 'required' in dtb\n");
+#else
+	fprintf(stderr,
+		"Signing / verified boot not supported (CONFIG_FIT_SIGNATURE undefined)\n");
+#endif
+	fprintf(stderr, "       %s -V ==> print version information and exit\n",
+		params.cmdname);
+	fprintf(stderr, "Use -T to see a list of available image types\n");
+
+	exit(EXIT_FAILURE);
+}
+
+static int add_content(int type, const char *fname)
+{
+	struct content_info *cont;
+
+	cont = calloc(1, sizeof(*cont));
+	if (!cont)
+		return -1;
+	cont->type = type;
+	cont->fname = fname;
+	if (params.content_tail)
+		params.content_tail->next = cont;
+	else
+		params.content_head = cont;
+	params.content_tail = cont;
+
+	return 0;
+}
+
+static void process_args(int argc, char **argv)
+{
+	char *ptr;
+	int type = IH_TYPE_INVALID;
+	char *datafile = NULL;
+	int expecting;
+	int opt;
+
+	expecting = IH_TYPE_COUNT;	/* Unknown */
+	while ((opt = getopt(argc, argv,
+			     "-a:A:bcC:d:D:e:Ef:Fk:K:ln:O:rR:sT:vVx")) != -1) {
+		switch (opt) {
+		case 'a':
+			params.addr = strtoull(optarg, &ptr, 16);
+			if (*ptr) {
+				fprintf(stderr, "%s: invalid load address %s\n",
+					params.cmdname, optarg);
+				exit(EXIT_FAILURE);
+			}
+			break;
+		case 'A':
+			params.arch = genimg_get_arch_id(optarg);
+			if (params.arch < 0)
+				usage("Invalid architecture");
+			break;
+		case 'b':
+			expecting = IH_TYPE_FLATDT;
+			break;
+		case 'c':
+			params.comment = optarg;
+			break;
+		case 'C':
+			params.comp = genimg_get_comp_id(optarg);
+			if (params.comp < 0)
+				usage("Invalid compression type");
+			break;
+		case 'd':
+			params.datafile = optarg;
+			params.dflag = 1;
+			break;
+		case 'D':
+			params.dtc = optarg;
+			break;
+		case 'e':
+			params.ep = strtoull(optarg, &ptr, 16);
+			if (*ptr) {
+				fprintf(stderr, "%s: invalid entry point %s\n",
+					params.cmdname, optarg);
+				exit(EXIT_FAILURE);
+			}
+			params.eflag = 1;
+			break;
+		case 'E':
+			params.external_data = true;
+			break;
+		case 'f':
+			datafile = optarg;
+			params.auto_its = !strcmp(datafile, "auto");
+			/* no break */
+		case 'F':
+			/*
+			 * The flattened image tree (FIT) format
+			 * requires a flattened device tree image type
+			 */
+			params.fit_image_type = params.type;
+			params.type = IH_TYPE_FLATDT;
+			params.fflag = 1;
+			break;
+		case 'k':
+			params.keydir = optarg;
+			break;
+		case 'K':
+			params.keydest = optarg;
+			break;
+		case 'l':
+			params.lflag = 1;
+			break;
+		case 'n':
+			params.imagename = optarg;
+			break;
+		case 'O':
+			params.os = genimg_get_os_id(optarg);
+			if (params.os < 0)
+				usage("Invalid operating system");
+			break;
+		case 'r':
+			params.require_keys = 1;
+			break;
+		case 'R':
+			/*
+			 * This entry is for the second configuration
+			 * file, if only one is not enough.
+			 */
+			params.imagename2 = optarg;
+			break;
+		case 's':
+			params.skipcpy = 1;
+			break;
+		case 'T':
+			type = genimg_get_type_id(optarg);
+			if (type < 0) {
+				show_image_types();
+				usage("Invalid image type");
+			}
+			expecting = type;
+			break;
+		case 'v':
+			params.vflag++;
+			break;
+		case 'V':
+			printf("mkimage version %s\n", PLAIN_VERSION);
+			exit(EXIT_SUCCESS);
+		case 'x':
+			params.xflag++;
+			break;
+		case 1:
+			if (expecting == type || optind == argc) {
+				params.imagefile = optarg;
+				expecting = IH_TYPE_INVALID;
+			} else if (expecting == IH_TYPE_INVALID) {
+				fprintf(stderr,
+					"%s: Unknown content type: use -b before device tree files",
+					params.cmdname);
+				exit(EXIT_FAILURE);
+			} else {
+				if (add_content(expecting, optarg)) {
+					fprintf(stderr,
+						"%s: Out of memory adding content '%s'",
+						params.cmdname, optarg);
+					exit(EXIT_FAILURE);
+				}
+			}
+			break;
+		default:
+			usage("Invalid option");
+		}
+	}
+
+	/*
+	 * For auto-generated FIT images we need to know the image type to put
+	 * in the FIT, which is separate from the file's image type (which
+	 * will always be IH_TYPE_FLATDT in this case).
+	 */
+	if (params.type == IH_TYPE_FLATDT) {
+		params.fit_image_type = type;
+		if (!params.auto_its)
+			params.datafile = datafile;
+	} else if (type != IH_TYPE_INVALID) {
+		params.type = type;
+	}
+
+	if (!params.imagefile)
+		usage("Missing output filename");
+}
+
+
 int main(int argc, char **argv)
 {
 	int ifd = -1;
@@ -78,144 +295,10 @@
 	int dfd;
 
 	params.cmdname = *argv;
-	params.addr = params.ep = 0;
-
-	while (--argc > 0 && **++argv == '-') {
-		while (*++*argv) {
-			switch (**argv) {
-			case 'l':
-				params.lflag = 1;
-				break;
-			case 'A':
-				if ((--argc <= 0) ||
-					(params.arch =
-					genimg_get_arch_id (*++argv)) < 0)
-					usage ();
-				goto NXTARG;
-			case 'c':
-				if (--argc <= 0)
-					usage();
-				params.comment = *++argv;
-				goto NXTARG;
-			case 'C':
-				if ((--argc <= 0) ||
-					(params.comp =
-					genimg_get_comp_id (*++argv)) < 0)
-					usage ();
-				goto NXTARG;
-			case 'D':
-				if (--argc <= 0)
-					usage ();
-				params.dtc = *++argv;
-				goto NXTARG;
-
-			case 'O':
-				if ((--argc <= 0) ||
-					(params.os =
-					genimg_get_os_id (*++argv)) < 0)
-					usage ();
-				goto NXTARG;
-			case 'T':
-				params.type = -1;
-				if (--argc >= 0 && argv[1]) {
-					params.type =
-						genimg_get_type_id(*++argv);
-				}
-				if (params.type < 0) {
-					show_image_types();
-					usage();
-				}
-				goto NXTARG;
-			case 'a':
-				if (--argc <= 0)
-					usage ();
-				params.addr = strtoull(*++argv, &ptr, 16);
-				if (*ptr) {
-					fprintf (stderr,
-						"%s: invalid load address %s\n",
-						params.cmdname, *argv);
-					exit (EXIT_FAILURE);
-				}
-				goto NXTARG;
-			case 'd':
-				if (--argc <= 0)
-					usage ();
-				params.datafile = *++argv;
-				params.dflag = 1;
-				goto NXTARG;
-			case 'e':
-				if (--argc <= 0)
-					usage ();
-				params.ep = strtoull(*++argv, &ptr, 16);
-				if (*ptr) {
-					fprintf (stderr,
-						"%s: invalid entry point %s\n",
-						params.cmdname, *argv);
-					exit (EXIT_FAILURE);
-				}
-				params.eflag = 1;
-				goto NXTARG;
-			case 'f':
-				if (--argc <= 0)
-					usage ();
-				params.datafile = *++argv;
-				/* no break */
-			case 'F':
-				/*
-				 * The flattened image tree (FIT) format
-				 * requires a flattened device tree image type
-				 */
-				params.type = IH_TYPE_FLATDT;
-				params.fflag = 1;
-				goto NXTARG;
-			case 'k':
-				if (--argc <= 0)
-					usage();
-				params.keydir = *++argv;
-				goto NXTARG;
-			case 'K':
-				if (--argc <= 0)
-					usage();
-				params.keydest = *++argv;
-				goto NXTARG;
-			case 'n':
-				if (--argc <= 0)
-					usage ();
-				params.imagename = *++argv;
-				goto NXTARG;
-			case 'r':
-				params.require_keys = 1;
-				break;
-			case 'R':
-				if (--argc <= 0)
-					usage();
-				/*
-				 * This entry is for the second configuration
-				 * file, if only one is not enough.
-				 */
-				params.imagename2 = *++argv;
-				goto NXTARG;
-			case 's':
-				params.skipcpy = 1;
-				break;
-			case 'v':
-				params.vflag++;
-				break;
-			case 'V':
-				printf("mkimage version %s\n", PLAIN_VERSION);
-				exit(EXIT_SUCCESS);
-			case 'x':
-				params.xflag++;
-				break;
-			default:
-				usage ();
-			}
-		}
-NXTARG:		;
-	}
+	params.addr = 0;
+	params.ep = 0;
 
-	if (argc != 1)
-		usage ();
+	process_args(argc, argv);
 
 	/* set tparams as per input type_id */
 	tparams = imagetool_get_type(params.type);
@@ -231,7 +314,7 @@
 	 */
 	if (tparams->check_params)
 		if (tparams->check_params (&params))
-			usage ();
+			usage("Bad parameters for image type");
 
 	if (!params.eflag) {
 		params.ep = params.addr;
@@ -240,8 +323,6 @@
 			params.ep += tparams->header_size;
 	}
 
-	params.imagefile = *argv;
-
 	if (params.fflag){
 		if (tparams->fflag_handle)
 			/*
@@ -579,41 +660,3 @@
 	(void) munmap((void *)ptr, sbuf.st_size);
 	(void) close (dfd);
 }
-
-static void usage(void)
-{
-	fprintf (stderr, "Usage: %s -l image\n"
-			 "          -l ==> list image header information\n",
-		params.cmdname);
-	fprintf (stderr, "       %s [-x] -A arch -O os -T type -C comp "
-			 "-a addr -e ep -n name -d data_file[:data_file...] image\n"
-			 "          -A ==> set architecture to 'arch'\n"
-			 "          -O ==> set operating system to 'os'\n"
-			 "          -T ==> set image type to 'type'\n"
-			 "          -C ==> set compression type 'comp'\n"
-			 "          -a ==> set load address to 'addr' (hex)\n"
-			 "          -e ==> set entry point to 'ep' (hex)\n"
-			 "          -n ==> set image name to 'name'\n"
-			 "          -d ==> use image data from 'datafile'\n"
-			 "          -x ==> set XIP (execute in place)\n",
-		params.cmdname);
-	fprintf(stderr, "       %s [-D dtc_options] [-f fit-image.its|-F] fit-image\n",
-		params.cmdname);
-	fprintf(stderr, "          -D => set all options for device tree compiler\n"
-			"          -f => input filename for FIT source\n");
-#ifdef CONFIG_FIT_SIGNATURE
-	fprintf(stderr, "Signing / verified boot options: [-k keydir] [-K dtb] [ -c <comment>] [-r]\n"
-			"          -k => set directory containing private keys\n"
-			"          -K => write public keys to this .dtb file\n"
-			"          -c => add comment in signature node\n"
-			"          -F => re-sign existing FIT image\n"
-			"          -r => mark keys used as 'required' in dtb\n");
-#else
-	fprintf(stderr, "Signing / verified boot not supported (CONFIG_FIT_SIGNATURE undefined)\n");
-#endif
-	fprintf (stderr, "       %s -V ==> print version information and exit\n",
-		params.cmdname);
-	fprintf(stderr, "Use -T to see a list of available image types\n");
-
-	exit (EXIT_FAILURE);
-}
diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py
index 5f1b4f6..e088bae 100644
--- a/tools/patman/gitutil.py
+++ b/tools/patman/gitutil.py
@@ -44,6 +44,11 @@
         cmd.append('-n%d' % count)
     if commit_range:
         cmd.append(commit_range)
+
+    # Add this in case we have a branch with the same name as a directory.
+    # This avoids messages like this, for example:
+    #   fatal: ambiguous argument 'test': both revision and filename
+    cmd.append('--')
     return cmd
 
 def CountCommitsToBranch():
diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index 6d3c41f..27d031e 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -376,7 +376,7 @@
     if not series:
         series = Series()
     series.allow_overwrite = allow_overwrite
-    params = gitutil.LogCmd(commit_range,reverse=True, count=count,
+    params = gitutil.LogCmd(commit_range, reverse=True, count=count,
                             git_dir=git_dir)
     stdout = command.RunPipe([params], capture=True).stdout
     ps = PatchStream(series, is_log=True)
diff --git a/tools/patman/patman.py b/tools/patman/patman.py
index d05c5ff..fe50eb4 100755
--- a/tools/patman/patman.py
+++ b/tools/patman/patman.py
@@ -117,7 +117,8 @@
     pager = os.getenv('PAGER')
     if not pager:
         pager = 'more'
-    fname = os.path.join(os.path.dirname(sys.argv[0]), 'README')
+    fname = os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])),
+                         'README')
     command.Run(pager, fname)
 
 # Process commits, produce patches files, check them, email them